5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
63 static struct nand_ecclayout nand_oob_16 = {
65 .eccpos = {0, 1, 2, 3, 6, 7},
71 static struct nand_ecclayout nand_oob_64 = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
82 static struct nand_ecclayout nand_oob_128 = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
106 DEFINE_LED_TRIGGER(nand_led_trigger);
108 static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
111 struct nand_chip *chip = mtd->priv;
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__);
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__);
126 /* Do not allow past end of device */
127 if (ofs + len > mtd->size) {
128 pr_debug("%s: past end of device\n", __func__);
136 * nand_release_device - [GENERIC] release chip
137 * @mtd: MTD device structure
139 * Deselect, release chip lock and wake up anyone waiting on the device.
141 static void nand_release_device(struct mtd_info *mtd)
143 struct nand_chip *chip = mtd->priv;
145 /* De-select the NAND device */
146 chip->select_chip(mtd, -1);
148 /* Release the controller and the chip */
149 spin_lock(&chip->controller->lock);
150 chip->controller->active = NULL;
151 chip->state = FL_READY;
152 wake_up(&chip->controller->wq);
153 spin_unlock(&chip->controller->lock);
157 * nand_read_byte - [DEFAULT] read one byte from the chip
158 * @mtd: MTD device structure
160 * Default read function for 8bit buswidth
162 static uint8_t nand_read_byte(struct mtd_info *mtd)
164 struct nand_chip *chip = mtd->priv;
165 return readb(chip->IO_ADDR_R);
169 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
170 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
171 * @mtd: MTD device structure
173 * Default read function for 16bit buswidth with endianness conversion.
176 static uint8_t nand_read_byte16(struct mtd_info *mtd)
178 struct nand_chip *chip = mtd->priv;
179 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
183 * nand_read_word - [DEFAULT] read one word from the chip
184 * @mtd: MTD device structure
186 * Default read function for 16bit buswidth without endianness conversion.
188 static u16 nand_read_word(struct mtd_info *mtd)
190 struct nand_chip *chip = mtd->priv;
191 return readw(chip->IO_ADDR_R);
195 * nand_select_chip - [DEFAULT] control CE line
196 * @mtd: MTD device structure
197 * @chipnr: chipnumber to select, -1 for deselect
199 * Default select function for 1 chip devices.
201 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
203 struct nand_chip *chip = mtd->priv;
207 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
218 * nand_write_buf - [DEFAULT] write buffer to chip
219 * @mtd: MTD device structure
221 * @len: number of bytes to write
223 * Default write function for 8bit buswidth.
225 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
228 struct nand_chip *chip = mtd->priv;
230 for (i = 0; i < len; i++)
231 writeb(buf[i], chip->IO_ADDR_W);
235 * nand_read_buf - [DEFAULT] read chip data into buffer
236 * @mtd: MTD device structure
237 * @buf: buffer to store date
238 * @len: number of bytes to read
240 * Default read function for 8bit buswidth.
242 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
245 struct nand_chip *chip = mtd->priv;
247 for (i = 0; i < len; i++)
248 buf[i] = readb(chip->IO_ADDR_R);
252 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
253 * @mtd: MTD device structure
254 * @buf: buffer containing the data to compare
255 * @len: number of bytes to compare
257 * Default verify function for 8bit buswidth.
259 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
262 struct nand_chip *chip = mtd->priv;
264 for (i = 0; i < len; i++)
265 if (buf[i] != readb(chip->IO_ADDR_R))
271 * nand_write_buf16 - [DEFAULT] write buffer to chip
272 * @mtd: MTD device structure
274 * @len: number of bytes to write
276 * Default write function for 16bit buswidth.
278 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
281 struct nand_chip *chip = mtd->priv;
282 u16 *p = (u16 *) buf;
285 for (i = 0; i < len; i++)
286 writew(p[i], chip->IO_ADDR_W);
291 * nand_read_buf16 - [DEFAULT] read chip data into buffer
292 * @mtd: MTD device structure
293 * @buf: buffer to store date
294 * @len: number of bytes to read
296 * Default read function for 16bit buswidth.
298 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
301 struct nand_chip *chip = mtd->priv;
302 u16 *p = (u16 *) buf;
305 for (i = 0; i < len; i++)
306 p[i] = readw(chip->IO_ADDR_R);
310 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
311 * @mtd: MTD device structure
312 * @buf: buffer containing the data to compare
313 * @len: number of bytes to compare
315 * Default verify function for 16bit buswidth.
317 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
320 struct nand_chip *chip = mtd->priv;
321 u16 *p = (u16 *) buf;
324 for (i = 0; i < len; i++)
325 if (p[i] != readw(chip->IO_ADDR_R))
332 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
333 * @mtd: MTD device structure
334 * @ofs: offset from device start
335 * @getchip: 0, if the chip is already selected
337 * Check, if the block is bad.
339 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
341 int page, chipnr, res = 0, i = 0;
342 struct nand_chip *chip = mtd->priv;
345 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
346 ofs += mtd->erasesize - mtd->writesize;
348 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
351 chipnr = (int)(ofs >> chip->chip_shift);
353 nand_get_device(chip, mtd, FL_READING);
355 /* Select the NAND device */
356 chip->select_chip(mtd, chipnr);
360 if (chip->options & NAND_BUSWIDTH_16) {
361 chip->cmdfunc(mtd, NAND_CMD_READOOB,
362 chip->badblockpos & 0xFE, page);
363 bad = cpu_to_le16(chip->read_word(mtd));
364 if (chip->badblockpos & 0x1)
369 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
371 bad = chip->read_byte(mtd);
374 if (likely(chip->badblockbits == 8))
377 res = hweight8(bad) < chip->badblockbits;
378 ofs += mtd->writesize;
379 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
381 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
384 nand_release_device(mtd);
390 * nand_default_block_markbad - [DEFAULT] mark a block bad
391 * @mtd: MTD device structure
392 * @ofs: offset from device start
394 * This is the default implementation, which can be overridden by a hardware
397 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399 struct nand_chip *chip = mtd->priv;
400 uint8_t buf[2] = { 0, 0 };
401 int block, ret, i = 0;
403 if (!(chip->bbt_options & NAND_BBT_USE_FLASH)) {
404 struct erase_info einfo;
406 /* Attempt erase before marking OOB */
407 memset(&einfo, 0, sizeof(einfo));
410 einfo.len = 1 << chip->phys_erase_shift;
411 nand_erase_nand(mtd, &einfo, 0);
414 /* Get block number */
415 block = (int)(ofs >> chip->bbt_erase_shift);
417 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
419 /* Do we have a flash based bad block table? */
420 if (chip->bbt_options & NAND_BBT_USE_FLASH)
421 ret = nand_update_bbt(mtd, ofs);
423 struct mtd_oob_ops ops;
426 nand_get_device(chip, mtd, FL_WRITING);
429 * Write to first/last page(s) if necessary. If we write to more
430 * than one location, the first error encountered quits the
435 ops.ooboffs = chip->badblockpos;
436 if (chip->options & NAND_BUSWIDTH_16) {
437 ops.ooboffs &= ~0x01;
438 ops.len = ops.ooblen = 2;
440 ops.len = ops.ooblen = 1;
442 ops.mode = MTD_OPS_PLACE_OOB;
444 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
445 wr_ofs += mtd->erasesize - mtd->writesize;
447 ret = nand_do_write_oob(mtd, wr_ofs, &ops);
450 wr_ofs += mtd->writesize;
451 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
454 nand_release_device(mtd);
457 mtd->ecc_stats.badblocks++;
463 * nand_check_wp - [GENERIC] check if the chip is write protected
464 * @mtd: MTD device structure
466 * Check, if the device is write protected. The function expects, that the
467 * device is already selected.
469 static int nand_check_wp(struct mtd_info *mtd)
471 struct nand_chip *chip = mtd->priv;
473 /* Broken xD cards report WP despite being writable */
474 if (chip->options & NAND_BROKEN_XD)
477 /* Check the WP bit */
478 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
479 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
483 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
484 * @mtd: MTD device structure
485 * @ofs: offset from device start
486 * @getchip: 0, if the chip is already selected
487 * @allowbbt: 1, if its allowed to access the bbt area
489 * Check, if the block is bad. Either by reading the bad block table or
490 * calling of the scan function.
492 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
495 struct nand_chip *chip = mtd->priv;
498 return chip->block_bad(mtd, ofs, getchip);
500 /* Return info from the table */
501 return nand_isbad_bbt(mtd, ofs, allowbbt);
505 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
506 * @mtd: MTD device structure
509 * Helper function for nand_wait_ready used when needing to wait in interrupt
512 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
514 struct nand_chip *chip = mtd->priv;
517 /* Wait for the device to get ready */
518 for (i = 0; i < timeo; i++) {
519 if (chip->dev_ready(mtd))
521 touch_softlockup_watchdog();
526 /* Wait for the ready pin, after a command. The timeout is caught later. */
527 void nand_wait_ready(struct mtd_info *mtd)
529 struct nand_chip *chip = mtd->priv;
530 unsigned long timeo = jiffies + 2;
533 if (in_interrupt() || oops_in_progress)
534 return panic_nand_wait_ready(mtd, 400);
536 led_trigger_event(nand_led_trigger, LED_FULL);
537 /* Wait until command is processed or timeout occurs */
539 if (chip->dev_ready(mtd))
541 touch_softlockup_watchdog();
542 } while (time_before(jiffies, timeo));
543 led_trigger_event(nand_led_trigger, LED_OFF);
545 EXPORT_SYMBOL_GPL(nand_wait_ready);
548 * nand_command - [DEFAULT] Send command to NAND device
549 * @mtd: MTD device structure
550 * @command: the command to be sent
551 * @column: the column address for this command, -1 if none
552 * @page_addr: the page address for this command, -1 if none
554 * Send command to NAND device. This function is used for small page devices
555 * (256/512 Bytes per page).
557 static void nand_command(struct mtd_info *mtd, unsigned int command,
558 int column, int page_addr)
560 register struct nand_chip *chip = mtd->priv;
561 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
563 /* Write out the command to the device */
564 if (command == NAND_CMD_SEQIN) {
567 if (column >= mtd->writesize) {
569 column -= mtd->writesize;
570 readcmd = NAND_CMD_READOOB;
571 } else if (column < 256) {
572 /* First 256 bytes --> READ0 */
573 readcmd = NAND_CMD_READ0;
576 readcmd = NAND_CMD_READ1;
578 chip->cmd_ctrl(mtd, readcmd, ctrl);
579 ctrl &= ~NAND_CTRL_CHANGE;
581 chip->cmd_ctrl(mtd, command, ctrl);
583 /* Address cycle, when necessary */
584 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
585 /* Serially input address */
587 /* Adjust columns for 16 bit buswidth */
588 if (chip->options & NAND_BUSWIDTH_16)
590 chip->cmd_ctrl(mtd, column, ctrl);
591 ctrl &= ~NAND_CTRL_CHANGE;
593 if (page_addr != -1) {
594 chip->cmd_ctrl(mtd, page_addr, ctrl);
595 ctrl &= ~NAND_CTRL_CHANGE;
596 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
597 /* One more address cycle for devices > 32MiB */
598 if (chip->chipsize > (32 << 20))
599 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
601 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
604 * Program and erase have their own busy handlers status and sequential
609 case NAND_CMD_PAGEPROG:
610 case NAND_CMD_ERASE1:
611 case NAND_CMD_ERASE2:
613 case NAND_CMD_STATUS:
619 udelay(chip->chip_delay);
620 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
621 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
623 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
624 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
628 /* This applies to read commands */
631 * If we don't have access to the busy pin, we apply the given
634 if (!chip->dev_ready) {
635 udelay(chip->chip_delay);
640 * Apply this short delay always to ensure that we do wait tWB in
641 * any case on any machine.
645 nand_wait_ready(mtd);
649 * nand_command_lp - [DEFAULT] Send command to NAND large page device
650 * @mtd: MTD device structure
651 * @command: the command to be sent
652 * @column: the column address for this command, -1 if none
653 * @page_addr: the page address for this command, -1 if none
655 * Send command to NAND device. This is the version for the new large page
656 * devices. We don't have the separate regions as we have in the small page
657 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
659 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
660 int column, int page_addr)
662 register struct nand_chip *chip = mtd->priv;
664 /* Emulate NAND_CMD_READOOB */
665 if (command == NAND_CMD_READOOB) {
666 column += mtd->writesize;
667 command = NAND_CMD_READ0;
670 /* Command latch cycle */
671 chip->cmd_ctrl(mtd, command & 0xff,
672 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
674 if (column != -1 || page_addr != -1) {
675 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
677 /* Serially input address */
679 /* Adjust columns for 16 bit buswidth */
680 if (chip->options & NAND_BUSWIDTH_16)
682 chip->cmd_ctrl(mtd, column, ctrl);
683 ctrl &= ~NAND_CTRL_CHANGE;
684 chip->cmd_ctrl(mtd, column >> 8, ctrl);
686 if (page_addr != -1) {
687 chip->cmd_ctrl(mtd, page_addr, ctrl);
688 chip->cmd_ctrl(mtd, page_addr >> 8,
689 NAND_NCE | NAND_ALE);
690 /* One more address cycle for devices > 128MiB */
691 if (chip->chipsize > (128 << 20))
692 chip->cmd_ctrl(mtd, page_addr >> 16,
693 NAND_NCE | NAND_ALE);
696 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
699 * Program and erase have their own busy handlers status, sequential
700 * in, and deplete1 need no delay.
704 case NAND_CMD_CACHEDPROG:
705 case NAND_CMD_PAGEPROG:
706 case NAND_CMD_ERASE1:
707 case NAND_CMD_ERASE2:
710 case NAND_CMD_STATUS:
711 case NAND_CMD_DEPLETE1:
714 case NAND_CMD_STATUS_ERROR:
715 case NAND_CMD_STATUS_ERROR0:
716 case NAND_CMD_STATUS_ERROR1:
717 case NAND_CMD_STATUS_ERROR2:
718 case NAND_CMD_STATUS_ERROR3:
719 /* Read error status commands require only a short delay */
720 udelay(chip->chip_delay);
726 udelay(chip->chip_delay);
727 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
728 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
729 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
730 NAND_NCE | NAND_CTRL_CHANGE);
731 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
735 case NAND_CMD_RNDOUT:
736 /* No ready / busy check necessary */
737 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
738 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
739 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
740 NAND_NCE | NAND_CTRL_CHANGE);
744 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
745 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
746 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
747 NAND_NCE | NAND_CTRL_CHANGE);
749 /* This applies to read commands */
752 * If we don't have access to the busy pin, we apply the given
755 if (!chip->dev_ready) {
756 udelay(chip->chip_delay);
762 * Apply this short delay always to ensure that we do wait tWB in
763 * any case on any machine.
767 nand_wait_ready(mtd);
771 * panic_nand_get_device - [GENERIC] Get chip for selected access
772 * @chip: the nand chip descriptor
773 * @mtd: MTD device structure
774 * @new_state: the state which is requested
776 * Used when in panic, no locks are taken.
778 static void panic_nand_get_device(struct nand_chip *chip,
779 struct mtd_info *mtd, int new_state)
781 /* Hardware controller shared among independent devices */
782 chip->controller->active = chip;
783 chip->state = new_state;
787 * nand_get_device - [GENERIC] Get chip for selected access
788 * @chip: the nand chip descriptor
789 * @mtd: MTD device structure
790 * @new_state: the state which is requested
792 * Get the device and lock it for exclusive access
795 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
797 spinlock_t *lock = &chip->controller->lock;
798 wait_queue_head_t *wq = &chip->controller->wq;
799 DECLARE_WAITQUEUE(wait, current);
803 /* Hardware controller shared among independent devices */
804 if (!chip->controller->active)
805 chip->controller->active = chip;
807 if (chip->controller->active == chip && chip->state == FL_READY) {
808 chip->state = new_state;
812 if (new_state == FL_PM_SUSPENDED) {
813 if (chip->controller->active->state == FL_PM_SUSPENDED) {
814 chip->state = FL_PM_SUSPENDED;
819 set_current_state(TASK_UNINTERRUPTIBLE);
820 add_wait_queue(wq, &wait);
823 remove_wait_queue(wq, &wait);
828 * panic_nand_wait - [GENERIC] wait until the command is done
829 * @mtd: MTD device structure
830 * @chip: NAND chip structure
833 * Wait for command done. This is a helper function for nand_wait used when
834 * we are in interrupt context. May happen when in panic and trying to write
835 * an oops through mtdoops.
837 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
841 for (i = 0; i < timeo; i++) {
842 if (chip->dev_ready) {
843 if (chip->dev_ready(mtd))
846 if (chip->read_byte(mtd) & NAND_STATUS_READY)
854 * nand_wait - [DEFAULT] wait until the command is done
855 * @mtd: MTD device structure
856 * @chip: NAND chip structure
858 * Wait for command done. This applies to erase and program only. Erase can
859 * take up to 400ms and program up to 20ms according to general NAND and
862 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
865 unsigned long timeo = jiffies;
866 int status, state = chip->state;
868 if (state == FL_ERASING)
869 timeo += (HZ * 400) / 1000;
871 timeo += (HZ * 20) / 1000;
873 led_trigger_event(nand_led_trigger, LED_FULL);
876 * Apply this short delay always to ensure that we do wait tWB in any
877 * case on any machine.
881 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
882 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
884 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
886 if (in_interrupt() || oops_in_progress)
887 panic_nand_wait(mtd, chip, timeo);
889 while (time_before(jiffies, timeo)) {
890 if (chip->dev_ready) {
891 if (chip->dev_ready(mtd))
894 if (chip->read_byte(mtd) & NAND_STATUS_READY)
900 led_trigger_event(nand_led_trigger, LED_OFF);
902 status = (int)chip->read_byte(mtd);
907 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
909 * @ofs: offset to start unlock from
910 * @len: length to unlock
911 * @invert: when = 0, unlock the range of blocks within the lower and
912 * upper boundary address
913 * when = 1, unlock the range of blocks outside the boundaries
914 * of the lower and upper boundary address
916 * Returs unlock status.
918 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
919 uint64_t len, int invert)
923 struct nand_chip *chip = mtd->priv;
925 /* Submit address of first page to unlock */
926 page = ofs >> chip->page_shift;
927 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
929 /* Submit address of last page to unlock */
930 page = (ofs + len) >> chip->page_shift;
931 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
932 (page | invert) & chip->pagemask);
934 /* Call wait ready function */
935 status = chip->waitfunc(mtd, chip);
936 /* See if device thinks it succeeded */
938 pr_debug("%s: error status = 0x%08x\n",
947 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
949 * @ofs: offset to start unlock from
950 * @len: length to unlock
952 * Returns unlock status.
954 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
958 struct nand_chip *chip = mtd->priv;
960 pr_debug("%s: start = 0x%012llx, len = %llu\n",
961 __func__, (unsigned long long)ofs, len);
963 if (check_offs_len(mtd, ofs, len))
966 /* Align to last block address if size addresses end of the device */
967 if (ofs + len == mtd->size)
968 len -= mtd->erasesize;
970 nand_get_device(chip, mtd, FL_UNLOCKING);
972 /* Shift to get chip number */
973 chipnr = ofs >> chip->chip_shift;
975 chip->select_chip(mtd, chipnr);
977 /* Check, if it is write protected */
978 if (nand_check_wp(mtd)) {
979 pr_debug("%s: device is write protected!\n",
985 ret = __nand_unlock(mtd, ofs, len, 0);
988 nand_release_device(mtd);
992 EXPORT_SYMBOL(nand_unlock);
995 * nand_lock - [REPLACEABLE] locks all blocks present in the device
997 * @ofs: offset to start unlock from
998 * @len: length to unlock
1000 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1001 * have this feature, but it allows only to lock all blocks, not for specified
1002 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1005 * Returns lock status.
1007 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1010 int chipnr, status, page;
1011 struct nand_chip *chip = mtd->priv;
1013 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1014 __func__, (unsigned long long)ofs, len);
1016 if (check_offs_len(mtd, ofs, len))
1019 nand_get_device(chip, mtd, FL_LOCKING);
1021 /* Shift to get chip number */
1022 chipnr = ofs >> chip->chip_shift;
1024 chip->select_chip(mtd, chipnr);
1026 /* Check, if it is write protected */
1027 if (nand_check_wp(mtd)) {
1028 pr_debug("%s: device is write protected!\n",
1030 status = MTD_ERASE_FAILED;
1035 /* Submit address of first page to lock */
1036 page = ofs >> chip->page_shift;
1037 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1039 /* Call wait ready function */
1040 status = chip->waitfunc(mtd, chip);
1041 /* See if device thinks it succeeded */
1042 if (status & 0x01) {
1043 pr_debug("%s: error status = 0x%08x\n",
1049 ret = __nand_unlock(mtd, ofs, len, 0x1);
1052 nand_release_device(mtd);
1056 EXPORT_SYMBOL(nand_lock);
1059 * nand_read_page_raw - [INTERN] read raw page data without ecc
1060 * @mtd: mtd info structure
1061 * @chip: nand chip info structure
1062 * @buf: buffer to store read data
1063 * @page: page number to read
1065 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1067 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1068 uint8_t *buf, int page)
1070 chip->read_buf(mtd, buf, mtd->writesize);
1071 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1076 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1077 * @mtd: mtd info structure
1078 * @chip: nand chip info structure
1079 * @buf: buffer to store read data
1080 * @page: page number to read
1082 * We need a special oob layout and handling even when OOB isn't used.
1084 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1085 struct nand_chip *chip,
1086 uint8_t *buf, int page)
1088 int eccsize = chip->ecc.size;
1089 int eccbytes = chip->ecc.bytes;
1090 uint8_t *oob = chip->oob_poi;
1093 for (steps = chip->ecc.steps; steps > 0; steps--) {
1094 chip->read_buf(mtd, buf, eccsize);
1097 if (chip->ecc.prepad) {
1098 chip->read_buf(mtd, oob, chip->ecc.prepad);
1099 oob += chip->ecc.prepad;
1102 chip->read_buf(mtd, oob, eccbytes);
1105 if (chip->ecc.postpad) {
1106 chip->read_buf(mtd, oob, chip->ecc.postpad);
1107 oob += chip->ecc.postpad;
1111 size = mtd->oobsize - (oob - chip->oob_poi);
1113 chip->read_buf(mtd, oob, size);
1119 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1120 * @mtd: mtd info structure
1121 * @chip: nand chip info structure
1122 * @buf: buffer to store read data
1123 * @page: page number to read
1125 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1126 uint8_t *buf, int page)
1128 int i, eccsize = chip->ecc.size;
1129 int eccbytes = chip->ecc.bytes;
1130 int eccsteps = chip->ecc.steps;
1132 uint8_t *ecc_calc = chip->buffers->ecccalc;
1133 uint8_t *ecc_code = chip->buffers->ecccode;
1134 uint32_t *eccpos = chip->ecc.layout->eccpos;
1136 chip->ecc.read_page_raw(mtd, chip, buf, page);
1138 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1139 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1141 for (i = 0; i < chip->ecc.total; i++)
1142 ecc_code[i] = chip->oob_poi[eccpos[i]];
1144 eccsteps = chip->ecc.steps;
1147 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1150 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1152 mtd->ecc_stats.failed++;
1154 mtd->ecc_stats.corrected += stat;
1160 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1161 * @mtd: mtd info structure
1162 * @chip: nand chip info structure
1163 * @data_offs: offset of requested data within the page
1164 * @readlen: data length
1165 * @bufpoi: buffer to store read data
1167 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1168 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1170 int start_step, end_step, num_steps;
1171 uint32_t *eccpos = chip->ecc.layout->eccpos;
1173 int data_col_addr, i, gaps = 0;
1174 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1175 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1178 /* Column address within the page aligned to ECC size (256bytes) */
1179 start_step = data_offs / chip->ecc.size;
1180 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1181 num_steps = end_step - start_step + 1;
1183 /* Data size aligned to ECC ecc.size */
1184 datafrag_len = num_steps * chip->ecc.size;
1185 eccfrag_len = num_steps * chip->ecc.bytes;
1187 data_col_addr = start_step * chip->ecc.size;
1188 /* If we read not a page aligned data */
1189 if (data_col_addr != 0)
1190 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1192 p = bufpoi + data_col_addr;
1193 chip->read_buf(mtd, p, datafrag_len);
1196 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1197 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1200 * The performance is faster if we position offsets according to
1201 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1203 for (i = 0; i < eccfrag_len - 1; i++) {
1204 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1205 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1211 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1212 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1215 * Send the command to read the particular ECC bytes take care
1216 * about buswidth alignment in read_buf.
1218 index = start_step * chip->ecc.bytes;
1220 aligned_pos = eccpos[index] & ~(busw - 1);
1221 aligned_len = eccfrag_len;
1222 if (eccpos[index] & (busw - 1))
1224 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1227 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1228 mtd->writesize + aligned_pos, -1);
1229 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1232 for (i = 0; i < eccfrag_len; i++)
1233 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1235 p = bufpoi + data_col_addr;
1236 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1239 stat = chip->ecc.correct(mtd, p,
1240 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1242 mtd->ecc_stats.failed++;
1244 mtd->ecc_stats.corrected += stat;
1250 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1251 * @mtd: mtd info structure
1252 * @chip: nand chip info structure
1253 * @buf: buffer to store read data
1254 * @page: page number to read
1256 * Not for syndrome calculating ECC controllers which need a special oob layout.
1258 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1259 uint8_t *buf, int page)
1261 int i, eccsize = chip->ecc.size;
1262 int eccbytes = chip->ecc.bytes;
1263 int eccsteps = chip->ecc.steps;
1265 uint8_t *ecc_calc = chip->buffers->ecccalc;
1266 uint8_t *ecc_code = chip->buffers->ecccode;
1267 uint32_t *eccpos = chip->ecc.layout->eccpos;
1269 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1270 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1271 chip->read_buf(mtd, p, eccsize);
1272 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1274 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1276 for (i = 0; i < chip->ecc.total; i++)
1277 ecc_code[i] = chip->oob_poi[eccpos[i]];
1279 eccsteps = chip->ecc.steps;
1282 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1285 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1287 mtd->ecc_stats.failed++;
1289 mtd->ecc_stats.corrected += stat;
1295 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1296 * @mtd: mtd info structure
1297 * @chip: nand chip info structure
1298 * @buf: buffer to store read data
1299 * @page: page number to read
1301 * Hardware ECC for large page chips, require OOB to be read first. For this
1302 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1303 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1304 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1305 * the data area, by overwriting the NAND manufacturer bad block markings.
1307 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1308 struct nand_chip *chip, uint8_t *buf, int page)
1310 int i, eccsize = chip->ecc.size;
1311 int eccbytes = chip->ecc.bytes;
1312 int eccsteps = chip->ecc.steps;
1314 uint8_t *ecc_code = chip->buffers->ecccode;
1315 uint32_t *eccpos = chip->ecc.layout->eccpos;
1316 uint8_t *ecc_calc = chip->buffers->ecccalc;
1318 /* Read the OOB area first */
1319 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1320 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1321 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1323 for (i = 0; i < chip->ecc.total; i++)
1324 ecc_code[i] = chip->oob_poi[eccpos[i]];
1326 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1329 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1330 chip->read_buf(mtd, p, eccsize);
1331 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1333 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1335 mtd->ecc_stats.failed++;
1337 mtd->ecc_stats.corrected += stat;
1343 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1344 * @mtd: mtd info structure
1345 * @chip: nand chip info structure
1346 * @buf: buffer to store read data
1347 * @page: page number to read
1349 * The hw generator calculates the error syndrome automatically. Therefore we
1350 * need a special oob layout and handling.
1352 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1353 uint8_t *buf, int page)
1355 int i, eccsize = chip->ecc.size;
1356 int eccbytes = chip->ecc.bytes;
1357 int eccsteps = chip->ecc.steps;
1359 uint8_t *oob = chip->oob_poi;
1361 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1364 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1365 chip->read_buf(mtd, p, eccsize);
1367 if (chip->ecc.prepad) {
1368 chip->read_buf(mtd, oob, chip->ecc.prepad);
1369 oob += chip->ecc.prepad;
1372 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1373 chip->read_buf(mtd, oob, eccbytes);
1374 stat = chip->ecc.correct(mtd, p, oob, NULL);
1377 mtd->ecc_stats.failed++;
1379 mtd->ecc_stats.corrected += stat;
1383 if (chip->ecc.postpad) {
1384 chip->read_buf(mtd, oob, chip->ecc.postpad);
1385 oob += chip->ecc.postpad;
1389 /* Calculate remaining oob bytes */
1390 i = mtd->oobsize - (oob - chip->oob_poi);
1392 chip->read_buf(mtd, oob, i);
1398 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1399 * @chip: nand chip structure
1400 * @oob: oob destination address
1401 * @ops: oob ops structure
1402 * @len: size of oob to transfer
1404 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1405 struct mtd_oob_ops *ops, size_t len)
1407 switch (ops->mode) {
1409 case MTD_OPS_PLACE_OOB:
1411 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1414 case MTD_OPS_AUTO_OOB: {
1415 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1416 uint32_t boffs = 0, roffs = ops->ooboffs;
1419 for (; free->length && len; free++, len -= bytes) {
1420 /* Read request not from offset 0? */
1421 if (unlikely(roffs)) {
1422 if (roffs >= free->length) {
1423 roffs -= free->length;
1426 boffs = free->offset + roffs;
1427 bytes = min_t(size_t, len,
1428 (free->length - roffs));
1431 bytes = min_t(size_t, len, free->length);
1432 boffs = free->offset;
1434 memcpy(oob, chip->oob_poi + boffs, bytes);
1446 * nand_do_read_ops - [INTERN] Read data with ECC
1447 * @mtd: MTD device structure
1448 * @from: offset to read from
1449 * @ops: oob ops structure
1451 * Internal function. Called with chip held.
1453 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1454 struct mtd_oob_ops *ops)
1456 int chipnr, page, realpage, col, bytes, aligned;
1457 struct nand_chip *chip = mtd->priv;
1458 struct mtd_ecc_stats stats;
1459 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1462 uint32_t readlen = ops->len;
1463 uint32_t oobreadlen = ops->ooblen;
1464 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1465 mtd->oobavail : mtd->oobsize;
1467 uint8_t *bufpoi, *oob, *buf;
1469 stats = mtd->ecc_stats;
1471 chipnr = (int)(from >> chip->chip_shift);
1472 chip->select_chip(mtd, chipnr);
1474 realpage = (int)(from >> chip->page_shift);
1475 page = realpage & chip->pagemask;
1477 col = (int)(from & (mtd->writesize - 1));
1483 bytes = min(mtd->writesize - col, readlen);
1484 aligned = (bytes == mtd->writesize);
1486 /* Is the current page in the buffer? */
1487 if (realpage != chip->pagebuf || oob) {
1488 bufpoi = aligned ? buf : chip->buffers->databuf;
1490 if (likely(sndcmd)) {
1491 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1495 /* Now read the page into the buffer */
1496 if (unlikely(ops->mode == MTD_OPS_RAW))
1497 ret = chip->ecc.read_page_raw(mtd, chip,
1499 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1500 ret = chip->ecc.read_subpage(mtd, chip,
1501 col, bytes, bufpoi);
1503 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1507 /* Invalidate page cache */
1512 /* Transfer not aligned data */
1514 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1515 !(mtd->ecc_stats.failed - stats.failed) &&
1516 (ops->mode != MTD_OPS_RAW))
1517 chip->pagebuf = realpage;
1519 /* Invalidate page cache */
1521 memcpy(buf, chip->buffers->databuf + col, bytes);
1526 if (unlikely(oob)) {
1528 int toread = min(oobreadlen, max_oobsize);
1531 oob = nand_transfer_oob(chip,
1533 oobreadlen -= toread;
1537 if (!(chip->options & NAND_NO_READRDY)) {
1539 * Apply delay or wait for ready/busy pin. Do
1540 * this before the AUTOINCR check, so no
1541 * problems arise if a chip which does auto
1542 * increment is marked as NOAUTOINCR by the
1545 if (!chip->dev_ready)
1546 udelay(chip->chip_delay);
1548 nand_wait_ready(mtd);
1551 memcpy(buf, chip->buffers->databuf + col, bytes);
1560 /* For subsequent reads align to page boundary */
1562 /* Increment page address */
1565 page = realpage & chip->pagemask;
1566 /* Check, if we cross a chip boundary */
1569 chip->select_chip(mtd, -1);
1570 chip->select_chip(mtd, chipnr);
1574 * Check, if the chip supports auto page increment or if we
1575 * have hit a block boundary.
1577 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1581 ops->retlen = ops->len - (size_t) readlen;
1583 ops->oobretlen = ops->ooblen - oobreadlen;
1588 if (mtd->ecc_stats.failed - stats.failed)
1591 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1595 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1596 * @mtd: MTD device structure
1597 * @from: offset to read from
1598 * @len: number of bytes to read
1599 * @retlen: pointer to variable to store the number of read bytes
1600 * @buf: the databuffer to put data
1602 * Get hold of the chip and call nand_do_read.
1604 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1605 size_t *retlen, uint8_t *buf)
1607 struct nand_chip *chip = mtd->priv;
1608 struct mtd_oob_ops ops;
1611 /* Do not allow reads past end of device */
1612 if ((from + len) > mtd->size)
1617 nand_get_device(chip, mtd, FL_READING);
1624 ret = nand_do_read_ops(mtd, from, &ops);
1626 *retlen = ops.retlen;
1628 nand_release_device(mtd);
1634 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1635 * @mtd: mtd info structure
1636 * @chip: nand chip info structure
1637 * @page: page number to read
1638 * @sndcmd: flag whether to issue read command or not
1640 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1641 int page, int sndcmd)
1644 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1647 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1652 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1654 * @mtd: mtd info structure
1655 * @chip: nand chip info structure
1656 * @page: page number to read
1657 * @sndcmd: flag whether to issue read command or not
1659 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1660 int page, int sndcmd)
1662 uint8_t *buf = chip->oob_poi;
1663 int length = mtd->oobsize;
1664 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1665 int eccsize = chip->ecc.size;
1666 uint8_t *bufpoi = buf;
1667 int i, toread, sndrnd = 0, pos;
1669 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1670 for (i = 0; i < chip->ecc.steps; i++) {
1672 pos = eccsize + i * (eccsize + chunk);
1673 if (mtd->writesize > 512)
1674 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1676 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1679 toread = min_t(int, length, chunk);
1680 chip->read_buf(mtd, bufpoi, toread);
1685 chip->read_buf(mtd, bufpoi, length);
1691 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1692 * @mtd: mtd info structure
1693 * @chip: nand chip info structure
1694 * @page: page number to write
1696 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1700 const uint8_t *buf = chip->oob_poi;
1701 int length = mtd->oobsize;
1703 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1704 chip->write_buf(mtd, buf, length);
1705 /* Send command to program the OOB data */
1706 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1708 status = chip->waitfunc(mtd, chip);
1710 return status & NAND_STATUS_FAIL ? -EIO : 0;
1714 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1715 * with syndrome - only for large page flash
1716 * @mtd: mtd info structure
1717 * @chip: nand chip info structure
1718 * @page: page number to write
1720 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1721 struct nand_chip *chip, int page)
1723 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1724 int eccsize = chip->ecc.size, length = mtd->oobsize;
1725 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1726 const uint8_t *bufpoi = chip->oob_poi;
1729 * data-ecc-data-ecc ... ecc-oob
1731 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1733 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1734 pos = steps * (eccsize + chunk);
1739 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1740 for (i = 0; i < steps; i++) {
1742 if (mtd->writesize <= 512) {
1743 uint32_t fill = 0xFFFFFFFF;
1747 int num = min_t(int, len, 4);
1748 chip->write_buf(mtd, (uint8_t *)&fill,
1753 pos = eccsize + i * (eccsize + chunk);
1754 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1758 len = min_t(int, length, chunk);
1759 chip->write_buf(mtd, bufpoi, len);
1764 chip->write_buf(mtd, bufpoi, length);
1766 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1767 status = chip->waitfunc(mtd, chip);
1769 return status & NAND_STATUS_FAIL ? -EIO : 0;
1773 * nand_do_read_oob - [INTERN] NAND read out-of-band
1774 * @mtd: MTD device structure
1775 * @from: offset to read from
1776 * @ops: oob operations description structure
1778 * NAND read out-of-band data from the spare area.
1780 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1781 struct mtd_oob_ops *ops)
1783 int page, realpage, chipnr, sndcmd = 1;
1784 struct nand_chip *chip = mtd->priv;
1785 struct mtd_ecc_stats stats;
1786 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1787 int readlen = ops->ooblen;
1789 uint8_t *buf = ops->oobbuf;
1791 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1792 __func__, (unsigned long long)from, readlen);
1794 stats = mtd->ecc_stats;
1796 if (ops->mode == MTD_OPS_AUTO_OOB)
1797 len = chip->ecc.layout->oobavail;
1801 if (unlikely(ops->ooboffs >= len)) {
1802 pr_debug("%s: attempt to start read outside oob\n",
1807 /* Do not allow reads past end of device */
1808 if (unlikely(from >= mtd->size ||
1809 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1810 (from >> chip->page_shift)) * len)) {
1811 pr_debug("%s: attempt to read beyond end of device\n",
1816 chipnr = (int)(from >> chip->chip_shift);
1817 chip->select_chip(mtd, chipnr);
1819 /* Shift to get page */
1820 realpage = (int)(from >> chip->page_shift);
1821 page = realpage & chip->pagemask;
1824 if (ops->mode == MTD_OPS_RAW)
1825 sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
1827 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1829 len = min(len, readlen);
1830 buf = nand_transfer_oob(chip, buf, ops, len);
1832 if (!(chip->options & NAND_NO_READRDY)) {
1834 * Apply delay or wait for ready/busy pin. Do this
1835 * before the AUTOINCR check, so no problems arise if a
1836 * chip which does auto increment is marked as
1837 * NOAUTOINCR by the board driver.
1839 if (!chip->dev_ready)
1840 udelay(chip->chip_delay);
1842 nand_wait_ready(mtd);
1849 /* Increment page address */
1852 page = realpage & chip->pagemask;
1853 /* Check, if we cross a chip boundary */
1856 chip->select_chip(mtd, -1);
1857 chip->select_chip(mtd, chipnr);
1861 * Check, if the chip supports auto page increment or if we
1862 * have hit a block boundary.
1864 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1868 ops->oobretlen = ops->ooblen;
1870 if (mtd->ecc_stats.failed - stats.failed)
1873 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1877 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1878 * @mtd: MTD device structure
1879 * @from: offset to read from
1880 * @ops: oob operation description structure
1882 * NAND read data and/or out-of-band data.
1884 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1885 struct mtd_oob_ops *ops)
1887 struct nand_chip *chip = mtd->priv;
1888 int ret = -ENOTSUPP;
1892 /* Do not allow reads past end of device */
1893 if (ops->datbuf && (from + ops->len) > mtd->size) {
1894 pr_debug("%s: attempt to read beyond end of device\n",
1899 nand_get_device(chip, mtd, FL_READING);
1901 switch (ops->mode) {
1902 case MTD_OPS_PLACE_OOB:
1903 case MTD_OPS_AUTO_OOB:
1912 ret = nand_do_read_oob(mtd, from, ops);
1914 ret = nand_do_read_ops(mtd, from, ops);
1917 nand_release_device(mtd);
1923 * nand_write_page_raw - [INTERN] raw page write function
1924 * @mtd: mtd info structure
1925 * @chip: nand chip info structure
1928 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1930 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1933 chip->write_buf(mtd, buf, mtd->writesize);
1934 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1938 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1939 * @mtd: mtd info structure
1940 * @chip: nand chip info structure
1943 * We need a special oob layout and handling even when ECC isn't checked.
1945 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1946 struct nand_chip *chip,
1949 int eccsize = chip->ecc.size;
1950 int eccbytes = chip->ecc.bytes;
1951 uint8_t *oob = chip->oob_poi;
1954 for (steps = chip->ecc.steps; steps > 0; steps--) {
1955 chip->write_buf(mtd, buf, eccsize);
1958 if (chip->ecc.prepad) {
1959 chip->write_buf(mtd, oob, chip->ecc.prepad);
1960 oob += chip->ecc.prepad;
1963 chip->read_buf(mtd, oob, eccbytes);
1966 if (chip->ecc.postpad) {
1967 chip->write_buf(mtd, oob, chip->ecc.postpad);
1968 oob += chip->ecc.postpad;
1972 size = mtd->oobsize - (oob - chip->oob_poi);
1974 chip->write_buf(mtd, oob, size);
1977 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1978 * @mtd: mtd info structure
1979 * @chip: nand chip info structure
1982 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1985 int i, eccsize = chip->ecc.size;
1986 int eccbytes = chip->ecc.bytes;
1987 int eccsteps = chip->ecc.steps;
1988 uint8_t *ecc_calc = chip->buffers->ecccalc;
1989 const uint8_t *p = buf;
1990 uint32_t *eccpos = chip->ecc.layout->eccpos;
1992 /* Software ECC calculation */
1993 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1994 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1996 for (i = 0; i < chip->ecc.total; i++)
1997 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1999 chip->ecc.write_page_raw(mtd, chip, buf);
2003 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2004 * @mtd: mtd info structure
2005 * @chip: nand chip info structure
2008 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2011 int i, eccsize = chip->ecc.size;
2012 int eccbytes = chip->ecc.bytes;
2013 int eccsteps = chip->ecc.steps;
2014 uint8_t *ecc_calc = chip->buffers->ecccalc;
2015 const uint8_t *p = buf;
2016 uint32_t *eccpos = chip->ecc.layout->eccpos;
2018 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2019 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2020 chip->write_buf(mtd, p, eccsize);
2021 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2024 for (i = 0; i < chip->ecc.total; i++)
2025 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2027 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2031 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2032 * @mtd: mtd info structure
2033 * @chip: nand chip info structure
2036 * The hw generator calculates the error syndrome automatically. Therefore we
2037 * need a special oob layout and handling.
2039 static void nand_write_page_syndrome(struct mtd_info *mtd,
2040 struct nand_chip *chip, const uint8_t *buf)
2042 int i, eccsize = chip->ecc.size;
2043 int eccbytes = chip->ecc.bytes;
2044 int eccsteps = chip->ecc.steps;
2045 const uint8_t *p = buf;
2046 uint8_t *oob = chip->oob_poi;
2048 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2050 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2051 chip->write_buf(mtd, p, eccsize);
2053 if (chip->ecc.prepad) {
2054 chip->write_buf(mtd, oob, chip->ecc.prepad);
2055 oob += chip->ecc.prepad;
2058 chip->ecc.calculate(mtd, p, oob);
2059 chip->write_buf(mtd, oob, eccbytes);
2062 if (chip->ecc.postpad) {
2063 chip->write_buf(mtd, oob, chip->ecc.postpad);
2064 oob += chip->ecc.postpad;
2068 /* Calculate remaining oob bytes */
2069 i = mtd->oobsize - (oob - chip->oob_poi);
2071 chip->write_buf(mtd, oob, i);
2075 * nand_write_page - [REPLACEABLE] write one page
2076 * @mtd: MTD device structure
2077 * @chip: NAND chip descriptor
2078 * @buf: the data to write
2079 * @page: page number to write
2080 * @cached: cached programming
2081 * @raw: use _raw version of write_page
2083 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2084 const uint8_t *buf, int page, int cached, int raw)
2088 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2091 chip->ecc.write_page_raw(mtd, chip, buf);
2093 chip->ecc.write_page(mtd, chip, buf);
2096 * Cached progamming disabled for now. Not sure if it's worth the
2097 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2101 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2103 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2104 status = chip->waitfunc(mtd, chip);
2106 * See if operation failed and additional status checks are
2109 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2110 status = chip->errstat(mtd, chip, FL_WRITING, status,
2113 if (status & NAND_STATUS_FAIL)
2116 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2117 status = chip->waitfunc(mtd, chip);
2120 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2121 /* Send command to read back the data */
2122 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2124 if (chip->verify_buf(mtd, buf, mtd->writesize))
2131 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2132 * @mtd: MTD device structure
2133 * @oob: oob data buffer
2134 * @len: oob data write length
2135 * @ops: oob ops structure
2137 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2138 struct mtd_oob_ops *ops)
2140 struct nand_chip *chip = mtd->priv;
2143 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2144 * data from a previous OOB read.
2146 memset(chip->oob_poi, 0xff, mtd->oobsize);
2148 switch (ops->mode) {
2150 case MTD_OPS_PLACE_OOB:
2152 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2155 case MTD_OPS_AUTO_OOB: {
2156 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2157 uint32_t boffs = 0, woffs = ops->ooboffs;
2160 for (; free->length && len; free++, len -= bytes) {
2161 /* Write request not from offset 0? */
2162 if (unlikely(woffs)) {
2163 if (woffs >= free->length) {
2164 woffs -= free->length;
2167 boffs = free->offset + woffs;
2168 bytes = min_t(size_t, len,
2169 (free->length - woffs));
2172 bytes = min_t(size_t, len, free->length);
2173 boffs = free->offset;
2175 memcpy(chip->oob_poi + boffs, oob, bytes);
2186 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2189 * nand_do_write_ops - [INTERN] NAND write with ECC
2190 * @mtd: MTD device structure
2191 * @to: offset to write to
2192 * @ops: oob operations description structure
2194 * NAND write with ECC.
2196 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2197 struct mtd_oob_ops *ops)
2199 int chipnr, realpage, page, blockmask, column;
2200 struct nand_chip *chip = mtd->priv;
2201 uint32_t writelen = ops->len;
2203 uint32_t oobwritelen = ops->ooblen;
2204 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2205 mtd->oobavail : mtd->oobsize;
2207 uint8_t *oob = ops->oobbuf;
2208 uint8_t *buf = ops->datbuf;
2215 /* Reject writes, which are not page aligned */
2216 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2217 pr_notice("%s: attempt to write non page aligned data\n",
2222 column = to & (mtd->writesize - 1);
2223 subpage = column || (writelen & (mtd->writesize - 1));
2228 chipnr = (int)(to >> chip->chip_shift);
2229 chip->select_chip(mtd, chipnr);
2231 /* Check, if it is write protected */
2232 if (nand_check_wp(mtd))
2235 realpage = (int)(to >> chip->page_shift);
2236 page = realpage & chip->pagemask;
2237 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2239 /* Invalidate the page cache, when we write to the cached page */
2240 if (to <= (chip->pagebuf << chip->page_shift) &&
2241 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2244 /* Don't allow multipage oob writes with offset */
2245 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2249 int bytes = mtd->writesize;
2250 int cached = writelen > bytes && page != blockmask;
2251 uint8_t *wbuf = buf;
2253 /* Partial page write? */
2254 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2256 bytes = min_t(int, bytes - column, (int) writelen);
2258 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2259 memcpy(&chip->buffers->databuf[column], buf, bytes);
2260 wbuf = chip->buffers->databuf;
2263 if (unlikely(oob)) {
2264 size_t len = min(oobwritelen, oobmaxlen);
2265 oob = nand_fill_oob(mtd, oob, len, ops);
2268 /* We still need to erase leftover OOB data */
2269 memset(chip->oob_poi, 0xff, mtd->oobsize);
2272 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2273 (ops->mode == MTD_OPS_RAW));
2285 page = realpage & chip->pagemask;
2286 /* Check, if we cross a chip boundary */
2289 chip->select_chip(mtd, -1);
2290 chip->select_chip(mtd, chipnr);
2294 ops->retlen = ops->len - writelen;
2296 ops->oobretlen = ops->ooblen;
2301 * panic_nand_write - [MTD Interface] NAND write with ECC
2302 * @mtd: MTD device structure
2303 * @to: offset to write to
2304 * @len: number of bytes to write
2305 * @retlen: pointer to variable to store the number of written bytes
2306 * @buf: the data to write
2308 * NAND write with ECC. Used when performing writes in interrupt context, this
2309 * may for example be called by mtdoops when writing an oops while in panic.
2311 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2312 size_t *retlen, const uint8_t *buf)
2314 struct nand_chip *chip = mtd->priv;
2315 struct mtd_oob_ops ops;
2318 /* Do not allow reads past end of device */
2319 if ((to + len) > mtd->size)
2324 /* Wait for the device to get ready */
2325 panic_nand_wait(mtd, chip, 400);
2327 /* Grab the device */
2328 panic_nand_get_device(chip, mtd, FL_WRITING);
2331 ops.datbuf = (uint8_t *)buf;
2335 ret = nand_do_write_ops(mtd, to, &ops);
2337 *retlen = ops.retlen;
2342 * nand_write - [MTD Interface] NAND write with ECC
2343 * @mtd: MTD device structure
2344 * @to: offset to write to
2345 * @len: number of bytes to write
2346 * @retlen: pointer to variable to store the number of written bytes
2347 * @buf: the data to write
2349 * NAND write with ECC.
2351 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2352 size_t *retlen, const uint8_t *buf)
2354 struct nand_chip *chip = mtd->priv;
2355 struct mtd_oob_ops ops;
2358 /* Do not allow reads past end of device */
2359 if ((to + len) > mtd->size)
2364 nand_get_device(chip, mtd, FL_WRITING);
2367 ops.datbuf = (uint8_t *)buf;
2371 ret = nand_do_write_ops(mtd, to, &ops);
2373 *retlen = ops.retlen;
2375 nand_release_device(mtd);
2381 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2382 * @mtd: MTD device structure
2383 * @to: offset to write to
2384 * @ops: oob operation description structure
2386 * NAND write out-of-band.
2388 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2389 struct mtd_oob_ops *ops)
2391 int chipnr, page, status, len;
2392 struct nand_chip *chip = mtd->priv;
2394 pr_debug("%s: to = 0x%08x, len = %i\n",
2395 __func__, (unsigned int)to, (int)ops->ooblen);
2397 if (ops->mode == MTD_OPS_AUTO_OOB)
2398 len = chip->ecc.layout->oobavail;
2402 /* Do not allow write past end of page */
2403 if ((ops->ooboffs + ops->ooblen) > len) {
2404 pr_debug("%s: attempt to write past end of page\n",
2409 if (unlikely(ops->ooboffs >= len)) {
2410 pr_debug("%s: attempt to start write outside oob\n",
2415 /* Do not allow write past end of device */
2416 if (unlikely(to >= mtd->size ||
2417 ops->ooboffs + ops->ooblen >
2418 ((mtd->size >> chip->page_shift) -
2419 (to >> chip->page_shift)) * len)) {
2420 pr_debug("%s: attempt to write beyond end of device\n",
2425 chipnr = (int)(to >> chip->chip_shift);
2426 chip->select_chip(mtd, chipnr);
2428 /* Shift to get page */
2429 page = (int)(to >> chip->page_shift);
2432 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2433 * of my DiskOnChip 2000 test units) will clear the whole data page too
2434 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2435 * it in the doc2000 driver in August 1999. dwmw2.
2437 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2439 /* Check, if it is write protected */
2440 if (nand_check_wp(mtd))
2443 /* Invalidate the page cache, if we write to the cached page */
2444 if (page == chip->pagebuf)
2447 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2449 if (ops->mode == MTD_OPS_RAW)
2450 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2452 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2457 ops->oobretlen = ops->ooblen;
2463 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2464 * @mtd: MTD device structure
2465 * @to: offset to write to
2466 * @ops: oob operation description structure
2468 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2469 struct mtd_oob_ops *ops)
2471 struct nand_chip *chip = mtd->priv;
2472 int ret = -ENOTSUPP;
2476 /* Do not allow writes past end of device */
2477 if (ops->datbuf && (to + ops->len) > mtd->size) {
2478 pr_debug("%s: attempt to write beyond end of device\n",
2483 nand_get_device(chip, mtd, FL_WRITING);
2485 switch (ops->mode) {
2486 case MTD_OPS_PLACE_OOB:
2487 case MTD_OPS_AUTO_OOB:
2496 ret = nand_do_write_oob(mtd, to, ops);
2498 ret = nand_do_write_ops(mtd, to, ops);
2501 nand_release_device(mtd);
2506 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2507 * @mtd: MTD device structure
2508 * @page: the page address of the block which will be erased
2510 * Standard erase command for NAND chips.
2512 static void single_erase_cmd(struct mtd_info *mtd, int page)
2514 struct nand_chip *chip = mtd->priv;
2515 /* Send commands to erase a block */
2516 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2517 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2521 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2522 * @mtd: MTD device structure
2523 * @page: the page address of the block which will be erased
2525 * AND multi block erase command function. Erase 4 consecutive blocks.
2527 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2529 struct nand_chip *chip = mtd->priv;
2530 /* Send commands to erase a block */
2531 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2532 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2533 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2534 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2535 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2539 * nand_erase - [MTD Interface] erase block(s)
2540 * @mtd: MTD device structure
2541 * @instr: erase instruction
2543 * Erase one ore more blocks.
2545 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2547 return nand_erase_nand(mtd, instr, 0);
2550 #define BBT_PAGE_MASK 0xffffff3f
2552 * nand_erase_nand - [INTERN] erase block(s)
2553 * @mtd: MTD device structure
2554 * @instr: erase instruction
2555 * @allowbbt: allow erasing the bbt area
2557 * Erase one ore more blocks.
2559 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2562 int page, status, pages_per_block, ret, chipnr;
2563 struct nand_chip *chip = mtd->priv;
2564 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2565 unsigned int bbt_masked_page = 0xffffffff;
2568 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2569 __func__, (unsigned long long)instr->addr,
2570 (unsigned long long)instr->len);
2572 if (check_offs_len(mtd, instr->addr, instr->len))
2575 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2577 /* Grab the lock and see if the device is available */
2578 nand_get_device(chip, mtd, FL_ERASING);
2580 /* Shift to get first page */
2581 page = (int)(instr->addr >> chip->page_shift);
2582 chipnr = (int)(instr->addr >> chip->chip_shift);
2584 /* Calculate pages in each block */
2585 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2587 /* Select the NAND device */
2588 chip->select_chip(mtd, chipnr);
2590 /* Check, if it is write protected */
2591 if (nand_check_wp(mtd)) {
2592 pr_debug("%s: device is write protected!\n",
2594 instr->state = MTD_ERASE_FAILED;
2599 * If BBT requires refresh, set the BBT page mask to see if the BBT
2600 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2601 * can not be matched. This is also done when the bbt is actually
2602 * erased to avoid recursive updates.
2604 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2605 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2607 /* Loop through the pages */
2610 instr->state = MTD_ERASING;
2613 /* Check if we have a bad block, we do not erase bad blocks! */
2614 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2615 chip->page_shift, 0, allowbbt)) {
2616 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2618 instr->state = MTD_ERASE_FAILED;
2623 * Invalidate the page cache, if we erase the block which
2624 * contains the current cached page.
2626 if (page <= chip->pagebuf && chip->pagebuf <
2627 (page + pages_per_block))
2630 chip->erase_cmd(mtd, page & chip->pagemask);
2632 status = chip->waitfunc(mtd, chip);
2635 * See if operation failed and additional status checks are
2638 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2639 status = chip->errstat(mtd, chip, FL_ERASING,
2642 /* See if block erase succeeded */
2643 if (status & NAND_STATUS_FAIL) {
2644 pr_debug("%s: failed erase, page 0x%08x\n",
2646 instr->state = MTD_ERASE_FAILED;
2648 ((loff_t)page << chip->page_shift);
2653 * If BBT requires refresh, set the BBT rewrite flag to the
2654 * page being erased.
2656 if (bbt_masked_page != 0xffffffff &&
2657 (page & BBT_PAGE_MASK) == bbt_masked_page)
2658 rewrite_bbt[chipnr] =
2659 ((loff_t)page << chip->page_shift);
2661 /* Increment page address and decrement length */
2662 len -= (1 << chip->phys_erase_shift);
2663 page += pages_per_block;
2665 /* Check, if we cross a chip boundary */
2666 if (len && !(page & chip->pagemask)) {
2668 chip->select_chip(mtd, -1);
2669 chip->select_chip(mtd, chipnr);
2672 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2673 * page mask to see if this BBT should be rewritten.
2675 if (bbt_masked_page != 0xffffffff &&
2676 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2677 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2681 instr->state = MTD_ERASE_DONE;
2685 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2687 /* Deselect and wake up anyone waiting on the device */
2688 nand_release_device(mtd);
2690 /* Do call back function */
2692 mtd_erase_callback(instr);
2695 * If BBT requires refresh and erase was successful, rewrite any
2696 * selected bad block tables.
2698 if (bbt_masked_page == 0xffffffff || ret)
2701 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2702 if (!rewrite_bbt[chipnr])
2704 /* Update the BBT for chip */
2705 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2706 __func__, chipnr, rewrite_bbt[chipnr],
2707 chip->bbt_td->pages[chipnr]);
2708 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2711 /* Return more or less happy */
2716 * nand_sync - [MTD Interface] sync
2717 * @mtd: MTD device structure
2719 * Sync is actually a wait for chip ready function.
2721 static void nand_sync(struct mtd_info *mtd)
2723 struct nand_chip *chip = mtd->priv;
2725 pr_debug("%s: called\n", __func__);
2727 /* Grab the lock and see if the device is available */
2728 nand_get_device(chip, mtd, FL_SYNCING);
2729 /* Release it and go back */
2730 nand_release_device(mtd);
2734 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2735 * @mtd: MTD device structure
2736 * @offs: offset relative to mtd start
2738 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2740 /* Check for invalid offset */
2741 if (offs > mtd->size)
2744 return nand_block_checkbad(mtd, offs, 1, 0);
2748 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2749 * @mtd: MTD device structure
2750 * @ofs: offset relative to mtd start
2752 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2754 struct nand_chip *chip = mtd->priv;
2757 ret = nand_block_isbad(mtd, ofs);
2759 /* If it was bad already, return success and do nothing */
2765 return chip->block_markbad(mtd, ofs);
2769 * nand_suspend - [MTD Interface] Suspend the NAND flash
2770 * @mtd: MTD device structure
2772 static int nand_suspend(struct mtd_info *mtd)
2774 struct nand_chip *chip = mtd->priv;
2776 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2780 * nand_resume - [MTD Interface] Resume the NAND flash
2781 * @mtd: MTD device structure
2783 static void nand_resume(struct mtd_info *mtd)
2785 struct nand_chip *chip = mtd->priv;
2787 if (chip->state == FL_PM_SUSPENDED)
2788 nand_release_device(mtd);
2790 pr_err("%s called for a chip which is not in suspended state\n",
2794 /* Set default functions */
2795 static void nand_set_defaults(struct nand_chip *chip, int busw)
2797 /* check for proper chip_delay setup, set 20us if not */
2798 if (!chip->chip_delay)
2799 chip->chip_delay = 20;
2801 /* check, if a user supplied command function given */
2802 if (chip->cmdfunc == NULL)
2803 chip->cmdfunc = nand_command;
2805 /* check, if a user supplied wait function given */
2806 if (chip->waitfunc == NULL)
2807 chip->waitfunc = nand_wait;
2809 if (!chip->select_chip)
2810 chip->select_chip = nand_select_chip;
2811 if (!chip->read_byte)
2812 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2813 if (!chip->read_word)
2814 chip->read_word = nand_read_word;
2815 if (!chip->block_bad)
2816 chip->block_bad = nand_block_bad;
2817 if (!chip->block_markbad)
2818 chip->block_markbad = nand_default_block_markbad;
2819 if (!chip->write_buf)
2820 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2821 if (!chip->read_buf)
2822 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2823 if (!chip->verify_buf)
2824 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2825 if (!chip->scan_bbt)
2826 chip->scan_bbt = nand_default_bbt;
2828 if (!chip->controller) {
2829 chip->controller = &chip->hwcontrol;
2830 spin_lock_init(&chip->controller->lock);
2831 init_waitqueue_head(&chip->controller->wq);
2836 /* Sanitize ONFI strings so we can safely print them */
2837 static void sanitize_string(uint8_t *s, size_t len)
2841 /* Null terminate */
2844 /* Remove non printable chars */
2845 for (i = 0; i < len - 1; i++) {
2846 if (s[i] < ' ' || s[i] > 127)
2850 /* Remove trailing spaces */
2854 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2859 for (i = 0; i < 8; i++)
2860 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2867 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2869 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2872 struct nand_onfi_params *p = &chip->onfi_params;
2876 /* Try ONFI for unknown chip or LP */
2877 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2878 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2879 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2882 pr_info("ONFI flash detected\n");
2883 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2884 for (i = 0; i < 3; i++) {
2885 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2886 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2887 le16_to_cpu(p->crc)) {
2888 pr_info("ONFI param page %d valid\n", i);
2897 val = le16_to_cpu(p->revision);
2899 chip->onfi_version = 23;
2900 else if (val & (1 << 4))
2901 chip->onfi_version = 22;
2902 else if (val & (1 << 3))
2903 chip->onfi_version = 21;
2904 else if (val & (1 << 2))
2905 chip->onfi_version = 20;
2906 else if (val & (1 << 1))
2907 chip->onfi_version = 10;
2909 chip->onfi_version = 0;
2911 if (!chip->onfi_version) {
2912 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2916 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2917 sanitize_string(p->model, sizeof(p->model));
2919 mtd->name = p->model;
2920 mtd->writesize = le32_to_cpu(p->byte_per_page);
2921 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2922 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2923 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2925 if (le16_to_cpu(p->features) & 1)
2926 *busw = NAND_BUSWIDTH_16;
2928 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2929 chip->options |= (NAND_NO_READRDY |
2930 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2936 * Get the flash and manufacturer id and lookup if the type is supported.
2938 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2939 struct nand_chip *chip,
2941 int *maf_id, int *dev_id,
2942 struct nand_flash_dev *type)
2948 /* Select the device */
2949 chip->select_chip(mtd, 0);
2952 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2955 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2957 /* Send the command for reading device ID */
2958 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2960 /* Read manufacturer and device IDs */
2961 *maf_id = chip->read_byte(mtd);
2962 *dev_id = chip->read_byte(mtd);
2965 * Try again to make sure, as some systems the bus-hold or other
2966 * interface concerns can cause random data which looks like a
2967 * possibly credible NAND flash to appear. If the two results do
2968 * not match, ignore the device completely.
2971 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2973 for (i = 0; i < 2; i++)
2974 id_data[i] = chip->read_byte(mtd);
2976 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2977 pr_info("%s: second ID read did not match "
2978 "%02x,%02x against %02x,%02x\n", __func__,
2979 *maf_id, *dev_id, id_data[0], id_data[1]);
2980 return ERR_PTR(-ENODEV);
2984 type = nand_flash_ids;
2986 for (; type->name != NULL; type++)
2987 if (*dev_id == type->id)
2990 chip->onfi_version = 0;
2991 if (!type->name || !type->pagesize) {
2992 /* Check is chip is ONFI compliant */
2993 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2998 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3000 /* Read entire ID string */
3002 for (i = 0; i < 8; i++)
3003 id_data[i] = chip->read_byte(mtd);
3006 return ERR_PTR(-ENODEV);
3009 mtd->name = type->name;
3011 chip->chipsize = (uint64_t)type->chipsize << 20;
3013 if (!type->pagesize && chip->init_size) {
3014 /* Set the pagesize, oobsize, erasesize by the driver */
3015 busw = chip->init_size(mtd, chip, id_data);
3016 } else if (!type->pagesize) {
3018 /* The 3rd id byte holds MLC / multichip data */
3019 chip->cellinfo = id_data[2];
3020 /* The 4th id byte is the important one */
3024 * Field definitions are in the following datasheets:
3025 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3026 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
3028 * Check for wraparound + Samsung ID + nonzero 6th byte
3029 * to decide what to do.
3031 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3032 id_data[0] == NAND_MFR_SAMSUNG &&
3033 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3034 id_data[5] != 0x00) {
3036 mtd->writesize = 2048 << (extid & 0x03);
3039 switch (extid & 0x03) {
3054 /* Calc blocksize */
3055 mtd->erasesize = (128 * 1024) <<
3056 (((extid >> 1) & 0x04) | (extid & 0x03));
3060 mtd->writesize = 1024 << (extid & 0x03);
3063 mtd->oobsize = (8 << (extid & 0x01)) *
3064 (mtd->writesize >> 9);
3066 /* Calc blocksize. Blocksize is multiples of 64KiB */
3067 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3069 /* Get buswidth information */
3070 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3074 * Old devices have chip data hardcoded in the device id table.
3076 mtd->erasesize = type->erasesize;
3077 mtd->writesize = type->pagesize;
3078 mtd->oobsize = mtd->writesize / 32;
3079 busw = type->options & NAND_BUSWIDTH_16;
3082 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3083 * some Spansion chips have erasesize that conflicts with size
3084 * listed in nand_ids table.
3085 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3087 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3088 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3089 id_data[7] == 0x00 && mtd->writesize == 512) {
3090 mtd->erasesize = 128 * 1024;
3091 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3094 /* Get chip options, preserve non chip based options */
3095 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3096 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3099 * Check if chip is not a Samsung device. Do not clear the
3100 * options for chips which do not have an extended id.
3102 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3103 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3107 * Set chip as a default. Board drivers can override it, if necessary.
3109 chip->options |= NAND_NO_AUTOINCR;
3111 /* Try to identify manufacturer */
3112 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3113 if (nand_manuf_ids[maf_idx].id == *maf_id)
3118 * Check, if buswidth is correct. Hardware drivers should set
3121 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3122 pr_info("NAND device: Manufacturer ID:"
3123 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3124 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3125 pr_warn("NAND bus width %d instead %d bit\n",
3126 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3128 return ERR_PTR(-EINVAL);
3131 /* Calculate the address shift from the page size */
3132 chip->page_shift = ffs(mtd->writesize) - 1;
3133 /* Convert chipsize to number of pages per chip -1 */
3134 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3136 chip->bbt_erase_shift = chip->phys_erase_shift =
3137 ffs(mtd->erasesize) - 1;
3138 if (chip->chipsize & 0xffffffff)
3139 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3141 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3142 chip->chip_shift += 32 - 1;
3145 chip->badblockbits = 8;
3147 /* Set the bad block position */
3148 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3149 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3151 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3154 * Bad block marker is stored in the last page of each block
3155 * on Samsung and Hynix MLC devices; stored in first two pages
3156 * of each block on Micron devices with 2KiB pages and on
3157 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3158 * All others scan only the first page.
3160 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3161 (*maf_id == NAND_MFR_SAMSUNG ||
3162 *maf_id == NAND_MFR_HYNIX))
3163 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3164 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3165 (*maf_id == NAND_MFR_SAMSUNG ||
3166 *maf_id == NAND_MFR_HYNIX ||
3167 *maf_id == NAND_MFR_TOSHIBA ||
3168 *maf_id == NAND_MFR_AMD ||
3169 *maf_id == NAND_MFR_MACRONIX)) ||
3170 (mtd->writesize == 2048 &&
3171 *maf_id == NAND_MFR_MICRON))
3172 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3174 /* Check for AND chips with 4 page planes */
3175 if (chip->options & NAND_4PAGE_ARRAY)
3176 chip->erase_cmd = multi_erase_cmd;
3178 chip->erase_cmd = single_erase_cmd;
3180 /* Do not replace user supplied command function! */
3181 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3182 chip->cmdfunc = nand_command_lp;
3184 pr_info("NAND device: Manufacturer ID:"
3185 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3186 nand_manuf_ids[maf_idx].name,
3187 chip->onfi_version ? chip->onfi_params.model : type->name);
3193 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3194 * @mtd: MTD device structure
3195 * @maxchips: number of chips to scan for
3196 * @table: alternative NAND ID table
3198 * This is the first phase of the normal nand_scan() function. It reads the
3199 * flash ID and sets up MTD fields accordingly.
3201 * The mtd->owner field must be set to the module of the caller.
3203 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3204 struct nand_flash_dev *table)
3206 int i, busw, nand_maf_id, nand_dev_id;
3207 struct nand_chip *chip = mtd->priv;
3208 struct nand_flash_dev *type;
3210 /* Get buswidth to select the correct functions */
3211 busw = chip->options & NAND_BUSWIDTH_16;
3212 /* Set the default functions */
3213 nand_set_defaults(chip, busw);
3215 /* Read the flash type */
3216 type = nand_get_flash_type(mtd, chip, busw,
3217 &nand_maf_id, &nand_dev_id, table);
3220 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3221 pr_warn("No NAND device found\n");
3222 chip->select_chip(mtd, -1);
3223 return PTR_ERR(type);
3226 /* Check for a chip array */
3227 for (i = 1; i < maxchips; i++) {
3228 chip->select_chip(mtd, i);
3229 /* See comment in nand_get_flash_type for reset */
3230 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3231 /* Send the command for reading device ID */
3232 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3233 /* Read manufacturer and device IDs */
3234 if (nand_maf_id != chip->read_byte(mtd) ||
3235 nand_dev_id != chip->read_byte(mtd))
3239 pr_info("%d NAND chips detected\n", i);
3241 /* Store the number of chips and calc total size for mtd */
3243 mtd->size = i * chip->chipsize;
3247 EXPORT_SYMBOL(nand_scan_ident);
3251 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3252 * @mtd: MTD device structure
3254 * This is the second phase of the normal nand_scan() function. It fills out
3255 * all the uninitialized function pointers with the defaults and scans for a
3256 * bad block table if appropriate.
3258 int nand_scan_tail(struct mtd_info *mtd)
3261 struct nand_chip *chip = mtd->priv;
3263 if (!(chip->options & NAND_OWN_BUFFERS))
3264 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3268 /* Set the internal oob buffer location, just after the page data */
3269 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3272 * If no default placement scheme is given, select an appropriate one.
3274 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3275 switch (mtd->oobsize) {
3277 chip->ecc.layout = &nand_oob_8;
3280 chip->ecc.layout = &nand_oob_16;
3283 chip->ecc.layout = &nand_oob_64;
3286 chip->ecc.layout = &nand_oob_128;
3289 pr_warn("No oob scheme defined for oobsize %d\n",
3295 if (!chip->write_page)
3296 chip->write_page = nand_write_page;
3299 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3300 * selected and we have 256 byte pagesize fallback to software ECC
3303 switch (chip->ecc.mode) {
3304 case NAND_ECC_HW_OOB_FIRST:
3305 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3306 if (!chip->ecc.calculate || !chip->ecc.correct ||
3308 pr_warn("No ECC functions supplied; "
3309 "hardware ECC not possible\n");
3312 if (!chip->ecc.read_page)
3313 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3316 /* Use standard hwecc read page function? */
3317 if (!chip->ecc.read_page)
3318 chip->ecc.read_page = nand_read_page_hwecc;
3319 if (!chip->ecc.write_page)
3320 chip->ecc.write_page = nand_write_page_hwecc;
3321 if (!chip->ecc.read_page_raw)
3322 chip->ecc.read_page_raw = nand_read_page_raw;
3323 if (!chip->ecc.write_page_raw)
3324 chip->ecc.write_page_raw = nand_write_page_raw;
3325 if (!chip->ecc.read_oob)
3326 chip->ecc.read_oob = nand_read_oob_std;
3327 if (!chip->ecc.write_oob)
3328 chip->ecc.write_oob = nand_write_oob_std;
3330 case NAND_ECC_HW_SYNDROME:
3331 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3332 !chip->ecc.hwctl) &&
3333 (!chip->ecc.read_page ||
3334 chip->ecc.read_page == nand_read_page_hwecc ||
3335 !chip->ecc.write_page ||
3336 chip->ecc.write_page == nand_write_page_hwecc)) {
3337 pr_warn("No ECC functions supplied; "
3338 "hardware ECC not possible\n");
3341 /* Use standard syndrome read/write page function? */
3342 if (!chip->ecc.read_page)
3343 chip->ecc.read_page = nand_read_page_syndrome;
3344 if (!chip->ecc.write_page)
3345 chip->ecc.write_page = nand_write_page_syndrome;
3346 if (!chip->ecc.read_page_raw)
3347 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3348 if (!chip->ecc.write_page_raw)
3349 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3350 if (!chip->ecc.read_oob)
3351 chip->ecc.read_oob = nand_read_oob_syndrome;
3352 if (!chip->ecc.write_oob)
3353 chip->ecc.write_oob = nand_write_oob_syndrome;
3355 if (mtd->writesize >= chip->ecc.size)
3357 pr_warn("%d byte HW ECC not possible on "
3358 "%d byte page size, fallback to SW ECC\n",
3359 chip->ecc.size, mtd->writesize);
3360 chip->ecc.mode = NAND_ECC_SOFT;
3363 chip->ecc.calculate = nand_calculate_ecc;
3364 chip->ecc.correct = nand_correct_data;
3365 chip->ecc.read_page = nand_read_page_swecc;
3366 chip->ecc.read_subpage = nand_read_subpage;
3367 chip->ecc.write_page = nand_write_page_swecc;
3368 chip->ecc.read_page_raw = nand_read_page_raw;
3369 chip->ecc.write_page_raw = nand_write_page_raw;
3370 chip->ecc.read_oob = nand_read_oob_std;
3371 chip->ecc.write_oob = nand_write_oob_std;
3372 if (!chip->ecc.size)
3373 chip->ecc.size = 256;
3374 chip->ecc.bytes = 3;
3377 case NAND_ECC_SOFT_BCH:
3378 if (!mtd_nand_has_bch()) {
3379 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3382 chip->ecc.calculate = nand_bch_calculate_ecc;
3383 chip->ecc.correct = nand_bch_correct_data;
3384 chip->ecc.read_page = nand_read_page_swecc;
3385 chip->ecc.read_subpage = nand_read_subpage;
3386 chip->ecc.write_page = nand_write_page_swecc;
3387 chip->ecc.read_page_raw = nand_read_page_raw;
3388 chip->ecc.write_page_raw = nand_write_page_raw;
3389 chip->ecc.read_oob = nand_read_oob_std;
3390 chip->ecc.write_oob = nand_write_oob_std;
3392 * Board driver should supply ecc.size and ecc.bytes values to
3393 * select how many bits are correctable; see nand_bch_init()
3394 * for details. Otherwise, default to 4 bits for large page
3397 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3398 chip->ecc.size = 512;
3399 chip->ecc.bytes = 7;
3401 chip->ecc.priv = nand_bch_init(mtd,
3405 if (!chip->ecc.priv) {
3406 pr_warn("BCH ECC initialization failed!\n");
3412 pr_warn("NAND_ECC_NONE selected by board driver. "
3413 "This is not recommended!\n");
3414 chip->ecc.read_page = nand_read_page_raw;
3415 chip->ecc.write_page = nand_write_page_raw;
3416 chip->ecc.read_oob = nand_read_oob_std;
3417 chip->ecc.read_page_raw = nand_read_page_raw;
3418 chip->ecc.write_page_raw = nand_write_page_raw;
3419 chip->ecc.write_oob = nand_write_oob_std;
3420 chip->ecc.size = mtd->writesize;
3421 chip->ecc.bytes = 0;
3425 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3429 /* For many systems, the standard OOB write also works for raw */
3430 if (!chip->ecc.read_oob_raw)
3431 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3432 if (!chip->ecc.write_oob_raw)
3433 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3436 * The number of bytes available for a client to place data into
3437 * the out of band area.
3439 chip->ecc.layout->oobavail = 0;
3440 for (i = 0; chip->ecc.layout->oobfree[i].length
3441 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3442 chip->ecc.layout->oobavail +=
3443 chip->ecc.layout->oobfree[i].length;
3444 mtd->oobavail = chip->ecc.layout->oobavail;
3447 * Set the number of read / write steps for one page depending on ECC
3450 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3451 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3452 pr_warn("Invalid ECC parameters\n");
3455 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3457 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3458 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3459 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3460 switch (chip->ecc.steps) {
3462 mtd->subpage_sft = 1;
3467 mtd->subpage_sft = 2;
3471 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3473 /* Initialize state */
3474 chip->state = FL_READY;
3476 /* De-select the device */
3477 chip->select_chip(mtd, -1);
3479 /* Invalidate the pagebuffer reference */
3482 /* Fill in remaining MTD driver data */
3483 mtd->type = MTD_NANDFLASH;
3484 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3486 mtd->_erase = nand_erase;
3488 mtd->_unpoint = NULL;
3489 mtd->_read = nand_read;
3490 mtd->_write = nand_write;
3491 mtd->_panic_write = panic_nand_write;
3492 mtd->_read_oob = nand_read_oob;
3493 mtd->_write_oob = nand_write_oob;
3494 mtd->_sync = nand_sync;
3496 mtd->_unlock = NULL;
3497 mtd->_suspend = nand_suspend;
3498 mtd->_resume = nand_resume;
3499 mtd->_block_isbad = nand_block_isbad;
3500 mtd->_block_markbad = nand_block_markbad;
3501 mtd->writebufsize = mtd->writesize;
3503 /* propagate ecc.layout to mtd_info */
3504 mtd->ecclayout = chip->ecc.layout;
3506 /* Check, if we should skip the bad block table scan */
3507 if (chip->options & NAND_SKIP_BBTSCAN)
3510 /* Build bad block table */
3511 return chip->scan_bbt(mtd);
3513 EXPORT_SYMBOL(nand_scan_tail);
3516 * is_module_text_address() isn't exported, and it's mostly a pointless
3517 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3518 * to call us from in-kernel code if the core NAND support is modular.
3521 #define caller_is_module() (1)
3523 #define caller_is_module() \
3524 is_module_text_address((unsigned long)__builtin_return_address(0))
3528 * nand_scan - [NAND Interface] Scan for the NAND device
3529 * @mtd: MTD device structure
3530 * @maxchips: number of chips to scan for
3532 * This fills out all the uninitialized function pointers with the defaults.
3533 * The flash ID is read and the mtd/chip structures are filled with the
3534 * appropriate values. The mtd->owner field must be set to the module of the
3537 int nand_scan(struct mtd_info *mtd, int maxchips)
3541 /* Many callers got this wrong, so check for it for a while... */
3542 if (!mtd->owner && caller_is_module()) {
3543 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3547 ret = nand_scan_ident(mtd, maxchips, NULL);
3549 ret = nand_scan_tail(mtd);
3552 EXPORT_SYMBOL(nand_scan);
3555 * nand_release - [NAND Interface] Free resources held by the NAND device
3556 * @mtd: MTD device structure
3558 void nand_release(struct mtd_info *mtd)
3560 struct nand_chip *chip = mtd->priv;
3562 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3563 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3565 mtd_device_unregister(mtd);
3567 /* Free bad block table memory */
3569 if (!(chip->options & NAND_OWN_BUFFERS))
3570 kfree(chip->buffers);
3572 /* Free bad block descriptor memory */
3573 if (chip->badblock_pattern && chip->badblock_pattern->options
3574 & NAND_BBT_DYNAMICSTRUCT)
3575 kfree(chip->badblock_pattern);
3577 EXPORT_SYMBOL_GPL(nand_release);
3579 static int __init nand_base_init(void)
3581 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3585 static void __exit nand_base_exit(void)
3587 led_trigger_unregister_simple(nand_led_trigger);
3590 module_init(nand_base_init);
3591 module_exit(nand_base_exit);
3593 MODULE_LICENSE("GPL");
3594 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3595 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3596 MODULE_DESCRIPTION("Generic NAND flash driver code");