5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
63 static struct nand_ecclayout nand_oob_16 = {
65 .eccpos = {0, 1, 2, 3, 6, 7},
71 static struct nand_ecclayout nand_oob_64 = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
82 static struct nand_ecclayout nand_oob_128 = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
96 static int nand_get_device(struct mtd_info *mtd, int new_state);
98 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
99 struct mtd_oob_ops *ops);
102 * For devices which display every fart in the system on a separate LED. Is
103 * compiled away when LED support is disabled.
105 DEFINE_LED_TRIGGER(nand_led_trigger);
107 static int check_offs_len(struct mtd_info *mtd,
108 loff_t ofs, uint64_t len)
110 struct nand_chip *chip = mtd->priv;
113 /* Start address must align on block boundary */
114 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
115 pr_debug("%s: unaligned address\n", __func__);
119 /* Length must align on block boundary */
120 if (len & ((1 << chip->phys_erase_shift) - 1)) {
121 pr_debug("%s: length not block aligned\n", __func__);
129 * nand_release_device - [GENERIC] release chip
130 * @mtd: MTD device structure
132 * Release chip lock and wake up anyone waiting on the device.
134 static void nand_release_device(struct mtd_info *mtd)
136 struct nand_chip *chip = mtd->priv;
138 /* Release the controller and the chip */
139 spin_lock(&chip->controller->lock);
140 chip->controller->active = NULL;
141 chip->state = FL_READY;
142 wake_up(&chip->controller->wq);
143 spin_unlock(&chip->controller->lock);
147 * nand_read_byte - [DEFAULT] read one byte from the chip
148 * @mtd: MTD device structure
150 * Default read function for 8bit buswidth
152 static uint8_t nand_read_byte(struct mtd_info *mtd)
154 struct nand_chip *chip = mtd->priv;
155 return readb(chip->IO_ADDR_R);
159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
160 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
161 * @mtd: MTD device structure
163 * Default read function for 16bit buswidth with endianness conversion.
166 static uint8_t nand_read_byte16(struct mtd_info *mtd)
168 struct nand_chip *chip = mtd->priv;
169 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
173 * nand_read_word - [DEFAULT] read one word from the chip
174 * @mtd: MTD device structure
176 * Default read function for 16bit buswidth without endianness conversion.
178 static u16 nand_read_word(struct mtd_info *mtd)
180 struct nand_chip *chip = mtd->priv;
181 return readw(chip->IO_ADDR_R);
185 * nand_select_chip - [DEFAULT] control CE line
186 * @mtd: MTD device structure
187 * @chipnr: chipnumber to select, -1 for deselect
189 * Default select function for 1 chip devices.
191 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
193 struct nand_chip *chip = mtd->priv;
197 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
208 * nand_write_buf - [DEFAULT] write buffer to chip
209 * @mtd: MTD device structure
211 * @len: number of bytes to write
213 * Default write function for 8bit buswidth.
215 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
218 struct nand_chip *chip = mtd->priv;
220 for (i = 0; i < len; i++)
221 writeb(buf[i], chip->IO_ADDR_W);
225 * nand_read_buf - [DEFAULT] read chip data into buffer
226 * @mtd: MTD device structure
227 * @buf: buffer to store date
228 * @len: number of bytes to read
230 * Default read function for 8bit buswidth.
232 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
235 struct nand_chip *chip = mtd->priv;
237 for (i = 0; i < len; i++)
238 buf[i] = readb(chip->IO_ADDR_R);
242 * nand_write_buf16 - [DEFAULT] write buffer to chip
243 * @mtd: MTD device structure
245 * @len: number of bytes to write
247 * Default write function for 16bit buswidth.
249 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
252 struct nand_chip *chip = mtd->priv;
253 u16 *p = (u16 *) buf;
256 for (i = 0; i < len; i++)
257 writew(p[i], chip->IO_ADDR_W);
262 * nand_read_buf16 - [DEFAULT] read chip data into buffer
263 * @mtd: MTD device structure
264 * @buf: buffer to store date
265 * @len: number of bytes to read
267 * Default read function for 16bit buswidth.
269 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
272 struct nand_chip *chip = mtd->priv;
273 u16 *p = (u16 *) buf;
276 for (i = 0; i < len; i++)
277 p[i] = readw(chip->IO_ADDR_R);
281 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
282 * @mtd: MTD device structure
283 * @ofs: offset from device start
284 * @getchip: 0, if the chip is already selected
286 * Check, if the block is bad.
288 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
290 int page, chipnr, res = 0, i = 0;
291 struct nand_chip *chip = mtd->priv;
294 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
295 ofs += mtd->erasesize - mtd->writesize;
297 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
300 chipnr = (int)(ofs >> chip->chip_shift);
302 nand_get_device(mtd, FL_READING);
304 /* Select the NAND device */
305 chip->select_chip(mtd, chipnr);
309 if (chip->options & NAND_BUSWIDTH_16) {
310 chip->cmdfunc(mtd, NAND_CMD_READOOB,
311 chip->badblockpos & 0xFE, page);
312 bad = cpu_to_le16(chip->read_word(mtd));
313 if (chip->badblockpos & 0x1)
318 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
320 bad = chip->read_byte(mtd);
323 if (likely(chip->badblockbits == 8))
326 res = hweight8(bad) < chip->badblockbits;
327 ofs += mtd->writesize;
328 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
330 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
333 chip->select_chip(mtd, -1);
334 nand_release_device(mtd);
341 * nand_default_block_markbad - [DEFAULT] mark a block bad
342 * @mtd: MTD device structure
343 * @ofs: offset from device start
345 * This is the default implementation, which can be overridden by a hardware
346 * specific driver. We try operations in the following order, according to our
347 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
348 * (1) erase the affected block, to allow OOB marker to be written cleanly
349 * (2) update in-memory BBT
350 * (3) write bad block marker to OOB area of affected block
351 * (4) update flash-based BBT
352 * Note that we retain the first error encountered in (3) or (4), finish the
353 * procedures, and dump the error in the end.
355 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
357 struct nand_chip *chip = mtd->priv;
358 uint8_t buf[2] = { 0, 0 };
359 int block, res, ret = 0, i = 0;
360 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
363 struct erase_info einfo;
365 /* Attempt erase before marking OOB */
366 memset(&einfo, 0, sizeof(einfo));
369 einfo.len = 1 << chip->phys_erase_shift;
370 nand_erase_nand(mtd, &einfo, 0);
373 /* Get block number */
374 block = (int)(ofs >> chip->bbt_erase_shift);
375 /* Mark block bad in memory-based BBT */
377 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
379 /* Write bad block marker to OOB */
381 struct mtd_oob_ops ops;
384 nand_get_device(mtd, FL_WRITING);
388 ops.ooboffs = chip->badblockpos;
389 if (chip->options & NAND_BUSWIDTH_16) {
390 ops.ooboffs &= ~0x01;
391 ops.len = ops.ooblen = 2;
393 ops.len = ops.ooblen = 1;
395 ops.mode = MTD_OPS_PLACE_OOB;
397 /* Write to first/last page(s) if necessary */
398 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
399 wr_ofs += mtd->erasesize - mtd->writesize;
401 res = nand_do_write_oob(mtd, wr_ofs, &ops);
406 wr_ofs += mtd->writesize;
407 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
409 nand_release_device(mtd);
412 /* Update flash-based bad block table */
413 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
414 res = nand_update_bbt(mtd, ofs);
420 mtd->ecc_stats.badblocks++;
426 * nand_check_wp - [GENERIC] check if the chip is write protected
427 * @mtd: MTD device structure
429 * Check, if the device is write protected. The function expects, that the
430 * device is already selected.
432 static int nand_check_wp(struct mtd_info *mtd)
434 struct nand_chip *chip = mtd->priv;
436 /* Broken xD cards report WP despite being writable */
437 if (chip->options & NAND_BROKEN_XD)
440 /* Check the WP bit */
441 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
442 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
446 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
447 * @mtd: MTD device structure
448 * @ofs: offset from device start
449 * @getchip: 0, if the chip is already selected
450 * @allowbbt: 1, if its allowed to access the bbt area
452 * Check, if the block is bad. Either by reading the bad block table or
453 * calling of the scan function.
455 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
458 struct nand_chip *chip = mtd->priv;
461 return chip->block_bad(mtd, ofs, getchip);
463 /* Return info from the table */
464 return nand_isbad_bbt(mtd, ofs, allowbbt);
468 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
469 * @mtd: MTD device structure
472 * Helper function for nand_wait_ready used when needing to wait in interrupt
475 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
477 struct nand_chip *chip = mtd->priv;
480 /* Wait for the device to get ready */
481 for (i = 0; i < timeo; i++) {
482 if (chip->dev_ready(mtd))
484 touch_softlockup_watchdog();
489 /* Wait for the ready pin, after a command. The timeout is caught later. */
490 void nand_wait_ready(struct mtd_info *mtd)
492 struct nand_chip *chip = mtd->priv;
493 unsigned long timeo = jiffies + msecs_to_jiffies(20);
496 if (in_interrupt() || oops_in_progress)
497 return panic_nand_wait_ready(mtd, 400);
499 led_trigger_event(nand_led_trigger, LED_FULL);
500 /* Wait until command is processed or timeout occurs */
502 if (chip->dev_ready(mtd))
504 touch_softlockup_watchdog();
505 } while (time_before(jiffies, timeo));
506 led_trigger_event(nand_led_trigger, LED_OFF);
508 EXPORT_SYMBOL_GPL(nand_wait_ready);
511 * nand_command - [DEFAULT] Send command to NAND device
512 * @mtd: MTD device structure
513 * @command: the command to be sent
514 * @column: the column address for this command, -1 if none
515 * @page_addr: the page address for this command, -1 if none
517 * Send command to NAND device. This function is used for small page devices
518 * (256/512 Bytes per page).
520 static void nand_command(struct mtd_info *mtd, unsigned int command,
521 int column, int page_addr)
523 register struct nand_chip *chip = mtd->priv;
524 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
526 /* Write out the command to the device */
527 if (command == NAND_CMD_SEQIN) {
530 if (column >= mtd->writesize) {
532 column -= mtd->writesize;
533 readcmd = NAND_CMD_READOOB;
534 } else if (column < 256) {
535 /* First 256 bytes --> READ0 */
536 readcmd = NAND_CMD_READ0;
539 readcmd = NAND_CMD_READ1;
541 chip->cmd_ctrl(mtd, readcmd, ctrl);
542 ctrl &= ~NAND_CTRL_CHANGE;
544 chip->cmd_ctrl(mtd, command, ctrl);
546 /* Address cycle, when necessary */
547 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
548 /* Serially input address */
550 /* Adjust columns for 16 bit buswidth */
551 if (chip->options & NAND_BUSWIDTH_16)
553 chip->cmd_ctrl(mtd, column, ctrl);
554 ctrl &= ~NAND_CTRL_CHANGE;
556 if (page_addr != -1) {
557 chip->cmd_ctrl(mtd, page_addr, ctrl);
558 ctrl &= ~NAND_CTRL_CHANGE;
559 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
560 /* One more address cycle for devices > 32MiB */
561 if (chip->chipsize > (32 << 20))
562 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
564 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
567 * Program and erase have their own busy handlers status and sequential
572 case NAND_CMD_PAGEPROG:
573 case NAND_CMD_ERASE1:
574 case NAND_CMD_ERASE2:
576 case NAND_CMD_STATUS:
582 udelay(chip->chip_delay);
583 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
584 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
586 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
587 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
591 /* This applies to read commands */
594 * If we don't have access to the busy pin, we apply the given
597 if (!chip->dev_ready) {
598 udelay(chip->chip_delay);
603 * Apply this short delay always to ensure that we do wait tWB in
604 * any case on any machine.
608 nand_wait_ready(mtd);
612 * nand_command_lp - [DEFAULT] Send command to NAND large page device
613 * @mtd: MTD device structure
614 * @command: the command to be sent
615 * @column: the column address for this command, -1 if none
616 * @page_addr: the page address for this command, -1 if none
618 * Send command to NAND device. This is the version for the new large page
619 * devices. We don't have the separate regions as we have in the small page
620 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
622 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
623 int column, int page_addr)
625 register struct nand_chip *chip = mtd->priv;
627 /* Emulate NAND_CMD_READOOB */
628 if (command == NAND_CMD_READOOB) {
629 column += mtd->writesize;
630 command = NAND_CMD_READ0;
633 /* Command latch cycle */
634 chip->cmd_ctrl(mtd, command & 0xff,
635 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
637 if (column != -1 || page_addr != -1) {
638 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
640 /* Serially input address */
642 /* Adjust columns for 16 bit buswidth */
643 if (chip->options & NAND_BUSWIDTH_16)
645 chip->cmd_ctrl(mtd, column, ctrl);
646 ctrl &= ~NAND_CTRL_CHANGE;
647 chip->cmd_ctrl(mtd, column >> 8, ctrl);
649 if (page_addr != -1) {
650 chip->cmd_ctrl(mtd, page_addr, ctrl);
651 chip->cmd_ctrl(mtd, page_addr >> 8,
652 NAND_NCE | NAND_ALE);
653 /* One more address cycle for devices > 128MiB */
654 if (chip->chipsize > (128 << 20))
655 chip->cmd_ctrl(mtd, page_addr >> 16,
656 NAND_NCE | NAND_ALE);
659 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
662 * Program and erase have their own busy handlers status, sequential
663 * in, and deplete1 need no delay.
667 case NAND_CMD_CACHEDPROG:
668 case NAND_CMD_PAGEPROG:
669 case NAND_CMD_ERASE1:
670 case NAND_CMD_ERASE2:
673 case NAND_CMD_STATUS:
674 case NAND_CMD_DEPLETE1:
677 case NAND_CMD_STATUS_ERROR:
678 case NAND_CMD_STATUS_ERROR0:
679 case NAND_CMD_STATUS_ERROR1:
680 case NAND_CMD_STATUS_ERROR2:
681 case NAND_CMD_STATUS_ERROR3:
682 /* Read error status commands require only a short delay */
683 udelay(chip->chip_delay);
689 udelay(chip->chip_delay);
690 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
691 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
692 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
693 NAND_NCE | NAND_CTRL_CHANGE);
694 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
698 case NAND_CMD_RNDOUT:
699 /* No ready / busy check necessary */
700 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
701 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
702 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
703 NAND_NCE | NAND_CTRL_CHANGE);
707 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
708 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
709 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
710 NAND_NCE | NAND_CTRL_CHANGE);
712 /* This applies to read commands */
715 * If we don't have access to the busy pin, we apply the given
718 if (!chip->dev_ready) {
719 udelay(chip->chip_delay);
725 * Apply this short delay always to ensure that we do wait tWB in
726 * any case on any machine.
730 nand_wait_ready(mtd);
734 * panic_nand_get_device - [GENERIC] Get chip for selected access
735 * @chip: the nand chip descriptor
736 * @mtd: MTD device structure
737 * @new_state: the state which is requested
739 * Used when in panic, no locks are taken.
741 static void panic_nand_get_device(struct nand_chip *chip,
742 struct mtd_info *mtd, int new_state)
744 /* Hardware controller shared among independent devices */
745 chip->controller->active = chip;
746 chip->state = new_state;
750 * nand_get_device - [GENERIC] Get chip for selected access
751 * @mtd: MTD device structure
752 * @new_state: the state which is requested
754 * Get the device and lock it for exclusive access
757 nand_get_device(struct mtd_info *mtd, int new_state)
759 struct nand_chip *chip = mtd->priv;
760 spinlock_t *lock = &chip->controller->lock;
761 wait_queue_head_t *wq = &chip->controller->wq;
762 DECLARE_WAITQUEUE(wait, current);
766 /* Hardware controller shared among independent devices */
767 if (!chip->controller->active)
768 chip->controller->active = chip;
770 if (chip->controller->active == chip && chip->state == FL_READY) {
771 chip->state = new_state;
775 if (new_state == FL_PM_SUSPENDED) {
776 if (chip->controller->active->state == FL_PM_SUSPENDED) {
777 chip->state = FL_PM_SUSPENDED;
782 set_current_state(TASK_UNINTERRUPTIBLE);
783 add_wait_queue(wq, &wait);
786 remove_wait_queue(wq, &wait);
791 * panic_nand_wait - [GENERIC] wait until the command is done
792 * @mtd: MTD device structure
793 * @chip: NAND chip structure
796 * Wait for command done. This is a helper function for nand_wait used when
797 * we are in interrupt context. May happen when in panic and trying to write
798 * an oops through mtdoops.
800 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
804 for (i = 0; i < timeo; i++) {
805 if (chip->dev_ready) {
806 if (chip->dev_ready(mtd))
809 if (chip->read_byte(mtd) & NAND_STATUS_READY)
817 * nand_wait - [DEFAULT] wait until the command is done
818 * @mtd: MTD device structure
819 * @chip: NAND chip structure
821 * Wait for command done. This applies to erase and program only. Erase can
822 * take up to 400ms and program up to 20ms according to general NAND and
825 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
828 unsigned long timeo = jiffies;
829 int status, state = chip->state;
831 if (state == FL_ERASING)
832 timeo += (HZ * 400) / 1000;
834 timeo += (HZ * 20) / 1000;
836 led_trigger_event(nand_led_trigger, LED_FULL);
839 * Apply this short delay always to ensure that we do wait tWB in any
840 * case on any machine.
844 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
845 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
847 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
849 if (in_interrupt() || oops_in_progress)
850 panic_nand_wait(mtd, chip, timeo);
852 while (time_before(jiffies, timeo)) {
853 if (chip->dev_ready) {
854 if (chip->dev_ready(mtd))
857 if (chip->read_byte(mtd) & NAND_STATUS_READY)
863 led_trigger_event(nand_led_trigger, LED_OFF);
865 status = (int)chip->read_byte(mtd);
866 /* This can happen if in case of timeout or buggy dev_ready */
867 WARN_ON(!(status & NAND_STATUS_READY));
872 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
874 * @ofs: offset to start unlock from
875 * @len: length to unlock
876 * @invert: when = 0, unlock the range of blocks within the lower and
877 * upper boundary address
878 * when = 1, unlock the range of blocks outside the boundaries
879 * of the lower and upper boundary address
881 * Returs unlock status.
883 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
884 uint64_t len, int invert)
888 struct nand_chip *chip = mtd->priv;
890 /* Submit address of first page to unlock */
891 page = ofs >> chip->page_shift;
892 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
894 /* Submit address of last page to unlock */
895 page = (ofs + len) >> chip->page_shift;
896 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
897 (page | invert) & chip->pagemask);
899 /* Call wait ready function */
900 status = chip->waitfunc(mtd, chip);
901 /* See if device thinks it succeeded */
902 if (status & NAND_STATUS_FAIL) {
903 pr_debug("%s: error status = 0x%08x\n",
912 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
914 * @ofs: offset to start unlock from
915 * @len: length to unlock
917 * Returns unlock status.
919 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
923 struct nand_chip *chip = mtd->priv;
925 pr_debug("%s: start = 0x%012llx, len = %llu\n",
926 __func__, (unsigned long long)ofs, len);
928 if (check_offs_len(mtd, ofs, len))
931 /* Align to last block address if size addresses end of the device */
932 if (ofs + len == mtd->size)
933 len -= mtd->erasesize;
935 nand_get_device(mtd, FL_UNLOCKING);
937 /* Shift to get chip number */
938 chipnr = ofs >> chip->chip_shift;
940 chip->select_chip(mtd, chipnr);
942 /* Check, if it is write protected */
943 if (nand_check_wp(mtd)) {
944 pr_debug("%s: device is write protected!\n",
950 ret = __nand_unlock(mtd, ofs, len, 0);
953 chip->select_chip(mtd, -1);
954 nand_release_device(mtd);
958 EXPORT_SYMBOL(nand_unlock);
961 * nand_lock - [REPLACEABLE] locks all blocks present in the device
963 * @ofs: offset to start unlock from
964 * @len: length to unlock
966 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
967 * have this feature, but it allows only to lock all blocks, not for specified
968 * range for block. Implementing 'lock' feature by making use of 'unlock', for
971 * Returns lock status.
973 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
976 int chipnr, status, page;
977 struct nand_chip *chip = mtd->priv;
979 pr_debug("%s: start = 0x%012llx, len = %llu\n",
980 __func__, (unsigned long long)ofs, len);
982 if (check_offs_len(mtd, ofs, len))
985 nand_get_device(mtd, FL_LOCKING);
987 /* Shift to get chip number */
988 chipnr = ofs >> chip->chip_shift;
990 chip->select_chip(mtd, chipnr);
992 /* Check, if it is write protected */
993 if (nand_check_wp(mtd)) {
994 pr_debug("%s: device is write protected!\n",
996 status = MTD_ERASE_FAILED;
1001 /* Submit address of first page to lock */
1002 page = ofs >> chip->page_shift;
1003 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1005 /* Call wait ready function */
1006 status = chip->waitfunc(mtd, chip);
1007 /* See if device thinks it succeeded */
1008 if (status & NAND_STATUS_FAIL) {
1009 pr_debug("%s: error status = 0x%08x\n",
1015 ret = __nand_unlock(mtd, ofs, len, 0x1);
1018 chip->select_chip(mtd, -1);
1019 nand_release_device(mtd);
1023 EXPORT_SYMBOL(nand_lock);
1026 * nand_read_page_raw - [INTERN] read raw page data without ecc
1027 * @mtd: mtd info structure
1028 * @chip: nand chip info structure
1029 * @buf: buffer to store read data
1030 * @oob_required: caller requires OOB data read to chip->oob_poi
1031 * @page: page number to read
1033 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1035 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1036 uint8_t *buf, int oob_required, int page)
1038 chip->read_buf(mtd, buf, mtd->writesize);
1040 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1045 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1046 * @mtd: mtd info structure
1047 * @chip: nand chip info structure
1048 * @buf: buffer to store read data
1049 * @oob_required: caller requires OOB data read to chip->oob_poi
1050 * @page: page number to read
1052 * We need a special oob layout and handling even when OOB isn't used.
1054 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1055 struct nand_chip *chip, uint8_t *buf,
1056 int oob_required, int page)
1058 int eccsize = chip->ecc.size;
1059 int eccbytes = chip->ecc.bytes;
1060 uint8_t *oob = chip->oob_poi;
1063 for (steps = chip->ecc.steps; steps > 0; steps--) {
1064 chip->read_buf(mtd, buf, eccsize);
1067 if (chip->ecc.prepad) {
1068 chip->read_buf(mtd, oob, chip->ecc.prepad);
1069 oob += chip->ecc.prepad;
1072 chip->read_buf(mtd, oob, eccbytes);
1075 if (chip->ecc.postpad) {
1076 chip->read_buf(mtd, oob, chip->ecc.postpad);
1077 oob += chip->ecc.postpad;
1081 size = mtd->oobsize - (oob - chip->oob_poi);
1083 chip->read_buf(mtd, oob, size);
1089 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1090 * @mtd: mtd info structure
1091 * @chip: nand chip info structure
1092 * @buf: buffer to store read data
1093 * @oob_required: caller requires OOB data read to chip->oob_poi
1094 * @page: page number to read
1096 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1097 uint8_t *buf, int oob_required, int page)
1099 int i, eccsize = chip->ecc.size;
1100 int eccbytes = chip->ecc.bytes;
1101 int eccsteps = chip->ecc.steps;
1103 uint8_t *ecc_calc = chip->buffers->ecccalc;
1104 uint8_t *ecc_code = chip->buffers->ecccode;
1105 uint32_t *eccpos = chip->ecc.layout->eccpos;
1106 unsigned int max_bitflips = 0;
1108 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1110 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1111 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1113 for (i = 0; i < chip->ecc.total; i++)
1114 ecc_code[i] = chip->oob_poi[eccpos[i]];
1116 eccsteps = chip->ecc.steps;
1119 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1122 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1124 mtd->ecc_stats.failed++;
1126 mtd->ecc_stats.corrected += stat;
1127 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1130 return max_bitflips;
1134 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1135 * @mtd: mtd info structure
1136 * @chip: nand chip info structure
1137 * @data_offs: offset of requested data within the page
1138 * @readlen: data length
1139 * @bufpoi: buffer to store read data
1141 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1142 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1144 int start_step, end_step, num_steps;
1145 uint32_t *eccpos = chip->ecc.layout->eccpos;
1147 int data_col_addr, i, gaps = 0;
1148 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1149 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1151 unsigned int max_bitflips = 0;
1153 /* Column address within the page aligned to ECC size (256bytes) */
1154 start_step = data_offs / chip->ecc.size;
1155 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1156 num_steps = end_step - start_step + 1;
1158 /* Data size aligned to ECC ecc.size */
1159 datafrag_len = num_steps * chip->ecc.size;
1160 eccfrag_len = num_steps * chip->ecc.bytes;
1162 data_col_addr = start_step * chip->ecc.size;
1163 /* If we read not a page aligned data */
1164 if (data_col_addr != 0)
1165 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1167 p = bufpoi + data_col_addr;
1168 chip->read_buf(mtd, p, datafrag_len);
1171 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1172 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1175 * The performance is faster if we position offsets according to
1176 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1178 for (i = 0; i < eccfrag_len - 1; i++) {
1179 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1180 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1186 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1187 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1190 * Send the command to read the particular ECC bytes take care
1191 * about buswidth alignment in read_buf.
1193 index = start_step * chip->ecc.bytes;
1195 aligned_pos = eccpos[index] & ~(busw - 1);
1196 aligned_len = eccfrag_len;
1197 if (eccpos[index] & (busw - 1))
1199 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1202 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1203 mtd->writesize + aligned_pos, -1);
1204 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1207 for (i = 0; i < eccfrag_len; i++)
1208 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1210 p = bufpoi + data_col_addr;
1211 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1214 stat = chip->ecc.correct(mtd, p,
1215 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1217 mtd->ecc_stats.failed++;
1219 mtd->ecc_stats.corrected += stat;
1220 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1223 return max_bitflips;
1227 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1228 * @mtd: mtd info structure
1229 * @chip: nand chip info structure
1230 * @buf: buffer to store read data
1231 * @oob_required: caller requires OOB data read to chip->oob_poi
1232 * @page: page number to read
1234 * Not for syndrome calculating ECC controllers which need a special oob layout.
1236 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1237 uint8_t *buf, int oob_required, int page)
1239 int i, eccsize = chip->ecc.size;
1240 int eccbytes = chip->ecc.bytes;
1241 int eccsteps = chip->ecc.steps;
1243 uint8_t *ecc_calc = chip->buffers->ecccalc;
1244 uint8_t *ecc_code = chip->buffers->ecccode;
1245 uint32_t *eccpos = chip->ecc.layout->eccpos;
1246 unsigned int max_bitflips = 0;
1248 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1249 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1250 chip->read_buf(mtd, p, eccsize);
1251 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1253 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1255 for (i = 0; i < chip->ecc.total; i++)
1256 ecc_code[i] = chip->oob_poi[eccpos[i]];
1258 eccsteps = chip->ecc.steps;
1261 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1264 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1266 mtd->ecc_stats.failed++;
1268 mtd->ecc_stats.corrected += stat;
1269 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1272 return max_bitflips;
1276 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1277 * @mtd: mtd info structure
1278 * @chip: nand chip info structure
1279 * @buf: buffer to store read data
1280 * @oob_required: caller requires OOB data read to chip->oob_poi
1281 * @page: page number to read
1283 * Hardware ECC for large page chips, require OOB to be read first. For this
1284 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1285 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1286 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1287 * the data area, by overwriting the NAND manufacturer bad block markings.
1289 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1290 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1292 int i, eccsize = chip->ecc.size;
1293 int eccbytes = chip->ecc.bytes;
1294 int eccsteps = chip->ecc.steps;
1296 uint8_t *ecc_code = chip->buffers->ecccode;
1297 uint32_t *eccpos = chip->ecc.layout->eccpos;
1298 uint8_t *ecc_calc = chip->buffers->ecccalc;
1299 unsigned int max_bitflips = 0;
1301 /* Read the OOB area first */
1302 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1303 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1304 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1306 for (i = 0; i < chip->ecc.total; i++)
1307 ecc_code[i] = chip->oob_poi[eccpos[i]];
1309 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1312 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1313 chip->read_buf(mtd, p, eccsize);
1314 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1316 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1318 mtd->ecc_stats.failed++;
1320 mtd->ecc_stats.corrected += stat;
1321 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1324 return max_bitflips;
1328 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1329 * @mtd: mtd info structure
1330 * @chip: nand chip info structure
1331 * @buf: buffer to store read data
1332 * @oob_required: caller requires OOB data read to chip->oob_poi
1333 * @page: page number to read
1335 * The hw generator calculates the error syndrome automatically. Therefore we
1336 * need a special oob layout and handling.
1338 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1339 uint8_t *buf, int oob_required, int page)
1341 int i, eccsize = chip->ecc.size;
1342 int eccbytes = chip->ecc.bytes;
1343 int eccsteps = chip->ecc.steps;
1345 uint8_t *oob = chip->oob_poi;
1346 unsigned int max_bitflips = 0;
1348 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1351 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1352 chip->read_buf(mtd, p, eccsize);
1354 if (chip->ecc.prepad) {
1355 chip->read_buf(mtd, oob, chip->ecc.prepad);
1356 oob += chip->ecc.prepad;
1359 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1360 chip->read_buf(mtd, oob, eccbytes);
1361 stat = chip->ecc.correct(mtd, p, oob, NULL);
1364 mtd->ecc_stats.failed++;
1366 mtd->ecc_stats.corrected += stat;
1367 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1372 if (chip->ecc.postpad) {
1373 chip->read_buf(mtd, oob, chip->ecc.postpad);
1374 oob += chip->ecc.postpad;
1378 /* Calculate remaining oob bytes */
1379 i = mtd->oobsize - (oob - chip->oob_poi);
1381 chip->read_buf(mtd, oob, i);
1383 return max_bitflips;
1387 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1388 * @chip: nand chip structure
1389 * @oob: oob destination address
1390 * @ops: oob ops structure
1391 * @len: size of oob to transfer
1393 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1394 struct mtd_oob_ops *ops, size_t len)
1396 switch (ops->mode) {
1398 case MTD_OPS_PLACE_OOB:
1400 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1403 case MTD_OPS_AUTO_OOB: {
1404 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1405 uint32_t boffs = 0, roffs = ops->ooboffs;
1408 for (; free->length && len; free++, len -= bytes) {
1409 /* Read request not from offset 0? */
1410 if (unlikely(roffs)) {
1411 if (roffs >= free->length) {
1412 roffs -= free->length;
1415 boffs = free->offset + roffs;
1416 bytes = min_t(size_t, len,
1417 (free->length - roffs));
1420 bytes = min_t(size_t, len, free->length);
1421 boffs = free->offset;
1423 memcpy(oob, chip->oob_poi + boffs, bytes);
1435 * nand_do_read_ops - [INTERN] Read data with ECC
1436 * @mtd: MTD device structure
1437 * @from: offset to read from
1438 * @ops: oob ops structure
1440 * Internal function. Called with chip held.
1442 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1443 struct mtd_oob_ops *ops)
1445 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1446 struct nand_chip *chip = mtd->priv;
1447 struct mtd_ecc_stats stats;
1449 uint32_t readlen = ops->len;
1450 uint32_t oobreadlen = ops->ooblen;
1451 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1452 mtd->oobavail : mtd->oobsize;
1454 uint8_t *bufpoi, *oob, *buf;
1455 unsigned int max_bitflips = 0;
1457 stats = mtd->ecc_stats;
1459 chipnr = (int)(from >> chip->chip_shift);
1460 chip->select_chip(mtd, chipnr);
1462 realpage = (int)(from >> chip->page_shift);
1463 page = realpage & chip->pagemask;
1465 col = (int)(from & (mtd->writesize - 1));
1469 oob_required = oob ? 1 : 0;
1472 bytes = min(mtd->writesize - col, readlen);
1473 aligned = (bytes == mtd->writesize);
1475 /* Is the current page in the buffer? */
1476 if (realpage != chip->pagebuf || oob) {
1477 bufpoi = aligned ? buf : chip->buffers->databuf;
1479 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1482 * Now read the page into the buffer. Absent an error,
1483 * the read methods return max bitflips per ecc step.
1485 if (unlikely(ops->mode == MTD_OPS_RAW))
1486 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1489 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1491 ret = chip->ecc.read_subpage(mtd, chip,
1492 col, bytes, bufpoi);
1494 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1495 oob_required, page);
1498 /* Invalidate page cache */
1503 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1505 /* Transfer not aligned data */
1507 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1508 !(mtd->ecc_stats.failed - stats.failed) &&
1509 (ops->mode != MTD_OPS_RAW)) {
1510 chip->pagebuf = realpage;
1511 chip->pagebuf_bitflips = ret;
1513 /* Invalidate page cache */
1516 memcpy(buf, chip->buffers->databuf + col, bytes);
1521 if (unlikely(oob)) {
1522 int toread = min(oobreadlen, max_oobsize);
1525 oob = nand_transfer_oob(chip,
1527 oobreadlen -= toread;
1531 memcpy(buf, chip->buffers->databuf + col, bytes);
1533 max_bitflips = max_t(unsigned int, max_bitflips,
1534 chip->pagebuf_bitflips);
1542 /* For subsequent reads align to page boundary */
1544 /* Increment page address */
1547 page = realpage & chip->pagemask;
1548 /* Check, if we cross a chip boundary */
1551 chip->select_chip(mtd, -1);
1552 chip->select_chip(mtd, chipnr);
1555 chip->select_chip(mtd, -1);
1557 ops->retlen = ops->len - (size_t) readlen;
1559 ops->oobretlen = ops->ooblen - oobreadlen;
1564 if (mtd->ecc_stats.failed - stats.failed)
1567 return max_bitflips;
1571 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1572 * @mtd: MTD device structure
1573 * @from: offset to read from
1574 * @len: number of bytes to read
1575 * @retlen: pointer to variable to store the number of read bytes
1576 * @buf: the databuffer to put data
1578 * Get hold of the chip and call nand_do_read.
1580 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1581 size_t *retlen, uint8_t *buf)
1583 struct mtd_oob_ops ops;
1586 nand_get_device(mtd, FL_READING);
1590 ops.mode = MTD_OPS_PLACE_OOB;
1591 ret = nand_do_read_ops(mtd, from, &ops);
1592 *retlen = ops.retlen;
1593 nand_release_device(mtd);
1598 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1599 * @mtd: mtd info structure
1600 * @chip: nand chip info structure
1601 * @page: page number to read
1603 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1606 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1607 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1612 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1614 * @mtd: mtd info structure
1615 * @chip: nand chip info structure
1616 * @page: page number to read
1618 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1621 uint8_t *buf = chip->oob_poi;
1622 int length = mtd->oobsize;
1623 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1624 int eccsize = chip->ecc.size;
1625 uint8_t *bufpoi = buf;
1626 int i, toread, sndrnd = 0, pos;
1628 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1629 for (i = 0; i < chip->ecc.steps; i++) {
1631 pos = eccsize + i * (eccsize + chunk);
1632 if (mtd->writesize > 512)
1633 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1635 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1638 toread = min_t(int, length, chunk);
1639 chip->read_buf(mtd, bufpoi, toread);
1644 chip->read_buf(mtd, bufpoi, length);
1650 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1651 * @mtd: mtd info structure
1652 * @chip: nand chip info structure
1653 * @page: page number to write
1655 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1659 const uint8_t *buf = chip->oob_poi;
1660 int length = mtd->oobsize;
1662 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1663 chip->write_buf(mtd, buf, length);
1664 /* Send command to program the OOB data */
1665 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1667 status = chip->waitfunc(mtd, chip);
1669 return status & NAND_STATUS_FAIL ? -EIO : 0;
1673 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1674 * with syndrome - only for large page flash
1675 * @mtd: mtd info structure
1676 * @chip: nand chip info structure
1677 * @page: page number to write
1679 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1680 struct nand_chip *chip, int page)
1682 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1683 int eccsize = chip->ecc.size, length = mtd->oobsize;
1684 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1685 const uint8_t *bufpoi = chip->oob_poi;
1688 * data-ecc-data-ecc ... ecc-oob
1690 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1692 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1693 pos = steps * (eccsize + chunk);
1698 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1699 for (i = 0; i < steps; i++) {
1701 if (mtd->writesize <= 512) {
1702 uint32_t fill = 0xFFFFFFFF;
1706 int num = min_t(int, len, 4);
1707 chip->write_buf(mtd, (uint8_t *)&fill,
1712 pos = eccsize + i * (eccsize + chunk);
1713 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1717 len = min_t(int, length, chunk);
1718 chip->write_buf(mtd, bufpoi, len);
1723 chip->write_buf(mtd, bufpoi, length);
1725 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1726 status = chip->waitfunc(mtd, chip);
1728 return status & NAND_STATUS_FAIL ? -EIO : 0;
1732 * nand_do_read_oob - [INTERN] NAND read out-of-band
1733 * @mtd: MTD device structure
1734 * @from: offset to read from
1735 * @ops: oob operations description structure
1737 * NAND read out-of-band data from the spare area.
1739 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1740 struct mtd_oob_ops *ops)
1742 int page, realpage, chipnr;
1743 struct nand_chip *chip = mtd->priv;
1744 struct mtd_ecc_stats stats;
1745 int readlen = ops->ooblen;
1747 uint8_t *buf = ops->oobbuf;
1750 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1751 __func__, (unsigned long long)from, readlen);
1753 stats = mtd->ecc_stats;
1755 if (ops->mode == MTD_OPS_AUTO_OOB)
1756 len = chip->ecc.layout->oobavail;
1760 if (unlikely(ops->ooboffs >= len)) {
1761 pr_debug("%s: attempt to start read outside oob\n",
1766 /* Do not allow reads past end of device */
1767 if (unlikely(from >= mtd->size ||
1768 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1769 (from >> chip->page_shift)) * len)) {
1770 pr_debug("%s: attempt to read beyond end of device\n",
1775 chipnr = (int)(from >> chip->chip_shift);
1776 chip->select_chip(mtd, chipnr);
1778 /* Shift to get page */
1779 realpage = (int)(from >> chip->page_shift);
1780 page = realpage & chip->pagemask;
1783 if (ops->mode == MTD_OPS_RAW)
1784 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1786 ret = chip->ecc.read_oob(mtd, chip, page);
1791 len = min(len, readlen);
1792 buf = nand_transfer_oob(chip, buf, ops, len);
1798 /* Increment page address */
1801 page = realpage & chip->pagemask;
1802 /* Check, if we cross a chip boundary */
1805 chip->select_chip(mtd, -1);
1806 chip->select_chip(mtd, chipnr);
1809 chip->select_chip(mtd, -1);
1811 ops->oobretlen = ops->ooblen - readlen;
1816 if (mtd->ecc_stats.failed - stats.failed)
1819 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1823 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1824 * @mtd: MTD device structure
1825 * @from: offset to read from
1826 * @ops: oob operation description structure
1828 * NAND read data and/or out-of-band data.
1830 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1831 struct mtd_oob_ops *ops)
1833 int ret = -ENOTSUPP;
1837 /* Do not allow reads past end of device */
1838 if (ops->datbuf && (from + ops->len) > mtd->size) {
1839 pr_debug("%s: attempt to read beyond end of device\n",
1844 nand_get_device(mtd, FL_READING);
1846 switch (ops->mode) {
1847 case MTD_OPS_PLACE_OOB:
1848 case MTD_OPS_AUTO_OOB:
1857 ret = nand_do_read_oob(mtd, from, ops);
1859 ret = nand_do_read_ops(mtd, from, ops);
1862 nand_release_device(mtd);
1868 * nand_write_page_raw - [INTERN] raw page write function
1869 * @mtd: mtd info structure
1870 * @chip: nand chip info structure
1872 * @oob_required: must write chip->oob_poi to OOB
1874 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1876 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1877 const uint8_t *buf, int oob_required)
1879 chip->write_buf(mtd, buf, mtd->writesize);
1881 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1887 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1888 * @mtd: mtd info structure
1889 * @chip: nand chip info structure
1891 * @oob_required: must write chip->oob_poi to OOB
1893 * We need a special oob layout and handling even when ECC isn't checked.
1895 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1896 struct nand_chip *chip,
1897 const uint8_t *buf, int oob_required)
1899 int eccsize = chip->ecc.size;
1900 int eccbytes = chip->ecc.bytes;
1901 uint8_t *oob = chip->oob_poi;
1904 for (steps = chip->ecc.steps; steps > 0; steps--) {
1905 chip->write_buf(mtd, buf, eccsize);
1908 if (chip->ecc.prepad) {
1909 chip->write_buf(mtd, oob, chip->ecc.prepad);
1910 oob += chip->ecc.prepad;
1913 chip->read_buf(mtd, oob, eccbytes);
1916 if (chip->ecc.postpad) {
1917 chip->write_buf(mtd, oob, chip->ecc.postpad);
1918 oob += chip->ecc.postpad;
1922 size = mtd->oobsize - (oob - chip->oob_poi);
1924 chip->write_buf(mtd, oob, size);
1929 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1930 * @mtd: mtd info structure
1931 * @chip: nand chip info structure
1933 * @oob_required: must write chip->oob_poi to OOB
1935 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1936 const uint8_t *buf, int oob_required)
1938 int i, eccsize = chip->ecc.size;
1939 int eccbytes = chip->ecc.bytes;
1940 int eccsteps = chip->ecc.steps;
1941 uint8_t *ecc_calc = chip->buffers->ecccalc;
1942 const uint8_t *p = buf;
1943 uint32_t *eccpos = chip->ecc.layout->eccpos;
1945 /* Software ECC calculation */
1946 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1947 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1949 for (i = 0; i < chip->ecc.total; i++)
1950 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1952 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1956 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1957 * @mtd: mtd info structure
1958 * @chip: nand chip info structure
1960 * @oob_required: must write chip->oob_poi to OOB
1962 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1963 const uint8_t *buf, int oob_required)
1965 int i, eccsize = chip->ecc.size;
1966 int eccbytes = chip->ecc.bytes;
1967 int eccsteps = chip->ecc.steps;
1968 uint8_t *ecc_calc = chip->buffers->ecccalc;
1969 const uint8_t *p = buf;
1970 uint32_t *eccpos = chip->ecc.layout->eccpos;
1972 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1973 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1974 chip->write_buf(mtd, p, eccsize);
1975 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1978 for (i = 0; i < chip->ecc.total; i++)
1979 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1981 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1987 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1988 * @mtd: mtd info structure
1989 * @chip: nand chip info structure
1991 * @oob_required: must write chip->oob_poi to OOB
1993 * The hw generator calculates the error syndrome automatically. Therefore we
1994 * need a special oob layout and handling.
1996 static int nand_write_page_syndrome(struct mtd_info *mtd,
1997 struct nand_chip *chip,
1998 const uint8_t *buf, int oob_required)
2000 int i, eccsize = chip->ecc.size;
2001 int eccbytes = chip->ecc.bytes;
2002 int eccsteps = chip->ecc.steps;
2003 const uint8_t *p = buf;
2004 uint8_t *oob = chip->oob_poi;
2006 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2008 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2009 chip->write_buf(mtd, p, eccsize);
2011 if (chip->ecc.prepad) {
2012 chip->write_buf(mtd, oob, chip->ecc.prepad);
2013 oob += chip->ecc.prepad;
2016 chip->ecc.calculate(mtd, p, oob);
2017 chip->write_buf(mtd, oob, eccbytes);
2020 if (chip->ecc.postpad) {
2021 chip->write_buf(mtd, oob, chip->ecc.postpad);
2022 oob += chip->ecc.postpad;
2026 /* Calculate remaining oob bytes */
2027 i = mtd->oobsize - (oob - chip->oob_poi);
2029 chip->write_buf(mtd, oob, i);
2035 * nand_write_page - [REPLACEABLE] write one page
2036 * @mtd: MTD device structure
2037 * @chip: NAND chip descriptor
2038 * @buf: the data to write
2039 * @oob_required: must write chip->oob_poi to OOB
2040 * @page: page number to write
2041 * @cached: cached programming
2042 * @raw: use _raw version of write_page
2044 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2045 const uint8_t *buf, int oob_required, int page,
2046 int cached, int raw)
2050 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2053 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
2055 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2061 * Cached progamming disabled for now. Not sure if it's worth the
2062 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2066 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2068 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2069 status = chip->waitfunc(mtd, chip);
2071 * See if operation failed and additional status checks are
2074 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2075 status = chip->errstat(mtd, chip, FL_WRITING, status,
2078 if (status & NAND_STATUS_FAIL)
2081 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2082 status = chip->waitfunc(mtd, chip);
2089 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2090 * @mtd: MTD device structure
2091 * @oob: oob data buffer
2092 * @len: oob data write length
2093 * @ops: oob ops structure
2095 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2096 struct mtd_oob_ops *ops)
2098 struct nand_chip *chip = mtd->priv;
2101 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2102 * data from a previous OOB read.
2104 memset(chip->oob_poi, 0xff, mtd->oobsize);
2106 switch (ops->mode) {
2108 case MTD_OPS_PLACE_OOB:
2110 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2113 case MTD_OPS_AUTO_OOB: {
2114 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2115 uint32_t boffs = 0, woffs = ops->ooboffs;
2118 for (; free->length && len; free++, len -= bytes) {
2119 /* Write request not from offset 0? */
2120 if (unlikely(woffs)) {
2121 if (woffs >= free->length) {
2122 woffs -= free->length;
2125 boffs = free->offset + woffs;
2126 bytes = min_t(size_t, len,
2127 (free->length - woffs));
2130 bytes = min_t(size_t, len, free->length);
2131 boffs = free->offset;
2133 memcpy(chip->oob_poi + boffs, oob, bytes);
2144 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2147 * nand_do_write_ops - [INTERN] NAND write with ECC
2148 * @mtd: MTD device structure
2149 * @to: offset to write to
2150 * @ops: oob operations description structure
2152 * NAND write with ECC.
2154 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2155 struct mtd_oob_ops *ops)
2157 int chipnr, realpage, page, blockmask, column;
2158 struct nand_chip *chip = mtd->priv;
2159 uint32_t writelen = ops->len;
2161 uint32_t oobwritelen = ops->ooblen;
2162 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2163 mtd->oobavail : mtd->oobsize;
2165 uint8_t *oob = ops->oobbuf;
2166 uint8_t *buf = ops->datbuf;
2168 int oob_required = oob ? 1 : 0;
2174 /* Reject writes, which are not page aligned */
2175 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2176 pr_notice("%s: attempt to write non page aligned data\n",
2181 column = to & (mtd->writesize - 1);
2182 subpage = column || (writelen & (mtd->writesize - 1));
2187 chipnr = (int)(to >> chip->chip_shift);
2188 chip->select_chip(mtd, chipnr);
2190 /* Check, if it is write protected */
2191 if (nand_check_wp(mtd)) {
2196 realpage = (int)(to >> chip->page_shift);
2197 page = realpage & chip->pagemask;
2198 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2200 /* Invalidate the page cache, when we write to the cached page */
2201 if (to <= (chip->pagebuf << chip->page_shift) &&
2202 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2205 /* Don't allow multipage oob writes with offset */
2206 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2212 int bytes = mtd->writesize;
2213 int cached = writelen > bytes && page != blockmask;
2214 uint8_t *wbuf = buf;
2216 /* Partial page write? */
2217 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2219 bytes = min_t(int, bytes - column, (int) writelen);
2221 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2222 memcpy(&chip->buffers->databuf[column], buf, bytes);
2223 wbuf = chip->buffers->databuf;
2226 if (unlikely(oob)) {
2227 size_t len = min(oobwritelen, oobmaxlen);
2228 oob = nand_fill_oob(mtd, oob, len, ops);
2231 /* We still need to erase leftover OOB data */
2232 memset(chip->oob_poi, 0xff, mtd->oobsize);
2235 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2236 cached, (ops->mode == MTD_OPS_RAW));
2248 page = realpage & chip->pagemask;
2249 /* Check, if we cross a chip boundary */
2252 chip->select_chip(mtd, -1);
2253 chip->select_chip(mtd, chipnr);
2257 ops->retlen = ops->len - writelen;
2259 ops->oobretlen = ops->ooblen;
2262 chip->select_chip(mtd, -1);
2267 * panic_nand_write - [MTD Interface] NAND write with ECC
2268 * @mtd: MTD device structure
2269 * @to: offset to write to
2270 * @len: number of bytes to write
2271 * @retlen: pointer to variable to store the number of written bytes
2272 * @buf: the data to write
2274 * NAND write with ECC. Used when performing writes in interrupt context, this
2275 * may for example be called by mtdoops when writing an oops while in panic.
2277 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2278 size_t *retlen, const uint8_t *buf)
2280 struct nand_chip *chip = mtd->priv;
2281 struct mtd_oob_ops ops;
2284 /* Wait for the device to get ready */
2285 panic_nand_wait(mtd, chip, 400);
2287 /* Grab the device */
2288 panic_nand_get_device(chip, mtd, FL_WRITING);
2291 ops.datbuf = (uint8_t *)buf;
2293 ops.mode = MTD_OPS_PLACE_OOB;
2295 ret = nand_do_write_ops(mtd, to, &ops);
2297 *retlen = ops.retlen;
2302 * nand_write - [MTD Interface] NAND write with ECC
2303 * @mtd: MTD device structure
2304 * @to: offset to write to
2305 * @len: number of bytes to write
2306 * @retlen: pointer to variable to store the number of written bytes
2307 * @buf: the data to write
2309 * NAND write with ECC.
2311 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2312 size_t *retlen, const uint8_t *buf)
2314 struct mtd_oob_ops ops;
2317 nand_get_device(mtd, FL_WRITING);
2319 ops.datbuf = (uint8_t *)buf;
2321 ops.mode = MTD_OPS_PLACE_OOB;
2322 ret = nand_do_write_ops(mtd, to, &ops);
2323 *retlen = ops.retlen;
2324 nand_release_device(mtd);
2329 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2330 * @mtd: MTD device structure
2331 * @to: offset to write to
2332 * @ops: oob operation description structure
2334 * NAND write out-of-band.
2336 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2337 struct mtd_oob_ops *ops)
2339 int chipnr, page, status, len;
2340 struct nand_chip *chip = mtd->priv;
2342 pr_debug("%s: to = 0x%08x, len = %i\n",
2343 __func__, (unsigned int)to, (int)ops->ooblen);
2345 if (ops->mode == MTD_OPS_AUTO_OOB)
2346 len = chip->ecc.layout->oobavail;
2350 /* Do not allow write past end of page */
2351 if ((ops->ooboffs + ops->ooblen) > len) {
2352 pr_debug("%s: attempt to write past end of page\n",
2357 if (unlikely(ops->ooboffs >= len)) {
2358 pr_debug("%s: attempt to start write outside oob\n",
2363 /* Do not allow write past end of device */
2364 if (unlikely(to >= mtd->size ||
2365 ops->ooboffs + ops->ooblen >
2366 ((mtd->size >> chip->page_shift) -
2367 (to >> chip->page_shift)) * len)) {
2368 pr_debug("%s: attempt to write beyond end of device\n",
2373 chipnr = (int)(to >> chip->chip_shift);
2374 chip->select_chip(mtd, chipnr);
2376 /* Shift to get page */
2377 page = (int)(to >> chip->page_shift);
2380 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2381 * of my DiskOnChip 2000 test units) will clear the whole data page too
2382 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2383 * it in the doc2000 driver in August 1999. dwmw2.
2385 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2387 /* Check, if it is write protected */
2388 if (nand_check_wp(mtd)) {
2389 chip->select_chip(mtd, -1);
2393 /* Invalidate the page cache, if we write to the cached page */
2394 if (page == chip->pagebuf)
2397 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2399 if (ops->mode == MTD_OPS_RAW)
2400 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2402 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2404 chip->select_chip(mtd, -1);
2409 ops->oobretlen = ops->ooblen;
2415 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2416 * @mtd: MTD device structure
2417 * @to: offset to write to
2418 * @ops: oob operation description structure
2420 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2421 struct mtd_oob_ops *ops)
2423 int ret = -ENOTSUPP;
2427 /* Do not allow writes past end of device */
2428 if (ops->datbuf && (to + ops->len) > mtd->size) {
2429 pr_debug("%s: attempt to write beyond end of device\n",
2434 nand_get_device(mtd, FL_WRITING);
2436 switch (ops->mode) {
2437 case MTD_OPS_PLACE_OOB:
2438 case MTD_OPS_AUTO_OOB:
2447 ret = nand_do_write_oob(mtd, to, ops);
2449 ret = nand_do_write_ops(mtd, to, ops);
2452 nand_release_device(mtd);
2457 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2458 * @mtd: MTD device structure
2459 * @page: the page address of the block which will be erased
2461 * Standard erase command for NAND chips.
2463 static void single_erase_cmd(struct mtd_info *mtd, int page)
2465 struct nand_chip *chip = mtd->priv;
2466 /* Send commands to erase a block */
2467 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2468 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2472 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2473 * @mtd: MTD device structure
2474 * @page: the page address of the block which will be erased
2476 * AND multi block erase command function. Erase 4 consecutive blocks.
2478 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2480 struct nand_chip *chip = mtd->priv;
2481 /* Send commands to erase a block */
2482 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2483 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2485 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2486 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2490 * nand_erase - [MTD Interface] erase block(s)
2491 * @mtd: MTD device structure
2492 * @instr: erase instruction
2494 * Erase one ore more blocks.
2496 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2498 return nand_erase_nand(mtd, instr, 0);
2501 #define BBT_PAGE_MASK 0xffffff3f
2503 * nand_erase_nand - [INTERN] erase block(s)
2504 * @mtd: MTD device structure
2505 * @instr: erase instruction
2506 * @allowbbt: allow erasing the bbt area
2508 * Erase one ore more blocks.
2510 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2513 int page, status, pages_per_block, ret, chipnr;
2514 struct nand_chip *chip = mtd->priv;
2515 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2516 unsigned int bbt_masked_page = 0xffffffff;
2519 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2520 __func__, (unsigned long long)instr->addr,
2521 (unsigned long long)instr->len);
2523 if (check_offs_len(mtd, instr->addr, instr->len))
2526 /* Grab the lock and see if the device is available */
2527 nand_get_device(mtd, FL_ERASING);
2529 /* Shift to get first page */
2530 page = (int)(instr->addr >> chip->page_shift);
2531 chipnr = (int)(instr->addr >> chip->chip_shift);
2533 /* Calculate pages in each block */
2534 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2536 /* Select the NAND device */
2537 chip->select_chip(mtd, chipnr);
2539 /* Check, if it is write protected */
2540 if (nand_check_wp(mtd)) {
2541 pr_debug("%s: device is write protected!\n",
2543 instr->state = MTD_ERASE_FAILED;
2548 * If BBT requires refresh, set the BBT page mask to see if the BBT
2549 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2550 * can not be matched. This is also done when the bbt is actually
2551 * erased to avoid recursive updates.
2553 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2554 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2556 /* Loop through the pages */
2559 instr->state = MTD_ERASING;
2562 /* Check if we have a bad block, we do not erase bad blocks! */
2563 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2564 chip->page_shift, 0, allowbbt)) {
2565 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2567 instr->state = MTD_ERASE_FAILED;
2572 * Invalidate the page cache, if we erase the block which
2573 * contains the current cached page.
2575 if (page <= chip->pagebuf && chip->pagebuf <
2576 (page + pages_per_block))
2579 chip->erase_cmd(mtd, page & chip->pagemask);
2581 status = chip->waitfunc(mtd, chip);
2584 * See if operation failed and additional status checks are
2587 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2588 status = chip->errstat(mtd, chip, FL_ERASING,
2591 /* See if block erase succeeded */
2592 if (status & NAND_STATUS_FAIL) {
2593 pr_debug("%s: failed erase, page 0x%08x\n",
2595 instr->state = MTD_ERASE_FAILED;
2597 ((loff_t)page << chip->page_shift);
2602 * If BBT requires refresh, set the BBT rewrite flag to the
2603 * page being erased.
2605 if (bbt_masked_page != 0xffffffff &&
2606 (page & BBT_PAGE_MASK) == bbt_masked_page)
2607 rewrite_bbt[chipnr] =
2608 ((loff_t)page << chip->page_shift);
2610 /* Increment page address and decrement length */
2611 len -= (1 << chip->phys_erase_shift);
2612 page += pages_per_block;
2614 /* Check, if we cross a chip boundary */
2615 if (len && !(page & chip->pagemask)) {
2617 chip->select_chip(mtd, -1);
2618 chip->select_chip(mtd, chipnr);
2621 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2622 * page mask to see if this BBT should be rewritten.
2624 if (bbt_masked_page != 0xffffffff &&
2625 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2626 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2630 instr->state = MTD_ERASE_DONE;
2634 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2636 /* Deselect and wake up anyone waiting on the device */
2637 chip->select_chip(mtd, -1);
2638 nand_release_device(mtd);
2640 /* Do call back function */
2642 mtd_erase_callback(instr);
2645 * If BBT requires refresh and erase was successful, rewrite any
2646 * selected bad block tables.
2648 if (bbt_masked_page == 0xffffffff || ret)
2651 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2652 if (!rewrite_bbt[chipnr])
2654 /* Update the BBT for chip */
2655 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2656 __func__, chipnr, rewrite_bbt[chipnr],
2657 chip->bbt_td->pages[chipnr]);
2658 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2661 /* Return more or less happy */
2666 * nand_sync - [MTD Interface] sync
2667 * @mtd: MTD device structure
2669 * Sync is actually a wait for chip ready function.
2671 static void nand_sync(struct mtd_info *mtd)
2673 pr_debug("%s: called\n", __func__);
2675 /* Grab the lock and see if the device is available */
2676 nand_get_device(mtd, FL_SYNCING);
2677 /* Release it and go back */
2678 nand_release_device(mtd);
2682 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2683 * @mtd: MTD device structure
2684 * @offs: offset relative to mtd start
2686 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2688 return nand_block_checkbad(mtd, offs, 1, 0);
2692 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2693 * @mtd: MTD device structure
2694 * @ofs: offset relative to mtd start
2696 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2698 struct nand_chip *chip = mtd->priv;
2701 ret = nand_block_isbad(mtd, ofs);
2703 /* If it was bad already, return success and do nothing */
2709 return chip->block_markbad(mtd, ofs);
2713 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2714 * @mtd: MTD device structure
2715 * @chip: nand chip info structure
2716 * @addr: feature address.
2717 * @subfeature_param: the subfeature parameters, a four bytes array.
2719 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2720 int addr, uint8_t *subfeature_param)
2724 if (!chip->onfi_version)
2727 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2728 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2729 status = chip->waitfunc(mtd, chip);
2730 if (status & NAND_STATUS_FAIL)
2736 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2737 * @mtd: MTD device structure
2738 * @chip: nand chip info structure
2739 * @addr: feature address.
2740 * @subfeature_param: the subfeature parameters, a four bytes array.
2742 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2743 int addr, uint8_t *subfeature_param)
2745 if (!chip->onfi_version)
2748 /* clear the sub feature parameters */
2749 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2751 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2752 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2757 * nand_suspend - [MTD Interface] Suspend the NAND flash
2758 * @mtd: MTD device structure
2760 static int nand_suspend(struct mtd_info *mtd)
2762 return nand_get_device(mtd, FL_PM_SUSPENDED);
2766 * nand_resume - [MTD Interface] Resume the NAND flash
2767 * @mtd: MTD device structure
2769 static void nand_resume(struct mtd_info *mtd)
2771 struct nand_chip *chip = mtd->priv;
2773 if (chip->state == FL_PM_SUSPENDED)
2774 nand_release_device(mtd);
2776 pr_err("%s called for a chip which is not in suspended state\n",
2780 /* Set default functions */
2781 static void nand_set_defaults(struct nand_chip *chip, int busw)
2783 /* check for proper chip_delay setup, set 20us if not */
2784 if (!chip->chip_delay)
2785 chip->chip_delay = 20;
2787 /* check, if a user supplied command function given */
2788 if (chip->cmdfunc == NULL)
2789 chip->cmdfunc = nand_command;
2791 /* check, if a user supplied wait function given */
2792 if (chip->waitfunc == NULL)
2793 chip->waitfunc = nand_wait;
2795 if (!chip->select_chip)
2796 chip->select_chip = nand_select_chip;
2797 if (!chip->read_byte)
2798 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2799 if (!chip->read_word)
2800 chip->read_word = nand_read_word;
2801 if (!chip->block_bad)
2802 chip->block_bad = nand_block_bad;
2803 if (!chip->block_markbad)
2804 chip->block_markbad = nand_default_block_markbad;
2805 if (!chip->write_buf)
2806 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2807 if (!chip->read_buf)
2808 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2809 if (!chip->scan_bbt)
2810 chip->scan_bbt = nand_default_bbt;
2812 if (!chip->controller) {
2813 chip->controller = &chip->hwcontrol;
2814 spin_lock_init(&chip->controller->lock);
2815 init_waitqueue_head(&chip->controller->wq);
2820 /* Sanitize ONFI strings so we can safely print them */
2821 static void sanitize_string(uint8_t *s, size_t len)
2825 /* Null terminate */
2828 /* Remove non printable chars */
2829 for (i = 0; i < len - 1; i++) {
2830 if (s[i] < ' ' || s[i] > 127)
2834 /* Remove trailing spaces */
2838 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2843 for (i = 0; i < 8; i++)
2844 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2851 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2853 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2856 struct nand_onfi_params *p = &chip->onfi_params;
2860 /* ONFI need to be probed in 8 bits mode */
2861 WARN_ON(chip->options & NAND_BUSWIDTH_16);
2862 /* Try ONFI for unknown chip or LP */
2863 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2864 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2865 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2868 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2869 for (i = 0; i < 3; i++) {
2870 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2871 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2872 le16_to_cpu(p->crc)) {
2873 pr_info("ONFI param page %d valid\n", i);
2882 val = le16_to_cpu(p->revision);
2884 chip->onfi_version = 23;
2885 else if (val & (1 << 4))
2886 chip->onfi_version = 22;
2887 else if (val & (1 << 3))
2888 chip->onfi_version = 21;
2889 else if (val & (1 << 2))
2890 chip->onfi_version = 20;
2891 else if (val & (1 << 1))
2892 chip->onfi_version = 10;
2894 chip->onfi_version = 0;
2896 if (!chip->onfi_version) {
2897 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2901 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2902 sanitize_string(p->model, sizeof(p->model));
2904 mtd->name = p->model;
2905 mtd->writesize = le32_to_cpu(p->byte_per_page);
2906 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2907 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2908 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2909 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2911 if (le16_to_cpu(p->features) & 1)
2912 *busw = NAND_BUSWIDTH_16;
2914 pr_info("ONFI flash detected\n");
2919 * nand_id_has_period - Check if an ID string has a given wraparound period
2920 * @id_data: the ID string
2921 * @arrlen: the length of the @id_data array
2922 * @period: the period of repitition
2924 * Check if an ID string is repeated within a given sequence of bytes at
2925 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2926 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
2927 * if the repetition has a period of @period; otherwise, returns zero.
2929 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2932 for (i = 0; i < period; i++)
2933 for (j = i + period; j < arrlen; j += period)
2934 if (id_data[i] != id_data[j])
2940 * nand_id_len - Get the length of an ID string returned by CMD_READID
2941 * @id_data: the ID string
2942 * @arrlen: the length of the @id_data array
2944 * Returns the length of the ID string, according to known wraparound/trailing
2945 * zero patterns. If no pattern exists, returns the length of the array.
2947 static int nand_id_len(u8 *id_data, int arrlen)
2949 int last_nonzero, period;
2951 /* Find last non-zero byte */
2952 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2953 if (id_data[last_nonzero])
2957 if (last_nonzero < 0)
2960 /* Calculate wraparound period */
2961 for (period = 1; period < arrlen; period++)
2962 if (nand_id_has_period(id_data, arrlen, period))
2965 /* There's a repeated pattern */
2966 if (period < arrlen)
2969 /* There are trailing zeros */
2970 if (last_nonzero < arrlen - 1)
2971 return last_nonzero + 1;
2973 /* No pattern detected */
2978 * Many new NAND share similar device ID codes, which represent the size of the
2979 * chip. The rest of the parameters must be decoded according to generic or
2980 * manufacturer-specific "extended ID" decoding patterns.
2982 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2983 u8 id_data[8], int *busw)
2986 /* The 3rd id byte holds MLC / multichip data */
2987 chip->cellinfo = id_data[2];
2988 /* The 4th id byte is the important one */
2991 id_len = nand_id_len(id_data, 8);
2994 * Field definitions are in the following datasheets:
2995 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2996 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2997 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
2999 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3000 * ID to decide what to do.
3002 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3003 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3004 id_data[5] != 0x00) {
3006 mtd->writesize = 2048 << (extid & 0x03);
3009 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3026 default: /* Other cases are "reserved" (unknown) */
3031 /* Calc blocksize */
3032 mtd->erasesize = (128 * 1024) <<
3033 (((extid >> 1) & 0x04) | (extid & 0x03));
3035 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3036 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3040 mtd->writesize = 2048 << (extid & 0x03);
3043 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3067 /* Calc blocksize */
3068 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3070 mtd->erasesize = (128 * 1024) << tmp;
3071 else if (tmp == 0x03)
3072 mtd->erasesize = 768 * 1024;
3074 mtd->erasesize = (64 * 1024) << tmp;
3078 mtd->writesize = 1024 << (extid & 0x03);
3081 mtd->oobsize = (8 << (extid & 0x01)) *
3082 (mtd->writesize >> 9);
3084 /* Calc blocksize. Blocksize is multiples of 64KiB */
3085 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3087 /* Get buswidth information */
3088 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3093 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3094 * decodes a matching ID table entry and assigns the MTD size parameters for
3097 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3098 struct nand_flash_dev *type, u8 id_data[8],
3101 int maf_id = id_data[0];
3103 mtd->erasesize = type->erasesize;
3104 mtd->writesize = type->pagesize;
3105 mtd->oobsize = mtd->writesize / 32;
3106 *busw = type->options & NAND_BUSWIDTH_16;
3109 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3110 * some Spansion chips have erasesize that conflicts with size
3111 * listed in nand_ids table.
3112 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3114 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3115 && id_data[6] == 0x00 && id_data[7] == 0x00
3116 && mtd->writesize == 512) {
3117 mtd->erasesize = 128 * 1024;
3118 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3123 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3124 * heuristic patterns using various detected parameters (e.g., manufacturer,
3125 * page size, cell-type information).
3127 static void nand_decode_bbm_options(struct mtd_info *mtd,
3128 struct nand_chip *chip, u8 id_data[8])
3130 int maf_id = id_data[0];
3132 /* Set the bad block position */
3133 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3134 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3136 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3139 * Bad block marker is stored in the last page of each block on Samsung
3140 * and Hynix MLC devices; stored in first two pages of each block on
3141 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3142 * AMD/Spansion, and Macronix. All others scan only the first page.
3144 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3145 (maf_id == NAND_MFR_SAMSUNG ||
3146 maf_id == NAND_MFR_HYNIX))
3147 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3148 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3149 (maf_id == NAND_MFR_SAMSUNG ||
3150 maf_id == NAND_MFR_HYNIX ||
3151 maf_id == NAND_MFR_TOSHIBA ||
3152 maf_id == NAND_MFR_AMD ||
3153 maf_id == NAND_MFR_MACRONIX)) ||
3154 (mtd->writesize == 2048 &&
3155 maf_id == NAND_MFR_MICRON))
3156 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3160 * Get the flash and manufacturer id and lookup if the type is supported.
3162 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3163 struct nand_chip *chip,
3165 int *maf_id, int *dev_id,
3166 struct nand_flash_dev *type)
3171 /* Select the device */
3172 chip->select_chip(mtd, 0);
3175 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3178 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3180 /* Send the command for reading device ID */
3181 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3183 /* Read manufacturer and device IDs */
3184 *maf_id = chip->read_byte(mtd);
3185 *dev_id = chip->read_byte(mtd);
3188 * Try again to make sure, as some systems the bus-hold or other
3189 * interface concerns can cause random data which looks like a
3190 * possibly credible NAND flash to appear. If the two results do
3191 * not match, ignore the device completely.
3194 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3196 /* Read entire ID string */
3197 for (i = 0; i < 8; i++)
3198 id_data[i] = chip->read_byte(mtd);
3200 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3201 pr_info("%s: second ID read did not match "
3202 "%02x,%02x against %02x,%02x\n", __func__,
3203 *maf_id, *dev_id, id_data[0], id_data[1]);
3204 return ERR_PTR(-ENODEV);
3208 type = nand_flash_ids;
3210 for (; type->name != NULL; type++)
3211 if (*dev_id == type->id)
3214 chip->onfi_version = 0;
3215 if (!type->name || !type->pagesize) {
3216 /* Check is chip is ONFI compliant */
3217 if (nand_flash_detect_onfi(mtd, chip, &busw))
3222 return ERR_PTR(-ENODEV);
3225 mtd->name = type->name;
3227 chip->chipsize = (uint64_t)type->chipsize << 20;
3229 if (!type->pagesize && chip->init_size) {
3230 /* Set the pagesize, oobsize, erasesize by the driver */
3231 busw = chip->init_size(mtd, chip, id_data);
3232 } else if (!type->pagesize) {
3233 /* Decode parameters from extended ID */
3234 nand_decode_ext_id(mtd, chip, id_data, &busw);
3236 nand_decode_id(mtd, chip, type, id_data, &busw);
3238 /* Get chip options */
3239 chip->options |= type->options;
3242 * Check if chip is not a Samsung device. Do not clear the
3243 * options for chips which do not have an extended id.
3245 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3246 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3249 /* Try to identify manufacturer */
3250 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3251 if (nand_manuf_ids[maf_idx].id == *maf_id)
3255 if (chip->options & NAND_BUSWIDTH_AUTO) {
3256 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3257 chip->options |= busw;
3258 nand_set_defaults(chip, busw);
3259 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3261 * Check, if buswidth is correct. Hardware drivers should set
3264 pr_info("NAND device: Manufacturer ID:"
3265 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3266 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3267 pr_warn("NAND bus width %d instead %d bit\n",
3268 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3270 return ERR_PTR(-EINVAL);
3273 nand_decode_bbm_options(mtd, chip, id_data);
3275 /* Calculate the address shift from the page size */
3276 chip->page_shift = ffs(mtd->writesize) - 1;
3277 /* Convert chipsize to number of pages per chip -1 */
3278 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3280 chip->bbt_erase_shift = chip->phys_erase_shift =
3281 ffs(mtd->erasesize) - 1;
3282 if (chip->chipsize & 0xffffffff)
3283 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3285 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3286 chip->chip_shift += 32 - 1;
3289 chip->badblockbits = 8;
3291 /* Check for AND chips with 4 page planes */
3292 if (chip->options & NAND_4PAGE_ARRAY)
3293 chip->erase_cmd = multi_erase_cmd;
3295 chip->erase_cmd = single_erase_cmd;
3297 /* Do not replace user supplied command function! */
3298 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3299 chip->cmdfunc = nand_command_lp;
3301 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3302 " %dMiB, page size: %d, OOB size: %d\n",
3303 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3304 chip->onfi_version ? chip->onfi_params.model : type->name,
3305 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
3311 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3312 * @mtd: MTD device structure
3313 * @maxchips: number of chips to scan for
3314 * @table: alternative NAND ID table
3316 * This is the first phase of the normal nand_scan() function. It reads the
3317 * flash ID and sets up MTD fields accordingly.
3319 * The mtd->owner field must be set to the module of the caller.
3321 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3322 struct nand_flash_dev *table)
3324 int i, busw, nand_maf_id, nand_dev_id;
3325 struct nand_chip *chip = mtd->priv;
3326 struct nand_flash_dev *type;
3328 /* Get buswidth to select the correct functions */
3329 busw = chip->options & NAND_BUSWIDTH_16;
3330 /* Set the default functions */
3331 nand_set_defaults(chip, busw);
3333 /* Read the flash type */
3334 type = nand_get_flash_type(mtd, chip, busw,
3335 &nand_maf_id, &nand_dev_id, table);
3338 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3339 pr_warn("No NAND device found\n");
3340 chip->select_chip(mtd, -1);
3341 return PTR_ERR(type);
3344 chip->select_chip(mtd, -1);
3346 /* Check for a chip array */
3347 for (i = 1; i < maxchips; i++) {
3348 chip->select_chip(mtd, i);
3349 /* See comment in nand_get_flash_type for reset */
3350 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3351 /* Send the command for reading device ID */
3352 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3353 /* Read manufacturer and device IDs */
3354 if (nand_maf_id != chip->read_byte(mtd) ||
3355 nand_dev_id != chip->read_byte(mtd)) {
3356 chip->select_chip(mtd, -1);
3359 chip->select_chip(mtd, -1);
3362 pr_info("%d NAND chips detected\n", i);
3364 /* Store the number of chips and calc total size for mtd */
3366 mtd->size = i * chip->chipsize;
3370 EXPORT_SYMBOL(nand_scan_ident);
3374 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3375 * @mtd: MTD device structure
3377 * This is the second phase of the normal nand_scan() function. It fills out
3378 * all the uninitialized function pointers with the defaults and scans for a
3379 * bad block table if appropriate.
3381 int nand_scan_tail(struct mtd_info *mtd)
3384 struct nand_chip *chip = mtd->priv;
3386 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3387 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3388 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3390 if (!(chip->options & NAND_OWN_BUFFERS))
3391 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3395 /* Set the internal oob buffer location, just after the page data */
3396 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3399 * If no default placement scheme is given, select an appropriate one.
3401 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3402 switch (mtd->oobsize) {
3404 chip->ecc.layout = &nand_oob_8;
3407 chip->ecc.layout = &nand_oob_16;
3410 chip->ecc.layout = &nand_oob_64;
3413 chip->ecc.layout = &nand_oob_128;
3416 pr_warn("No oob scheme defined for oobsize %d\n",
3422 if (!chip->write_page)
3423 chip->write_page = nand_write_page;
3425 /* set for ONFI nand */
3426 if (!chip->onfi_set_features)
3427 chip->onfi_set_features = nand_onfi_set_features;
3428 if (!chip->onfi_get_features)
3429 chip->onfi_get_features = nand_onfi_get_features;
3432 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3433 * selected and we have 256 byte pagesize fallback to software ECC
3436 switch (chip->ecc.mode) {
3437 case NAND_ECC_HW_OOB_FIRST:
3438 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3439 if (!chip->ecc.calculate || !chip->ecc.correct ||
3441 pr_warn("No ECC functions supplied; "
3442 "hardware ECC not possible\n");
3445 if (!chip->ecc.read_page)
3446 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3449 /* Use standard hwecc read page function? */
3450 if (!chip->ecc.read_page)
3451 chip->ecc.read_page = nand_read_page_hwecc;
3452 if (!chip->ecc.write_page)
3453 chip->ecc.write_page = nand_write_page_hwecc;
3454 if (!chip->ecc.read_page_raw)
3455 chip->ecc.read_page_raw = nand_read_page_raw;
3456 if (!chip->ecc.write_page_raw)
3457 chip->ecc.write_page_raw = nand_write_page_raw;
3458 if (!chip->ecc.read_oob)
3459 chip->ecc.read_oob = nand_read_oob_std;
3460 if (!chip->ecc.write_oob)
3461 chip->ecc.write_oob = nand_write_oob_std;
3463 case NAND_ECC_HW_SYNDROME:
3464 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3465 !chip->ecc.hwctl) &&
3466 (!chip->ecc.read_page ||
3467 chip->ecc.read_page == nand_read_page_hwecc ||
3468 !chip->ecc.write_page ||
3469 chip->ecc.write_page == nand_write_page_hwecc)) {
3470 pr_warn("No ECC functions supplied; "
3471 "hardware ECC not possible\n");
3474 /* Use standard syndrome read/write page function? */
3475 if (!chip->ecc.read_page)
3476 chip->ecc.read_page = nand_read_page_syndrome;
3477 if (!chip->ecc.write_page)
3478 chip->ecc.write_page = nand_write_page_syndrome;
3479 if (!chip->ecc.read_page_raw)
3480 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3481 if (!chip->ecc.write_page_raw)
3482 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3483 if (!chip->ecc.read_oob)
3484 chip->ecc.read_oob = nand_read_oob_syndrome;
3485 if (!chip->ecc.write_oob)
3486 chip->ecc.write_oob = nand_write_oob_syndrome;
3488 if (mtd->writesize >= chip->ecc.size) {
3489 if (!chip->ecc.strength) {
3490 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3495 pr_warn("%d byte HW ECC not possible on "
3496 "%d byte page size, fallback to SW ECC\n",
3497 chip->ecc.size, mtd->writesize);
3498 chip->ecc.mode = NAND_ECC_SOFT;
3501 chip->ecc.calculate = nand_calculate_ecc;
3502 chip->ecc.correct = nand_correct_data;
3503 chip->ecc.read_page = nand_read_page_swecc;
3504 chip->ecc.read_subpage = nand_read_subpage;
3505 chip->ecc.write_page = nand_write_page_swecc;
3506 chip->ecc.read_page_raw = nand_read_page_raw;
3507 chip->ecc.write_page_raw = nand_write_page_raw;
3508 chip->ecc.read_oob = nand_read_oob_std;
3509 chip->ecc.write_oob = nand_write_oob_std;
3510 if (!chip->ecc.size)
3511 chip->ecc.size = 256;
3512 chip->ecc.bytes = 3;
3513 chip->ecc.strength = 1;
3516 case NAND_ECC_SOFT_BCH:
3517 if (!mtd_nand_has_bch()) {
3518 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3521 chip->ecc.calculate = nand_bch_calculate_ecc;
3522 chip->ecc.correct = nand_bch_correct_data;
3523 chip->ecc.read_page = nand_read_page_swecc;
3524 chip->ecc.read_subpage = nand_read_subpage;
3525 chip->ecc.write_page = nand_write_page_swecc;
3526 chip->ecc.read_page_raw = nand_read_page_raw;
3527 chip->ecc.write_page_raw = nand_write_page_raw;
3528 chip->ecc.read_oob = nand_read_oob_std;
3529 chip->ecc.write_oob = nand_write_oob_std;
3531 * Board driver should supply ecc.size and ecc.bytes values to
3532 * select how many bits are correctable; see nand_bch_init()
3533 * for details. Otherwise, default to 4 bits for large page
3536 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3537 chip->ecc.size = 512;
3538 chip->ecc.bytes = 7;
3540 chip->ecc.priv = nand_bch_init(mtd,
3544 if (!chip->ecc.priv) {
3545 pr_warn("BCH ECC initialization failed!\n");
3548 chip->ecc.strength =
3549 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3553 pr_warn("NAND_ECC_NONE selected by board driver. "
3554 "This is not recommended!\n");
3555 chip->ecc.read_page = nand_read_page_raw;
3556 chip->ecc.write_page = nand_write_page_raw;
3557 chip->ecc.read_oob = nand_read_oob_std;
3558 chip->ecc.read_page_raw = nand_read_page_raw;
3559 chip->ecc.write_page_raw = nand_write_page_raw;
3560 chip->ecc.write_oob = nand_write_oob_std;
3561 chip->ecc.size = mtd->writesize;
3562 chip->ecc.bytes = 0;
3563 chip->ecc.strength = 0;
3567 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3571 /* For many systems, the standard OOB write also works for raw */
3572 if (!chip->ecc.read_oob_raw)
3573 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3574 if (!chip->ecc.write_oob_raw)
3575 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3578 * The number of bytes available for a client to place data into
3579 * the out of band area.
3581 chip->ecc.layout->oobavail = 0;
3582 for (i = 0; chip->ecc.layout->oobfree[i].length
3583 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3584 chip->ecc.layout->oobavail +=
3585 chip->ecc.layout->oobfree[i].length;
3586 mtd->oobavail = chip->ecc.layout->oobavail;
3589 * Set the number of read / write steps for one page depending on ECC
3592 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3593 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3594 pr_warn("Invalid ECC parameters\n");
3597 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3599 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3600 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3601 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3602 switch (chip->ecc.steps) {
3604 mtd->subpage_sft = 1;
3609 mtd->subpage_sft = 2;
3613 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3615 /* Initialize state */
3616 chip->state = FL_READY;
3618 /* Invalidate the pagebuffer reference */
3621 /* Large page NAND with SOFT_ECC should support subpage reads */
3622 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3623 chip->options |= NAND_SUBPAGE_READ;
3625 /* Fill in remaining MTD driver data */
3626 mtd->type = MTD_NANDFLASH;
3627 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3629 mtd->_erase = nand_erase;
3631 mtd->_unpoint = NULL;
3632 mtd->_read = nand_read;
3633 mtd->_write = nand_write;
3634 mtd->_panic_write = panic_nand_write;
3635 mtd->_read_oob = nand_read_oob;
3636 mtd->_write_oob = nand_write_oob;
3637 mtd->_sync = nand_sync;
3639 mtd->_unlock = NULL;
3640 mtd->_suspend = nand_suspend;
3641 mtd->_resume = nand_resume;
3642 mtd->_block_isbad = nand_block_isbad;
3643 mtd->_block_markbad = nand_block_markbad;
3644 mtd->writebufsize = mtd->writesize;
3646 /* propagate ecc info to mtd_info */
3647 mtd->ecclayout = chip->ecc.layout;
3648 mtd->ecc_strength = chip->ecc.strength;
3650 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3651 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3654 if (!mtd->bitflip_threshold)
3655 mtd->bitflip_threshold = mtd->ecc_strength;
3657 /* Check, if we should skip the bad block table scan */
3658 if (chip->options & NAND_SKIP_BBTSCAN)
3661 /* Build bad block table */
3662 return chip->scan_bbt(mtd);
3664 EXPORT_SYMBOL(nand_scan_tail);
3667 * is_module_text_address() isn't exported, and it's mostly a pointless
3668 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3669 * to call us from in-kernel code if the core NAND support is modular.
3672 #define caller_is_module() (1)
3674 #define caller_is_module() \
3675 is_module_text_address((unsigned long)__builtin_return_address(0))
3679 * nand_scan - [NAND Interface] Scan for the NAND device
3680 * @mtd: MTD device structure
3681 * @maxchips: number of chips to scan for
3683 * This fills out all the uninitialized function pointers with the defaults.
3684 * The flash ID is read and the mtd/chip structures are filled with the
3685 * appropriate values. The mtd->owner field must be set to the module of the
3688 int nand_scan(struct mtd_info *mtd, int maxchips)
3692 /* Many callers got this wrong, so check for it for a while... */
3693 if (!mtd->owner && caller_is_module()) {
3694 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3698 ret = nand_scan_ident(mtd, maxchips, NULL);
3700 ret = nand_scan_tail(mtd);
3703 EXPORT_SYMBOL(nand_scan);
3706 * nand_release - [NAND Interface] Free resources held by the NAND device
3707 * @mtd: MTD device structure
3709 void nand_release(struct mtd_info *mtd)
3711 struct nand_chip *chip = mtd->priv;
3713 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3714 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3716 mtd_device_unregister(mtd);
3718 /* Free bad block table memory */
3720 if (!(chip->options & NAND_OWN_BUFFERS))
3721 kfree(chip->buffers);
3723 /* Free bad block descriptor memory */
3724 if (chip->badblock_pattern && chip->badblock_pattern->options
3725 & NAND_BBT_DYNAMICSTRUCT)
3726 kfree(chip->badblock_pattern);
3728 EXPORT_SYMBOL_GPL(nand_release);
3730 static int __init nand_base_init(void)
3732 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3736 static void __exit nand_base_exit(void)
3738 led_trigger_unregister_simple(nand_led_trigger);
3741 module_init(nand_base_init);
3742 module_exit(nand_base_exit);
3744 MODULE_LICENSE("GPL");
3745 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3746 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3747 MODULE_DESCRIPTION("Generic NAND flash driver code");