drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 /* XXX U-BOOT XXX */
  36 #if 0
  37 #include <linux/module.h>
  38 #include <linux/delay.h>
  39 #include <linux/errno.h>
  40 #include <linux/err.h>
  41 #include <linux/sched.h>
  42 #include <linux/slab.h>
  43 #include <linux/types.h>
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/compatmac.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/bitops.h>
  50 #include <linux/leds.h>
  51 #include <asm/io.h>
  52
  53 #ifdef CONFIG_MTD_PARTITIONS
  54 #include <linux/mtd/partitions.h>
  55 #endif
  56
  57 #endif
  58
  59 #include <common.h>
  60
  61 #define ENOTSUPP        524     /* Operation is not supported */
  62
  63 #include <malloc.h>
  64 #include <watchdog.h>
  65 #include <linux/err.h>
  66 #include <linux/mtd/compat.h>
  67 #include <linux/mtd/mtd.h>
  68 #include <linux/mtd/nand.h>
  69 #include <linux/mtd/nand_ecc.h>
  70
  71 #ifdef CONFIG_MTD_PARTITIONS
  72 #include <linux/mtd/partitions.h>
  73 #endif
  74
  75 #include <asm/io.h>
  76 #include <asm/errno.h>
  77
  78 #ifdef CONFIG_JFFS2_NAND
  79 #include <jffs2/jffs2.h>
  80 #endif
  81
  82 /*
  83  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  84  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  85  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  86  * which is greater than (max NAND reset time / NAND status read time).
  87  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  88  */
  89 #ifndef CONFIG_SYS_NAND_RESET_CNT
  90 #define CONFIG_SYS_NAND_RESET_CNT 200000
  91 #endif
  92
  93 /* Define default oob placement schemes for large and small page devices */
  94 static struct nand_ecclayout nand_oob_8 = {
  95         .eccbytes = 3,
  96         .eccpos = {0, 1, 2},
  97         .oobfree = {
  98                 {.offset = 3,
  99                  .length = 2},
 100                 {.offset = 6,
 101                  .length = 2}}
 102 };
 103
 104 static struct nand_ecclayout nand_oob_16 = {
 105         .eccbytes = 6,
 106         .eccpos = {0, 1, 2, 3, 6, 7},
 107         .oobfree = {
 108                 {.offset = 8,
 109                  . length = 8}}
 110 };
 111
 112 static struct nand_ecclayout nand_oob_64 = {
 113         .eccbytes = 24,
 114         .eccpos = {
 115                    40, 41, 42, 43, 44, 45, 46, 47,
 116                    48, 49, 50, 51, 52, 53, 54, 55,
 117                    56, 57, 58, 59, 60, 61, 62, 63},
 118         .oobfree = {
 119                 {.offset = 2,
 120                  .length = 38}}
 121 };
 122
 123 static struct nand_ecclayout nand_oob_128 = {
 124         .eccbytes = 48,
 125         .eccpos = {
 126                     80,  81,  82,  83,  84,  85,  86,  87,
 127                     88,  89,  90,  91,  92,  93,  94,  95,
 128                     96,  97,  98,  99, 100, 101, 102, 103,
 129                    104, 105, 106, 107, 108, 109, 110, 111,
 130                    112, 113, 114, 115, 116, 117, 118, 119,
 131                    120, 121, 122, 123, 124, 125, 126, 127},
 132         .oobfree = {
 133                 {.offset = 2,
 134                  .length = 78}}
 135 };
 136
 137
 138 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 139                            int new_state);
 140
 141 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 142                              struct mtd_oob_ops *ops);
 143
 144 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 145
 146 /*
 147  * For devices which display every fart in the system on a separate LED. Is
 148  * compiled away when LED support is disabled.
 149  */
 150 /* XXX U-BOOT XXX */
 151 #if 0
 152 DEFINE_LED_TRIGGER(nand_led_trigger);
 153 #endif
 154
 155 /**
 156  * nand_release_device - [GENERIC] release chip
 157  * @mtd:        MTD device structure
 158  *
 159  * Deselect, release chip lock and wake up anyone waiting on the device
 160  */
 161 /* XXX U-BOOT XXX */
 162 #if 0
 163 static void nand_release_device(struct mtd_info *mtd)
 164 {
 165         struct nand_chip *chip = mtd->priv;
 166
 167         /* De-select the NAND device */
 168         chip->select_chip(mtd, -1);
 169
 170         /* Release the controller and the chip */
 171         spin_lock(&chip->controller->lock);
 172         chip->controller->active = NULL;
 173         chip->state = FL_READY;
 174         wake_up(&chip->controller->wq);
 175         spin_unlock(&chip->controller->lock);
 176 }
 177 #else
 178 static void nand_release_device (struct mtd_info *mtd)
 179 {
 180         struct nand_chip *this = mtd->priv;
 181         this->select_chip(mtd, -1);     /* De-select the NAND device */
 182 }
 183 #endif
 184
 185 /**
 186  * nand_read_byte - [DEFAULT] read one byte from the chip
 187  * @mtd:        MTD device structure
 188  *
 189  * Default read function for 8bit buswith
 190  */
 191 static uint8_t nand_read_byte(struct mtd_info *mtd)
 192 {
 193         struct nand_chip *chip = mtd->priv;
 194         return readb(chip->IO_ADDR_R);
 195 }
 196
 197 /**
 198  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 199  * @mtd:        MTD device structure
 200  *
 201  * Default read function for 16bit buswith with
 202  * endianess conversion
 203  */
 204 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 205 {
 206         struct nand_chip *chip = mtd->priv;
 207         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 208 }
 209
 210 /**
 211  * nand_read_word - [DEFAULT] read one word from the chip
 212  * @mtd:        MTD device structure
 213  *
 214  * Default read function for 16bit buswith without
 215  * endianess conversion
 216  */
 217 static u16 nand_read_word(struct mtd_info *mtd)
 218 {
 219         struct nand_chip *chip = mtd->priv;
 220         return readw(chip->IO_ADDR_R);
 221 }
 222
 223 /**
 224  * nand_select_chip - [DEFAULT] control CE line
 225  * @mtd:        MTD device structure
 226  * @chipnr:     chipnumber to select, -1 for deselect
 227  *
 228  * Default select function for 1 chip devices.
 229  */
 230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 231 {
 232         struct nand_chip *chip = mtd->priv;
 233
 234         switch (chipnr) {
 235         case -1:
 236                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 237                 break;
 238         case 0:
 239                 break;
 240
 241         default:
 242                 BUG();
 243         }
 244 }
 245
 246 /**
 247  * nand_write_buf - [DEFAULT] write buffer to chip
 248  * @mtd:        MTD device structure
 249  * @buf:        data buffer
 250  * @len:        number of bytes to write
 251  *
 252  * Default write function for 8bit buswith
 253  */
 254 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 255 {
 256         int i;
 257         struct nand_chip *chip = mtd->priv;
 258
 259         for (i = 0; i < len; i++)
 260                 writeb(buf[i], chip->IO_ADDR_W);
 261 }
 262
 263 /**
 264  * nand_read_buf - [DEFAULT] read chip data into buffer
 265  * @mtd:        MTD device structure
 266  * @buf:        buffer to store date
 267  * @len:        number of bytes to read
 268  *
 269  * Default read function for 8bit buswith
 270  */
 271 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 272 {
 273         int i;
 274         struct nand_chip *chip = mtd->priv;
 275
 276         for (i = 0; i < len; i++)
 277                 buf[i] = readb(chip->IO_ADDR_R);
 278 }
 279
 280 /**
 281  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 282  * @mtd:        MTD device structure
 283  * @buf:        buffer containing the data to compare
 284  * @len:        number of bytes to compare
 285  *
 286  * Default verify function for 8bit buswith
 287  */
 288 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 289 {
 290         int i;
 291         struct nand_chip *chip = mtd->priv;
 292
 293         for (i = 0; i < len; i++)
 294                 if (buf[i] != readb(chip->IO_ADDR_R))
 295                         return -EFAULT;
 296         return 0;
 297 }
 298
 299 /**
 300  * nand_write_buf16 - [DEFAULT] write buffer to chip
 301  * @mtd:        MTD device structure
 302  * @buf:        data buffer
 303  * @len:        number of bytes to write
 304  *
 305  * Default write function for 16bit buswith
 306  */
 307 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 308 {
 309         int i;
 310         struct nand_chip *chip = mtd->priv;
 311         u16 *p = (u16 *) buf;
 312         len >>= 1;
 313
 314         for (i = 0; i < len; i++)
 315                 writew(p[i], chip->IO_ADDR_W);
 316
 317 }
 318
 319 /**
 320  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 321  * @mtd:        MTD device structure
 322  * @buf:        buffer to store date
 323  * @len:        number of bytes to read
 324  *
 325  * Default read function for 16bit buswith
 326  */
 327 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 328 {
 329         int i;
 330         struct nand_chip *chip = mtd->priv;
 331         u16 *p = (u16 *) buf;
 332         len >>= 1;
 333
 334         for (i = 0; i < len; i++)
 335                 p[i] = readw(chip->IO_ADDR_R);
 336 }
 337
 338 /**
 339  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 340  * @mtd:        MTD device structure
 341  * @buf:        buffer containing the data to compare
 342  * @len:        number of bytes to compare
 343  *
 344  * Default verify function for 16bit buswith
 345  */
 346 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 347 {
 348         int i;
 349         struct nand_chip *chip = mtd->priv;
 350         u16 *p = (u16 *) buf;
 351         len >>= 1;
 352
 353         for (i = 0; i < len; i++)
 354                 if (p[i] != readw(chip->IO_ADDR_R))
 355                         return -EFAULT;
 356
 357         return 0;
 358 }
 359
 360 /**
 361  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 362  * @mtd:        MTD device structure
 363  * @ofs:        offset from device start
 364  * @getchip:    0, if the chip is already selected
 365  *
 366  * Check, if the block is bad.
 367  */
 368 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 369 {
 370         int page, chipnr, res = 0;
 371         struct nand_chip *chip = mtd->priv;
 372         u16 bad;
 373
 374         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 375
 376         if (getchip) {
 377                 chipnr = (int)(ofs >> chip->chip_shift);
 378
 379                 nand_get_device(chip, mtd, FL_READING);
 380
 381                 /* Select the NAND device */
 382                 chip->select_chip(mtd, chipnr);
 383         }
 384
 385         if (chip->options & NAND_BUSWIDTH_16) {
 386                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 387                               page);
 388                 bad = cpu_to_le16(chip->read_word(mtd));
 389                 if (chip->badblockpos & 0x1)
 390                         bad >>= 8;
 391                 if ((bad & 0xFF) != 0xff)
 392                         res = 1;
 393         } else {
 394                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 395                 if (chip->read_byte(mtd) != 0xff)
 396                         res = 1;
 397         }
 398
 399         if (getchip)
 400                 nand_release_device(mtd);
 401
 402         return res;
 403 }
 404
 405 /**
 406  * nand_default_block_markbad - [DEFAULT] mark a block bad
 407  * @mtd:        MTD device structure
 408  * @ofs:        offset from device start
 409  *
 410  * This is the default implementation, which can be overridden by
 411  * a hardware specific driver.
 412 */
 413 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 414 {
 415         struct nand_chip *chip = mtd->priv;
 416         uint8_t buf[2] = { 0, 0 };
 417         int block, ret;
 418
 419         /* Get block number */
 420         block = (int)(ofs >> chip->bbt_erase_shift);
 421         if (chip->bbt)
 422                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 423
 424         /* Do we have a flash based bad block table ? */
 425         if (chip->options & NAND_USE_FLASH_BBT)
 426                 ret = nand_update_bbt(mtd, ofs);
 427         else {
 428                 /* We write two bytes, so we dont have to mess with 16 bit
 429                  * access
 430                  */
 431                 nand_get_device(chip, mtd, FL_WRITING);
 432                 ofs += mtd->oobsize;
 433                 chip->ops.len = chip->ops.ooblen = 2;
 434                 chip->ops.datbuf = NULL;
 435                 chip->ops.oobbuf = buf;
 436                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 437
 438                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 439                 nand_release_device(mtd);
 440         }
 441         if (!ret)
 442                 mtd->ecc_stats.badblocks++;
 443
 444         return ret;
 445 }
 446
 447 /**
 448  * nand_check_wp - [GENERIC] check if the chip is write protected
 449  * @mtd:        MTD device structure
 450  * Check, if the device is write protected
 451  *
 452  * The function expects, that the device is already selected
 453  */
 454 static int nand_check_wp(struct mtd_info *mtd)
 455 {
 456         struct nand_chip *chip = mtd->priv;
 457         /* Check the WP bit */
 458         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 459         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 460 }
 461
 462 /**
 463  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 464  * @mtd:        MTD device structure
 465  * @ofs:        offset from device start
 466  * @getchip:    0, if the chip is already selected
 467  * @allowbbt:   1, if its allowed to access the bbt area
 468  *
 469  * Check, if the block is bad. Either by reading the bad block table or
 470  * calling of the scan function.
 471  */
 472 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 473                                int allowbbt)
 474 {
 475         struct nand_chip *chip = mtd->priv;
 476
 477         if (!(chip->options & NAND_BBT_SCANNED)) {
 478                 chip->options |= NAND_BBT_SCANNED;
 479                 chip->scan_bbt(mtd);
 480         }
 481
 482         if (!chip->bbt)
 483                 return chip->block_bad(mtd, ofs, getchip);
 484
 485         /* Return info from the table */
 486         return nand_isbad_bbt(mtd, ofs, allowbbt);
 487 }
 488
 489 /*
 490  * Wait for the ready pin, after a command
 491  * The timeout is catched later.
 492  */
 493 /* XXX U-BOOT XXX */
 494 #if 0
 495 void nand_wait_ready(struct mtd_info *mtd)
 496 {
 497         struct nand_chip *chip = mtd->priv;
 498         unsigned long timeo = jiffies + 2;
 499
 500         led_trigger_event(nand_led_trigger, LED_FULL);
 501         /* wait until command is processed or timeout occures */
 502         do {
 503                 if (chip->dev_ready(mtd))
 504                         break;
 505                 touch_softlockup_watchdog();
 506         } while (time_before(jiffies, timeo));
 507         led_trigger_event(nand_led_trigger, LED_OFF);
 508 }
 509 EXPORT_SYMBOL_GPL(nand_wait_ready);
 510 #else
 511 void nand_wait_ready(struct mtd_info *mtd)
 512 {
 513         struct nand_chip *chip = mtd->priv;
 514         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 515
 516         reset_timer();
 517
 518         /* wait until command is processed or timeout occures */
 519         while (get_timer(0) < timeo) {
 520                 if (chip->dev_ready)
 521                         if (chip->dev_ready(mtd))
 522                                 break;
 523         }
 524 }
 525 #endif
 526
 527 /**
 528  * nand_command - [DEFAULT] Send command to NAND device
 529  * @mtd:        MTD device structure
 530  * @command:    the command to be sent
 531  * @column:     the column address for this command, -1 if none
 532  * @page_addr:  the page address for this command, -1 if none
 533  *
 534  * Send command to NAND device. This function is used for small page
 535  * devices (256/512 Bytes per page)
 536  */
 537 static void nand_command(struct mtd_info *mtd, unsigned int command,
 538                          int column, int page_addr)
 539 {
 540         register struct nand_chip *chip = mtd->priv;
 541         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 542         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 543
 544         /*
 545          * Write out the command to the device.
 546          */
 547         if (command == NAND_CMD_SEQIN) {
 548                 int readcmd;
 549
 550                 if (column >= mtd->writesize) {
 551                         /* OOB area */
 552                         column -= mtd->writesize;
 553                         readcmd = NAND_CMD_READOOB;
 554                 } else if (column < 256) {
 555                         /* First 256 bytes --> READ0 */
 556                         readcmd = NAND_CMD_READ0;
 557                 } else {
 558                         column -= 256;
 559                         readcmd = NAND_CMD_READ1;
 560                 }
 561                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 562                 ctrl &= ~NAND_CTRL_CHANGE;
 563         }
 564         chip->cmd_ctrl(mtd, command, ctrl);
 565
 566         /*
 567          * Address cycle, when necessary
 568          */
 569         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 570         /* Serially input address */
 571         if (column != -1) {
 572                 /* Adjust columns for 16 bit buswidth */
 573                 if (chip->options & NAND_BUSWIDTH_16)
 574                         column >>= 1;
 575                 chip->cmd_ctrl(mtd, column, ctrl);
 576                 ctrl &= ~NAND_CTRL_CHANGE;
 577         }
 578         if (page_addr != -1) {
 579                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 580                 ctrl &= ~NAND_CTRL_CHANGE;
 581                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 582                 /* One more address cycle for devices > 32MiB */
 583                 if (chip->chipsize > (32 << 20))
 584                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 585         }
 586         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587
 588         /*
 589          * program and erase have their own busy handlers
 590          * status and sequential in needs no delay
 591          */
 592         switch (command) {
 593
 594         case NAND_CMD_PAGEPROG:
 595         case NAND_CMD_ERASE1:
 596         case NAND_CMD_ERASE2:
 597         case NAND_CMD_SEQIN:
 598         case NAND_CMD_STATUS:
 599                 return;
 600
 601         case NAND_CMD_RESET:
 602                 if (chip->dev_ready)
 603                         break;
 604                 udelay(chip->chip_delay);
 605                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 606                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 607                 chip->cmd_ctrl(mtd,
 608                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 609                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 610                         (rst_sts_cnt--));
 611                 return;
 612
 613                 /* This applies to read commands */
 614         default:
 615                 /*
 616                  * If we don't have access to the busy pin, we apply the given
 617                  * command delay
 618                  */
 619                 if (!chip->dev_ready) {
 620                         udelay(chip->chip_delay);
 621                         return;
 622                 }
 623         }
 624         /* Apply this short delay always to ensure that we do wait tWB in
 625          * any case on any machine. */
 626         ndelay(100);
 627
 628         nand_wait_ready(mtd);
 629 }
 630
 631 /**
 632  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 633  * @mtd:        MTD device structure
 634  * @command:    the command to be sent
 635  * @column:     the column address for this command, -1 if none
 636  * @page_addr:  the page address for this command, -1 if none
 637  *
 638  * Send command to NAND device. This is the version for the new large page
 639  * devices We dont have the separate regions as we have in the small page
 640  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 641  */
 642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 643                             int column, int page_addr)
 644 {
 645         register struct nand_chip *chip = mtd->priv;
 646         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 647
 648         /* Emulate NAND_CMD_READOOB */
 649         if (command == NAND_CMD_READOOB) {
 650                 column += mtd->writesize;
 651                 command = NAND_CMD_READ0;
 652         }
 653
 654         /* Command latch cycle */
 655         chip->cmd_ctrl(mtd, command & 0xff,
 656                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 657
 658         if (column != -1 || page_addr != -1) {
 659                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 660
 661                 /* Serially input address */
 662                 if (column != -1) {
 663                         /* Adjust columns for 16 bit buswidth */
 664                         if (chip->options & NAND_BUSWIDTH_16)
 665                                 column >>= 1;
 666                         chip->cmd_ctrl(mtd, column, ctrl);
 667                         ctrl &= ~NAND_CTRL_CHANGE;
 668                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 669                 }
 670                 if (page_addr != -1) {
 671                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 672                         chip->cmd_ctrl(mtd, page_addr >> 8,
 673                                        NAND_NCE | NAND_ALE);
 674                         /* One more address cycle for devices > 128MiB */
 675                         if (chip->chipsize > (128 << 20))
 676                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 677                                                NAND_NCE | NAND_ALE);
 678                 }
 679         }
 680         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 681
 682         /*
 683          * program and erase have their own busy handlers
 684          * status, sequential in, and deplete1 need no delay
 685          */
 686         switch (command) {
 687
 688         case NAND_CMD_CACHEDPROG:
 689         case NAND_CMD_PAGEPROG:
 690         case NAND_CMD_ERASE1:
 691         case NAND_CMD_ERASE2:
 692         case NAND_CMD_SEQIN:
 693         case NAND_CMD_RNDIN:
 694         case NAND_CMD_STATUS:
 695         case NAND_CMD_DEPLETE1:
 696                 return;
 697
 698                 /*
 699                  * read error status commands require only a short delay
 700                  */
 701         case NAND_CMD_STATUS_ERROR:
 702         case NAND_CMD_STATUS_ERROR0:
 703         case NAND_CMD_STATUS_ERROR1:
 704         case NAND_CMD_STATUS_ERROR2:
 705         case NAND_CMD_STATUS_ERROR3:
 706                 udelay(chip->chip_delay);
 707                 return;
 708
 709         case NAND_CMD_RESET:
 710                 if (chip->dev_ready)
 711                         break;
 712                 udelay(chip->chip_delay);
 713                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 714                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 715                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 716                                NAND_NCE | NAND_CTRL_CHANGE);
 717                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 718                         (rst_sts_cnt--));
 719                 return;
 720
 721         case NAND_CMD_RNDOUT:
 722                 /* No ready / busy check necessary */
 723                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 724                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 725                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 726                                NAND_NCE | NAND_CTRL_CHANGE);
 727                 return;
 728
 729         case NAND_CMD_READ0:
 730                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 731                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 732                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 733                                NAND_NCE | NAND_CTRL_CHANGE);
 734
 735                 /* This applies to read commands */
 736         default:
 737                 /*
 738                  * If we don't have access to the busy pin, we apply the given
 739                  * command delay
 740                  */
 741                 if (!chip->dev_ready) {
 742                         udelay(chip->chip_delay);
 743                         return;
 744                 }
 745         }
 746
 747         /* Apply this short delay always to ensure that we do wait tWB in
 748          * any case on any machine. */
 749         ndelay(100);
 750
 751         nand_wait_ready(mtd);
 752 }
 753
 754 /**
 755  * nand_get_device - [GENERIC] Get chip for selected access
 756  * @chip:       the nand chip descriptor
 757  * @mtd:        MTD device structure
 758  * @new_state:  the state which is requested
 759  *
 760  * Get the device and lock it for exclusive access
 761  */
 762 /* XXX U-BOOT XXX */
 763 #if 0
 764 static int
 765 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 766 {
 767         spinlock_t *lock = &chip->controller->lock;
 768         wait_queue_head_t *wq = &chip->controller->wq;
 769         DECLARE_WAITQUEUE(wait, current);
 770  retry:
 771         spin_lock(lock);
 772
 773         /* Hardware controller shared among independend devices */
 774         /* Hardware controller shared among independend devices */
 775         if (!chip->controller->active)
 776                 chip->controller->active = chip;
 777
 778         if (chip->controller->active == chip && chip->state == FL_READY) {
 779                 chip->state = new_state;
 780                 spin_unlock(lock);
 781                 return 0;
 782         }
 783         if (new_state == FL_PM_SUSPENDED) {
 784                 spin_unlock(lock);
 785                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 786         }
 787         set_current_state(TASK_UNINTERRUPTIBLE);
 788         add_wait_queue(wq, &wait);
 789         spin_unlock(lock);
 790         schedule();
 791         remove_wait_queue(wq, &wait);
 792         goto retry;
 793 }
 794 #else
 795 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 796 {
 797         this->state = new_state;
 798         return 0;
 799 }
 800 #endif
 801
 802 /**
 803  * nand_wait - [DEFAULT]  wait until the command is done
 804  * @mtd:        MTD device structure
 805  * @chip:       NAND chip structure
 806  *
 807  * Wait for command done. This applies to erase and program only
 808  * Erase can take up to 400ms and program up to 20ms according to
 809  * general NAND and SmartMedia specs
 810  */
 811 /* XXX U-BOOT XXX */
 812 #if 0
 813 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 814 {
 815
 816         unsigned long timeo = jiffies;
 817         int status, state = chip->state;
 818
 819         if (state == FL_ERASING)
 820                 timeo += (HZ * 400) / 1000;
 821         else
 822                 timeo += (HZ * 20) / 1000;
 823
 824         led_trigger_event(nand_led_trigger, LED_FULL);
 825
 826         /* Apply this short delay always to ensure that we do wait tWB in
 827          * any case on any machine. */
 828         ndelay(100);
 829
 830         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 831                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 832         else
 833                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 834
 835         while (time_before(jiffies, timeo)) {
 836                 if (chip->dev_ready) {
 837                         if (chip->dev_ready(mtd))
 838                                 break;
 839                 } else {
 840                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 841                                 break;
 842                 }
 843                 cond_resched();
 844         }
 845         led_trigger_event(nand_led_trigger, LED_OFF);
 846
 847         status = (int)chip->read_byte(mtd);
 848         return status;
 849 }
 850 #else
 851 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 852 {
 853         unsigned long   timeo;
 854         int state = this->state;
 855
 856         if (state == FL_ERASING)
 857                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 858         else
 859                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 860
 861         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 862                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 863         else
 864                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 865
 866         reset_timer();
 867
 868         while (1) {
 869                 if (get_timer(0) > timeo) {
 870                         printf("Timeout!");
 871                         return 0x01;
 872                 }
 873
 874                 if (this->dev_ready) {
 875                         if (this->dev_ready(mtd))
 876                                 break;
 877                 } else {
 878                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 879                                 break;
 880                 }
 881         }
 882 #ifdef PPCHAMELON_NAND_TIMER_HACK
 883         reset_timer();
 884         while (get_timer(0) < 10);
 885 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 886
 887         return this->read_byte(mtd);
 888 }
 889 #endif
 890
 891 /**
 892  * nand_read_page_raw - [Intern] read raw page data without ecc
 893  * @mtd:        mtd info structure
 894  * @chip:       nand chip info structure
 895  * @buf:        buffer to store read data
 896  * @page:       page number to read
 897  *
 898  * Not for syndrome calculating ecc controllers, which use a special oob layout
 899  */
 900 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 901                               uint8_t *buf, int page)
 902 {
 903         chip->read_buf(mtd, buf, mtd->writesize);
 904         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 905         return 0;
 906 }
 907
 908 /**
 909  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 910  * @mtd:        mtd info structure
 911  * @chip:       nand chip info structure
 912  * @buf:        buffer to store read data
 913  * @page:       page number to read
 914  *
 915  * We need a special oob layout and handling even when OOB isn't used.
 916  */
 917 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 918                               uint8_t *buf, int page)
 919 {
 920         int eccsize = chip->ecc.size;
 921         int eccbytes = chip->ecc.bytes;
 922         uint8_t *oob = chip->oob_poi;
 923         int steps, size;
 924
 925         for (steps = chip->ecc.steps; steps > 0; steps--) {
 926                 chip->read_buf(mtd, buf, eccsize);
 927                 buf += eccsize;
 928
 929                 if (chip->ecc.prepad) {
 930                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 931                         oob += chip->ecc.prepad;
 932                 }
 933
 934                 chip->read_buf(mtd, oob, eccbytes);
 935                 oob += eccbytes;
 936
 937                 if (chip->ecc.postpad) {
 938                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 939                         oob += chip->ecc.postpad;
 940                 }
 941         }
 942
 943         size = mtd->oobsize - (oob - chip->oob_poi);
 944         if (size)
 945                 chip->read_buf(mtd, oob, size);
 946
 947         return 0;
 948 }
 949
 950 /**
 951  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 952  * @mtd:        mtd info structure
 953  * @chip:       nand chip info structure
 954  * @buf:        buffer to store read data
 955  * @page:       page number to read
 956  */
 957 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 958                                 uint8_t *buf, int page)
 959 {
 960         int i, eccsize = chip->ecc.size;
 961         int eccbytes = chip->ecc.bytes;
 962         int eccsteps = chip->ecc.steps;
 963         uint8_t *p = buf;
 964         uint8_t *ecc_calc = chip->buffers->ecccalc;
 965         uint8_t *ecc_code = chip->buffers->ecccode;
 966         uint32_t *eccpos = chip->ecc.layout->eccpos;
 967
 968         chip->ecc.read_page_raw(mtd, chip, buf, page);
 969
 970         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 971                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 972
 973         for (i = 0; i < chip->ecc.total; i++)
 974                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 975
 976         eccsteps = chip->ecc.steps;
 977         p = buf;
 978
 979         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 980                 int stat;
 981
 982                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 983                 if (stat < 0)
 984                         mtd->ecc_stats.failed++;
 985                 else
 986                         mtd->ecc_stats.corrected += stat;
 987         }
 988         return 0;
 989 }
 990
 991 /**
 992  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 993  * @mtd:        mtd info structure
 994  * @chip:       nand chip info structure
 995  * @data_offs:  offset of requested data within the page
 996  * @readlen:    data length
 997  * @bufpoi:     buffer to store read data
 998  */
 999 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1000 {
1001         int start_step, end_step, num_steps;
1002         uint32_t *eccpos = chip->ecc.layout->eccpos;
1003         uint8_t *p;
1004         int data_col_addr, i, gaps = 0;
1005         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1006         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1007
1008         /* Column address wihin the page aligned to ECC size (256bytes). */
1009         start_step = data_offs / chip->ecc.size;
1010         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1011         num_steps = end_step - start_step + 1;
1012
1013         /* Data size aligned to ECC ecc.size*/
1014         datafrag_len = num_steps * chip->ecc.size;
1015         eccfrag_len = num_steps * chip->ecc.bytes;
1016
1017         data_col_addr = start_step * chip->ecc.size;
1018         /* If we read not a page aligned data */
1019         if (data_col_addr != 0)
1020                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1021
1022         p = bufpoi + data_col_addr;
1023         chip->read_buf(mtd, p, datafrag_len);
1024
1025         /* Calculate  ECC */
1026         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1027                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1028
1029         /* The performance is faster if to position offsets
1030            according to ecc.pos. Let make sure here that
1031            there are no gaps in ecc positions */
1032         for (i = 0; i < eccfrag_len - 1; i++) {
1033                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1034                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1035                         gaps = 1;
1036                         break;
1037                 }
1038         }
1039         if (gaps) {
1040                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1041                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1042         } else {
1043                 /* send the command to read the particular ecc bytes */
1044                 /* take care about buswidth alignment in read_buf */
1045                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1046                 aligned_len = eccfrag_len;
1047                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1048                         aligned_len++;
1049                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1050                         aligned_len++;
1051
1052                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1053                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1054         }
1055
1056         for (i = 0; i < eccfrag_len; i++)
1057                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1058
1059         p = bufpoi + data_col_addr;
1060         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1061                 int stat;
1062
1063                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1064                 if (stat == -1)
1065                         mtd->ecc_stats.failed++;
1066                 else
1067                         mtd->ecc_stats.corrected += stat;
1068         }
1069         return 0;
1070 }
1071
1072 /**
1073  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1074  * @mtd:        mtd info structure
1075  * @chip:       nand chip info structure
1076  * @buf:        buffer to store read data
1077  * @page:       page number to read
1078  *
1079  * Not for syndrome calculating ecc controllers which need a special oob layout
1080  */
1081 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1082                                 uint8_t *buf, int page)
1083 {
1084         int i, eccsize = chip->ecc.size;
1085         int eccbytes = chip->ecc.bytes;
1086         int eccsteps = chip->ecc.steps;
1087         uint8_t *p = buf;
1088         uint8_t *ecc_calc = chip->buffers->ecccalc;
1089         uint8_t *ecc_code = chip->buffers->ecccode;
1090         uint32_t *eccpos = chip->ecc.layout->eccpos;
1091
1092         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1093                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1094                 chip->read_buf(mtd, p, eccsize);
1095                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1096         }
1097         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1098
1099         for (i = 0; i < chip->ecc.total; i++)
1100                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1101
1102         eccsteps = chip->ecc.steps;
1103         p = buf;
1104
1105         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1106                 int stat;
1107
1108                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1109                 if (stat < 0)
1110                         mtd->ecc_stats.failed++;
1111                 else
1112                         mtd->ecc_stats.corrected += stat;
1113         }
1114         return 0;
1115 }
1116
1117 /**
1118  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1119  * @mtd:        mtd info structure
1120  * @chip:       nand chip info structure
1121  * @buf:        buffer to store read data
1122  * @page:       page number to read
1123  *
1124  * Hardware ECC for large page chips, require OOB to be read first.
1125  * For this ECC mode, the write_page method is re-used from ECC_HW.
1126  * These methods read/write ECC from the OOB area, unlike the
1127  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1128  * "infix ECC" scheme and reads/writes ECC from the data area, by
1129  * overwriting the NAND manufacturer bad block markings.
1130  */
1131 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1132         struct nand_chip *chip, uint8_t *buf, int page)
1133 {
1134         int i, eccsize = chip->ecc.size;
1135         int eccbytes = chip->ecc.bytes;
1136         int eccsteps = chip->ecc.steps;
1137         uint8_t *p = buf;
1138         uint8_t *ecc_code = chip->buffers->ecccode;
1139         uint32_t *eccpos = chip->ecc.layout->eccpos;
1140         uint8_t *ecc_calc = chip->buffers->ecccalc;
1141
1142         /* Read the OOB area first */
1143         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1144         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1145         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1146
1147         for (i = 0; i < chip->ecc.total; i++)
1148                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1149
1150         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1151                 int stat;
1152
1153                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1154                 chip->read_buf(mtd, p, eccsize);
1155                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1156
1157                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1158                 if (stat < 0)
1159                         mtd->ecc_stats.failed++;
1160                 else
1161                         mtd->ecc_stats.corrected += stat;
1162         }
1163         return 0;
1164 }
1165
1166 /**
1167  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1168  * @mtd:        mtd info structure
1169  * @chip:       nand chip info structure
1170  * @buf:        buffer to store read data
1171  * @page:       page number to read
1172  *
1173  * The hw generator calculates the error syndrome automatically. Therefor
1174  * we need a special oob layout and handling.
1175  */
1176 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1177                                    uint8_t *buf, int page)
1178 {
1179         int i, eccsize = chip->ecc.size;
1180         int eccbytes = chip->ecc.bytes;
1181         int eccsteps = chip->ecc.steps;
1182         uint8_t *p = buf;
1183         uint8_t *oob = chip->oob_poi;
1184
1185         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1186                 int stat;
1187
1188                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1189                 chip->read_buf(mtd, p, eccsize);
1190
1191                 if (chip->ecc.prepad) {
1192                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1193                         oob += chip->ecc.prepad;
1194                 }
1195
1196                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1197                 chip->read_buf(mtd, oob, eccbytes);
1198                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1199
1200                 if (stat < 0)
1201                         mtd->ecc_stats.failed++;
1202                 else
1203                         mtd->ecc_stats.corrected += stat;
1204
1205                 oob += eccbytes;
1206
1207                 if (chip->ecc.postpad) {
1208                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1209                         oob += chip->ecc.postpad;
1210                 }
1211         }
1212
1213         /* Calculate remaining oob bytes */
1214         i = mtd->oobsize - (oob - chip->oob_poi);
1215         if (i)
1216                 chip->read_buf(mtd, oob, i);
1217
1218         return 0;
1219 }
1220
1221 /**
1222  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1223  * @chip:       nand chip structure
1224  * @oob:        oob destination address
1225  * @ops:        oob ops structure
1226  * @len:        size of oob to transfer
1227  */
1228 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1229                                   struct mtd_oob_ops *ops, size_t len)
1230 {
1231         switch(ops->mode) {
1232
1233         case MTD_OOB_PLACE:
1234         case MTD_OOB_RAW:
1235                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1236                 return oob + len;
1237
1238         case MTD_OOB_AUTO: {
1239                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1240                 uint32_t boffs = 0, roffs = ops->ooboffs;
1241                 size_t bytes = 0;
1242
1243                 for(; free->length && len; free++, len -= bytes) {
1244                         /* Read request not from offset 0 ? */
1245                         if (unlikely(roffs)) {
1246                                 if (roffs >= free->length) {
1247                                         roffs -= free->length;
1248                                         continue;
1249                                 }
1250                                 boffs = free->offset + roffs;
1251                                 bytes = min_t(size_t, len,
1252                                               (free->length - roffs));
1253                                 roffs = 0;
1254                         } else {
1255                                 bytes = min_t(size_t, len, free->length);
1256                                 boffs = free->offset;
1257                         }
1258                         memcpy(oob, chip->oob_poi + boffs, bytes);
1259                         oob += bytes;
1260                 }
1261                 return oob;
1262         }
1263         default:
1264                 BUG();
1265         }
1266         return NULL;
1267 }
1268
1269 /**
1270  * nand_do_read_ops - [Internal] Read data with ECC
1271  *
1272  * @mtd:        MTD device structure
1273  * @from:       offset to read from
1274  * @ops:        oob ops structure
1275  *
1276  * Internal function. Called with chip held.
1277  */
1278 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1279                             struct mtd_oob_ops *ops)
1280 {
1281         int chipnr, page, realpage, col, bytes, aligned;
1282         struct nand_chip *chip = mtd->priv;
1283         struct mtd_ecc_stats stats;
1284         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1285         int sndcmd = 1;
1286         int ret = 0;
1287         uint32_t readlen = ops->len;
1288         uint32_t oobreadlen = ops->ooblen;
1289         uint8_t *bufpoi, *oob, *buf;
1290
1291         stats = mtd->ecc_stats;
1292
1293         chipnr = (int)(from >> chip->chip_shift);
1294         chip->select_chip(mtd, chipnr);
1295
1296         realpage = (int)(from >> chip->page_shift);
1297         page = realpage & chip->pagemask;
1298
1299         col = (int)(from & (mtd->writesize - 1));
1300
1301         buf = ops->datbuf;
1302         oob = ops->oobbuf;
1303
1304         while(1) {
1305                 bytes = min(mtd->writesize - col, readlen);
1306                 aligned = (bytes == mtd->writesize);
1307
1308                 /* Is the current page in the buffer ? */
1309                 if (realpage != chip->pagebuf || oob) {
1310                         bufpoi = aligned ? buf : chip->buffers->databuf;
1311
1312                         if (likely(sndcmd)) {
1313                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1314                                 sndcmd = 0;
1315                         }
1316
1317                         /* Now read the page into the buffer */
1318                         if (unlikely(ops->mode == MTD_OOB_RAW))
1319                                 ret = chip->ecc.read_page_raw(mtd, chip,
1320                                                 bufpoi, page);
1321                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1322                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1323                         else
1324                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1325                                                 page);
1326                         if (ret < 0)
1327                                 break;
1328
1329                         /* Transfer not aligned data */
1330                         if (!aligned) {
1331                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1332                                         chip->pagebuf = realpage;
1333                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1334                         }
1335
1336                         buf += bytes;
1337
1338                         if (unlikely(oob)) {
1339                                 /* Raw mode does data:oob:data:oob */
1340                                 if (ops->mode != MTD_OOB_RAW) {
1341                                         int toread = min(oobreadlen,
1342                                                 chip->ecc.layout->oobavail);
1343                                         if (toread) {
1344                                                 oob = nand_transfer_oob(chip,
1345                                                         oob, ops, toread);
1346                                                 oobreadlen -= toread;
1347                                         }
1348                                 } else
1349                                         buf = nand_transfer_oob(chip,
1350                                                 buf, ops, mtd->oobsize);
1351                         }
1352
1353                         if (!(chip->options & NAND_NO_READRDY)) {
1354                                 /*
1355                                  * Apply delay or wait for ready/busy pin. Do
1356                                  * this before the AUTOINCR check, so no
1357                                  * problems arise if a chip which does auto
1358                                  * increment is marked as NOAUTOINCR by the
1359                                  * board driver.
1360                                  */
1361                                 if (!chip->dev_ready)
1362                                         udelay(chip->chip_delay);
1363                                 else
1364                                         nand_wait_ready(mtd);
1365                         }
1366                 } else {
1367                         memcpy(buf, chip->buffers->databuf + col, bytes);
1368                         buf += bytes;
1369                 }
1370
1371                 readlen -= bytes;
1372
1373                 if (!readlen)
1374                         break;
1375
1376                 /* For subsequent reads align to page boundary. */
1377                 col = 0;
1378                 /* Increment page address */
1379                 realpage++;
1380
1381                 page = realpage & chip->pagemask;
1382                 /* Check, if we cross a chip boundary */
1383                 if (!page) {
1384                         chipnr++;
1385                         chip->select_chip(mtd, -1);
1386                         chip->select_chip(mtd, chipnr);
1387                 }
1388
1389                 /* Check, if the chip supports auto page increment
1390                  * or if we have hit a block boundary.
1391                  */
1392                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1393                         sndcmd = 1;
1394         }
1395
1396         ops->retlen = ops->len - (size_t) readlen;
1397         if (oob)
1398                 ops->oobretlen = ops->ooblen - oobreadlen;
1399
1400         if (ret)
1401                 return ret;
1402
1403         if (mtd->ecc_stats.failed - stats.failed)
1404                 return -EBADMSG;
1405
1406         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1407 }
1408
1409 /**
1410  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1411  * @mtd:        MTD device structure
1412  * @from:       offset to read from
1413  * @len:        number of bytes to read
1414  * @retlen:     pointer to variable to store the number of read bytes
1415  * @buf:        the databuffer to put data
1416  *
1417  * Get hold of the chip and call nand_do_read
1418  */
1419 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1420                      size_t *retlen, uint8_t *buf)
1421 {
1422         struct nand_chip *chip = mtd->priv;
1423         int ret;
1424
1425         /* Do not allow reads past end of device */
1426         if ((from + len) > mtd->size)
1427                 return -EINVAL;
1428         if (!len)
1429                 return 0;
1430
1431         nand_get_device(chip, mtd, FL_READING);
1432
1433         chip->ops.len = len;
1434         chip->ops.datbuf = buf;
1435         chip->ops.oobbuf = NULL;
1436
1437         ret = nand_do_read_ops(mtd, from, &chip->ops);
1438
1439         *retlen = chip->ops.retlen;
1440
1441         nand_release_device(mtd);
1442
1443         return ret;
1444 }
1445
1446 /**
1447  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1448  * @mtd:        mtd info structure
1449  * @chip:       nand chip info structure
1450  * @page:       page number to read
1451  * @sndcmd:     flag whether to issue read command or not
1452  */
1453 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1454                              int page, int sndcmd)
1455 {
1456         if (sndcmd) {
1457                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1458                 sndcmd = 0;
1459         }
1460         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1461         return sndcmd;
1462 }
1463
1464 /**
1465  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1466  *                          with syndromes
1467  * @mtd:        mtd info structure
1468  * @chip:       nand chip info structure
1469  * @page:       page number to read
1470  * @sndcmd:     flag whether to issue read command or not
1471  */
1472 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1473                                   int page, int sndcmd)
1474 {
1475         uint8_t *buf = chip->oob_poi;
1476         int length = mtd->oobsize;
1477         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1478         int eccsize = chip->ecc.size;
1479         uint8_t *bufpoi = buf;
1480         int i, toread, sndrnd = 0, pos;
1481
1482         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1483         for (i = 0; i < chip->ecc.steps; i++) {
1484                 if (sndrnd) {
1485                         pos = eccsize + i * (eccsize + chunk);
1486                         if (mtd->writesize > 512)
1487                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1488                         else
1489                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1490                 } else
1491                         sndrnd = 1;
1492                 toread = min_t(int, length, chunk);
1493                 chip->read_buf(mtd, bufpoi, toread);
1494                 bufpoi += toread;
1495                 length -= toread;
1496         }
1497         if (length > 0)
1498                 chip->read_buf(mtd, bufpoi, length);
1499
1500         return 1;
1501 }
1502
1503 /**
1504  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1505  * @mtd:        mtd info structure
1506  * @chip:       nand chip info structure
1507  * @page:       page number to write
1508  */
1509 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1510                               int page)
1511 {
1512         int status = 0;
1513         const uint8_t *buf = chip->oob_poi;
1514         int length = mtd->oobsize;
1515
1516         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1517         chip->write_buf(mtd, buf, length);
1518         /* Send command to program the OOB data */
1519         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1520
1521         status = chip->waitfunc(mtd, chip);
1522
1523         return status & NAND_STATUS_FAIL ? -EIO : 0;
1524 }
1525
1526 /**
1527  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1528  *                           with syndrome - only for large page flash !
1529  * @mtd:        mtd info structure
1530  * @chip:       nand chip info structure
1531  * @page:       page number to write
1532  */
1533 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1534                                    struct nand_chip *chip, int page)
1535 {
1536         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1537         int eccsize = chip->ecc.size, length = mtd->oobsize;
1538         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1539         const uint8_t *bufpoi = chip->oob_poi;
1540
1541         /*
1542          * data-ecc-data-ecc ... ecc-oob
1543          * or
1544          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1545          */
1546         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1547                 pos = steps * (eccsize + chunk);
1548                 steps = 0;
1549         } else
1550                 pos = eccsize;
1551
1552         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1553         for (i = 0; i < steps; i++) {
1554                 if (sndcmd) {
1555                         if (mtd->writesize <= 512) {
1556                                 uint32_t fill = 0xFFFFFFFF;
1557
1558                                 len = eccsize;
1559                                 while (len > 0) {
1560                                         int num = min_t(int, len, 4);
1561                                         chip->write_buf(mtd, (uint8_t *)&fill,
1562                                                         num);
1563                                         len -= num;
1564                                 }
1565                         } else {
1566                                 pos = eccsize + i * (eccsize + chunk);
1567                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1568                         }
1569                 } else
1570                         sndcmd = 1;
1571                 len = min_t(int, length, chunk);
1572                 chip->write_buf(mtd, bufpoi, len);
1573                 bufpoi += len;
1574                 length -= len;
1575         }
1576         if (length > 0)
1577                 chip->write_buf(mtd, bufpoi, length);
1578
1579         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1580         status = chip->waitfunc(mtd, chip);
1581
1582         return status & NAND_STATUS_FAIL ? -EIO : 0;
1583 }
1584
1585 /**
1586  * nand_do_read_oob - [Intern] NAND read out-of-band
1587  * @mtd:        MTD device structure
1588  * @from:       offset to read from
1589  * @ops:        oob operations description structure
1590  *
1591  * NAND read out-of-band data from the spare area
1592  */
1593 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1594                             struct mtd_oob_ops *ops)
1595 {
1596         int page, realpage, chipnr, sndcmd = 1;
1597         struct nand_chip *chip = mtd->priv;
1598         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1599         int readlen = ops->ooblen;
1600         int len;
1601         uint8_t *buf = ops->oobbuf;
1602
1603         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1604                   (unsigned long long)from, readlen);
1605
1606         if (ops->mode == MTD_OOB_AUTO)
1607                 len = chip->ecc.layout->oobavail;
1608         else
1609                 len = mtd->oobsize;
1610
1611         if (unlikely(ops->ooboffs >= len)) {
1612                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1613                           "Attempt to start read outside oob\n");
1614                 return -EINVAL;
1615         }
1616
1617         /* Do not allow reads past end of device */
1618         if (unlikely(from >= mtd->size ||
1619                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1620                                         (from >> chip->page_shift)) * len)) {
1621                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1622                           "Attempt read beyond end of device\n");
1623                 return -EINVAL;
1624         }
1625
1626         chipnr = (int)(from >> chip->chip_shift);
1627         chip->select_chip(mtd, chipnr);
1628
1629         /* Shift to get page */
1630         realpage = (int)(from >> chip->page_shift);
1631         page = realpage & chip->pagemask;
1632
1633         while(1) {
1634                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1635
1636                 len = min(len, readlen);
1637                 buf = nand_transfer_oob(chip, buf, ops, len);
1638
1639                 if (!(chip->options & NAND_NO_READRDY)) {
1640                         /*
1641                          * Apply delay or wait for ready/busy pin. Do this
1642                          * before the AUTOINCR check, so no problems arise if a
1643                          * chip which does auto increment is marked as
1644                          * NOAUTOINCR by the board driver.
1645                          */
1646                         if (!chip->dev_ready)
1647                                 udelay(chip->chip_delay);
1648                         else
1649                                 nand_wait_ready(mtd);
1650                 }
1651
1652                 readlen -= len;
1653                 if (!readlen)
1654                         break;
1655
1656                 /* Increment page address */
1657                 realpage++;
1658
1659                 page = realpage & chip->pagemask;
1660                 /* Check, if we cross a chip boundary */
1661                 if (!page) {
1662                         chipnr++;
1663                         chip->select_chip(mtd, -1);
1664                         chip->select_chip(mtd, chipnr);
1665                 }
1666
1667                 /* Check, if the chip supports auto page increment
1668                  * or if we have hit a block boundary.
1669                  */
1670                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1671                         sndcmd = 1;
1672         }
1673
1674         ops->oobretlen = ops->ooblen;
1675         return 0;
1676 }
1677
1678 /**
1679  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1680  * @mtd:        MTD device structure
1681  * @from:       offset to read from
1682  * @ops:        oob operation description structure
1683  *
1684  * NAND read data and/or out-of-band data
1685  */
1686 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1687                          struct mtd_oob_ops *ops)
1688 {
1689         struct nand_chip *chip = mtd->priv;
1690         int ret = -ENOTSUPP;
1691
1692         ops->retlen = 0;
1693
1694         /* Do not allow reads past end of device */
1695         if (ops->datbuf && (from + ops->len) > mtd->size) {
1696                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1697                           "Attempt read beyond end of device\n");
1698                 return -EINVAL;
1699         }
1700
1701         nand_get_device(chip, mtd, FL_READING);
1702
1703         switch(ops->mode) {
1704         case MTD_OOB_PLACE:
1705         case MTD_OOB_AUTO:
1706         case MTD_OOB_RAW:
1707                 break;
1708
1709         default:
1710                 goto out;
1711         }
1712
1713         if (!ops->datbuf)
1714                 ret = nand_do_read_oob(mtd, from, ops);
1715         else
1716                 ret = nand_do_read_ops(mtd, from, ops);
1717
1718  out:
1719         nand_release_device(mtd);
1720         return ret;
1721 }
1722
1723
1724 /**
1725  * nand_write_page_raw - [Intern] raw page write function
1726  * @mtd:        mtd info structure
1727  * @chip:       nand chip info structure
1728  * @buf:        data buffer
1729  *
1730  * Not for syndrome calculating ecc controllers, which use a special oob layout
1731  */
1732 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1733                                 const uint8_t *buf)
1734 {
1735         chip->write_buf(mtd, buf, mtd->writesize);
1736         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1737 }
1738
1739 /**
1740  * nand_write_page_raw_syndrome - [Intern] raw page write function
1741  * @mtd:        mtd info structure
1742  * @chip:       nand chip info structure
1743  * @buf:        data buffer
1744  *
1745  * We need a special oob layout and handling even when ECC isn't checked.
1746  */
1747 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1748                                 const uint8_t *buf)
1749 {
1750         int eccsize = chip->ecc.size;
1751         int eccbytes = chip->ecc.bytes;
1752         uint8_t *oob = chip->oob_poi;
1753         int steps, size;
1754
1755         for (steps = chip->ecc.steps; steps > 0; steps--) {
1756                 chip->write_buf(mtd, buf, eccsize);
1757                 buf += eccsize;
1758
1759                 if (chip->ecc.prepad) {
1760                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1761                         oob += chip->ecc.prepad;
1762                 }
1763
1764                 chip->read_buf(mtd, oob, eccbytes);
1765                 oob += eccbytes;
1766
1767                 if (chip->ecc.postpad) {
1768                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1769                         oob += chip->ecc.postpad;
1770                 }
1771         }
1772
1773         size = mtd->oobsize - (oob - chip->oob_poi);
1774         if (size)
1775                 chip->write_buf(mtd, oob, size);
1776 }
1777 /**
1778  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1779  * @mtd:        mtd info structure
1780  * @chip:       nand chip info structure
1781  * @buf:        data buffer
1782  */
1783 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1784                                   const uint8_t *buf)
1785 {
1786         int i, eccsize = chip->ecc.size;
1787         int eccbytes = chip->ecc.bytes;
1788         int eccsteps = chip->ecc.steps;
1789         uint8_t *ecc_calc = chip->buffers->ecccalc;
1790         const uint8_t *p = buf;
1791         uint32_t *eccpos = chip->ecc.layout->eccpos;
1792
1793         /* Software ecc calculation */
1794         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1795                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1796
1797         for (i = 0; i < chip->ecc.total; i++)
1798                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1799
1800         chip->ecc.write_page_raw(mtd, chip, buf);
1801 }
1802
1803 /**
1804  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1805  * @mtd:        mtd info structure
1806  * @chip:       nand chip info structure
1807  * @buf:        data buffer
1808  */
1809 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1810                                   const uint8_t *buf)
1811 {
1812         int i, eccsize = chip->ecc.size;
1813         int eccbytes = chip->ecc.bytes;
1814         int eccsteps = chip->ecc.steps;
1815         uint8_t *ecc_calc = chip->buffers->ecccalc;
1816         const uint8_t *p = buf;
1817         uint32_t *eccpos = chip->ecc.layout->eccpos;
1818
1819         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1820                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1821                 chip->write_buf(mtd, p, eccsize);
1822                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1823         }
1824
1825         for (i = 0; i < chip->ecc.total; i++)
1826                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1827
1828         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1829 }
1830
1831 /**
1832  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1833  * @mtd:        mtd info structure
1834  * @chip:       nand chip info structure
1835  * @buf:        data buffer
1836  *
1837  * The hw generator calculates the error syndrome automatically. Therefor
1838  * we need a special oob layout and handling.
1839  */
1840 static void nand_write_page_syndrome(struct mtd_info *mtd,
1841                                     struct nand_chip *chip, const uint8_t *buf)
1842 {
1843         int i, eccsize = chip->ecc.size;
1844         int eccbytes = chip->ecc.bytes;
1845         int eccsteps = chip->ecc.steps;
1846         const uint8_t *p = buf;
1847         uint8_t *oob = chip->oob_poi;
1848
1849         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1850
1851                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1852                 chip->write_buf(mtd, p, eccsize);
1853
1854                 if (chip->ecc.prepad) {
1855                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1856                         oob += chip->ecc.prepad;
1857                 }
1858
1859                 chip->ecc.calculate(mtd, p, oob);
1860                 chip->write_buf(mtd, oob, eccbytes);
1861                 oob += eccbytes;
1862
1863                 if (chip->ecc.postpad) {
1864                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1865                         oob += chip->ecc.postpad;
1866                 }
1867         }
1868
1869         /* Calculate remaining oob bytes */
1870         i = mtd->oobsize - (oob - chip->oob_poi);
1871         if (i)
1872                 chip->write_buf(mtd, oob, i);
1873 }
1874
1875 /**
1876  * nand_write_page - [REPLACEABLE] write one page
1877  * @mtd:        MTD device structure
1878  * @chip:       NAND chip descriptor
1879  * @buf:        the data to write
1880  * @page:       page number to write
1881  * @cached:     cached programming
1882  * @raw:        use _raw version of write_page
1883  */
1884 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1885                            const uint8_t *buf, int page, int cached, int raw)
1886 {
1887         int status;
1888
1889         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1890
1891         if (unlikely(raw))
1892                 chip->ecc.write_page_raw(mtd, chip, buf);
1893         else
1894                 chip->ecc.write_page(mtd, chip, buf);
1895
1896         /*
1897          * Cached progamming disabled for now, Not sure if its worth the
1898          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1899          */
1900         cached = 0;
1901
1902         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1903
1904                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1905                 status = chip->waitfunc(mtd, chip);
1906                 /*
1907                  * See if operation failed and additional status checks are
1908                  * available
1909                  */
1910                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1911                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1912                                                page);
1913
1914                 if (status & NAND_STATUS_FAIL)
1915                         return -EIO;
1916         } else {
1917                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1918                 status = chip->waitfunc(mtd, chip);
1919         }
1920
1921 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1922         /* Send command to read back the data */
1923         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1924
1925         if (chip->verify_buf(mtd, buf, mtd->writesize))
1926                 return -EIO;
1927 #endif
1928         return 0;
1929 }
1930
1931 /**
1932  * nand_fill_oob - [Internal] Transfer client buffer to oob
1933  * @chip:       nand chip structure
1934  * @oob:        oob data buffer
1935  * @ops:        oob ops structure
1936  */
1937 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1938                                   struct mtd_oob_ops *ops)
1939 {
1940         size_t len = ops->ooblen;
1941
1942         switch(ops->mode) {
1943
1944         case MTD_OOB_PLACE:
1945         case MTD_OOB_RAW:
1946                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1947                 return oob + len;
1948
1949         case MTD_OOB_AUTO: {
1950                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1951                 uint32_t boffs = 0, woffs = ops->ooboffs;
1952                 size_t bytes = 0;
1953
1954                 for(; free->length && len; free++, len -= bytes) {
1955                         /* Write request not from offset 0 ? */
1956                         if (unlikely(woffs)) {
1957                                 if (woffs >= free->length) {
1958                                         woffs -= free->length;
1959                                         continue;
1960                                 }
1961                                 boffs = free->offset + woffs;
1962                                 bytes = min_t(size_t, len,
1963                                               (free->length - woffs));
1964                                 woffs = 0;
1965                         } else {
1966                                 bytes = min_t(size_t, len, free->length);
1967                                 boffs = free->offset;
1968                         }
1969                         memcpy(chip->oob_poi + boffs, oob, bytes);
1970                         oob += bytes;
1971                 }
1972                 return oob;
1973         }
1974         default:
1975                 BUG();
1976         }
1977         return NULL;
1978 }
1979
1980 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1981
1982 /**
1983  * nand_do_write_ops - [Internal] NAND write with ECC
1984  * @mtd:        MTD device structure
1985  * @to:         offset to write to
1986  * @ops:        oob operations description structure
1987  *
1988  * NAND write with ECC
1989  */
1990 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1991                              struct mtd_oob_ops *ops)
1992 {
1993         int chipnr, realpage, page, blockmask, column;
1994         struct nand_chip *chip = mtd->priv;
1995         uint32_t writelen = ops->len;
1996         uint8_t *oob = ops->oobbuf;
1997         uint8_t *buf = ops->datbuf;
1998         int ret, subpage;
1999
2000         ops->retlen = 0;
2001         if (!writelen)
2002                 return 0;
2003
2004         /* reject writes, which are not page aligned */
2005         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2006                 printk(KERN_NOTICE "nand_write: "
2007                        "Attempt to write not page aligned data\n");
2008                 return -EINVAL;
2009         }
2010
2011         column = to & (mtd->writesize - 1);
2012         subpage = column || (writelen & (mtd->writesize - 1));
2013
2014         if (subpage && oob)
2015                 return -EINVAL;
2016
2017         chipnr = (int)(to >> chip->chip_shift);
2018         chip->select_chip(mtd, chipnr);
2019
2020         /* Check, if it is write protected */
2021         if (nand_check_wp(mtd)) {
2022                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
2023                 return -EIO;
2024         }
2025
2026         realpage = (int)(to >> chip->page_shift);
2027         page = realpage & chip->pagemask;
2028         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2029
2030         /* Invalidate the page cache, when we write to the cached page */
2031         if (to <= (chip->pagebuf << chip->page_shift) &&
2032             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2033                 chip->pagebuf = -1;
2034
2035         /* If we're not given explicit OOB data, let it be 0xFF */
2036         if (likely(!oob))
2037                 memset(chip->oob_poi, 0xff, mtd->oobsize);
2038
2039         while(1) {
2040                 int bytes = mtd->writesize;
2041                 int cached = writelen > bytes && page != blockmask;
2042                 uint8_t *wbuf = buf;
2043
2044                 /* Partial page write ? */
2045                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2046                         cached = 0;
2047                         bytes = min_t(int, bytes - column, (int) writelen);
2048                         chip->pagebuf = -1;
2049                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2050                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2051                         wbuf = chip->buffers->databuf;
2052                 }
2053
2054                 if (unlikely(oob))
2055                         oob = nand_fill_oob(chip, oob, ops);
2056
2057                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2058                                        (ops->mode == MTD_OOB_RAW));
2059                 if (ret)
2060                         break;
2061
2062                 writelen -= bytes;
2063                 if (!writelen)
2064                         break;
2065
2066                 column = 0;
2067                 buf += bytes;
2068                 realpage++;
2069
2070                 page = realpage & chip->pagemask;
2071                 /* Check, if we cross a chip boundary */
2072                 if (!page) {
2073                         chipnr++;
2074                         chip->select_chip(mtd, -1);
2075                         chip->select_chip(mtd, chipnr);
2076                 }
2077         }
2078
2079         ops->retlen = ops->len - writelen;
2080         if (unlikely(oob))
2081                 ops->oobretlen = ops->ooblen;
2082         return ret;
2083 }
2084
2085 /**
2086  * nand_write - [MTD Interface] NAND write with ECC
2087  * @mtd:        MTD device structure
2088  * @to:         offset to write to
2089  * @len:        number of bytes to write
2090  * @retlen:     pointer to variable to store the number of written bytes
2091  * @buf:        the data to write
2092  *
2093  * NAND write with ECC
2094  */
2095 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2096                           size_t *retlen, const uint8_t *buf)
2097 {
2098         struct nand_chip *chip = mtd->priv;
2099         int ret;
2100
2101         /* Do not allow reads past end of device */
2102         if ((to + len) > mtd->size)
2103                 return -EINVAL;
2104         if (!len)
2105                 return 0;
2106
2107         nand_get_device(chip, mtd, FL_WRITING);
2108
2109         chip->ops.len = len;
2110         chip->ops.datbuf = (uint8_t *)buf;
2111         chip->ops.oobbuf = NULL;
2112
2113         ret = nand_do_write_ops(mtd, to, &chip->ops);
2114
2115         *retlen = chip->ops.retlen;
2116
2117         nand_release_device(mtd);
2118
2119         return ret;
2120 }
2121
2122 /**
2123  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2124  * @mtd:        MTD device structure
2125  * @to:         offset to write to
2126  * @ops:        oob operation description structure
2127  *
2128  * NAND write out-of-band
2129  */
2130 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2131                              struct mtd_oob_ops *ops)
2132 {
2133         int chipnr, page, status, len;
2134         struct nand_chip *chip = mtd->priv;
2135
2136         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
2137                   (unsigned int)to, (int)ops->ooblen);
2138
2139         if (ops->mode == MTD_OOB_AUTO)
2140                 len = chip->ecc.layout->oobavail;
2141         else
2142                 len = mtd->oobsize;
2143
2144         /* Do not allow write past end of page */
2145         if ((ops->ooboffs + ops->ooblen) > len) {
2146                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2147                           "Attempt to write past end of page\n");
2148                 return -EINVAL;
2149         }
2150
2151         if (unlikely(ops->ooboffs >= len)) {
2152                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2153                           "Attempt to start write outside oob\n");
2154                 return -EINVAL;
2155         }
2156
2157         /* Do not allow reads past end of device */
2158         if (unlikely(to >= mtd->size ||
2159                      ops->ooboffs + ops->ooblen >
2160                         ((mtd->size >> chip->page_shift) -
2161                          (to >> chip->page_shift)) * len)) {
2162                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2163                           "Attempt write beyond end of device\n");
2164                 return -EINVAL;
2165         }
2166
2167         chipnr = (int)(to >> chip->chip_shift);
2168         chip->select_chip(mtd, chipnr);
2169
2170         /* Shift to get page */
2171         page = (int)(to >> chip->page_shift);
2172
2173         /*
2174          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2175          * of my DiskOnChip 2000 test units) will clear the whole data page too
2176          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2177          * it in the doc2000 driver in August 1999.  dwmw2.
2178          */
2179         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2180
2181         /* Check, if it is write protected */
2182         if (nand_check_wp(mtd))
2183                 return -EROFS;
2184
2185         /* Invalidate the page cache, if we write to the cached page */
2186         if (page == chip->pagebuf)
2187                 chip->pagebuf = -1;
2188
2189         memset(chip->oob_poi, 0xff, mtd->oobsize);
2190         nand_fill_oob(chip, ops->oobbuf, ops);
2191         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2192         memset(chip->oob_poi, 0xff, mtd->oobsize);
2193
2194         if (status)
2195                 return status;
2196
2197         ops->oobretlen = ops->ooblen;
2198
2199         return 0;
2200 }
2201
2202 /**
2203  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2204  * @mtd:        MTD device structure
2205  * @to:         offset to write to
2206  * @ops:        oob operation description structure
2207  */
2208 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2209                           struct mtd_oob_ops *ops)
2210 {
2211         struct nand_chip *chip = mtd->priv;
2212         int ret = -ENOTSUPP;
2213
2214         ops->retlen = 0;
2215
2216         /* Do not allow writes past end of device */
2217         if (ops->datbuf && (to + ops->len) > mtd->size) {
2218                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2219                           "Attempt read beyond end of device\n");
2220                 return -EINVAL;
2221         }
2222
2223         nand_get_device(chip, mtd, FL_WRITING);
2224
2225         switch(ops->mode) {
2226         case MTD_OOB_PLACE:
2227         case MTD_OOB_AUTO:
2228         case MTD_OOB_RAW:
2229                 break;
2230
2231         default:
2232                 goto out;
2233         }
2234
2235         if (!ops->datbuf)
2236                 ret = nand_do_write_oob(mtd, to, ops);
2237         else
2238                 ret = nand_do_write_ops(mtd, to, ops);
2239
2240  out:
2241         nand_release_device(mtd);
2242         return ret;
2243 }
2244
2245 /**
2246  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2247  * @mtd:        MTD device structure
2248  * @page:       the page address of the block which will be erased
2249  *
2250  * Standard erase command for NAND chips
2251  */
2252 static void single_erase_cmd(struct mtd_info *mtd, int page)
2253 {
2254         struct nand_chip *chip = mtd->priv;
2255         /* Send commands to erase a block */
2256         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2257         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2258 }
2259
2260 /**
2261  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2262  * @mtd:        MTD device structure
2263  * @page:       the page address of the block which will be erased
2264  *
2265  * AND multi block erase command function
2266  * Erase 4 consecutive blocks
2267  */
2268 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2269 {
2270         struct nand_chip *chip = mtd->priv;
2271         /* Send commands to erase a block */
2272         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2273         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2274         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2275         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2276         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2277 }
2278
2279 /**
2280  * nand_erase - [MTD Interface] erase block(s)
2281  * @mtd:        MTD device structure
2282  * @instr:      erase instruction
2283  *
2284  * Erase one ore more blocks
2285  */
2286 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2287 {
2288         return nand_erase_nand(mtd, instr, 0);
2289 }
2290
2291 #define BBT_PAGE_MASK   0xffffff3f
2292 /**
2293  * nand_erase_nand - [Internal] erase block(s)
2294  * @mtd:        MTD device structure
2295  * @instr:      erase instruction
2296  * @allowbbt:   allow erasing the bbt area
2297  *
2298  * Erase one ore more blocks
2299  */
2300 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2301                     int allowbbt)
2302 {
2303         int page, status, pages_per_block, ret, chipnr;
2304         struct nand_chip *chip = mtd->priv;
2305         loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2306         unsigned int bbt_masked_page = 0xffffffff;
2307         loff_t len;
2308
2309         MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2310                  "len = %llu\n", (unsigned long long) instr->addr,
2311                  (unsigned long long) instr->len);
2312
2313         /* Start address must align on block boundary */
2314         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2315                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2316                 return -EINVAL;
2317         }
2318
2319         /* Length must align on block boundary */
2320         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2321                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2322                           "nand_erase: Length not block aligned\n");
2323                 return -EINVAL;
2324         }
2325
2326         /* Do not allow erase past end of device */
2327         if ((instr->len + instr->addr) > mtd->size) {
2328                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2329                           "nand_erase: Erase past end of device\n");
2330                 return -EINVAL;
2331         }
2332
2333         instr->fail_addr = 0xffffffff;
2334
2335         /* Grab the lock and see if the device is available */
2336         nand_get_device(chip, mtd, FL_ERASING);
2337
2338         /* Shift to get first page */
2339         page = (int)(instr->addr >> chip->page_shift);
2340         chipnr = (int)(instr->addr >> chip->chip_shift);
2341
2342         /* Calculate pages in each block */
2343         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2344
2345         /* Select the NAND device */
2346         chip->select_chip(mtd, chipnr);
2347
2348         /* Check, if it is write protected */
2349         if (nand_check_wp(mtd)) {
2350                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2351                           "nand_erase: Device is write protected!!!\n");
2352                 instr->state = MTD_ERASE_FAILED;
2353                 goto erase_exit;
2354         }
2355
2356         /*
2357          * If BBT requires refresh, set the BBT page mask to see if the BBT
2358          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2359          * can not be matched. This is also done when the bbt is actually
2360          * erased to avoid recusrsive updates
2361          */
2362         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2363                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2364
2365         /* Loop through the pages */
2366         len = instr->len;
2367
2368         instr->state = MTD_ERASING;
2369
2370         while (len) {
2371                 /*
2372                  * heck if we have a bad block, we do not erase bad blocks !
2373                  */
2374                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2375                                         chip->page_shift, 0, allowbbt)) {
2376                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2377                                "bad block at page 0x%08x\n", page);
2378                         instr->state = MTD_ERASE_FAILED;
2379                         goto erase_exit;
2380                 }
2381
2382                 /*
2383                  * Invalidate the page cache, if we erase the block which
2384                  * contains the current cached page
2385                  */
2386                 if (page <= chip->pagebuf && chip->pagebuf <
2387                     (page + pages_per_block))
2388                         chip->pagebuf = -1;
2389
2390                 chip->erase_cmd(mtd, page & chip->pagemask);
2391
2392                 status = chip->waitfunc(mtd, chip);
2393
2394                 /*
2395                  * See if operation failed and additional status checks are
2396                  * available
2397                  */
2398                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2399                         status = chip->errstat(mtd, chip, FL_ERASING,
2400                                                status, page);
2401
2402                 /* See if block erase succeeded */
2403                 if (status & NAND_STATUS_FAIL) {
2404                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2405                                   "Failed erase, page 0x%08x\n", page);
2406                         instr->state = MTD_ERASE_FAILED;
2407                         instr->fail_addr = ((loff_t)page << chip->page_shift);
2408                         goto erase_exit;
2409                 }
2410
2411                 /*
2412                  * If BBT requires refresh, set the BBT rewrite flag to the
2413                  * page being erased
2414                  */
2415                 if (bbt_masked_page != 0xffffffff &&
2416                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2417                         rewrite_bbt[chipnr] =
2418                                 ((loff_t)page << chip->page_shift);
2419
2420                 /* Increment page address and decrement length */
2421                 len -= (1 << chip->phys_erase_shift);
2422                 page += pages_per_block;
2423
2424                 /* Check, if we cross a chip boundary */
2425                 if (len && !(page & chip->pagemask)) {
2426                         chipnr++;
2427                         chip->select_chip(mtd, -1);
2428                         chip->select_chip(mtd, chipnr);
2429
2430                         /*
2431                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2432                          * page mask to see if this BBT should be rewritten
2433                          */
2434                         if (bbt_masked_page != 0xffffffff &&
2435                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2436                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2437                                         BBT_PAGE_MASK;
2438                 }
2439         }
2440         instr->state = MTD_ERASE_DONE;
2441
2442  erase_exit:
2443
2444         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2445
2446         /* Deselect and wake up anyone waiting on the device */
2447         nand_release_device(mtd);
2448
2449         /* Do call back function */
2450         if (!ret)
2451                 mtd_erase_callback(instr);
2452
2453         /*
2454          * If BBT requires refresh and erase was successful, rewrite any
2455          * selected bad block tables
2456          */
2457         if (bbt_masked_page == 0xffffffff || ret)
2458                 return ret;
2459
2460         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2461                 if (!rewrite_bbt[chipnr])
2462                         continue;
2463                 /* update the BBT for chip */
2464                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2465                           "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2466                           chip->bbt_td->pages[chipnr]);
2467                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2468         }
2469
2470         /* Return more or less happy */
2471         return ret;
2472 }
2473
2474 /**
2475  * nand_sync - [MTD Interface] sync
2476  * @mtd:        MTD device structure
2477  *
2478  * Sync is actually a wait for chip ready function
2479  */
2480 static void nand_sync(struct mtd_info *mtd)
2481 {
2482         struct nand_chip *chip = mtd->priv;
2483
2484         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2485
2486         /* Grab the lock and see if the device is available */
2487         nand_get_device(chip, mtd, FL_SYNCING);
2488         /* Release it and go back */
2489         nand_release_device(mtd);
2490 }
2491
2492 /**
2493  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2494  * @mtd:        MTD device structure
2495  * @offs:       offset relative to mtd start
2496  */
2497 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2498 {
2499         /* Check for invalid offset */
2500         if (offs > mtd->size)
2501                 return -EINVAL;
2502
2503         return nand_block_checkbad(mtd, offs, 1, 0);
2504 }
2505
2506 /**
2507  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2508  * @mtd:        MTD device structure
2509  * @ofs:        offset relative to mtd start
2510  */
2511 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2512 {
2513         struct nand_chip *chip = mtd->priv;
2514         int ret;
2515
2516         if ((ret = nand_block_isbad(mtd, ofs))) {
2517                 /* If it was bad already, return success and do nothing. */
2518                 if (ret > 0)
2519                         return 0;
2520                 return ret;
2521         }
2522
2523         return chip->block_markbad(mtd, ofs);
2524 }
2525
2526 /**
2527  * nand_suspend - [MTD Interface] Suspend the NAND flash
2528  * @mtd:        MTD device structure
2529  */
2530 static int nand_suspend(struct mtd_info *mtd)
2531 {
2532         struct nand_chip *chip = mtd->priv;
2533
2534         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2535 }
2536
2537 /**
2538  * nand_resume - [MTD Interface] Resume the NAND flash
2539  * @mtd:        MTD device structure
2540  */
2541 static void nand_resume(struct mtd_info *mtd)
2542 {
2543         struct nand_chip *chip = mtd->priv;
2544
2545         if (chip->state == FL_PM_SUSPENDED)
2546                 nand_release_device(mtd);
2547         else
2548                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2549                        "in suspended state\n");
2550 }
2551
2552 /*
2553  * Set default functions
2554  */
2555 static void nand_set_defaults(struct nand_chip *chip, int busw)
2556 {
2557         /* check for proper chip_delay setup, set 20us if not */
2558         if (!chip->chip_delay)
2559                 chip->chip_delay = 20;
2560
2561         /* check, if a user supplied command function given */
2562         if (chip->cmdfunc == NULL)
2563                 chip->cmdfunc = nand_command;
2564
2565         /* check, if a user supplied wait function given */
2566         if (chip->waitfunc == NULL)
2567                 chip->waitfunc = nand_wait;
2568
2569         if (!chip->select_chip)
2570                 chip->select_chip = nand_select_chip;
2571         if (!chip->read_byte)
2572                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2573         if (!chip->read_word)
2574                 chip->read_word = nand_read_word;
2575         if (!chip->block_bad)
2576                 chip->block_bad = nand_block_bad;
2577         if (!chip->block_markbad)
2578                 chip->block_markbad = nand_default_block_markbad;
2579         if (!chip->write_buf)
2580                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2581         if (!chip->read_buf)
2582                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2583         if (!chip->verify_buf)
2584                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2585         if (!chip->scan_bbt)
2586                 chip->scan_bbt = nand_default_bbt;
2587
2588         if (!chip->controller) {
2589                 chip->controller = &chip->hwcontrol;
2590
2591                 /* XXX U-BOOT XXX */
2592 #if 0
2593                 spin_lock_init(&chip->controller->lock);
2594                 init_waitqueue_head(&chip->controller->wq);
2595 #endif
2596         }
2597
2598 }
2599
2600 /*
2601  * Get the flash and manufacturer id and lookup if the type is supported
2602  */
2603 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2604                                                   struct nand_chip *chip,
2605                                                   int busw, int *maf_id)
2606 {
2607         struct nand_flash_dev *type = NULL;
2608         int i, dev_id, maf_idx;
2609         int tmp_id, tmp_manf;
2610
2611         /* Select the device */
2612         chip->select_chip(mtd, 0);
2613
2614         /*
2615          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2616          * after power-up
2617          */
2618         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2619
2620         /* Send the command for reading device ID */
2621         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2622
2623         /* Read manufacturer and device IDs */
2624         *maf_id = chip->read_byte(mtd);
2625         dev_id = chip->read_byte(mtd);
2626
2627         /* Try again to make sure, as some systems the bus-hold or other
2628          * interface concerns can cause random data which looks like a
2629          * possibly credible NAND flash to appear. If the two results do
2630          * not match, ignore the device completely.
2631          */
2632
2633         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2634
2635         /* Read manufacturer and device IDs */
2636
2637         tmp_manf = chip->read_byte(mtd);
2638         tmp_id = chip->read_byte(mtd);
2639
2640         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2641                 printk(KERN_INFO "%s: second ID read did not match "
2642                        "%02x,%02x against %02x,%02x\n", __func__,
2643                        *maf_id, dev_id, tmp_manf, tmp_id);
2644                 return ERR_PTR(-ENODEV);
2645         }
2646
2647         /* Lookup the flash id */
2648         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2649                 if (dev_id == nand_flash_ids[i].id) {
2650                         type =  &nand_flash_ids[i];
2651                         break;
2652                 }
2653         }
2654
2655         if (!type) {
2656                 /* supress warning if there is no nand */
2657                 if (*maf_id != 0x00 && *maf_id != 0xff &&
2658                     dev_id  != 0x00 && dev_id  != 0xff)
2659                         printk(KERN_INFO "%s: unknown NAND device: "
2660                                 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2661                                 __func__, *maf_id, dev_id);
2662                 return ERR_PTR(-ENODEV);
2663         }
2664
2665         if (!mtd->name)
2666                 mtd->name = type->name;
2667
2668         chip->chipsize = (uint64_t)type->chipsize << 20;
2669
2670         /* Newer devices have all the information in additional id bytes */
2671         if (!type->pagesize) {
2672                 int extid;
2673                 /* The 3rd id byte holds MLC / multichip data */
2674                 chip->cellinfo = chip->read_byte(mtd);
2675                 /* The 4th id byte is the important one */
2676                 extid = chip->read_byte(mtd);
2677                 /* Calc pagesize */
2678                 mtd->writesize = 1024 << (extid & 0x3);
2679                 extid >>= 2;
2680                 /* Calc oobsize */
2681                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2682                 extid >>= 2;
2683                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2684                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2685                 extid >>= 2;
2686                 /* Get buswidth information */
2687                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2688
2689         } else {
2690                 /*
2691                  * Old devices have chip data hardcoded in the device id table
2692                  */
2693                 mtd->erasesize = type->erasesize;
2694                 mtd->writesize = type->pagesize;
2695                 mtd->oobsize = mtd->writesize / 32;
2696                 busw = type->options & NAND_BUSWIDTH_16;
2697         }
2698
2699         /* Try to identify manufacturer */
2700         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2701                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2702                         break;
2703         }
2704
2705         /*
2706          * Check, if buswidth is correct. Hardware drivers should set
2707          * chip correct !
2708          */
2709         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2710                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2711                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2712                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2713                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2714                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2715                        busw ? 16 : 8);
2716                 return ERR_PTR(-EINVAL);
2717         }
2718
2719         /* Calculate the address shift from the page size */
2720         chip->page_shift = ffs(mtd->writesize) - 1;
2721         /* Convert chipsize to number of pages per chip -1. */
2722         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2723
2724         chip->bbt_erase_shift = chip->phys_erase_shift =
2725                 ffs(mtd->erasesize) - 1;
2726         if (chip->chipsize & 0xffffffff)
2727                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2728         else
2729                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2730
2731         /* Set the bad block position */
2732         chip->badblockpos = mtd->writesize > 512 ?
2733                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2734
2735         /* Get chip options, preserve non chip based options */
2736         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2737         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2738
2739         /*
2740          * Set chip as a default. Board drivers can override it, if necessary
2741          */
2742         chip->options |= NAND_NO_AUTOINCR;
2743
2744         /* Check if chip is a not a samsung device. Do not clear the
2745          * options for chips which are not having an extended id.
2746          */
2747         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2748                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2749
2750         /* Check for AND chips with 4 page planes */
2751         if (chip->options & NAND_4PAGE_ARRAY)
2752                 chip->erase_cmd = multi_erase_cmd;
2753         else
2754                 chip->erase_cmd = single_erase_cmd;
2755
2756         /* Do not replace user supplied command function ! */
2757         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2758                 chip->cmdfunc = nand_command_lp;
2759
2760         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2761                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2762                   nand_manuf_ids[maf_idx].name, type->name);
2763
2764         return type;
2765 }
2766
2767 /**
2768  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2769  * @mtd:             MTD device structure
2770  * @maxchips:        Number of chips to scan for
2771  *
2772  * This is the first phase of the normal nand_scan() function. It
2773  * reads the flash ID and sets up MTD fields accordingly.
2774  *
2775  * The mtd->owner field must be set to the module of the caller.
2776  */
2777 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2778 {
2779         int i, busw, nand_maf_id;
2780         struct nand_chip *chip = mtd->priv;
2781         struct nand_flash_dev *type;
2782
2783         /* Get buswidth to select the correct functions */
2784         busw = chip->options & NAND_BUSWIDTH_16;
2785         /* Set the default functions */
2786         nand_set_defaults(chip, busw);
2787
2788         /* Read the flash type */
2789         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2790
2791         if (IS_ERR(type)) {
2792 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2793                 printk(KERN_WARNING "No NAND device found!!!\n");
2794 #endif
2795                 chip->select_chip(mtd, -1);
2796                 return PTR_ERR(type);
2797         }
2798
2799         /* Check for a chip array */
2800         for (i = 1; i < maxchips; i++) {
2801                 chip->select_chip(mtd, i);
2802                 /* See comment in nand_get_flash_type for reset */
2803                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2804                 /* Send the command for reading device ID */
2805                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2806                 /* Read manufacturer and device IDs */
2807                 if (nand_maf_id != chip->read_byte(mtd) ||
2808                     type->id != chip->read_byte(mtd))
2809                         break;
2810         }
2811 #ifdef DEBUG
2812         if (i > 1)
2813                 printk(KERN_INFO "%d NAND chips detected\n", i);
2814 #endif
2815
2816         /* Store the number of chips and calc total size for mtd */
2817         chip->numchips = i;
2818         mtd->size = i * chip->chipsize;
2819
2820         return 0;
2821 }
2822
2823
2824 /**
2825  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2826  * @mtd:            MTD device structure
2827  *
2828  * This is the second phase of the normal nand_scan() function. It
2829  * fills out all the uninitialized function pointers with the defaults
2830  * and scans for a bad block table if appropriate.
2831  */
2832 int nand_scan_tail(struct mtd_info *mtd)
2833 {
2834         int i;
2835         struct nand_chip *chip = mtd->priv;
2836
2837         if (!(chip->options & NAND_OWN_BUFFERS))
2838                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2839         if (!chip->buffers)
2840                 return -ENOMEM;
2841
2842         /* Set the internal oob buffer location, just after the page data */
2843         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2844
2845         /*
2846          * If no default placement scheme is given, select an appropriate one
2847          */
2848         if (!chip->ecc.layout) {
2849                 switch (mtd->oobsize) {
2850                 case 8:
2851                         chip->ecc.layout = &nand_oob_8;
2852                         break;
2853                 case 16:
2854                         chip->ecc.layout = &nand_oob_16;
2855                         break;
2856                 case 64:
2857                         chip->ecc.layout = &nand_oob_64;
2858                         break;
2859                 case 128:
2860                         chip->ecc.layout = &nand_oob_128;
2861                         break;
2862                 default:
2863                         printk(KERN_WARNING "No oob scheme defined for "
2864                                "oobsize %d\n", mtd->oobsize);
2865                 }
2866         }
2867
2868         if (!chip->write_page)
2869                 chip->write_page = nand_write_page;
2870
2871         /*
2872          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2873          * selected and we have 256 byte pagesize fallback to software ECC
2874          */
2875
2876         switch (chip->ecc.mode) {
2877         case NAND_ECC_HW_OOB_FIRST:
2878                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2879                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2880                      !chip->ecc.hwctl) {
2881                         printk(KERN_WARNING "No ECC functions supplied, "
2882                                "Hardware ECC not possible\n");
2883                         BUG();
2884                 }
2885                 if (!chip->ecc.read_page)
2886                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2887
2888         case NAND_ECC_HW:
2889                 /* Use standard hwecc read page function ? */
2890                 if (!chip->ecc.read_page)
2891                         chip->ecc.read_page = nand_read_page_hwecc;
2892                 if (!chip->ecc.write_page)
2893                         chip->ecc.write_page = nand_write_page_hwecc;
2894                 if (!chip->ecc.read_page_raw)
2895                         chip->ecc.read_page_raw = nand_read_page_raw;
2896                 if (!chip->ecc.write_page_raw)
2897                         chip->ecc.write_page_raw = nand_write_page_raw;
2898                 if (!chip->ecc.read_oob)
2899                         chip->ecc.read_oob = nand_read_oob_std;
2900                 if (!chip->ecc.write_oob)
2901                         chip->ecc.write_oob = nand_write_oob_std;
2902
2903         case NAND_ECC_HW_SYNDROME:
2904                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2905                      !chip->ecc.hwctl) &&
2906                     (!chip->ecc.read_page ||
2907                      chip->ecc.read_page == nand_read_page_hwecc ||
2908                      !chip->ecc.write_page ||
2909                      chip->ecc.write_page == nand_write_page_hwecc)) {
2910                         printk(KERN_WARNING "No ECC functions supplied, "
2911                                "Hardware ECC not possible\n");
2912                         BUG();
2913                 }
2914                 /* Use standard syndrome read/write page function ? */
2915                 if (!chip->ecc.read_page)
2916                         chip->ecc.read_page = nand_read_page_syndrome;
2917                 if (!chip->ecc.write_page)
2918                         chip->ecc.write_page = nand_write_page_syndrome;
2919                 if (!chip->ecc.read_page_raw)
2920                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2921                 if (!chip->ecc.write_page_raw)
2922                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2923                 if (!chip->ecc.read_oob)
2924                         chip->ecc.read_oob = nand_read_oob_syndrome;
2925                 if (!chip->ecc.write_oob)
2926                         chip->ecc.write_oob = nand_write_oob_syndrome;
2927
2928                 if (mtd->writesize >= chip->ecc.size)
2929                         break;
2930                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2931                        "%d byte page size, fallback to SW ECC\n",
2932                        chip->ecc.size, mtd->writesize);
2933                 chip->ecc.mode = NAND_ECC_SOFT;
2934
2935         case NAND_ECC_SOFT:
2936                 chip->ecc.calculate = nand_calculate_ecc;
2937                 chip->ecc.correct = nand_correct_data;
2938                 chip->ecc.read_page = nand_read_page_swecc;
2939                 chip->ecc.read_subpage = nand_read_subpage;
2940                 chip->ecc.write_page = nand_write_page_swecc;
2941                 chip->ecc.read_page_raw = nand_read_page_raw;
2942                 chip->ecc.write_page_raw = nand_write_page_raw;
2943                 chip->ecc.read_oob = nand_read_oob_std;
2944                 chip->ecc.write_oob = nand_write_oob_std;
2945                 chip->ecc.size = 256;
2946                 chip->ecc.bytes = 3;
2947                 break;
2948
2949         case NAND_ECC_NONE:
2950                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2951                        "This is not recommended !!\n");
2952                 chip->ecc.read_page = nand_read_page_raw;
2953                 chip->ecc.write_page = nand_write_page_raw;
2954                 chip->ecc.read_oob = nand_read_oob_std;
2955                 chip->ecc.read_page_raw = nand_read_page_raw;
2956                 chip->ecc.write_page_raw = nand_write_page_raw;
2957                 chip->ecc.write_oob = nand_write_oob_std;
2958                 chip->ecc.size = mtd->writesize;
2959                 chip->ecc.bytes = 0;
2960                 break;
2961
2962         default:
2963                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2964                        chip->ecc.mode);
2965                 BUG();
2966         }
2967
2968         /*
2969          * The number of bytes available for a client to place data into
2970          * the out of band area
2971          */
2972         chip->ecc.layout->oobavail = 0;
2973         for (i = 0; chip->ecc.layout->oobfree[i].length
2974                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2975                 chip->ecc.layout->oobavail +=
2976                         chip->ecc.layout->oobfree[i].length;
2977         mtd->oobavail = chip->ecc.layout->oobavail;
2978
2979         /*
2980          * Set the number of read / write steps for one page depending on ECC
2981          * mode
2982          */
2983         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2984         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2985                 printk(KERN_WARNING "Invalid ecc parameters\n");
2986                 BUG();
2987         }
2988         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2989
2990         /*
2991          * Allow subpage writes up to ecc.steps. Not possible for MLC
2992          * FLASH.
2993          */
2994         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2995             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2996                 switch(chip->ecc.steps) {
2997                 case 2:
2998                         mtd->subpage_sft = 1;
2999                         break;
3000                 case 4:
3001                 case 8:
3002                 case 16:
3003                         mtd->subpage_sft = 2;
3004                         break;
3005                 }
3006         }
3007         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3008
3009         /* Initialize state */
3010         chip->state = FL_READY;
3011
3012         /* De-select the device */
3013         chip->select_chip(mtd, -1);
3014
3015         /* Invalidate the pagebuffer reference */
3016         chip->pagebuf = -1;
3017
3018         /* Fill in remaining MTD driver data */
3019         mtd->type = MTD_NANDFLASH;
3020         mtd->flags = MTD_CAP_NANDFLASH;
3021         mtd->erase = nand_erase;
3022         mtd->point = NULL;
3023         mtd->unpoint = NULL;
3024         mtd->read = nand_read;
3025         mtd->write = nand_write;
3026         mtd->read_oob = nand_read_oob;
3027         mtd->write_oob = nand_write_oob;
3028         mtd->sync = nand_sync;
3029         mtd->lock = NULL;
3030         mtd->unlock = NULL;
3031         mtd->suspend = nand_suspend;
3032         mtd->resume = nand_resume;
3033         mtd->block_isbad = nand_block_isbad;
3034         mtd->block_markbad = nand_block_markbad;
3035
3036         /* propagate ecc.layout to mtd_info */
3037         mtd->ecclayout = chip->ecc.layout;
3038
3039         /* Check, if we should skip the bad block table scan */
3040         if (chip->options & NAND_SKIP_BBTSCAN)
3041                 chip->options |= NAND_BBT_SCANNED;
3042
3043         return 0;
3044 }
3045
3046 /* module_text_address() isn't exported, and it's mostly a pointless
3047    test if this is a module _anyway_ -- they'd have to try _really_ hard
3048    to call us from in-kernel code if the core NAND support is modular. */
3049 #ifdef MODULE
3050 #define caller_is_module() (1)
3051 #else
3052 #define caller_is_module() \
3053         module_text_address((unsigned long)__builtin_return_address(0))
3054 #endif
3055
3056 /**
3057  * nand_scan - [NAND Interface] Scan for the NAND device
3058  * @mtd:        MTD device structure
3059  * @maxchips:   Number of chips to scan for
3060  *
3061  * This fills out all the uninitialized function pointers
3062  * with the defaults.
3063  * The flash ID is read and the mtd/chip structures are
3064  * filled with the appropriate values.
3065  * The mtd->owner field must be set to the module of the caller
3066  *
3067  */
3068 int nand_scan(struct mtd_info *mtd, int maxchips)
3069 {
3070         int ret;
3071
3072         /* Many callers got this wrong, so check for it for a while... */
3073         /* XXX U-BOOT XXX */
3074 #if 0
3075         if (!mtd->owner && caller_is_module()) {
3076                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
3077                 BUG();
3078         }
3079 #endif
3080
3081         ret = nand_scan_ident(mtd, maxchips);
3082         if (!ret)
3083                 ret = nand_scan_tail(mtd);
3084         return ret;
3085 }
3086
3087 /**
3088  * nand_release - [NAND Interface] Free resources held by the NAND device
3089  * @mtd:        MTD device structure
3090 */
3091 void nand_release(struct mtd_info *mtd)
3092 {
3093         struct nand_chip *chip = mtd->priv;
3094
3095 #ifdef CONFIG_MTD_PARTITIONS
3096         /* Deregister partitions */
3097         del_mtd_partitions(mtd);
3098 #endif
3099         /* Deregister the device */
3100         /* XXX U-BOOT XXX */
3101 #if 0
3102         del_mtd_device(mtd);
3103 #endif
3104
3105         /* Free bad block table memory */
3106         kfree(chip->bbt);
3107         if (!(chip->options & NAND_OWN_BUFFERS))
3108                 kfree(chip->buffers);
3109 }
3110
3111 /* XXX U-BOOT XXX */
3112 #if 0
3113 EXPORT_SYMBOL_GPL(nand_scan);
3114 EXPORT_SYMBOL_GPL(nand_scan_ident);
3115 EXPORT_SYMBOL_GPL(nand_scan_tail);
3116 EXPORT_SYMBOL_GPL(nand_release);
3117
3118 static int __init nand_base_init(void)
3119 {
3120         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3121         return 0;
3122 }
3123
3124 static void __exit nand_base_exit(void)
3125 {
3126         led_trigger_unregister_simple(nand_led_trigger);
3127 }
3128
3129 module_init(nand_base_init);
3130 module_exit(nand_base_exit);
3131
3132 MODULE_LICENSE("GPL");
3133 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3134 MODULE_DESCRIPTION("Generic NAND flash driver code");
3135 #endif