drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 /* XXX U-BOOT XXX */
  36 #if 0
  37 #include <linux/module.h>
  38 #include <linux/delay.h>
  39 #include <linux/errno.h>
  40 #include <linux/err.h>
  41 #include <linux/sched.h>
  42 #include <linux/slab.h>
  43 #include <linux/types.h>
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/compatmac.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/bitops.h>
  50 #include <linux/leds.h>
  51 #include <asm/io.h>
  52
  53 #ifdef CONFIG_MTD_PARTITIONS
  54 #include <linux/mtd/partitions.h>
  55 #endif
  56
  57 #endif
  58
  59 #include <common.h>
  60
  61 #define ENOTSUPP        524     /* Operation is not supported */
  62
  63 #include <malloc.h>
  64 #include <watchdog.h>
  65 #include <linux/err.h>
  66 #include <linux/mtd/compat.h>
  67 #include <linux/mtd/mtd.h>
  68 #include <linux/mtd/nand.h>
  69 #include <linux/mtd/nand_ecc.h>
  70
  71 #include <asm/io.h>
  72 #include <asm/errno.h>
  73
  74 #ifdef CONFIG_JFFS2_NAND
  75 #include <jffs2/jffs2.h>
  76 #endif
  77
  78 /* Define default oob placement schemes for large and small page devices */
  79 static struct nand_ecclayout nand_oob_8 = {
  80         .eccbytes = 3,
  81         .eccpos = {0, 1, 2},
  82         .oobfree = {
  83                 {.offset = 3,
  84                  .length = 2},
  85                 {.offset = 6,
  86                  .length = 2}}
  87 };
  88
  89 static struct nand_ecclayout nand_oob_16 = {
  90         .eccbytes = 6,
  91         .eccpos = {0, 1, 2, 3, 6, 7},
  92         .oobfree = {
  93                 {.offset = 8,
  94                  . length = 8}}
  95 };
  96
  97 static struct nand_ecclayout nand_oob_64 = {
  98         .eccbytes = 24,
  99         .eccpos = {
 100                    40, 41, 42, 43, 44, 45, 46, 47,
 101                    48, 49, 50, 51, 52, 53, 54, 55,
 102                    56, 57, 58, 59, 60, 61, 62, 63},
 103         .oobfree = {
 104                 {.offset = 2,
 105                  .length = 38}}
 106 };
 107
 108 static struct nand_ecclayout nand_oob_128 = {
 109         .eccbytes = 48,
 110         .eccpos = {
 111                     80,  81,  82,  83,  84,  85,  86,  87,
 112                     88,  89,  90,  91,  92,  93,  94,  95,
 113                     96,  97,  98,  99, 100, 101, 102, 103,
 114                    104, 105, 106, 107, 108, 109, 110, 111,
 115                    112, 113, 114, 115, 116, 117, 118, 119,
 116                    120, 121, 122, 123, 124, 125, 126, 127},
 117         .oobfree = {
 118                 {.offset = 2,
 119                  .length = 78}}
 120 };
 121
 122
 123 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 124                            int new_state);
 125
 126 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 127                              struct mtd_oob_ops *ops);
 128
 129 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 130
 131 /*
 132  * For devices which display every fart in the system on a separate LED. Is
 133  * compiled away when LED support is disabled.
 134  */
 135 /* XXX U-BOOT XXX */
 136 #if 0
 137 DEFINE_LED_TRIGGER(nand_led_trigger);
 138 #endif
 139
 140 /**
 141  * nand_release_device - [GENERIC] release chip
 142  * @mtd:        MTD device structure
 143  *
 144  * Deselect, release chip lock and wake up anyone waiting on the device
 145  */
 146 /* XXX U-BOOT XXX */
 147 #if 0
 148 static void nand_release_device(struct mtd_info *mtd)
 149 {
 150         struct nand_chip *chip = mtd->priv;
 151
 152         /* De-select the NAND device */
 153         chip->select_chip(mtd, -1);
 154
 155         /* Release the controller and the chip */
 156         spin_lock(&chip->controller->lock);
 157         chip->controller->active = NULL;
 158         chip->state = FL_READY;
 159         wake_up(&chip->controller->wq);
 160         spin_unlock(&chip->controller->lock);
 161 }
 162 #else
 163 static void nand_release_device (struct mtd_info *mtd)
 164 {
 165         struct nand_chip *this = mtd->priv;
 166         this->select_chip(mtd, -1);     /* De-select the NAND device */
 167 }
 168 #endif
 169
 170 /**
 171  * nand_read_byte - [DEFAULT] read one byte from the chip
 172  * @mtd:        MTD device structure
 173  *
 174  * Default read function for 8bit buswith
 175  */
 176 static uint8_t nand_read_byte(struct mtd_info *mtd)
 177 {
 178         struct nand_chip *chip = mtd->priv;
 179         return readb(chip->IO_ADDR_R);
 180 }
 181
 182 /**
 183  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 184  * @mtd:        MTD device structure
 185  *
 186  * Default read function for 16bit buswith with
 187  * endianess conversion
 188  */
 189 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 190 {
 191         struct nand_chip *chip = mtd->priv;
 192         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 193 }
 194
 195 /**
 196  * nand_read_word - [DEFAULT] read one word from the chip
 197  * @mtd:        MTD device structure
 198  *
 199  * Default read function for 16bit buswith without
 200  * endianess conversion
 201  */
 202 static u16 nand_read_word(struct mtd_info *mtd)
 203 {
 204         struct nand_chip *chip = mtd->priv;
 205         return readw(chip->IO_ADDR_R);
 206 }
 207
 208 /**
 209  * nand_select_chip - [DEFAULT] control CE line
 210  * @mtd:        MTD device structure
 211  * @chipnr:     chipnumber to select, -1 for deselect
 212  *
 213  * Default select function for 1 chip devices.
 214  */
 215 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 216 {
 217         struct nand_chip *chip = mtd->priv;
 218
 219         switch (chipnr) {
 220         case -1:
 221                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 222                 break;
 223         case 0:
 224                 break;
 225
 226         default:
 227                 BUG();
 228         }
 229 }
 230
 231 /**
 232  * nand_write_buf - [DEFAULT] write buffer to chip
 233  * @mtd:        MTD device structure
 234  * @buf:        data buffer
 235  * @len:        number of bytes to write
 236  *
 237  * Default write function for 8bit buswith
 238  */
 239 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 240 {
 241         int i;
 242         struct nand_chip *chip = mtd->priv;
 243
 244         for (i = 0; i < len; i++)
 245                 writeb(buf[i], chip->IO_ADDR_W);
 246 }
 247
 248 /**
 249  * nand_read_buf - [DEFAULT] read chip data into buffer
 250  * @mtd:        MTD device structure
 251  * @buf:        buffer to store date
 252  * @len:        number of bytes to read
 253  *
 254  * Default read function for 8bit buswith
 255  */
 256 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 257 {
 258         int i;
 259         struct nand_chip *chip = mtd->priv;
 260
 261         for (i = 0; i < len; i++)
 262                 buf[i] = readb(chip->IO_ADDR_R);
 263 }
 264
 265 /**
 266  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 267  * @mtd:        MTD device structure
 268  * @buf:        buffer containing the data to compare
 269  * @len:        number of bytes to compare
 270  *
 271  * Default verify function for 8bit buswith
 272  */
 273 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 274 {
 275         int i;
 276         struct nand_chip *chip = mtd->priv;
 277
 278         for (i = 0; i < len; i++)
 279                 if (buf[i] != readb(chip->IO_ADDR_R))
 280                         return -EFAULT;
 281         return 0;
 282 }
 283
 284 /**
 285  * nand_write_buf16 - [DEFAULT] write buffer to chip
 286  * @mtd:        MTD device structure
 287  * @buf:        data buffer
 288  * @len:        number of bytes to write
 289  *
 290  * Default write function for 16bit buswith
 291  */
 292 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 293 {
 294         int i;
 295         struct nand_chip *chip = mtd->priv;
 296         u16 *p = (u16 *) buf;
 297         len >>= 1;
 298
 299         for (i = 0; i < len; i++)
 300                 writew(p[i], chip->IO_ADDR_W);
 301
 302 }
 303
 304 /**
 305  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 306  * @mtd:        MTD device structure
 307  * @buf:        buffer to store date
 308  * @len:        number of bytes to read
 309  *
 310  * Default read function for 16bit buswith
 311  */
 312 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 313 {
 314         int i;
 315         struct nand_chip *chip = mtd->priv;
 316         u16 *p = (u16 *) buf;
 317         len >>= 1;
 318
 319         for (i = 0; i < len; i++)
 320                 p[i] = readw(chip->IO_ADDR_R);
 321 }
 322
 323 /**
 324  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 325  * @mtd:        MTD device structure
 326  * @buf:        buffer containing the data to compare
 327  * @len:        number of bytes to compare
 328  *
 329  * Default verify function for 16bit buswith
 330  */
 331 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 332 {
 333         int i;
 334         struct nand_chip *chip = mtd->priv;
 335         u16 *p = (u16 *) buf;
 336         len >>= 1;
 337
 338         for (i = 0; i < len; i++)
 339                 if (p[i] != readw(chip->IO_ADDR_R))
 340                         return -EFAULT;
 341
 342         return 0;
 343 }
 344
 345 /**
 346  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 347  * @mtd:        MTD device structure
 348  * @ofs:        offset from device start
 349  * @getchip:    0, if the chip is already selected
 350  *
 351  * Check, if the block is bad.
 352  */
 353 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 354 {
 355         int page, chipnr, res = 0;
 356         struct nand_chip *chip = mtd->priv;
 357         u16 bad;
 358
 359         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 360
 361         if (getchip) {
 362                 chipnr = (int)(ofs >> chip->chip_shift);
 363
 364                 nand_get_device(chip, mtd, FL_READING);
 365
 366                 /* Select the NAND device */
 367                 chip->select_chip(mtd, chipnr);
 368         }
 369
 370         if (chip->options & NAND_BUSWIDTH_16) {
 371                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 372                               page);
 373                 bad = cpu_to_le16(chip->read_word(mtd));
 374                 if (chip->badblockpos & 0x1)
 375                         bad >>= 8;
 376                 if ((bad & 0xFF) != 0xff)
 377                         res = 1;
 378         } else {
 379                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 380                 if (chip->read_byte(mtd) != 0xff)
 381                         res = 1;
 382         }
 383
 384         if (getchip)
 385                 nand_release_device(mtd);
 386
 387         return res;
 388 }
 389
 390 /**
 391  * nand_default_block_markbad - [DEFAULT] mark a block bad
 392  * @mtd:        MTD device structure
 393  * @ofs:        offset from device start
 394  *
 395  * This is the default implementation, which can be overridden by
 396  * a hardware specific driver.
 397 */
 398 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 399 {
 400         struct nand_chip *chip = mtd->priv;
 401         uint8_t buf[2] = { 0, 0 };
 402         int block, ret;
 403
 404         /* Get block number */
 405         block = (int)(ofs >> chip->bbt_erase_shift);
 406         if (chip->bbt)
 407                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 408
 409         /* Do we have a flash based bad block table ? */
 410         if (chip->options & NAND_USE_FLASH_BBT)
 411                 ret = nand_update_bbt(mtd, ofs);
 412         else {
 413                 /* We write two bytes, so we dont have to mess with 16 bit
 414                  * access
 415                  */
 416                 nand_get_device(chip, mtd, FL_WRITING);
 417                 ofs += mtd->oobsize;
 418                 chip->ops.len = chip->ops.ooblen = 2;
 419                 chip->ops.datbuf = NULL;
 420                 chip->ops.oobbuf = buf;
 421                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 422
 423                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 424                 nand_release_device(mtd);
 425         }
 426         if (!ret)
 427                 mtd->ecc_stats.badblocks++;
 428
 429         return ret;
 430 }
 431
 432 /**
 433  * nand_check_wp - [GENERIC] check if the chip is write protected
 434  * @mtd:        MTD device structure
 435  * Check, if the device is write protected
 436  *
 437  * The function expects, that the device is already selected
 438  */
 439 static int nand_check_wp(struct mtd_info *mtd)
 440 {
 441         struct nand_chip *chip = mtd->priv;
 442         /* Check the WP bit */
 443         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 444         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 445 }
 446
 447 /**
 448  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 449  * @mtd:        MTD device structure
 450  * @ofs:        offset from device start
 451  * @getchip:    0, if the chip is already selected
 452  * @allowbbt:   1, if its allowed to access the bbt area
 453  *
 454  * Check, if the block is bad. Either by reading the bad block table or
 455  * calling of the scan function.
 456  */
 457 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 458                                int allowbbt)
 459 {
 460         struct nand_chip *chip = mtd->priv;
 461
 462         if (!(chip->options & NAND_BBT_SCANNED)) {
 463                 chip->scan_bbt(mtd);
 464                 chip->options |= NAND_BBT_SCANNED;
 465         }
 466
 467         if (!chip->bbt)
 468                 return chip->block_bad(mtd, ofs, getchip);
 469
 470         /* Return info from the table */
 471         return nand_isbad_bbt(mtd, ofs, allowbbt);
 472 }
 473
 474 /*
 475  * Wait for the ready pin, after a command
 476  * The timeout is catched later.
 477  */
 478 /* XXX U-BOOT XXX */
 479 #if 0
 480 void nand_wait_ready(struct mtd_info *mtd)
 481 {
 482         struct nand_chip *chip = mtd->priv;
 483         unsigned long timeo = jiffies + 2;
 484
 485         led_trigger_event(nand_led_trigger, LED_FULL);
 486         /* wait until command is processed or timeout occures */
 487         do {
 488                 if (chip->dev_ready(mtd))
 489                         break;
 490                 touch_softlockup_watchdog();
 491         } while (time_before(jiffies, timeo));
 492         led_trigger_event(nand_led_trigger, LED_OFF);
 493 }
 494 EXPORT_SYMBOL_GPL(nand_wait_ready);
 495 #else
 496 void nand_wait_ready(struct mtd_info *mtd)
 497 {
 498         struct nand_chip *chip = mtd->priv;
 499         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 500
 501         reset_timer();
 502
 503         /* wait until command is processed or timeout occures */
 504         while (get_timer(0) < timeo) {
 505                 if (chip->dev_ready)
 506                         if (chip->dev_ready(mtd))
 507                                 break;
 508         }
 509 }
 510 #endif
 511
 512 /**
 513  * nand_command - [DEFAULT] Send command to NAND device
 514  * @mtd:        MTD device structure
 515  * @command:    the command to be sent
 516  * @column:     the column address for this command, -1 if none
 517  * @page_addr:  the page address for this command, -1 if none
 518  *
 519  * Send command to NAND device. This function is used for small page
 520  * devices (256/512 Bytes per page)
 521  */
 522 static void nand_command(struct mtd_info *mtd, unsigned int command,
 523                          int column, int page_addr)
 524 {
 525         register struct nand_chip *chip = mtd->priv;
 526         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 527
 528         /*
 529          * Write out the command to the device.
 530          */
 531         if (command == NAND_CMD_SEQIN) {
 532                 int readcmd;
 533
 534                 if (column >= mtd->writesize) {
 535                         /* OOB area */
 536                         column -= mtd->writesize;
 537                         readcmd = NAND_CMD_READOOB;
 538                 } else if (column < 256) {
 539                         /* First 256 bytes --> READ0 */
 540                         readcmd = NAND_CMD_READ0;
 541                 } else {
 542                         column -= 256;
 543                         readcmd = NAND_CMD_READ1;
 544                 }
 545                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 546                 ctrl &= ~NAND_CTRL_CHANGE;
 547         }
 548         chip->cmd_ctrl(mtd, command, ctrl);
 549
 550         /*
 551          * Address cycle, when necessary
 552          */
 553         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 554         /* Serially input address */
 555         if (column != -1) {
 556                 /* Adjust columns for 16 bit buswidth */
 557                 if (chip->options & NAND_BUSWIDTH_16)
 558                         column >>= 1;
 559                 chip->cmd_ctrl(mtd, column, ctrl);
 560                 ctrl &= ~NAND_CTRL_CHANGE;
 561         }
 562         if (page_addr != -1) {
 563                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 564                 ctrl &= ~NAND_CTRL_CHANGE;
 565                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 566                 /* One more address cycle for devices > 32MiB */
 567                 if (chip->chipsize > (32 << 20))
 568                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 569         }
 570         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 571
 572         /*
 573          * program and erase have their own busy handlers
 574          * status and sequential in needs no delay
 575          */
 576         switch (command) {
 577
 578         case NAND_CMD_PAGEPROG:
 579         case NAND_CMD_ERASE1:
 580         case NAND_CMD_ERASE2:
 581         case NAND_CMD_SEQIN:
 582         case NAND_CMD_STATUS:
 583                 return;
 584
 585         case NAND_CMD_RESET:
 586                 if (chip->dev_ready)
 587                         break;
 588                 udelay(chip->chip_delay);
 589                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 590                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 591                 chip->cmd_ctrl(mtd,
 592                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 593                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 594                 return;
 595
 596                 /* This applies to read commands */
 597         default:
 598                 /*
 599                  * If we don't have access to the busy pin, we apply the given
 600                  * command delay
 601                  */
 602                 if (!chip->dev_ready) {
 603                         udelay(chip->chip_delay);
 604                         return;
 605                 }
 606         }
 607         /* Apply this short delay always to ensure that we do wait tWB in
 608          * any case on any machine. */
 609         ndelay(100);
 610
 611         nand_wait_ready(mtd);
 612 }
 613
 614 /**
 615  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 616  * @mtd:        MTD device structure
 617  * @command:    the command to be sent
 618  * @column:     the column address for this command, -1 if none
 619  * @page_addr:  the page address for this command, -1 if none
 620  *
 621  * Send command to NAND device. This is the version for the new large page
 622  * devices We dont have the separate regions as we have in the small page
 623  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 624  */
 625 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 626                             int column, int page_addr)
 627 {
 628         register struct nand_chip *chip = mtd->priv;
 629
 630         /* Emulate NAND_CMD_READOOB */
 631         if (command == NAND_CMD_READOOB) {
 632                 column += mtd->writesize;
 633                 command = NAND_CMD_READ0;
 634         }
 635
 636         /* Command latch cycle */
 637         chip->cmd_ctrl(mtd, command & 0xff,
 638                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 639
 640         if (column != -1 || page_addr != -1) {
 641                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 642
 643                 /* Serially input address */
 644                 if (column != -1) {
 645                         /* Adjust columns for 16 bit buswidth */
 646                         if (chip->options & NAND_BUSWIDTH_16)
 647                                 column >>= 1;
 648                         chip->cmd_ctrl(mtd, column, ctrl);
 649                         ctrl &= ~NAND_CTRL_CHANGE;
 650                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 651                 }
 652                 if (page_addr != -1) {
 653                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 654                         chip->cmd_ctrl(mtd, page_addr >> 8,
 655                                        NAND_NCE | NAND_ALE);
 656                         /* One more address cycle for devices > 128MiB */
 657                         if (chip->chipsize > (128 << 20))
 658                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 659                                                NAND_NCE | NAND_ALE);
 660                 }
 661         }
 662         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 663
 664         /*
 665          * program and erase have their own busy handlers
 666          * status, sequential in, and deplete1 need no delay
 667          */
 668         switch (command) {
 669
 670         case NAND_CMD_CACHEDPROG:
 671         case NAND_CMD_PAGEPROG:
 672         case NAND_CMD_ERASE1:
 673         case NAND_CMD_ERASE2:
 674         case NAND_CMD_SEQIN:
 675         case NAND_CMD_RNDIN:
 676         case NAND_CMD_STATUS:
 677         case NAND_CMD_DEPLETE1:
 678                 return;
 679
 680                 /*
 681                  * read error status commands require only a short delay
 682                  */
 683         case NAND_CMD_STATUS_ERROR:
 684         case NAND_CMD_STATUS_ERROR0:
 685         case NAND_CMD_STATUS_ERROR1:
 686         case NAND_CMD_STATUS_ERROR2:
 687         case NAND_CMD_STATUS_ERROR3:
 688                 udelay(chip->chip_delay);
 689                 return;
 690
 691         case NAND_CMD_RESET:
 692                 if (chip->dev_ready)
 693                         break;
 694                 udelay(chip->chip_delay);
 695                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 696                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 697                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 698                                NAND_NCE | NAND_CTRL_CHANGE);
 699                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 700                 return;
 701
 702         case NAND_CMD_RNDOUT:
 703                 /* No ready / busy check necessary */
 704                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 705                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 706                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 707                                NAND_NCE | NAND_CTRL_CHANGE);
 708                 return;
 709
 710         case NAND_CMD_READ0:
 711                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 712                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 713                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 714                                NAND_NCE | NAND_CTRL_CHANGE);
 715
 716                 /* This applies to read commands */
 717         default:
 718                 /*
 719                  * If we don't have access to the busy pin, we apply the given
 720                  * command delay
 721                  */
 722                 if (!chip->dev_ready) {
 723                         udelay(chip->chip_delay);
 724                         return;
 725                 }
 726         }
 727
 728         /* Apply this short delay always to ensure that we do wait tWB in
 729          * any case on any machine. */
 730         ndelay(100);
 731
 732         nand_wait_ready(mtd);
 733 }
 734
 735 /**
 736  * nand_get_device - [GENERIC] Get chip for selected access
 737  * @chip:       the nand chip descriptor
 738  * @mtd:        MTD device structure
 739  * @new_state:  the state which is requested
 740  *
 741  * Get the device and lock it for exclusive access
 742  */
 743 /* XXX U-BOOT XXX */
 744 #if 0
 745 static int
 746 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 747 {
 748         spinlock_t *lock = &chip->controller->lock;
 749         wait_queue_head_t *wq = &chip->controller->wq;
 750         DECLARE_WAITQUEUE(wait, current);
 751  retry:
 752         spin_lock(lock);
 753
 754         /* Hardware controller shared among independend devices */
 755         /* Hardware controller shared among independend devices */
 756         if (!chip->controller->active)
 757                 chip->controller->active = chip;
 758
 759         if (chip->controller->active == chip && chip->state == FL_READY) {
 760                 chip->state = new_state;
 761                 spin_unlock(lock);
 762                 return 0;
 763         }
 764         if (new_state == FL_PM_SUSPENDED) {
 765                 spin_unlock(lock);
 766                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 767         }
 768         set_current_state(TASK_UNINTERRUPTIBLE);
 769         add_wait_queue(wq, &wait);
 770         spin_unlock(lock);
 771         schedule();
 772         remove_wait_queue(wq, &wait);
 773         goto retry;
 774 }
 775 #else
 776 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 777 {
 778         this->state = new_state;
 779         return 0;
 780 }
 781 #endif
 782
 783 /**
 784  * nand_wait - [DEFAULT]  wait until the command is done
 785  * @mtd:        MTD device structure
 786  * @chip:       NAND chip structure
 787  *
 788  * Wait for command done. This applies to erase and program only
 789  * Erase can take up to 400ms and program up to 20ms according to
 790  * general NAND and SmartMedia specs
 791  */
 792 /* XXX U-BOOT XXX */
 793 #if 0
 794 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 795 {
 796
 797         unsigned long timeo = jiffies;
 798         int status, state = chip->state;
 799
 800         if (state == FL_ERASING)
 801                 timeo += (HZ * 400) / 1000;
 802         else
 803                 timeo += (HZ * 20) / 1000;
 804
 805         led_trigger_event(nand_led_trigger, LED_FULL);
 806
 807         /* Apply this short delay always to ensure that we do wait tWB in
 808          * any case on any machine. */
 809         ndelay(100);
 810
 811         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 812                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 813         else
 814                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 815
 816         while (time_before(jiffies, timeo)) {
 817                 if (chip->dev_ready) {
 818                         if (chip->dev_ready(mtd))
 819                                 break;
 820                 } else {
 821                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 822                                 break;
 823                 }
 824                 cond_resched();
 825         }
 826         led_trigger_event(nand_led_trigger, LED_OFF);
 827
 828         status = (int)chip->read_byte(mtd);
 829         return status;
 830 }
 831 #else
 832 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 833 {
 834         unsigned long   timeo;
 835         int state = this->state;
 836
 837         if (state == FL_ERASING)
 838                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 839         else
 840                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 841
 842         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 843                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 844         else
 845                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 846
 847         reset_timer();
 848
 849         while (1) {
 850                 if (get_timer(0) > timeo) {
 851                         printf("Timeout!");
 852                         return 0x01;
 853                 }
 854
 855                 if (this->dev_ready) {
 856                         if (this->dev_ready(mtd))
 857                                 break;
 858                 } else {
 859                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 860                                 break;
 861                 }
 862         }
 863 #ifdef PPCHAMELON_NAND_TIMER_HACK
 864         reset_timer();
 865         while (get_timer(0) < 10);
 866 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 867
 868         return this->read_byte(mtd);
 869 }
 870 #endif
 871
 872 /**
 873  * nand_read_page_raw - [Intern] read raw page data without ecc
 874  * @mtd:        mtd info structure
 875  * @chip:       nand chip info structure
 876  * @buf:        buffer to store read data
 877  */
 878 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 879                               uint8_t *buf)
 880 {
 881         chip->read_buf(mtd, buf, mtd->writesize);
 882         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 883         return 0;
 884 }
 885
 886 /**
 887  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 888  * @mtd:        mtd info structure
 889  * @chip:       nand chip info structure
 890  * @buf:        buffer to store read data
 891  */
 892 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 893                                 uint8_t *buf)
 894 {
 895         int i, eccsize = chip->ecc.size;
 896         int eccbytes = chip->ecc.bytes;
 897         int eccsteps = chip->ecc.steps;
 898         uint8_t *p = buf;
 899         uint8_t *ecc_calc = chip->buffers->ecccalc;
 900         uint8_t *ecc_code = chip->buffers->ecccode;
 901         uint32_t *eccpos = chip->ecc.layout->eccpos;
 902
 903         chip->ecc.read_page_raw(mtd, chip, buf);
 904
 905         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 906                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 907
 908         for (i = 0; i < chip->ecc.total; i++)
 909                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 910
 911         eccsteps = chip->ecc.steps;
 912         p = buf;
 913
 914         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 915                 int stat;
 916
 917                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 918                 if (stat < 0)
 919                         mtd->ecc_stats.failed++;
 920                 else
 921                         mtd->ecc_stats.corrected += stat;
 922         }
 923         return 0;
 924 }
 925
 926 /**
 927  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 928  * @mtd:        mtd info structure
 929  * @chip:       nand chip info structure
 930  * @dataofs     offset of requested data within the page
 931  * @readlen     data length
 932  * @buf:        buffer to store read data
 933  */
 934 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 935 {
 936         int start_step, end_step, num_steps;
 937         uint32_t *eccpos = chip->ecc.layout->eccpos;
 938         uint8_t *p;
 939         int data_col_addr, i, gaps = 0;
 940         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 941         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 942
 943         /* Column address wihin the page aligned to ECC size (256bytes). */
 944         start_step = data_offs / chip->ecc.size;
 945         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 946         num_steps = end_step - start_step + 1;
 947
 948         /* Data size aligned to ECC ecc.size*/
 949         datafrag_len = num_steps * chip->ecc.size;
 950         eccfrag_len = num_steps * chip->ecc.bytes;
 951
 952         data_col_addr = start_step * chip->ecc.size;
 953         /* If we read not a page aligned data */
 954         if (data_col_addr != 0)
 955                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 956
 957         p = bufpoi + data_col_addr;
 958         chip->read_buf(mtd, p, datafrag_len);
 959
 960         /* Calculate  ECC */
 961         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 962                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 963
 964         /* The performance is faster if to position offsets
 965            according to ecc.pos. Let make sure here that
 966            there are no gaps in ecc positions */
 967         for (i = 0; i < eccfrag_len - 1; i++) {
 968                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 969                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 970                         gaps = 1;
 971                         break;
 972                 }
 973         }
 974         if (gaps) {
 975                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 976                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 977         } else {
 978                 /* send the command to read the particular ecc bytes */
 979                 /* take care about buswidth alignment in read_buf */
 980                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 981                 aligned_len = eccfrag_len;
 982                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 983                         aligned_len++;
 984                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
 985                         aligned_len++;
 986
 987                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
 988                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
 989         }
 990
 991         for (i = 0; i < eccfrag_len; i++)
 992                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
 993
 994         p = bufpoi + data_col_addr;
 995         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
 996                 int stat;
 997
 998                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
 999                 if (stat < 0)
1000                         mtd->ecc_stats.failed++;
1001                 else
1002                         mtd->ecc_stats.corrected += stat;
1003         }
1004         return 0;
1005 }
1006
1007 /**
1008  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1009  * @mtd:        mtd info structure
1010  * @chip:       nand chip info structure
1011  * @buf:        buffer to store read data
1012  *
1013  * Not for syndrome calculating ecc controllers which need a special oob layout
1014  */
1015 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1016                                 uint8_t *buf)
1017 {
1018         int i, eccsize = chip->ecc.size;
1019         int eccbytes = chip->ecc.bytes;
1020         int eccsteps = chip->ecc.steps;
1021         uint8_t *p = buf;
1022         uint8_t *ecc_calc = chip->buffers->ecccalc;
1023         uint8_t *ecc_code = chip->buffers->ecccode;
1024         uint32_t *eccpos = chip->ecc.layout->eccpos;
1025
1026         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1027                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1028                 chip->read_buf(mtd, p, eccsize);
1029                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1030         }
1031         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1032
1033         for (i = 0; i < chip->ecc.total; i++)
1034                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1035
1036         eccsteps = chip->ecc.steps;
1037         p = buf;
1038
1039         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1040                 int stat;
1041
1042                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1043                 if (stat == -1)
1044                         mtd->ecc_stats.failed++;
1045                 else
1046                         mtd->ecc_stats.corrected += stat;
1047         }
1048         return 0;
1049 }
1050
1051 /**
1052  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1053  * @mtd:        mtd info structure
1054  * @chip:       nand chip info structure
1055  * @buf:        buffer to store read data
1056  *
1057  * The hw generator calculates the error syndrome automatically. Therefor
1058  * we need a special oob layout and handling.
1059  */
1060 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1061                                    uint8_t *buf)
1062 {
1063         int i, eccsize = chip->ecc.size;
1064         int eccbytes = chip->ecc.bytes;
1065         int eccsteps = chip->ecc.steps;
1066         uint8_t *p = buf;
1067         uint8_t *oob = chip->oob_poi;
1068
1069         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1070                 int stat;
1071
1072                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1073                 chip->read_buf(mtd, p, eccsize);
1074
1075                 if (chip->ecc.prepad) {
1076                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1077                         oob += chip->ecc.prepad;
1078                 }
1079
1080                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1081                 chip->read_buf(mtd, oob, eccbytes);
1082                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1083
1084                 if (stat < 0)
1085                         mtd->ecc_stats.failed++;
1086                 else
1087                         mtd->ecc_stats.corrected += stat;
1088
1089                 oob += eccbytes;
1090
1091                 if (chip->ecc.postpad) {
1092                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1093                         oob += chip->ecc.postpad;
1094                 }
1095         }
1096
1097         /* Calculate remaining oob bytes */
1098         i = mtd->oobsize - (oob - chip->oob_poi);
1099         if (i)
1100                 chip->read_buf(mtd, oob, i);
1101
1102         return 0;
1103 }
1104
1105 /**
1106  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1107  * @chip:       nand chip structure
1108  * @oob:        oob destination address
1109  * @ops:        oob ops structure
1110  * @len:        size of oob to transfer
1111  */
1112 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1113                                   struct mtd_oob_ops *ops, size_t len)
1114 {
1115         switch(ops->mode) {
1116
1117         case MTD_OOB_PLACE:
1118         case MTD_OOB_RAW:
1119                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1120                 return oob + len;
1121
1122         case MTD_OOB_AUTO: {
1123                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1124                 uint32_t boffs = 0, roffs = ops->ooboffs;
1125                 size_t bytes = 0;
1126
1127                 for(; free->length && len; free++, len -= bytes) {
1128                         /* Read request not from offset 0 ? */
1129                         if (unlikely(roffs)) {
1130                                 if (roffs >= free->length) {
1131                                         roffs -= free->length;
1132                                         continue;
1133                                 }
1134                                 boffs = free->offset + roffs;
1135                                 bytes = min_t(size_t, len,
1136                                               (free->length - roffs));
1137                                 roffs = 0;
1138                         } else {
1139                                 bytes = min_t(size_t, len, free->length);
1140                                 boffs = free->offset;
1141                         }
1142                         memcpy(oob, chip->oob_poi + boffs, bytes);
1143                         oob += bytes;
1144                 }
1145                 return oob;
1146         }
1147         default:
1148                 BUG();
1149         }
1150         return NULL;
1151 }
1152
1153 /**
1154  * nand_do_read_ops - [Internal] Read data with ECC
1155  *
1156  * @mtd:        MTD device structure
1157  * @from:       offset to read from
1158  * @ops:        oob ops structure
1159  *
1160  * Internal function. Called with chip held.
1161  */
1162 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1163                             struct mtd_oob_ops *ops)
1164 {
1165         int chipnr, page, realpage, col, bytes, aligned;
1166         struct nand_chip *chip = mtd->priv;
1167         struct mtd_ecc_stats stats;
1168         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1169         int sndcmd = 1;
1170         int ret = 0;
1171         uint32_t readlen = ops->len;
1172         uint32_t oobreadlen = ops->ooblen;
1173         uint8_t *bufpoi, *oob, *buf;
1174
1175         stats = mtd->ecc_stats;
1176
1177         chipnr = (int)(from >> chip->chip_shift);
1178         chip->select_chip(mtd, chipnr);
1179
1180         realpage = (int)(from >> chip->page_shift);
1181         page = realpage & chip->pagemask;
1182
1183         col = (int)(from & (mtd->writesize - 1));
1184
1185         buf = ops->datbuf;
1186         oob = ops->oobbuf;
1187
1188         while(1) {
1189                 bytes = min(mtd->writesize - col, readlen);
1190                 aligned = (bytes == mtd->writesize);
1191
1192                 /* Is the current page in the buffer ? */
1193                 if (realpage != chip->pagebuf || oob) {
1194                         bufpoi = aligned ? buf : chip->buffers->databuf;
1195
1196                         if (likely(sndcmd)) {
1197                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1198                                 sndcmd = 0;
1199                         }
1200
1201                         /* Now read the page into the buffer */
1202                         if (unlikely(ops->mode == MTD_OOB_RAW))
1203                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1204                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1205                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1206                         else
1207                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1208                         if (ret < 0)
1209                                 break;
1210
1211                         /* Transfer not aligned data */
1212                         if (!aligned) {
1213                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1214                                         chip->pagebuf = realpage;
1215                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1216                         }
1217
1218                         buf += bytes;
1219
1220                         if (unlikely(oob)) {
1221                                 /* Raw mode does data:oob:data:oob */
1222                                 if (ops->mode != MTD_OOB_RAW) {
1223                                         int toread = min(oobreadlen,
1224                                                 chip->ecc.layout->oobavail);
1225                                         if (toread) {
1226                                                 oob = nand_transfer_oob(chip,
1227                                                         oob, ops, toread);
1228                                                 oobreadlen -= toread;
1229                                         }
1230                                 } else
1231                                         buf = nand_transfer_oob(chip,
1232                                                 buf, ops, mtd->oobsize);
1233                         }
1234
1235                         if (!(chip->options & NAND_NO_READRDY)) {
1236                                 /*
1237                                  * Apply delay or wait for ready/busy pin. Do
1238                                  * this before the AUTOINCR check, so no
1239                                  * problems arise if a chip which does auto
1240                                  * increment is marked as NOAUTOINCR by the
1241                                  * board driver.
1242                                  */
1243                                 if (!chip->dev_ready)
1244                                         udelay(chip->chip_delay);
1245                                 else
1246                                         nand_wait_ready(mtd);
1247                         }
1248                 } else {
1249                         memcpy(buf, chip->buffers->databuf + col, bytes);
1250                         buf += bytes;
1251                 }
1252
1253                 readlen -= bytes;
1254
1255                 if (!readlen)
1256                         break;
1257
1258                 /* For subsequent reads align to page boundary. */
1259                 col = 0;
1260                 /* Increment page address */
1261                 realpage++;
1262
1263                 page = realpage & chip->pagemask;
1264                 /* Check, if we cross a chip boundary */
1265                 if (!page) {
1266                         chipnr++;
1267                         chip->select_chip(mtd, -1);
1268                         chip->select_chip(mtd, chipnr);
1269                 }
1270
1271                 /* Check, if the chip supports auto page increment
1272                  * or if we have hit a block boundary.
1273                  */
1274                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1275                         sndcmd = 1;
1276         }
1277
1278         ops->retlen = ops->len - (size_t) readlen;
1279         if (oob)
1280                 ops->oobretlen = ops->ooblen - oobreadlen;
1281
1282         if (ret)
1283                 return ret;
1284
1285         if (mtd->ecc_stats.failed - stats.failed)
1286                 return -EBADMSG;
1287
1288         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1289 }
1290
1291 /**
1292  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1293  * @mtd:        MTD device structure
1294  * @from:       offset to read from
1295  * @len:        number of bytes to read
1296  * @retlen:     pointer to variable to store the number of read bytes
1297  * @buf:        the databuffer to put data
1298  *
1299  * Get hold of the chip and call nand_do_read
1300  */
1301 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1302                      size_t *retlen, uint8_t *buf)
1303 {
1304         struct nand_chip *chip = mtd->priv;
1305         int ret;
1306
1307         /* Do not allow reads past end of device */
1308         if ((from + len) > mtd->size)
1309                 return -EINVAL;
1310         if (!len)
1311                 return 0;
1312
1313         nand_get_device(chip, mtd, FL_READING);
1314
1315         chip->ops.len = len;
1316         chip->ops.datbuf = buf;
1317         chip->ops.oobbuf = NULL;
1318
1319         ret = nand_do_read_ops(mtd, from, &chip->ops);
1320
1321         *retlen = chip->ops.retlen;
1322
1323         nand_release_device(mtd);
1324
1325         return ret;
1326 }
1327
1328 /**
1329  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1330  * @mtd:        mtd info structure
1331  * @chip:       nand chip info structure
1332  * @page:       page number to read
1333  * @sndcmd:     flag whether to issue read command or not
1334  */
1335 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1336                              int page, int sndcmd)
1337 {
1338         if (sndcmd) {
1339                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1340                 sndcmd = 0;
1341         }
1342         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1343         return sndcmd;
1344 }
1345
1346 /**
1347  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1348  *                          with syndromes
1349  * @mtd:        mtd info structure
1350  * @chip:       nand chip info structure
1351  * @page:       page number to read
1352  * @sndcmd:     flag whether to issue read command or not
1353  */
1354 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1355                                   int page, int sndcmd)
1356 {
1357         uint8_t *buf = chip->oob_poi;
1358         int length = mtd->oobsize;
1359         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1360         int eccsize = chip->ecc.size;
1361         uint8_t *bufpoi = buf;
1362         int i, toread, sndrnd = 0, pos;
1363
1364         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1365         for (i = 0; i < chip->ecc.steps; i++) {
1366                 if (sndrnd) {
1367                         pos = eccsize + i * (eccsize + chunk);
1368                         if (mtd->writesize > 512)
1369                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1370                         else
1371                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1372                 } else
1373                         sndrnd = 1;
1374                 toread = min_t(int, length, chunk);
1375                 chip->read_buf(mtd, bufpoi, toread);
1376                 bufpoi += toread;
1377                 length -= toread;
1378         }
1379         if (length > 0)
1380                 chip->read_buf(mtd, bufpoi, length);
1381
1382         return 1;
1383 }
1384
1385 /**
1386  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1387  * @mtd:        mtd info structure
1388  * @chip:       nand chip info structure
1389  * @page:       page number to write
1390  */
1391 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1392                               int page)
1393 {
1394         int status = 0;
1395         const uint8_t *buf = chip->oob_poi;
1396         int length = mtd->oobsize;
1397
1398         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1399         chip->write_buf(mtd, buf, length);
1400         /* Send command to program the OOB data */
1401         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1402
1403         status = chip->waitfunc(mtd, chip);
1404
1405         return status & NAND_STATUS_FAIL ? -EIO : 0;
1406 }
1407
1408 /**
1409  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1410  *                           with syndrome - only for large page flash !
1411  * @mtd:        mtd info structure
1412  * @chip:       nand chip info structure
1413  * @page:       page number to write
1414  */
1415 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1416                                    struct nand_chip *chip, int page)
1417 {
1418         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1419         int eccsize = chip->ecc.size, length = mtd->oobsize;
1420         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1421         const uint8_t *bufpoi = chip->oob_poi;
1422
1423         /*
1424          * data-ecc-data-ecc ... ecc-oob
1425          * or
1426          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1427          */
1428         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1429                 pos = steps * (eccsize + chunk);
1430                 steps = 0;
1431         } else
1432                 pos = eccsize;
1433
1434         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1435         for (i = 0; i < steps; i++) {
1436                 if (sndcmd) {
1437                         if (mtd->writesize <= 512) {
1438                                 uint32_t fill = 0xFFFFFFFF;
1439
1440                                 len = eccsize;
1441                                 while (len > 0) {
1442                                         int num = min_t(int, len, 4);
1443                                         chip->write_buf(mtd, (uint8_t *)&fill,
1444                                                         num);
1445                                         len -= num;
1446                                 }
1447                         } else {
1448                                 pos = eccsize + i * (eccsize + chunk);
1449                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1450                         }
1451                 } else
1452                         sndcmd = 1;
1453                 len = min_t(int, length, chunk);
1454                 chip->write_buf(mtd, bufpoi, len);
1455                 bufpoi += len;
1456                 length -= len;
1457         }
1458         if (length > 0)
1459                 chip->write_buf(mtd, bufpoi, length);
1460
1461         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1462         status = chip->waitfunc(mtd, chip);
1463
1464         return status & NAND_STATUS_FAIL ? -EIO : 0;
1465 }
1466
1467 /**
1468  * nand_do_read_oob - [Intern] NAND read out-of-band
1469  * @mtd:        MTD device structure
1470  * @from:       offset to read from
1471  * @ops:        oob operations description structure
1472  *
1473  * NAND read out-of-band data from the spare area
1474  */
1475 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1476                             struct mtd_oob_ops *ops)
1477 {
1478         int page, realpage, chipnr, sndcmd = 1;
1479         struct nand_chip *chip = mtd->priv;
1480         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1481         int readlen = ops->ooblen;
1482         int len;
1483         uint8_t *buf = ops->oobbuf;
1484
1485         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1486                   (unsigned long long)from, readlen);
1487
1488         if (ops->mode == MTD_OOB_AUTO)
1489                 len = chip->ecc.layout->oobavail;
1490         else
1491                 len = mtd->oobsize;
1492
1493         if (unlikely(ops->ooboffs >= len)) {
1494                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1495                           "Attempt to start read outside oob\n");
1496                 return -EINVAL;
1497         }
1498
1499         /* Do not allow reads past end of device */
1500         if (unlikely(from >= mtd->size ||
1501                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1502                                         (from >> chip->page_shift)) * len)) {
1503                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1504                           "Attempt read beyond end of device\n");
1505                 return -EINVAL;
1506         }
1507
1508         chipnr = (int)(from >> chip->chip_shift);
1509         chip->select_chip(mtd, chipnr);
1510
1511         /* Shift to get page */
1512         realpage = (int)(from >> chip->page_shift);
1513         page = realpage & chip->pagemask;
1514
1515         while(1) {
1516                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1517
1518                 len = min(len, readlen);
1519                 buf = nand_transfer_oob(chip, buf, ops, len);
1520
1521                 if (!(chip->options & NAND_NO_READRDY)) {
1522                         /*
1523                          * Apply delay or wait for ready/busy pin. Do this
1524                          * before the AUTOINCR check, so no problems arise if a
1525                          * chip which does auto increment is marked as
1526                          * NOAUTOINCR by the board driver.
1527                          */
1528                         if (!chip->dev_ready)
1529                                 udelay(chip->chip_delay);
1530                         else
1531                                 nand_wait_ready(mtd);
1532                 }
1533
1534                 readlen -= len;
1535                 if (!readlen)
1536                         break;
1537
1538                 /* Increment page address */
1539                 realpage++;
1540
1541                 page = realpage & chip->pagemask;
1542                 /* Check, if we cross a chip boundary */
1543                 if (!page) {
1544                         chipnr++;
1545                         chip->select_chip(mtd, -1);
1546                         chip->select_chip(mtd, chipnr);
1547                 }
1548
1549                 /* Check, if the chip supports auto page increment
1550                  * or if we have hit a block boundary.
1551                  */
1552                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1553                         sndcmd = 1;
1554         }
1555
1556         ops->oobretlen = ops->ooblen;
1557         return 0;
1558 }
1559
1560 /**
1561  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1562  * @mtd:        MTD device structure
1563  * @from:       offset to read from
1564  * @ops:        oob operation description structure
1565  *
1566  * NAND read data and/or out-of-band data
1567  */
1568 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1569                          struct mtd_oob_ops *ops)
1570 {
1571         struct nand_chip *chip = mtd->priv;
1572         int ret = -ENOTSUPP;
1573
1574         ops->retlen = 0;
1575
1576         /* Do not allow reads past end of device */
1577         if (ops->datbuf && (from + ops->len) > mtd->size) {
1578                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1579                           "Attempt read beyond end of device\n");
1580                 return -EINVAL;
1581         }
1582
1583         nand_get_device(chip, mtd, FL_READING);
1584
1585         switch(ops->mode) {
1586         case MTD_OOB_PLACE:
1587         case MTD_OOB_AUTO:
1588         case MTD_OOB_RAW:
1589                 break;
1590
1591         default:
1592                 goto out;
1593         }
1594
1595         if (!ops->datbuf)
1596                 ret = nand_do_read_oob(mtd, from, ops);
1597         else
1598                 ret = nand_do_read_ops(mtd, from, ops);
1599
1600  out:
1601         nand_release_device(mtd);
1602         return ret;
1603 }
1604
1605
1606 /**
1607  * nand_write_page_raw - [Intern] raw page write function
1608  * @mtd:        mtd info structure
1609  * @chip:       nand chip info structure
1610  * @buf:        data buffer
1611  */
1612 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1613                                 const uint8_t *buf)
1614 {
1615         chip->write_buf(mtd, buf, mtd->writesize);
1616         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1617 }
1618
1619 /**
1620  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1621  * @mtd:        mtd info structure
1622  * @chip:       nand chip info structure
1623  * @buf:        data buffer
1624  */
1625 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1626                                   const uint8_t *buf)
1627 {
1628         int i, eccsize = chip->ecc.size;
1629         int eccbytes = chip->ecc.bytes;
1630         int eccsteps = chip->ecc.steps;
1631         uint8_t *ecc_calc = chip->buffers->ecccalc;
1632         const uint8_t *p = buf;
1633         uint32_t *eccpos = chip->ecc.layout->eccpos;
1634
1635         /* Software ecc calculation */
1636         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1637                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1638
1639         for (i = 0; i < chip->ecc.total; i++)
1640                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1641
1642         chip->ecc.write_page_raw(mtd, chip, buf);
1643 }
1644
1645 /**
1646  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1647  * @mtd:        mtd info structure
1648  * @chip:       nand chip info structure
1649  * @buf:        data buffer
1650  */
1651 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1652                                   const uint8_t *buf)
1653 {
1654         int i, eccsize = chip->ecc.size;
1655         int eccbytes = chip->ecc.bytes;
1656         int eccsteps = chip->ecc.steps;
1657         uint8_t *ecc_calc = chip->buffers->ecccalc;
1658         const uint8_t *p = buf;
1659         uint32_t *eccpos = chip->ecc.layout->eccpos;
1660
1661         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1662                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1663                 chip->write_buf(mtd, p, eccsize);
1664                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1665         }
1666
1667         for (i = 0; i < chip->ecc.total; i++)
1668                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1669
1670         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1671 }
1672
1673 /**
1674  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1675  * @mtd:        mtd info structure
1676  * @chip:       nand chip info structure
1677  * @buf:        data buffer
1678  *
1679  * The hw generator calculates the error syndrome automatically. Therefor
1680  * we need a special oob layout and handling.
1681  */
1682 static void nand_write_page_syndrome(struct mtd_info *mtd,
1683                                     struct nand_chip *chip, const uint8_t *buf)
1684 {
1685         int i, eccsize = chip->ecc.size;
1686         int eccbytes = chip->ecc.bytes;
1687         int eccsteps = chip->ecc.steps;
1688         const uint8_t *p = buf;
1689         uint8_t *oob = chip->oob_poi;
1690
1691         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1692
1693                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1694                 chip->write_buf(mtd, p, eccsize);
1695
1696                 if (chip->ecc.prepad) {
1697                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1698                         oob += chip->ecc.prepad;
1699                 }
1700
1701                 chip->ecc.calculate(mtd, p, oob);
1702                 chip->write_buf(mtd, oob, eccbytes);
1703                 oob += eccbytes;
1704
1705                 if (chip->ecc.postpad) {
1706                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1707                         oob += chip->ecc.postpad;
1708                 }
1709         }
1710
1711         /* Calculate remaining oob bytes */
1712         i = mtd->oobsize - (oob - chip->oob_poi);
1713         if (i)
1714                 chip->write_buf(mtd, oob, i);
1715 }
1716
1717 /**
1718  * nand_write_page - [REPLACEABLE] write one page
1719  * @mtd:        MTD device structure
1720  * @chip:       NAND chip descriptor
1721  * @buf:        the data to write
1722  * @page:       page number to write
1723  * @cached:     cached programming
1724  * @raw:        use _raw version of write_page
1725  */
1726 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1727                            const uint8_t *buf, int page, int cached, int raw)
1728 {
1729         int status;
1730
1731         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1732
1733         if (unlikely(raw))
1734                 chip->ecc.write_page_raw(mtd, chip, buf);
1735         else
1736                 chip->ecc.write_page(mtd, chip, buf);
1737
1738         /*
1739          * Cached progamming disabled for now, Not sure if its worth the
1740          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1741          */
1742         cached = 0;
1743
1744         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1745
1746                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1747                 status = chip->waitfunc(mtd, chip);
1748                 /*
1749                  * See if operation failed and additional status checks are
1750                  * available
1751                  */
1752                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1753                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1754                                                page);
1755
1756                 if (status & NAND_STATUS_FAIL)
1757                         return -EIO;
1758         } else {
1759                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1760                 status = chip->waitfunc(mtd, chip);
1761         }
1762
1763 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1764         /* Send command to read back the data */
1765         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1766
1767         if (chip->verify_buf(mtd, buf, mtd->writesize))
1768                 return -EIO;
1769 #endif
1770         return 0;
1771 }
1772
1773 /**
1774  * nand_fill_oob - [Internal] Transfer client buffer to oob
1775  * @chip:       nand chip structure
1776  * @oob:        oob data buffer
1777  * @ops:        oob ops structure
1778  */
1779 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1780                                   struct mtd_oob_ops *ops)
1781 {
1782         size_t len = ops->ooblen;
1783
1784         switch(ops->mode) {
1785
1786         case MTD_OOB_PLACE:
1787         case MTD_OOB_RAW:
1788                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1789                 return oob + len;
1790
1791         case MTD_OOB_AUTO: {
1792                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1793                 uint32_t boffs = 0, woffs = ops->ooboffs;
1794                 size_t bytes = 0;
1795
1796                 for(; free->length && len; free++, len -= bytes) {
1797                         /* Write request not from offset 0 ? */
1798                         if (unlikely(woffs)) {
1799                                 if (woffs >= free->length) {
1800                                         woffs -= free->length;
1801                                         continue;
1802                                 }
1803                                 boffs = free->offset + woffs;
1804                                 bytes = min_t(size_t, len,
1805                                               (free->length - woffs));
1806                                 woffs = 0;
1807                         } else {
1808                                 bytes = min_t(size_t, len, free->length);
1809                                 boffs = free->offset;
1810                         }
1811                         memcpy(chip->oob_poi + boffs, oob, bytes);
1812                         oob += bytes;
1813                 }
1814                 return oob;
1815         }
1816         default:
1817                 BUG();
1818         }
1819         return NULL;
1820 }
1821
1822 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1823
1824 /**
1825  * nand_do_write_ops - [Internal] NAND write with ECC
1826  * @mtd:        MTD device structure
1827  * @to:         offset to write to
1828  * @ops:        oob operations description structure
1829  *
1830  * NAND write with ECC
1831  */
1832 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1833                              struct mtd_oob_ops *ops)
1834 {
1835         int chipnr, realpage, page, blockmask, column;
1836         struct nand_chip *chip = mtd->priv;
1837         uint32_t writelen = ops->len;
1838         uint8_t *oob = ops->oobbuf;
1839         uint8_t *buf = ops->datbuf;
1840         int ret, subpage;
1841
1842         ops->retlen = 0;
1843         if (!writelen)
1844                 return 0;
1845
1846         /* reject writes, which are not page aligned */
1847         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1848                 printk(KERN_NOTICE "nand_write: "
1849                        "Attempt to write not page aligned data\n");
1850                 return -EINVAL;
1851         }
1852
1853         column = to & (mtd->writesize - 1);
1854         subpage = column || (writelen & (mtd->writesize - 1));
1855
1856         if (subpage && oob)
1857                 return -EINVAL;
1858
1859         chipnr = (int)(to >> chip->chip_shift);
1860         chip->select_chip(mtd, chipnr);
1861
1862         /* Check, if it is write protected */
1863         if (nand_check_wp(mtd)) {
1864                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1865                 return -EIO;
1866         }
1867
1868         realpage = (int)(to >> chip->page_shift);
1869         page = realpage & chip->pagemask;
1870         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1871
1872         /* Invalidate the page cache, when we write to the cached page */
1873         if (to <= (chip->pagebuf << chip->page_shift) &&
1874             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1875                 chip->pagebuf = -1;
1876
1877         /* If we're not given explicit OOB data, let it be 0xFF */
1878         if (likely(!oob))
1879                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1880
1881         while(1) {
1882                 int bytes = mtd->writesize;
1883                 int cached = writelen > bytes && page != blockmask;
1884                 uint8_t *wbuf = buf;
1885
1886                 /* Partial page write ? */
1887                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1888                         cached = 0;
1889                         bytes = min_t(int, bytes - column, (int) writelen);
1890                         chip->pagebuf = -1;
1891                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1892                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1893                         wbuf = chip->buffers->databuf;
1894                 }
1895
1896                 if (unlikely(oob))
1897                         oob = nand_fill_oob(chip, oob, ops);
1898
1899                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1900                                        (ops->mode == MTD_OOB_RAW));
1901                 if (ret)
1902                         break;
1903
1904                 writelen -= bytes;
1905                 if (!writelen)
1906                         break;
1907
1908                 column = 0;
1909                 buf += bytes;
1910                 realpage++;
1911
1912                 page = realpage & chip->pagemask;
1913                 /* Check, if we cross a chip boundary */
1914                 if (!page) {
1915                         chipnr++;
1916                         chip->select_chip(mtd, -1);
1917                         chip->select_chip(mtd, chipnr);
1918                 }
1919         }
1920
1921         ops->retlen = ops->len - writelen;
1922         if (unlikely(oob))
1923                 ops->oobretlen = ops->ooblen;
1924         return ret;
1925 }
1926
1927 /**
1928  * nand_write - [MTD Interface] NAND write with ECC
1929  * @mtd:        MTD device structure
1930  * @to:         offset to write to
1931  * @len:        number of bytes to write
1932  * @retlen:     pointer to variable to store the number of written bytes
1933  * @buf:        the data to write
1934  *
1935  * NAND write with ECC
1936  */
1937 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1938                           size_t *retlen, const uint8_t *buf)
1939 {
1940         struct nand_chip *chip = mtd->priv;
1941         int ret;
1942
1943         /* Do not allow reads past end of device */
1944         if ((to + len) > mtd->size)
1945                 return -EINVAL;
1946         if (!len)
1947                 return 0;
1948
1949         nand_get_device(chip, mtd, FL_WRITING);
1950
1951         chip->ops.len = len;
1952         chip->ops.datbuf = (uint8_t *)buf;
1953         chip->ops.oobbuf = NULL;
1954
1955         ret = nand_do_write_ops(mtd, to, &chip->ops);
1956
1957         *retlen = chip->ops.retlen;
1958
1959         nand_release_device(mtd);
1960
1961         return ret;
1962 }
1963
1964 /**
1965  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1966  * @mtd:        MTD device structure
1967  * @to:         offset to write to
1968  * @ops:        oob operation description structure
1969  *
1970  * NAND write out-of-band
1971  */
1972 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1973                              struct mtd_oob_ops *ops)
1974 {
1975         int chipnr, page, status, len;
1976         struct nand_chip *chip = mtd->priv;
1977
1978         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1979                   (unsigned int)to, (int)ops->ooblen);
1980
1981         if (ops->mode == MTD_OOB_AUTO)
1982                 len = chip->ecc.layout->oobavail;
1983         else
1984                 len = mtd->oobsize;
1985
1986         /* Do not allow write past end of page */
1987         if ((ops->ooboffs + ops->ooblen) > len) {
1988                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1989                           "Attempt to write past end of page\n");
1990                 return -EINVAL;
1991         }
1992
1993         if (unlikely(ops->ooboffs >= len)) {
1994                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1995                           "Attempt to start write outside oob\n");
1996                 return -EINVAL;
1997         }
1998
1999         /* Do not allow reads past end of device */
2000         if (unlikely(to >= mtd->size ||
2001                      ops->ooboffs + ops->ooblen >
2002                         ((mtd->size >> chip->page_shift) -
2003                          (to >> chip->page_shift)) * len)) {
2004                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2005                           "Attempt write beyond end of device\n");
2006                 return -EINVAL;
2007         }
2008
2009         chipnr = (int)(to >> chip->chip_shift);
2010         chip->select_chip(mtd, chipnr);
2011
2012         /* Shift to get page */
2013         page = (int)(to >> chip->page_shift);
2014
2015         /*
2016          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2017          * of my DiskOnChip 2000 test units) will clear the whole data page too
2018          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2019          * it in the doc2000 driver in August 1999.  dwmw2.
2020          */
2021         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2022
2023         /* Check, if it is write protected */
2024         if (nand_check_wp(mtd))
2025                 return -EROFS;
2026
2027         /* Invalidate the page cache, if we write to the cached page */
2028         if (page == chip->pagebuf)
2029                 chip->pagebuf = -1;
2030
2031         memset(chip->oob_poi, 0xff, mtd->oobsize);
2032         nand_fill_oob(chip, ops->oobbuf, ops);
2033         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2034         memset(chip->oob_poi, 0xff, mtd->oobsize);
2035
2036         if (status)
2037                 return status;
2038
2039         ops->oobretlen = ops->ooblen;
2040
2041         return 0;
2042 }
2043
2044 /**
2045  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2046  * @mtd:        MTD device structure
2047  * @to:         offset to write to
2048  * @ops:        oob operation description structure
2049  */
2050 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2051                           struct mtd_oob_ops *ops)
2052 {
2053         struct nand_chip *chip = mtd->priv;
2054         int ret = -ENOTSUPP;
2055
2056         ops->retlen = 0;
2057
2058         /* Do not allow writes past end of device */
2059         if (ops->datbuf && (to + ops->len) > mtd->size) {
2060                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2061                           "Attempt read beyond end of device\n");
2062                 return -EINVAL;
2063         }
2064
2065         nand_get_device(chip, mtd, FL_WRITING);
2066
2067         switch(ops->mode) {
2068         case MTD_OOB_PLACE:
2069         case MTD_OOB_AUTO:
2070         case MTD_OOB_RAW:
2071                 break;
2072
2073         default:
2074                 goto out;
2075         }
2076
2077         if (!ops->datbuf)
2078                 ret = nand_do_write_oob(mtd, to, ops);
2079         else
2080                 ret = nand_do_write_ops(mtd, to, ops);
2081
2082  out:
2083         nand_release_device(mtd);
2084         return ret;
2085 }
2086
2087 /**
2088  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2089  * @mtd:        MTD device structure
2090  * @page:       the page address of the block which will be erased
2091  *
2092  * Standard erase command for NAND chips
2093  */
2094 static void single_erase_cmd(struct mtd_info *mtd, int page)
2095 {
2096         struct nand_chip *chip = mtd->priv;
2097         /* Send commands to erase a block */
2098         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2099         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2100 }
2101
2102 /**
2103  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2104  * @mtd:        MTD device structure
2105  * @page:       the page address of the block which will be erased
2106  *
2107  * AND multi block erase command function
2108  * Erase 4 consecutive blocks
2109  */
2110 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2111 {
2112         struct nand_chip *chip = mtd->priv;
2113         /* Send commands to erase a block */
2114         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2115         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2116         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2117         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2118         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2119 }
2120
2121 /**
2122  * nand_erase - [MTD Interface] erase block(s)
2123  * @mtd:        MTD device structure
2124  * @instr:      erase instruction
2125  *
2126  * Erase one ore more blocks
2127  */
2128 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2129 {
2130         return nand_erase_nand(mtd, instr, 0);
2131 }
2132
2133 #define BBT_PAGE_MASK   0xffffff3f
2134 /**
2135  * nand_erase_nand - [Internal] erase block(s)
2136  * @mtd:        MTD device structure
2137  * @instr:      erase instruction
2138  * @allowbbt:   allow erasing the bbt area
2139  *
2140  * Erase one ore more blocks
2141  */
2142 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2143                     int allowbbt)
2144 {
2145         int page, len, status, pages_per_block, ret, chipnr;
2146         struct nand_chip *chip = mtd->priv;
2147         int rewrite_bbt[NAND_MAX_CHIPS]={0};
2148         unsigned int bbt_masked_page = 0xffffffff;
2149
2150         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2151                   (unsigned int) instr->addr, (unsigned int) instr->len);
2152
2153         /* Start address must align on block boundary */
2154         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2155                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2156                 return -EINVAL;
2157         }
2158
2159         /* Length must align on block boundary */
2160         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2161                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2162                           "nand_erase: Length not block aligned\n");
2163                 return -EINVAL;
2164         }
2165
2166         /* Do not allow erase past end of device */
2167         if ((instr->len + instr->addr) > mtd->size) {
2168                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2169                           "nand_erase: Erase past end of device\n");
2170                 return -EINVAL;
2171         }
2172
2173         instr->fail_addr = 0xffffffff;
2174
2175         /* Grab the lock and see if the device is available */
2176         nand_get_device(chip, mtd, FL_ERASING);
2177
2178         /* Shift to get first page */
2179         page = (int)(instr->addr >> chip->page_shift);
2180         chipnr = (int)(instr->addr >> chip->chip_shift);
2181
2182         /* Calculate pages in each block */
2183         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2184
2185         /* Select the NAND device */
2186         chip->select_chip(mtd, chipnr);
2187
2188         /* Check, if it is write protected */
2189         if (nand_check_wp(mtd)) {
2190                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2191                           "nand_erase: Device is write protected!!!\n");
2192                 instr->state = MTD_ERASE_FAILED;
2193                 goto erase_exit;
2194         }
2195
2196         /*
2197          * If BBT requires refresh, set the BBT page mask to see if the BBT
2198          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2199          * can not be matched. This is also done when the bbt is actually
2200          * erased to avoid recusrsive updates
2201          */
2202         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2203                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2204
2205         /* Loop through the pages */
2206         len = instr->len;
2207
2208         instr->state = MTD_ERASING;
2209
2210         while (len) {
2211                 /*
2212                  * heck if we have a bad block, we do not erase bad blocks !
2213                  */
2214                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2215                                         chip->page_shift, 0, allowbbt)) {
2216                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2217                                "bad block at page 0x%08x\n", page);
2218                         instr->state = MTD_ERASE_FAILED;
2219                         goto erase_exit;
2220                 }
2221
2222                 /*
2223                  * Invalidate the page cache, if we erase the block which
2224                  * contains the current cached page
2225                  */
2226                 if (page <= chip->pagebuf && chip->pagebuf <
2227                     (page + pages_per_block))
2228                         chip->pagebuf = -1;
2229
2230                 chip->erase_cmd(mtd, page & chip->pagemask);
2231
2232                 status = chip->waitfunc(mtd, chip);
2233
2234                 /*
2235                  * See if operation failed and additional status checks are
2236                  * available
2237                  */
2238                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2239                         status = chip->errstat(mtd, chip, FL_ERASING,
2240                                                status, page);
2241
2242                 /* See if block erase succeeded */
2243                 if (status & NAND_STATUS_FAIL) {
2244                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2245                                   "Failed erase, page 0x%08x\n", page);
2246                         instr->state = MTD_ERASE_FAILED;
2247                         instr->fail_addr = (page << chip->page_shift);
2248                         goto erase_exit;
2249                 }
2250
2251                 /*
2252                  * If BBT requires refresh, set the BBT rewrite flag to the
2253                  * page being erased
2254                  */
2255                 if (bbt_masked_page != 0xffffffff &&
2256                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2257                             rewrite_bbt[chipnr] = (page << chip->page_shift);
2258
2259                 /* Increment page address and decrement length */
2260                 len -= (1 << chip->phys_erase_shift);
2261                 page += pages_per_block;
2262
2263                 /* Check, if we cross a chip boundary */
2264                 if (len && !(page & chip->pagemask)) {
2265                         chipnr++;
2266                         chip->select_chip(mtd, -1);
2267                         chip->select_chip(mtd, chipnr);
2268
2269                         /*
2270                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2271                          * page mask to see if this BBT should be rewritten
2272                          */
2273                         if (bbt_masked_page != 0xffffffff &&
2274                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2275                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2276                                         BBT_PAGE_MASK;
2277                 }
2278         }
2279         instr->state = MTD_ERASE_DONE;
2280
2281  erase_exit:
2282
2283         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2284
2285         /* Deselect and wake up anyone waiting on the device */
2286         nand_release_device(mtd);
2287
2288         /* Do call back function */
2289         if (!ret)
2290                 mtd_erase_callback(instr);
2291
2292         /*
2293          * If BBT requires refresh and erase was successful, rewrite any
2294          * selected bad block tables
2295          */
2296         if (bbt_masked_page == 0xffffffff || ret)
2297                 return ret;
2298
2299         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2300                 if (!rewrite_bbt[chipnr])
2301                         continue;
2302                 /* update the BBT for chip */
2303                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2304                           "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2305                           chip->bbt_td->pages[chipnr]);
2306                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2307         }
2308
2309         /* Return more or less happy */
2310         return ret;
2311 }
2312
2313 /**
2314  * nand_sync - [MTD Interface] sync
2315  * @mtd:        MTD device structure
2316  *
2317  * Sync is actually a wait for chip ready function
2318  */
2319 static void nand_sync(struct mtd_info *mtd)
2320 {
2321         struct nand_chip *chip = mtd->priv;
2322
2323         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2324
2325         /* Grab the lock and see if the device is available */
2326         nand_get_device(chip, mtd, FL_SYNCING);
2327         /* Release it and go back */
2328         nand_release_device(mtd);
2329 }
2330
2331 /**
2332  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2333  * @mtd:        MTD device structure
2334  * @offs:       offset relative to mtd start
2335  */
2336 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2337 {
2338         /* Check for invalid offset */
2339         if (offs > mtd->size)
2340                 return -EINVAL;
2341
2342         return nand_block_checkbad(mtd, offs, 1, 0);
2343 }
2344
2345 /**
2346  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2347  * @mtd:        MTD device structure
2348  * @ofs:        offset relative to mtd start
2349  */
2350 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2351 {
2352         struct nand_chip *chip = mtd->priv;
2353         int ret;
2354
2355         if ((ret = nand_block_isbad(mtd, ofs))) {
2356                 /* If it was bad already, return success and do nothing. */
2357                 if (ret > 0)
2358                         return 0;
2359                 return ret;
2360         }
2361
2362         return chip->block_markbad(mtd, ofs);
2363 }
2364
2365 /**
2366  * nand_suspend - [MTD Interface] Suspend the NAND flash
2367  * @mtd:        MTD device structure
2368  */
2369 static int nand_suspend(struct mtd_info *mtd)
2370 {
2371         struct nand_chip *chip = mtd->priv;
2372
2373         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2374 }
2375
2376 /**
2377  * nand_resume - [MTD Interface] Resume the NAND flash
2378  * @mtd:        MTD device structure
2379  */
2380 static void nand_resume(struct mtd_info *mtd)
2381 {
2382         struct nand_chip *chip = mtd->priv;
2383
2384         if (chip->state == FL_PM_SUSPENDED)
2385                 nand_release_device(mtd);
2386         else
2387                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2388                        "in suspended state\n");
2389 }
2390
2391 /*
2392  * Set default functions
2393  */
2394 static void nand_set_defaults(struct nand_chip *chip, int busw)
2395 {
2396         /* check for proper chip_delay setup, set 20us if not */
2397         if (!chip->chip_delay)
2398                 chip->chip_delay = 20;
2399
2400         /* check, if a user supplied command function given */
2401         if (chip->cmdfunc == NULL)
2402                 chip->cmdfunc = nand_command;
2403
2404         /* check, if a user supplied wait function given */
2405         if (chip->waitfunc == NULL)
2406                 chip->waitfunc = nand_wait;
2407
2408         if (!chip->select_chip)
2409                 chip->select_chip = nand_select_chip;
2410         if (!chip->read_byte)
2411                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2412         if (!chip->read_word)
2413                 chip->read_word = nand_read_word;
2414         if (!chip->block_bad)
2415                 chip->block_bad = nand_block_bad;
2416         if (!chip->block_markbad)
2417                 chip->block_markbad = nand_default_block_markbad;
2418         if (!chip->write_buf)
2419                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2420         if (!chip->read_buf)
2421                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2422         if (!chip->verify_buf)
2423                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2424         if (!chip->scan_bbt)
2425                 chip->scan_bbt = nand_default_bbt;
2426
2427         if (!chip->controller) {
2428                 chip->controller = &chip->hwcontrol;
2429
2430                 /* XXX U-BOOT XXX */
2431 #if 0
2432                 spin_lock_init(&chip->controller->lock);
2433                 init_waitqueue_head(&chip->controller->wq);
2434 #endif
2435         }
2436
2437 }
2438
2439 /*
2440  * Get the flash and manufacturer id and lookup if the type is supported
2441  */
2442 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2443                                                   struct nand_chip *chip,
2444                                                   int busw, int *maf_id)
2445 {
2446         struct nand_flash_dev *type = NULL;
2447         int i, dev_id, maf_idx;
2448         int tmp_id, tmp_manf;
2449
2450         /* Select the device */
2451         chip->select_chip(mtd, 0);
2452
2453         /*
2454          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2455          * after power-up
2456          */
2457         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2458
2459         /* Send the command for reading device ID */
2460         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2461
2462         /* Read manufacturer and device IDs */
2463         *maf_id = chip->read_byte(mtd);
2464         dev_id = chip->read_byte(mtd);
2465
2466         /* Try again to make sure, as some systems the bus-hold or other
2467          * interface concerns can cause random data which looks like a
2468          * possibly credible NAND flash to appear. If the two results do
2469          * not match, ignore the device completely.
2470          */
2471
2472         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2473
2474         /* Read manufacturer and device IDs */
2475
2476         tmp_manf = chip->read_byte(mtd);
2477         tmp_id = chip->read_byte(mtd);
2478
2479         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2480                 printk(KERN_INFO "%s: second ID read did not match "
2481                        "%02x,%02x against %02x,%02x\n", __func__,
2482                        *maf_id, dev_id, tmp_manf, tmp_id);
2483                 return ERR_PTR(-ENODEV);
2484         }
2485
2486         /* Lookup the flash id */
2487         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2488                 if (dev_id == nand_flash_ids[i].id) {
2489                         type =  &nand_flash_ids[i];
2490                         break;
2491                 }
2492         }
2493
2494         if (!type)
2495                 return ERR_PTR(-ENODEV);
2496
2497         if (!mtd->name)
2498                 mtd->name = type->name;
2499
2500         chip->chipsize = type->chipsize << 20;
2501
2502         /* Newer devices have all the information in additional id bytes */
2503         if (!type->pagesize) {
2504                 int extid;
2505                 /* The 3rd id byte holds MLC / multichip data */
2506                 chip->cellinfo = chip->read_byte(mtd);
2507                 /* The 4th id byte is the important one */
2508                 extid = chip->read_byte(mtd);
2509                 /* Calc pagesize */
2510                 mtd->writesize = 1024 << (extid & 0x3);
2511                 extid >>= 2;
2512                 /* Calc oobsize */
2513                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2514                 extid >>= 2;
2515                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2516                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2517                 extid >>= 2;
2518                 /* Get buswidth information */
2519                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2520
2521         } else {
2522                 /*
2523                  * Old devices have chip data hardcoded in the device id table
2524                  */
2525                 mtd->erasesize = type->erasesize;
2526                 mtd->writesize = type->pagesize;
2527                 mtd->oobsize = mtd->writesize / 32;
2528                 busw = type->options & NAND_BUSWIDTH_16;
2529         }
2530
2531         /* Try to identify manufacturer */
2532         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2533                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2534                         break;
2535         }
2536
2537         /*
2538          * Check, if buswidth is correct. Hardware drivers should set
2539          * chip correct !
2540          */
2541         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2542                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2543                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2544                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2545                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2546                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2547                        busw ? 16 : 8);
2548                 return ERR_PTR(-EINVAL);
2549         }
2550
2551         /* Calculate the address shift from the page size */
2552         chip->page_shift = ffs(mtd->writesize) - 1;
2553         /* Convert chipsize to number of pages per chip -1. */
2554         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2555
2556         chip->bbt_erase_shift = chip->phys_erase_shift =
2557                 ffs(mtd->erasesize) - 1;
2558         chip->chip_shift = ffs(chip->chipsize) - 1;
2559
2560         /* Set the bad block position */
2561         chip->badblockpos = mtd->writesize > 512 ?
2562                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2563
2564         /* Get chip options, preserve non chip based options */
2565         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2566         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2567
2568         /*
2569          * Set chip as a default. Board drivers can override it, if necessary
2570          */
2571         chip->options |= NAND_NO_AUTOINCR;
2572
2573         /* Check if chip is a not a samsung device. Do not clear the
2574          * options for chips which are not having an extended id.
2575          */
2576         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2577                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2578
2579         /* Check for AND chips with 4 page planes */
2580         if (chip->options & NAND_4PAGE_ARRAY)
2581                 chip->erase_cmd = multi_erase_cmd;
2582         else
2583                 chip->erase_cmd = single_erase_cmd;
2584
2585         /* Do not replace user supplied command function ! */
2586         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2587                 chip->cmdfunc = nand_command_lp;
2588
2589         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2590                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2591                   nand_manuf_ids[maf_idx].name, type->name);
2592
2593         return type;
2594 }
2595
2596 /**
2597  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2598  * @mtd:             MTD device structure
2599  * @maxchips:        Number of chips to scan for
2600  *
2601  * This is the first phase of the normal nand_scan() function. It
2602  * reads the flash ID and sets up MTD fields accordingly.
2603  *
2604  * The mtd->owner field must be set to the module of the caller.
2605  */
2606 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2607 {
2608         int i, busw, nand_maf_id;
2609         struct nand_chip *chip = mtd->priv;
2610         struct nand_flash_dev *type;
2611
2612         /* Get buswidth to select the correct functions */
2613         busw = chip->options & NAND_BUSWIDTH_16;
2614         /* Set the default functions */
2615         nand_set_defaults(chip, busw);
2616
2617         /* Read the flash type */
2618         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2619
2620         if (IS_ERR(type)) {
2621                 printk(KERN_WARNING "No NAND device found!!!\n");
2622                 chip->select_chip(mtd, -1);
2623                 return PTR_ERR(type);
2624         }
2625
2626         /* Check for a chip array */
2627         for (i = 1; i < maxchips; i++) {
2628                 chip->select_chip(mtd, i);
2629                 /* See comment in nand_get_flash_type for reset */
2630                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2631                 /* Send the command for reading device ID */
2632                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2633                 /* Read manufacturer and device IDs */
2634                 if (nand_maf_id != chip->read_byte(mtd) ||
2635                     type->id != chip->read_byte(mtd))
2636                         break;
2637         }
2638         if (i > 1)
2639                 printk(KERN_INFO "%d NAND chips detected\n", i);
2640
2641         /* Store the number of chips and calc total size for mtd */
2642         chip->numchips = i;
2643         mtd->size = i * chip->chipsize;
2644
2645         return 0;
2646 }
2647
2648
2649 /**
2650  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2651  * @mtd:            MTD device structure
2652  * @maxchips:       Number of chips to scan for
2653  *
2654  * This is the second phase of the normal nand_scan() function. It
2655  * fills out all the uninitialized function pointers with the defaults
2656  * and scans for a bad block table if appropriate.
2657  */
2658 int nand_scan_tail(struct mtd_info *mtd)
2659 {
2660         int i;
2661         struct nand_chip *chip = mtd->priv;
2662
2663         if (!(chip->options & NAND_OWN_BUFFERS))
2664                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2665         if (!chip->buffers)
2666                 return -ENOMEM;
2667
2668         /* Set the internal oob buffer location, just after the page data */
2669         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2670
2671         /*
2672          * If no default placement scheme is given, select an appropriate one
2673          */
2674         if (!chip->ecc.layout) {
2675                 switch (mtd->oobsize) {
2676                 case 8:
2677                         chip->ecc.layout = &nand_oob_8;
2678                         break;
2679                 case 16:
2680                         chip->ecc.layout = &nand_oob_16;
2681                         break;
2682                 case 64:
2683                         chip->ecc.layout = &nand_oob_64;
2684                         break;
2685                 case 128:
2686                         chip->ecc.layout = &nand_oob_128;
2687                         break;
2688                 default:
2689                         printk(KERN_WARNING "No oob scheme defined for "
2690                                "oobsize %d\n", mtd->oobsize);
2691 /*                      BUG(); */
2692                 }
2693         }
2694
2695         if (!chip->write_page)
2696                 chip->write_page = nand_write_page;
2697
2698         /*
2699          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2700          * selected and we have 256 byte pagesize fallback to software ECC
2701          */
2702         if (!chip->ecc.read_page_raw)
2703                 chip->ecc.read_page_raw = nand_read_page_raw;
2704         if (!chip->ecc.write_page_raw)
2705                 chip->ecc.write_page_raw = nand_write_page_raw;
2706
2707         switch (chip->ecc.mode) {
2708         case NAND_ECC_HW:
2709                 /* Use standard hwecc read page function ? */
2710                 if (!chip->ecc.read_page)
2711                         chip->ecc.read_page = nand_read_page_hwecc;
2712                 if (!chip->ecc.write_page)
2713                         chip->ecc.write_page = nand_write_page_hwecc;
2714                 if (!chip->ecc.read_oob)
2715                         chip->ecc.read_oob = nand_read_oob_std;
2716                 if (!chip->ecc.write_oob)
2717                         chip->ecc.write_oob = nand_write_oob_std;
2718
2719         case NAND_ECC_HW_SYNDROME:
2720                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2721                      !chip->ecc.hwctl) &&
2722                     (!chip->ecc.read_page ||
2723                      chip->ecc.read_page == nand_read_page_hwecc ||
2724                      !chip->ecc.write_page ||
2725                      chip->ecc.write_page == nand_write_page_hwecc)) {
2726                         printk(KERN_WARNING "No ECC functions supplied, "
2727                                "Hardware ECC not possible\n");
2728                         BUG();
2729                 }
2730                 /* Use standard syndrome read/write page function ? */
2731                 if (!chip->ecc.read_page)
2732                         chip->ecc.read_page = nand_read_page_syndrome;
2733                 if (!chip->ecc.write_page)
2734                         chip->ecc.write_page = nand_write_page_syndrome;
2735                 if (!chip->ecc.read_oob)
2736                         chip->ecc.read_oob = nand_read_oob_syndrome;
2737                 if (!chip->ecc.write_oob)
2738                         chip->ecc.write_oob = nand_write_oob_syndrome;
2739
2740                 if (mtd->writesize >= chip->ecc.size)
2741                         break;
2742                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2743                        "%d byte page size, fallback to SW ECC\n",
2744                        chip->ecc.size, mtd->writesize);
2745                 chip->ecc.mode = NAND_ECC_SOFT;
2746
2747         case NAND_ECC_SOFT:
2748                 chip->ecc.calculate = nand_calculate_ecc;
2749                 chip->ecc.correct = nand_correct_data;
2750                 chip->ecc.read_page = nand_read_page_swecc;
2751                 chip->ecc.read_subpage = nand_read_subpage;
2752                 chip->ecc.write_page = nand_write_page_swecc;
2753                 chip->ecc.read_oob = nand_read_oob_std;
2754                 chip->ecc.write_oob = nand_write_oob_std;
2755                 chip->ecc.size = 256;
2756                 chip->ecc.bytes = 3;
2757                 break;
2758
2759         case NAND_ECC_NONE:
2760                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2761                        "This is not recommended !!\n");
2762                 chip->ecc.read_page = nand_read_page_raw;
2763                 chip->ecc.write_page = nand_write_page_raw;
2764                 chip->ecc.read_oob = nand_read_oob_std;
2765                 chip->ecc.write_oob = nand_write_oob_std;
2766                 chip->ecc.size = mtd->writesize;
2767                 chip->ecc.bytes = 0;
2768                 break;
2769
2770         default:
2771                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2772                        chip->ecc.mode);
2773                 BUG();
2774         }
2775
2776         /*
2777          * The number of bytes available for a client to place data into
2778          * the out of band area
2779          */
2780         chip->ecc.layout->oobavail = 0;
2781         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2782                 chip->ecc.layout->oobavail +=
2783                         chip->ecc.layout->oobfree[i].length;
2784         mtd->oobavail = chip->ecc.layout->oobavail;
2785
2786         /*
2787          * Set the number of read / write steps for one page depending on ECC
2788          * mode
2789          */
2790         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2791         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2792                 printk(KERN_WARNING "Invalid ecc parameters\n");
2793                 BUG();
2794         }
2795         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2796
2797         /*
2798          * Allow subpage writes up to ecc.steps. Not possible for MLC
2799          * FLASH.
2800          */
2801         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2802             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2803                 switch(chip->ecc.steps) {
2804                 case 2:
2805                         mtd->subpage_sft = 1;
2806                         break;
2807                 case 4:
2808                 case 8:
2809                         mtd->subpage_sft = 2;
2810                         break;
2811                 }
2812         }
2813         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2814
2815         /* Initialize state */
2816         chip->state = FL_READY;
2817
2818         /* De-select the device */
2819         chip->select_chip(mtd, -1);
2820
2821         /* Invalidate the pagebuffer reference */
2822         chip->pagebuf = -1;
2823
2824         /* Fill in remaining MTD driver data */
2825         mtd->type = MTD_NANDFLASH;
2826         mtd->flags = MTD_CAP_NANDFLASH;
2827         mtd->erase = nand_erase;
2828         mtd->point = NULL;
2829         mtd->unpoint = NULL;
2830         mtd->read = nand_read;
2831         mtd->write = nand_write;
2832         mtd->read_oob = nand_read_oob;
2833         mtd->write_oob = nand_write_oob;
2834         mtd->sync = nand_sync;
2835         mtd->lock = NULL;
2836         mtd->unlock = NULL;
2837         mtd->suspend = nand_suspend;
2838         mtd->resume = nand_resume;
2839         mtd->block_isbad = nand_block_isbad;
2840         mtd->block_markbad = nand_block_markbad;
2841
2842         /* propagate ecc.layout to mtd_info */
2843         mtd->ecclayout = chip->ecc.layout;
2844
2845         /* Check, if we should skip the bad block table scan */
2846         if (chip->options & NAND_SKIP_BBTSCAN)
2847                 chip->options |= NAND_BBT_SCANNED;
2848
2849         return 0;
2850 }
2851
2852 /* module_text_address() isn't exported, and it's mostly a pointless
2853    test if this is a module _anyway_ -- they'd have to try _really_ hard
2854    to call us from in-kernel code if the core NAND support is modular. */
2855 #ifdef MODULE
2856 #define caller_is_module() (1)
2857 #else
2858 #define caller_is_module() \
2859         module_text_address((unsigned long)__builtin_return_address(0))
2860 #endif
2861
2862 /**
2863  * nand_scan - [NAND Interface] Scan for the NAND device
2864  * @mtd:        MTD device structure
2865  * @maxchips:   Number of chips to scan for
2866  *
2867  * This fills out all the uninitialized function pointers
2868  * with the defaults.
2869  * The flash ID is read and the mtd/chip structures are
2870  * filled with the appropriate values.
2871  * The mtd->owner field must be set to the module of the caller
2872  *
2873  */
2874 int nand_scan(struct mtd_info *mtd, int maxchips)
2875 {
2876         int ret;
2877
2878         /* Many callers got this wrong, so check for it for a while... */
2879         /* XXX U-BOOT XXX */
2880 #if 0
2881         if (!mtd->owner && caller_is_module()) {
2882                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2883                 BUG();
2884         }
2885 #endif
2886
2887         ret = nand_scan_ident(mtd, maxchips);
2888         if (!ret)
2889                 ret = nand_scan_tail(mtd);
2890         return ret;
2891 }
2892
2893 /**
2894  * nand_release - [NAND Interface] Free resources held by the NAND device
2895  * @mtd:        MTD device structure
2896 */
2897 void nand_release(struct mtd_info *mtd)
2898 {
2899         struct nand_chip *chip = mtd->priv;
2900
2901 #ifdef CONFIG_MTD_PARTITIONS
2902         /* Deregister partitions */
2903         del_mtd_partitions(mtd);
2904 #endif
2905         /* Deregister the device */
2906         /* XXX U-BOOT XXX */
2907 #if 0
2908         del_mtd_device(mtd);
2909 #endif
2910
2911         /* Free bad block table memory */
2912         kfree(chip->bbt);
2913         if (!(chip->options & NAND_OWN_BUFFERS))
2914                 kfree(chip->buffers);
2915 }
2916
2917 /* XXX U-BOOT XXX */
2918 #if 0
2919 EXPORT_SYMBOL_GPL(nand_scan);
2920 EXPORT_SYMBOL_GPL(nand_scan_ident);
2921 EXPORT_SYMBOL_GPL(nand_scan_tail);
2922 EXPORT_SYMBOL_GPL(nand_release);
2923
2924 static int __init nand_base_init(void)
2925 {
2926         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2927         return 0;
2928 }
2929
2930 static void __exit nand_base_exit(void)
2931 {
2932         led_trigger_unregister_simple(nand_led_trigger);
2933 }
2934
2935 module_init(nand_base_init);
2936 module_exit(nand_base_exit);
2937
2938 MODULE_LICENSE("GPL");
2939 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2940 MODULE_DESCRIPTION("Generic NAND flash driver code");
2941 #endif