3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/nmi.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/nand_bch.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
48 #include <linux/mtd/partitions.h>
51 static int nand_get_device(struct mtd_info *mtd, int new_state);
53 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
54 struct mtd_oob_ops *ops);
56 /* Define default oob placement schemes for large and small page devices */
57 static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
58 struct mtd_oob_region *oobregion)
60 struct nand_chip *chip = mtd_to_nand(mtd);
61 struct nand_ecc_ctrl *ecc = &chip->ecc;
67 oobregion->offset = 0;
68 oobregion->length = 4;
70 oobregion->offset = 6;
71 oobregion->length = ecc->total - 4;
77 static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
78 struct mtd_oob_region *oobregion)
83 if (mtd->oobsize == 16) {
87 oobregion->length = 8;
88 oobregion->offset = 8;
90 oobregion->length = 2;
92 oobregion->offset = 3;
94 oobregion->offset = 6;
100 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
101 .ecc = nand_ooblayout_ecc_sp,
102 .free = nand_ooblayout_free_sp,
104 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
106 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
107 struct mtd_oob_region *oobregion)
109 struct nand_chip *chip = mtd_to_nand(mtd);
110 struct nand_ecc_ctrl *ecc = &chip->ecc;
115 oobregion->length = ecc->total;
116 oobregion->offset = mtd->oobsize - oobregion->length;
121 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
122 struct mtd_oob_region *oobregion)
124 struct nand_chip *chip = mtd_to_nand(mtd);
125 struct nand_ecc_ctrl *ecc = &chip->ecc;
130 oobregion->length = mtd->oobsize - ecc->total - 2;
131 oobregion->offset = 2;
136 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
137 .ecc = nand_ooblayout_ecc_lp,
138 .free = nand_ooblayout_free_lp,
140 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
143 * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
144 * are placed at a fixed offset.
146 static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
147 struct mtd_oob_region *oobregion)
149 struct nand_chip *chip = mtd_to_nand(mtd);
150 struct nand_ecc_ctrl *ecc = &chip->ecc;
155 switch (mtd->oobsize) {
157 oobregion->offset = 40;
160 oobregion->offset = 80;
166 oobregion->length = ecc->total;
167 if (oobregion->offset + oobregion->length > mtd->oobsize)
173 static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
174 struct mtd_oob_region *oobregion)
176 struct nand_chip *chip = mtd_to_nand(mtd);
177 struct nand_ecc_ctrl *ecc = &chip->ecc;
180 if (section < 0 || section > 1)
183 switch (mtd->oobsize) {
195 oobregion->offset = 2;
196 oobregion->length = ecc_offset - 2;
198 oobregion->offset = ecc_offset + ecc->total;
199 oobregion->length = mtd->oobsize - oobregion->offset;
205 const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
206 .ecc = nand_ooblayout_ecc_lp_hamming,
207 .free = nand_ooblayout_free_lp_hamming,
210 static int check_offs_len(struct mtd_info *mtd,
211 loff_t ofs, uint64_t len)
213 struct nand_chip *chip = mtd_to_nand(mtd);
216 /* Start address must align on block boundary */
217 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
218 pr_debug("%s: unaligned address\n", __func__);
222 /* Length must align on block boundary */
223 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
224 pr_debug("%s: length not block aligned\n", __func__);
232 * nand_release_device - [GENERIC] release chip
233 * @mtd: MTD device structure
235 * Release chip lock and wake up anyone waiting on the device.
237 static void nand_release_device(struct mtd_info *mtd)
239 struct nand_chip *chip = mtd_to_nand(mtd);
241 /* Release the controller and the chip */
242 spin_lock(&chip->controller->lock);
243 chip->controller->active = NULL;
244 chip->state = FL_READY;
245 wake_up(&chip->controller->wq);
246 spin_unlock(&chip->controller->lock);
250 * nand_read_byte - [DEFAULT] read one byte from the chip
251 * @mtd: MTD device structure
253 * Default read function for 8bit buswidth
255 static uint8_t nand_read_byte(struct mtd_info *mtd)
257 struct nand_chip *chip = mtd_to_nand(mtd);
258 return readb(chip->IO_ADDR_R);
262 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
263 * @mtd: MTD device structure
265 * Default read function for 16bit buswidth with endianness conversion.
268 static uint8_t nand_read_byte16(struct mtd_info *mtd)
270 struct nand_chip *chip = mtd_to_nand(mtd);
271 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
275 * nand_read_word - [DEFAULT] read one word from the chip
276 * @mtd: MTD device structure
278 * Default read function for 16bit buswidth without endianness conversion.
280 static u16 nand_read_word(struct mtd_info *mtd)
282 struct nand_chip *chip = mtd_to_nand(mtd);
283 return readw(chip->IO_ADDR_R);
287 * nand_select_chip - [DEFAULT] control CE line
288 * @mtd: MTD device structure
289 * @chipnr: chipnumber to select, -1 for deselect
291 * Default select function for 1 chip devices.
293 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
295 struct nand_chip *chip = mtd_to_nand(mtd);
299 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
310 * nand_write_byte - [DEFAULT] write single byte to chip
311 * @mtd: MTD device structure
312 * @byte: value to write
314 * Default function to write a byte to I/O[7:0]
316 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
318 struct nand_chip *chip = mtd_to_nand(mtd);
320 chip->write_buf(mtd, &byte, 1);
324 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
325 * @mtd: MTD device structure
326 * @byte: value to write
328 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
330 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
332 struct nand_chip *chip = mtd_to_nand(mtd);
333 uint16_t word = byte;
336 * It's not entirely clear what should happen to I/O[15:8] when writing
337 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
339 * When the host supports a 16-bit bus width, only data is
340 * transferred at the 16-bit width. All address and command line
341 * transfers shall use only the lower 8-bits of the data bus. During
342 * command transfers, the host may place any value on the upper
343 * 8-bits of the data bus. During address transfers, the host shall
344 * set the upper 8-bits of the data bus to 00h.
346 * One user of the write_byte callback is nand_onfi_set_features. The
347 * four parameters are specified to be written to I/O[7:0], but this is
348 * neither an address nor a command transfer. Let's assume a 0 on the
349 * upper I/O lines is OK.
351 chip->write_buf(mtd, (uint8_t *)&word, 2);
355 * nand_write_buf - [DEFAULT] write buffer to chip
356 * @mtd: MTD device structure
358 * @len: number of bytes to write
360 * Default write function for 8bit buswidth.
362 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
364 struct nand_chip *chip = mtd_to_nand(mtd);
366 iowrite8_rep(chip->IO_ADDR_W, buf, len);
370 * nand_read_buf - [DEFAULT] read chip data into buffer
371 * @mtd: MTD device structure
372 * @buf: buffer to store date
373 * @len: number of bytes to read
375 * Default read function for 8bit buswidth.
377 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
379 struct nand_chip *chip = mtd_to_nand(mtd);
381 ioread8_rep(chip->IO_ADDR_R, buf, len);
385 * nand_write_buf16 - [DEFAULT] write buffer to chip
386 * @mtd: MTD device structure
388 * @len: number of bytes to write
390 * Default write function for 16bit buswidth.
392 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
394 struct nand_chip *chip = mtd_to_nand(mtd);
395 u16 *p = (u16 *) buf;
397 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
401 * nand_read_buf16 - [DEFAULT] read chip data into buffer
402 * @mtd: MTD device structure
403 * @buf: buffer to store date
404 * @len: number of bytes to read
406 * Default read function for 16bit buswidth.
408 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
410 struct nand_chip *chip = mtd_to_nand(mtd);
411 u16 *p = (u16 *) buf;
413 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
417 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
418 * @mtd: MTD device structure
419 * @ofs: offset from device start
421 * Check, if the block is bad.
423 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
425 int page, page_end, res;
426 struct nand_chip *chip = mtd_to_nand(mtd);
429 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
430 ofs += mtd->erasesize - mtd->writesize;
432 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
433 page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1);
435 for (; page < page_end; page++) {
436 res = chip->ecc.read_oob(mtd, chip, page);
440 bad = chip->oob_poi[chip->badblockpos];
442 if (likely(chip->badblockbits == 8))
445 res = hweight8(bad) < chip->badblockbits;
454 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
455 * @mtd: MTD device structure
456 * @ofs: offset from device start
458 * This is the default implementation, which can be overridden by a hardware
459 * specific driver. It provides the details for writing a bad block marker to a
462 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
464 struct nand_chip *chip = mtd_to_nand(mtd);
465 struct mtd_oob_ops ops;
466 uint8_t buf[2] = { 0, 0 };
467 int ret = 0, res, i = 0;
469 memset(&ops, 0, sizeof(ops));
471 ops.ooboffs = chip->badblockpos;
472 if (chip->options & NAND_BUSWIDTH_16) {
473 ops.ooboffs &= ~0x01;
474 ops.len = ops.ooblen = 2;
476 ops.len = ops.ooblen = 1;
478 ops.mode = MTD_OPS_PLACE_OOB;
480 /* Write to first/last page(s) if necessary */
481 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
482 ofs += mtd->erasesize - mtd->writesize;
484 res = nand_do_write_oob(mtd, ofs, &ops);
489 ofs += mtd->writesize;
490 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
496 * nand_block_markbad_lowlevel - mark a block bad
497 * @mtd: MTD device structure
498 * @ofs: offset from device start
500 * This function performs the generic NAND bad block marking steps (i.e., bad
501 * block table(s) and/or marker(s)). We only allow the hardware driver to
502 * specify how to write bad block markers to OOB (chip->block_markbad).
504 * We try operations in the following order:
505 * (1) erase the affected block, to allow OOB marker to be written cleanly
506 * (2) write bad block marker to OOB area of affected block (unless flag
507 * NAND_BBT_NO_OOB_BBM is present)
509 * Note that we retain the first error encountered in (2) or (3), finish the
510 * procedures, and dump the error in the end.
512 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
514 struct nand_chip *chip = mtd_to_nand(mtd);
517 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
518 struct erase_info einfo;
520 /* Attempt erase before marking OOB */
521 memset(&einfo, 0, sizeof(einfo));
524 einfo.len = 1ULL << chip->phys_erase_shift;
525 nand_erase_nand(mtd, &einfo, 0);
527 /* Write bad block marker to OOB */
528 nand_get_device(mtd, FL_WRITING);
529 ret = chip->block_markbad(mtd, ofs);
530 nand_release_device(mtd);
533 /* Mark block bad in BBT */
535 res = nand_markbad_bbt(mtd, ofs);
541 mtd->ecc_stats.badblocks++;
547 * nand_check_wp - [GENERIC] check if the chip is write protected
548 * @mtd: MTD device structure
550 * Check, if the device is write protected. The function expects, that the
551 * device is already selected.
553 static int nand_check_wp(struct mtd_info *mtd)
555 struct nand_chip *chip = mtd_to_nand(mtd);
557 /* Broken xD cards report WP despite being writable */
558 if (chip->options & NAND_BROKEN_XD)
561 /* Check the WP bit */
562 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
563 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
567 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
568 * @mtd: MTD device structure
569 * @ofs: offset from device start
571 * Check if the block is marked as reserved.
573 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
575 struct nand_chip *chip = mtd_to_nand(mtd);
579 /* Return info from the table */
580 return nand_isreserved_bbt(mtd, ofs);
584 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
585 * @mtd: MTD device structure
586 * @ofs: offset from device start
587 * @allowbbt: 1, if its allowed to access the bbt area
589 * Check, if the block is bad. Either by reading the bad block table or
590 * calling of the scan function.
592 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
594 struct nand_chip *chip = mtd_to_nand(mtd);
597 return chip->block_bad(mtd, ofs);
599 /* Return info from the table */
600 return nand_isbad_bbt(mtd, ofs, allowbbt);
604 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
605 * @mtd: MTD device structure
608 * Helper function for nand_wait_ready used when needing to wait in interrupt
611 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
613 struct nand_chip *chip = mtd_to_nand(mtd);
616 /* Wait for the device to get ready */
617 for (i = 0; i < timeo; i++) {
618 if (chip->dev_ready(mtd))
620 touch_softlockup_watchdog();
626 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
627 * @mtd: MTD device structure
629 * Wait for the ready pin after a command, and warn if a timeout occurs.
631 void nand_wait_ready(struct mtd_info *mtd)
633 struct nand_chip *chip = mtd_to_nand(mtd);
634 unsigned long timeo = 400;
636 if (in_interrupt() || oops_in_progress)
637 return panic_nand_wait_ready(mtd, timeo);
639 /* Wait until command is processed or timeout occurs */
640 timeo = jiffies + msecs_to_jiffies(timeo);
642 if (chip->dev_ready(mtd))
645 } while (time_before(jiffies, timeo));
647 if (!chip->dev_ready(mtd))
648 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
650 EXPORT_SYMBOL_GPL(nand_wait_ready);
653 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
654 * @mtd: MTD device structure
655 * @timeo: Timeout in ms
657 * Wait for status ready (i.e. command done) or timeout.
659 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
661 register struct nand_chip *chip = mtd_to_nand(mtd);
663 timeo = jiffies + msecs_to_jiffies(timeo);
665 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
667 touch_softlockup_watchdog();
668 } while (time_before(jiffies, timeo));
672 * nand_command - [DEFAULT] Send command to NAND device
673 * @mtd: MTD device structure
674 * @command: the command to be sent
675 * @column: the column address for this command, -1 if none
676 * @page_addr: the page address for this command, -1 if none
678 * Send command to NAND device. This function is used for small page devices
679 * (512 Bytes per page).
681 static void nand_command(struct mtd_info *mtd, unsigned int command,
682 int column, int page_addr)
684 register struct nand_chip *chip = mtd_to_nand(mtd);
685 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
687 /* Write out the command to the device */
688 if (command == NAND_CMD_SEQIN) {
691 if (column >= mtd->writesize) {
693 column -= mtd->writesize;
694 readcmd = NAND_CMD_READOOB;
695 } else if (column < 256) {
696 /* First 256 bytes --> READ0 */
697 readcmd = NAND_CMD_READ0;
700 readcmd = NAND_CMD_READ1;
702 chip->cmd_ctrl(mtd, readcmd, ctrl);
703 ctrl &= ~NAND_CTRL_CHANGE;
705 chip->cmd_ctrl(mtd, command, ctrl);
707 /* Address cycle, when necessary */
708 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
709 /* Serially input address */
711 /* Adjust columns for 16 bit buswidth */
712 if (chip->options & NAND_BUSWIDTH_16 &&
713 !nand_opcode_8bits(command))
715 chip->cmd_ctrl(mtd, column, ctrl);
716 ctrl &= ~NAND_CTRL_CHANGE;
718 if (page_addr != -1) {
719 chip->cmd_ctrl(mtd, page_addr, ctrl);
720 ctrl &= ~NAND_CTRL_CHANGE;
721 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
722 /* One more address cycle for devices > 32MiB */
723 if (chip->chipsize > (32 << 20))
724 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
726 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
729 * Program and erase have their own busy handlers status and sequential
734 case NAND_CMD_PAGEPROG:
735 case NAND_CMD_ERASE1:
736 case NAND_CMD_ERASE2:
738 case NAND_CMD_STATUS:
739 case NAND_CMD_READID:
740 case NAND_CMD_SET_FEATURES:
746 udelay(chip->chip_delay);
747 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
748 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
750 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
751 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
752 nand_wait_status_ready(mtd, 250);
755 /* This applies to read commands */
758 * If we don't have access to the busy pin, we apply the given
761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
767 * Apply this short delay always to ensure that we do wait tWB in
768 * any case on any machine.
772 nand_wait_ready(mtd);
775 static void nand_ccs_delay(struct nand_chip *chip)
778 * The controller already takes care of waiting for tCCS when the RNDIN
779 * or RNDOUT command is sent, return directly.
781 if (!(chip->options & NAND_WAIT_TCCS))
785 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
786 * (which should be safe for all NANDs).
788 if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min)
789 ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000);
795 * nand_command_lp - [DEFAULT] Send command to NAND large page device
796 * @mtd: MTD device structure
797 * @command: the command to be sent
798 * @column: the column address for this command, -1 if none
799 * @page_addr: the page address for this command, -1 if none
801 * Send command to NAND device. This is the version for the new large page
802 * devices. We don't have the separate regions as we have in the small page
803 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
805 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
806 int column, int page_addr)
808 register struct nand_chip *chip = mtd_to_nand(mtd);
810 /* Emulate NAND_CMD_READOOB */
811 if (command == NAND_CMD_READOOB) {
812 column += mtd->writesize;
813 command = NAND_CMD_READ0;
816 /* Command latch cycle */
817 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
819 if (column != -1 || page_addr != -1) {
820 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
822 /* Serially input address */
824 /* Adjust columns for 16 bit buswidth */
825 if (chip->options & NAND_BUSWIDTH_16 &&
826 !nand_opcode_8bits(command))
828 chip->cmd_ctrl(mtd, column, ctrl);
829 ctrl &= ~NAND_CTRL_CHANGE;
831 /* Only output a single addr cycle for 8bits opcodes. */
832 if (!nand_opcode_8bits(command))
833 chip->cmd_ctrl(mtd, column >> 8, ctrl);
835 if (page_addr != -1) {
836 chip->cmd_ctrl(mtd, page_addr, ctrl);
837 chip->cmd_ctrl(mtd, page_addr >> 8,
838 NAND_NCE | NAND_ALE);
839 /* One more address cycle for devices > 128MiB */
840 if (chip->chipsize > (128 << 20))
841 chip->cmd_ctrl(mtd, page_addr >> 16,
842 NAND_NCE | NAND_ALE);
845 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
848 * Program and erase have their own busy handlers status, sequential
849 * in and status need no delay.
853 case NAND_CMD_CACHEDPROG:
854 case NAND_CMD_PAGEPROG:
855 case NAND_CMD_ERASE1:
856 case NAND_CMD_ERASE2:
858 case NAND_CMD_STATUS:
859 case NAND_CMD_READID:
860 case NAND_CMD_SET_FEATURES:
864 nand_ccs_delay(chip);
870 udelay(chip->chip_delay);
871 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
872 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
873 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
874 NAND_NCE | NAND_CTRL_CHANGE);
875 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
876 nand_wait_status_ready(mtd, 250);
879 case NAND_CMD_RNDOUT:
880 /* No ready / busy check necessary */
881 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
882 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
883 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
884 NAND_NCE | NAND_CTRL_CHANGE);
886 nand_ccs_delay(chip);
890 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
891 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
892 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
893 NAND_NCE | NAND_CTRL_CHANGE);
895 /* This applies to read commands */
898 * If we don't have access to the busy pin, we apply the given
901 if (!chip->dev_ready) {
902 udelay(chip->chip_delay);
908 * Apply this short delay always to ensure that we do wait tWB in
909 * any case on any machine.
913 nand_wait_ready(mtd);
917 * panic_nand_get_device - [GENERIC] Get chip for selected access
918 * @chip: the nand chip descriptor
919 * @mtd: MTD device structure
920 * @new_state: the state which is requested
922 * Used when in panic, no locks are taken.
924 static void panic_nand_get_device(struct nand_chip *chip,
925 struct mtd_info *mtd, int new_state)
927 /* Hardware controller shared among independent devices */
928 chip->controller->active = chip;
929 chip->state = new_state;
933 * nand_get_device - [GENERIC] Get chip for selected access
934 * @mtd: MTD device structure
935 * @new_state: the state which is requested
937 * Get the device and lock it for exclusive access
940 nand_get_device(struct mtd_info *mtd, int new_state)
942 struct nand_chip *chip = mtd_to_nand(mtd);
943 spinlock_t *lock = &chip->controller->lock;
944 wait_queue_head_t *wq = &chip->controller->wq;
945 DECLARE_WAITQUEUE(wait, current);
949 /* Hardware controller shared among independent devices */
950 if (!chip->controller->active)
951 chip->controller->active = chip;
953 if (chip->controller->active == chip && chip->state == FL_READY) {
954 chip->state = new_state;
958 if (new_state == FL_PM_SUSPENDED) {
959 if (chip->controller->active->state == FL_PM_SUSPENDED) {
960 chip->state = FL_PM_SUSPENDED;
965 set_current_state(TASK_UNINTERRUPTIBLE);
966 add_wait_queue(wq, &wait);
969 remove_wait_queue(wq, &wait);
974 * panic_nand_wait - [GENERIC] wait until the command is done
975 * @mtd: MTD device structure
976 * @chip: NAND chip structure
979 * Wait for command done. This is a helper function for nand_wait used when
980 * we are in interrupt context. May happen when in panic and trying to write
981 * an oops through mtdoops.
983 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
987 for (i = 0; i < timeo; i++) {
988 if (chip->dev_ready) {
989 if (chip->dev_ready(mtd))
992 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1000 * nand_wait - [DEFAULT] wait until the command is done
1001 * @mtd: MTD device structure
1002 * @chip: NAND chip structure
1004 * Wait for command done. This applies to erase and program only.
1006 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1010 unsigned long timeo = 400;
1013 * Apply this short delay always to ensure that we do wait tWB in any
1014 * case on any machine.
1018 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1020 if (in_interrupt() || oops_in_progress)
1021 panic_nand_wait(mtd, chip, timeo);
1023 timeo = jiffies + msecs_to_jiffies(timeo);
1025 if (chip->dev_ready) {
1026 if (chip->dev_ready(mtd))
1029 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1033 } while (time_before(jiffies, timeo));
1036 status = (int)chip->read_byte(mtd);
1037 /* This can happen if in case of timeout or buggy dev_ready */
1038 WARN_ON(!(status & NAND_STATUS_READY));
1043 * nand_reset_data_interface - Reset data interface and timings
1044 * @chip: The NAND chip
1046 * Reset the Data interface and timings to ONFI mode 0.
1048 * Returns 0 for success or negative error code otherwise.
1050 static int nand_reset_data_interface(struct nand_chip *chip)
1052 struct mtd_info *mtd = nand_to_mtd(chip);
1053 const struct nand_data_interface *conf;
1056 if (!chip->setup_data_interface)
1060 * The ONFI specification says:
1062 * To transition from NV-DDR or NV-DDR2 to the SDR data
1063 * interface, the host shall use the Reset (FFh) command
1064 * using SDR timing mode 0. A device in any timing mode is
1065 * required to recognize Reset (FFh) command issued in SDR
1069 * Configure the data interface in SDR mode and set the
1070 * timings to timing mode 0.
1073 conf = nand_get_default_data_interface();
1074 ret = chip->setup_data_interface(mtd, conf, false);
1076 pr_err("Failed to configure data interface to SDR timing mode 0\n");
1082 * nand_setup_data_interface - Setup the best data interface and timings
1083 * @chip: The NAND chip
1085 * Find and configure the best data interface and NAND timings supported by
1086 * the chip and the driver.
1087 * First tries to retrieve supported timing modes from ONFI information,
1088 * and if the NAND chip does not support ONFI, relies on the
1089 * ->onfi_timing_mode_default specified in the nand_ids table.
1091 * Returns 0 for success or negative error code otherwise.
1093 static int nand_setup_data_interface(struct nand_chip *chip)
1095 struct mtd_info *mtd = nand_to_mtd(chip);
1098 if (!chip->setup_data_interface || !chip->data_interface)
1102 * Ensure the timing mode has been changed on the chip side
1103 * before changing timings on the controller side.
1105 if (chip->onfi_version) {
1106 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1107 chip->onfi_timing_mode_default,
1110 ret = chip->onfi_set_features(mtd, chip,
1111 ONFI_FEATURE_ADDR_TIMING_MODE,
1117 ret = chip->setup_data_interface(mtd, chip->data_interface, false);
1123 * nand_init_data_interface - find the best data interface and timings
1124 * @chip: The NAND chip
1126 * Find the best data interface and NAND timings supported by the chip
1128 * First tries to retrieve supported timing modes from ONFI information,
1129 * and if the NAND chip does not support ONFI, relies on the
1130 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1131 * function nand_chip->data_interface is initialized with the best timing mode
1134 * Returns 0 for success or negative error code otherwise.
1136 static int nand_init_data_interface(struct nand_chip *chip)
1138 struct mtd_info *mtd = nand_to_mtd(chip);
1139 int modes, mode, ret;
1141 if (!chip->setup_data_interface)
1145 * First try to identify the best timings from ONFI parameters and
1146 * if the NAND does not support ONFI, fallback to the default ONFI
1149 modes = onfi_get_async_timing_mode(chip);
1150 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1151 if (!chip->onfi_timing_mode_default)
1154 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1157 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1159 if (!chip->data_interface)
1162 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1163 ret = onfi_init_data_interface(chip, chip->data_interface,
1164 NAND_SDR_IFACE, mode);
1168 ret = chip->setup_data_interface(mtd, chip->data_interface,
1171 chip->onfi_timing_mode_default = mode;
1179 static void nand_release_data_interface(struct nand_chip *chip)
1181 kfree(chip->data_interface);
1185 * nand_reset - Reset and initialize a NAND device
1186 * @chip: The NAND chip
1187 * @chipnr: Internal die id
1189 * Returns 0 for success or negative error code otherwise
1191 int nand_reset(struct nand_chip *chip, int chipnr)
1193 struct mtd_info *mtd = nand_to_mtd(chip);
1196 ret = nand_reset_data_interface(chip);
1201 * The CS line has to be released before we can apply the new NAND
1202 * interface settings, hence this weird ->select_chip() dance.
1204 chip->select_chip(mtd, chipnr);
1205 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1206 chip->select_chip(mtd, -1);
1208 chip->select_chip(mtd, chipnr);
1209 ret = nand_setup_data_interface(chip);
1210 chip->select_chip(mtd, -1);
1218 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1220 * @ofs: offset to start unlock from
1221 * @len: length to unlock
1222 * @invert: when = 0, unlock the range of blocks within the lower and
1223 * upper boundary address
1224 * when = 1, unlock the range of blocks outside the boundaries
1225 * of the lower and upper boundary address
1227 * Returs unlock status.
1229 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1230 uint64_t len, int invert)
1234 struct nand_chip *chip = mtd_to_nand(mtd);
1236 /* Submit address of first page to unlock */
1237 page = ofs >> chip->page_shift;
1238 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1240 /* Submit address of last page to unlock */
1241 page = (ofs + len) >> chip->page_shift;
1242 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1243 (page | invert) & chip->pagemask);
1245 /* Call wait ready function */
1246 status = chip->waitfunc(mtd, chip);
1247 /* See if device thinks it succeeded */
1248 if (status & NAND_STATUS_FAIL) {
1249 pr_debug("%s: error status = 0x%08x\n",
1258 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1260 * @ofs: offset to start unlock from
1261 * @len: length to unlock
1263 * Returns unlock status.
1265 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1269 struct nand_chip *chip = mtd_to_nand(mtd);
1271 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1272 __func__, (unsigned long long)ofs, len);
1274 if (check_offs_len(mtd, ofs, len))
1277 /* Align to last block address if size addresses end of the device */
1278 if (ofs + len == mtd->size)
1279 len -= mtd->erasesize;
1281 nand_get_device(mtd, FL_UNLOCKING);
1283 /* Shift to get chip number */
1284 chipnr = ofs >> chip->chip_shift;
1288 * If we want to check the WP through READ STATUS and check the bit 7
1289 * we must reset the chip
1290 * some operation can also clear the bit 7 of status register
1291 * eg. erase/program a locked block
1293 nand_reset(chip, chipnr);
1295 chip->select_chip(mtd, chipnr);
1297 /* Check, if it is write protected */
1298 if (nand_check_wp(mtd)) {
1299 pr_debug("%s: device is write protected!\n",
1305 ret = __nand_unlock(mtd, ofs, len, 0);
1308 chip->select_chip(mtd, -1);
1309 nand_release_device(mtd);
1313 EXPORT_SYMBOL(nand_unlock);
1316 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1318 * @ofs: offset to start unlock from
1319 * @len: length to unlock
1321 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1322 * have this feature, but it allows only to lock all blocks, not for specified
1323 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1326 * Returns lock status.
1328 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1331 int chipnr, status, page;
1332 struct nand_chip *chip = mtd_to_nand(mtd);
1334 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1335 __func__, (unsigned long long)ofs, len);
1337 if (check_offs_len(mtd, ofs, len))
1340 nand_get_device(mtd, FL_LOCKING);
1342 /* Shift to get chip number */
1343 chipnr = ofs >> chip->chip_shift;
1347 * If we want to check the WP through READ STATUS and check the bit 7
1348 * we must reset the chip
1349 * some operation can also clear the bit 7 of status register
1350 * eg. erase/program a locked block
1352 nand_reset(chip, chipnr);
1354 chip->select_chip(mtd, chipnr);
1356 /* Check, if it is write protected */
1357 if (nand_check_wp(mtd)) {
1358 pr_debug("%s: device is write protected!\n",
1360 status = MTD_ERASE_FAILED;
1365 /* Submit address of first page to lock */
1366 page = ofs >> chip->page_shift;
1367 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1369 /* Call wait ready function */
1370 status = chip->waitfunc(mtd, chip);
1371 /* See if device thinks it succeeded */
1372 if (status & NAND_STATUS_FAIL) {
1373 pr_debug("%s: error status = 0x%08x\n",
1379 ret = __nand_unlock(mtd, ofs, len, 0x1);
1382 chip->select_chip(mtd, -1);
1383 nand_release_device(mtd);
1387 EXPORT_SYMBOL(nand_lock);
1390 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1391 * @buf: buffer to test
1392 * @len: buffer length
1393 * @bitflips_threshold: maximum number of bitflips
1395 * Check if a buffer contains only 0xff, which means the underlying region
1396 * has been erased and is ready to be programmed.
1397 * The bitflips_threshold specify the maximum number of bitflips before
1398 * considering the region is not erased.
1399 * Note: The logic of this function has been extracted from the memweight
1400 * implementation, except that nand_check_erased_buf function exit before
1401 * testing the whole buffer if the number of bitflips exceed the
1402 * bitflips_threshold value.
1404 * Returns a positive number of bitflips less than or equal to
1405 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1408 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1410 const unsigned char *bitmap = buf;
1414 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1416 weight = hweight8(*bitmap);
1417 bitflips += BITS_PER_BYTE - weight;
1418 if (unlikely(bitflips > bitflips_threshold))
1422 for (; len >= sizeof(long);
1423 len -= sizeof(long), bitmap += sizeof(long)) {
1424 weight = hweight_long(*((unsigned long *)bitmap));
1425 bitflips += BITS_PER_LONG - weight;
1426 if (unlikely(bitflips > bitflips_threshold))
1430 for (; len > 0; len--, bitmap++) {
1431 weight = hweight8(*bitmap);
1432 bitflips += BITS_PER_BYTE - weight;
1433 if (unlikely(bitflips > bitflips_threshold))
1441 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1443 * @data: data buffer to test
1444 * @datalen: data length
1446 * @ecclen: ECC length
1447 * @extraoob: extra OOB buffer
1448 * @extraooblen: extra OOB length
1449 * @bitflips_threshold: maximum number of bitflips
1451 * Check if a data buffer and its associated ECC and OOB data contains only
1452 * 0xff pattern, which means the underlying region has been erased and is
1453 * ready to be programmed.
1454 * The bitflips_threshold specify the maximum number of bitflips before
1455 * considering the region as not erased.
1458 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1459 * different from the NAND page size. When fixing bitflips, ECC engines will
1460 * report the number of errors per chunk, and the NAND core infrastructure
1461 * expect you to return the maximum number of bitflips for the whole page.
1462 * This is why you should always use this function on a single chunk and
1463 * not on the whole page. After checking each chunk you should update your
1464 * max_bitflips value accordingly.
1465 * 2/ When checking for bitflips in erased pages you should not only check
1466 * the payload data but also their associated ECC data, because a user might
1467 * have programmed almost all bits to 1 but a few. In this case, we
1468 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1470 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1471 * data are protected by the ECC engine.
1472 * It could also be used if you support subpages and want to attach some
1473 * extra OOB data to an ECC chunk.
1475 * Returns a positive number of bitflips less than or equal to
1476 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1477 * threshold. In case of success, the passed buffers are filled with 0xff.
1479 int nand_check_erased_ecc_chunk(void *data, int datalen,
1480 void *ecc, int ecclen,
1481 void *extraoob, int extraooblen,
1482 int bitflips_threshold)
1484 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1486 data_bitflips = nand_check_erased_buf(data, datalen,
1487 bitflips_threshold);
1488 if (data_bitflips < 0)
1489 return data_bitflips;
1491 bitflips_threshold -= data_bitflips;
1493 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1494 if (ecc_bitflips < 0)
1495 return ecc_bitflips;
1497 bitflips_threshold -= ecc_bitflips;
1499 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1500 bitflips_threshold);
1501 if (extraoob_bitflips < 0)
1502 return extraoob_bitflips;
1505 memset(data, 0xff, datalen);
1508 memset(ecc, 0xff, ecclen);
1510 if (extraoob_bitflips)
1511 memset(extraoob, 0xff, extraooblen);
1513 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1515 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1518 * nand_read_page_raw - [INTERN] read raw page data without ecc
1519 * @mtd: mtd info structure
1520 * @chip: nand chip info structure
1521 * @buf: buffer to store read data
1522 * @oob_required: caller requires OOB data read to chip->oob_poi
1523 * @page: page number to read
1525 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1527 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1528 uint8_t *buf, int oob_required, int page)
1530 chip->read_buf(mtd, buf, mtd->writesize);
1532 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1537 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1538 * @mtd: mtd info structure
1539 * @chip: nand chip info structure
1540 * @buf: buffer to store read data
1541 * @oob_required: caller requires OOB data read to chip->oob_poi
1542 * @page: page number to read
1544 * We need a special oob layout and handling even when OOB isn't used.
1546 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1547 struct nand_chip *chip, uint8_t *buf,
1548 int oob_required, int page)
1550 int eccsize = chip->ecc.size;
1551 int eccbytes = chip->ecc.bytes;
1552 uint8_t *oob = chip->oob_poi;
1555 for (steps = chip->ecc.steps; steps > 0; steps--) {
1556 chip->read_buf(mtd, buf, eccsize);
1559 if (chip->ecc.prepad) {
1560 chip->read_buf(mtd, oob, chip->ecc.prepad);
1561 oob += chip->ecc.prepad;
1564 chip->read_buf(mtd, oob, eccbytes);
1567 if (chip->ecc.postpad) {
1568 chip->read_buf(mtd, oob, chip->ecc.postpad);
1569 oob += chip->ecc.postpad;
1573 size = mtd->oobsize - (oob - chip->oob_poi);
1575 chip->read_buf(mtd, oob, size);
1581 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1582 * @mtd: mtd info structure
1583 * @chip: nand chip info structure
1584 * @buf: buffer to store read data
1585 * @oob_required: caller requires OOB data read to chip->oob_poi
1586 * @page: page number to read
1588 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1589 uint8_t *buf, int oob_required, int page)
1591 int i, eccsize = chip->ecc.size, ret;
1592 int eccbytes = chip->ecc.bytes;
1593 int eccsteps = chip->ecc.steps;
1595 uint8_t *ecc_calc = chip->buffers->ecccalc;
1596 uint8_t *ecc_code = chip->buffers->ecccode;
1597 unsigned int max_bitflips = 0;
1599 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1601 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1602 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1604 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1609 eccsteps = chip->ecc.steps;
1612 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1615 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1617 mtd->ecc_stats.failed++;
1619 mtd->ecc_stats.corrected += stat;
1620 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1623 return max_bitflips;
1627 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1628 * @mtd: mtd info structure
1629 * @chip: nand chip info structure
1630 * @data_offs: offset of requested data within the page
1631 * @readlen: data length
1632 * @bufpoi: buffer to store read data
1633 * @page: page number to read
1635 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1636 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1639 int start_step, end_step, num_steps, ret;
1641 int data_col_addr, i, gaps = 0;
1642 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1643 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1644 int index, section = 0;
1645 unsigned int max_bitflips = 0;
1646 struct mtd_oob_region oobregion = { };
1648 /* Column address within the page aligned to ECC size (256bytes) */
1649 start_step = data_offs / chip->ecc.size;
1650 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1651 num_steps = end_step - start_step + 1;
1652 index = start_step * chip->ecc.bytes;
1654 /* Data size aligned to ECC ecc.size */
1655 datafrag_len = num_steps * chip->ecc.size;
1656 eccfrag_len = num_steps * chip->ecc.bytes;
1658 data_col_addr = start_step * chip->ecc.size;
1659 /* If we read not a page aligned data */
1660 if (data_col_addr != 0)
1661 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1663 p = bufpoi + data_col_addr;
1664 chip->read_buf(mtd, p, datafrag_len);
1667 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1668 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1671 * The performance is faster if we position offsets according to
1672 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1674 ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion);
1678 if (oobregion.length < eccfrag_len)
1682 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1683 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1686 * Send the command to read the particular ECC bytes take care
1687 * about buswidth alignment in read_buf.
1689 aligned_pos = oobregion.offset & ~(busw - 1);
1690 aligned_len = eccfrag_len;
1691 if (oobregion.offset & (busw - 1))
1693 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
1697 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1698 mtd->writesize + aligned_pos, -1);
1699 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1702 ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode,
1703 chip->oob_poi, index, eccfrag_len);
1707 p = bufpoi + data_col_addr;
1708 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1711 stat = chip->ecc.correct(mtd, p,
1712 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1713 if (stat == -EBADMSG &&
1714 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1715 /* check for empty pages with bitflips */
1716 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1717 &chip->buffers->ecccode[i],
1720 chip->ecc.strength);
1724 mtd->ecc_stats.failed++;
1726 mtd->ecc_stats.corrected += stat;
1727 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1730 return max_bitflips;
1734 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1735 * @mtd: mtd info structure
1736 * @chip: nand chip info structure
1737 * @buf: buffer to store read data
1738 * @oob_required: caller requires OOB data read to chip->oob_poi
1739 * @page: page number to read
1741 * Not for syndrome calculating ECC controllers which need a special oob layout.
1743 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1744 uint8_t *buf, int oob_required, int page)
1746 int i, eccsize = chip->ecc.size, ret;
1747 int eccbytes = chip->ecc.bytes;
1748 int eccsteps = chip->ecc.steps;
1750 uint8_t *ecc_calc = chip->buffers->ecccalc;
1751 uint8_t *ecc_code = chip->buffers->ecccode;
1752 unsigned int max_bitflips = 0;
1754 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1755 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1756 chip->read_buf(mtd, p, eccsize);
1757 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1759 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1761 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1766 eccsteps = chip->ecc.steps;
1769 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1772 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1773 if (stat == -EBADMSG &&
1774 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1775 /* check for empty pages with bitflips */
1776 stat = nand_check_erased_ecc_chunk(p, eccsize,
1777 &ecc_code[i], eccbytes,
1779 chip->ecc.strength);
1783 mtd->ecc_stats.failed++;
1785 mtd->ecc_stats.corrected += stat;
1786 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1789 return max_bitflips;
1793 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1794 * @mtd: mtd info structure
1795 * @chip: nand chip info structure
1796 * @buf: buffer to store read data
1797 * @oob_required: caller requires OOB data read to chip->oob_poi
1798 * @page: page number to read
1800 * Hardware ECC for large page chips, require OOB to be read first. For this
1801 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1802 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1803 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1804 * the data area, by overwriting the NAND manufacturer bad block markings.
1806 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1807 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1809 int i, eccsize = chip->ecc.size, ret;
1810 int eccbytes = chip->ecc.bytes;
1811 int eccsteps = chip->ecc.steps;
1813 uint8_t *ecc_code = chip->buffers->ecccode;
1814 uint8_t *ecc_calc = chip->buffers->ecccalc;
1815 unsigned int max_bitflips = 0;
1817 /* Read the OOB area first */
1818 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1819 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1820 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1822 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1827 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1830 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1831 chip->read_buf(mtd, p, eccsize);
1832 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1834 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1835 if (stat == -EBADMSG &&
1836 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1837 /* check for empty pages with bitflips */
1838 stat = nand_check_erased_ecc_chunk(p, eccsize,
1839 &ecc_code[i], eccbytes,
1841 chip->ecc.strength);
1845 mtd->ecc_stats.failed++;
1847 mtd->ecc_stats.corrected += stat;
1848 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1851 return max_bitflips;
1855 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1856 * @mtd: mtd info structure
1857 * @chip: nand chip info structure
1858 * @buf: buffer to store read data
1859 * @oob_required: caller requires OOB data read to chip->oob_poi
1860 * @page: page number to read
1862 * The hw generator calculates the error syndrome automatically. Therefore we
1863 * need a special oob layout and handling.
1865 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1866 uint8_t *buf, int oob_required, int page)
1868 int i, eccsize = chip->ecc.size;
1869 int eccbytes = chip->ecc.bytes;
1870 int eccsteps = chip->ecc.steps;
1871 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
1873 uint8_t *oob = chip->oob_poi;
1874 unsigned int max_bitflips = 0;
1876 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1879 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1880 chip->read_buf(mtd, p, eccsize);
1882 if (chip->ecc.prepad) {
1883 chip->read_buf(mtd, oob, chip->ecc.prepad);
1884 oob += chip->ecc.prepad;
1887 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1888 chip->read_buf(mtd, oob, eccbytes);
1889 stat = chip->ecc.correct(mtd, p, oob, NULL);
1893 if (chip->ecc.postpad) {
1894 chip->read_buf(mtd, oob, chip->ecc.postpad);
1895 oob += chip->ecc.postpad;
1898 if (stat == -EBADMSG &&
1899 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1900 /* check for empty pages with bitflips */
1901 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1905 chip->ecc.strength);
1909 mtd->ecc_stats.failed++;
1911 mtd->ecc_stats.corrected += stat;
1912 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1916 /* Calculate remaining oob bytes */
1917 i = mtd->oobsize - (oob - chip->oob_poi);
1919 chip->read_buf(mtd, oob, i);
1921 return max_bitflips;
1925 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1926 * @mtd: mtd info structure
1927 * @oob: oob destination address
1928 * @ops: oob ops structure
1929 * @len: size of oob to transfer
1931 static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
1932 struct mtd_oob_ops *ops, size_t len)
1934 struct nand_chip *chip = mtd_to_nand(mtd);
1937 switch (ops->mode) {
1939 case MTD_OPS_PLACE_OOB:
1941 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1944 case MTD_OPS_AUTO_OOB:
1945 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
1957 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1958 * @mtd: MTD device structure
1959 * @retry_mode: the retry mode to use
1961 * Some vendors supply a special command to shift the Vt threshold, to be used
1962 * when there are too many bitflips in a page (i.e., ECC error). After setting
1963 * a new threshold, the host should retry reading the page.
1965 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1967 struct nand_chip *chip = mtd_to_nand(mtd);
1969 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1971 if (retry_mode >= chip->read_retries)
1974 if (!chip->setup_read_retry)
1977 return chip->setup_read_retry(mtd, retry_mode);
1981 * nand_do_read_ops - [INTERN] Read data with ECC
1982 * @mtd: MTD device structure
1983 * @from: offset to read from
1984 * @ops: oob ops structure
1986 * Internal function. Called with chip held.
1988 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1989 struct mtd_oob_ops *ops)
1991 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1992 struct nand_chip *chip = mtd_to_nand(mtd);
1994 uint32_t readlen = ops->len;
1995 uint32_t oobreadlen = ops->ooblen;
1996 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
1998 uint8_t *bufpoi, *oob, *buf;
2000 unsigned int max_bitflips = 0;
2002 bool ecc_fail = false;
2004 chipnr = (int)(from >> chip->chip_shift);
2005 chip->select_chip(mtd, chipnr);
2007 realpage = (int)(from >> chip->page_shift);
2008 page = realpage & chip->pagemask;
2010 col = (int)(from & (mtd->writesize - 1));
2014 oob_required = oob ? 1 : 0;
2017 unsigned int ecc_failures = mtd->ecc_stats.failed;
2019 bytes = min(mtd->writesize - col, readlen);
2020 aligned = (bytes == mtd->writesize);
2024 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2025 use_bufpoi = !virt_addr_valid(buf) ||
2026 !IS_ALIGNED((unsigned long)buf,
2031 /* Is the current page in the buffer? */
2032 if (realpage != chip->pagebuf || oob) {
2033 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
2035 if (use_bufpoi && aligned)
2036 pr_debug("%s: using read bounce buffer for buf@%p\n",
2040 if (nand_standard_page_accessors(&chip->ecc))
2041 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
2044 * Now read the page into the buffer. Absent an error,
2045 * the read methods return max bitflips per ecc step.
2047 if (unlikely(ops->mode == MTD_OPS_RAW))
2048 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
2051 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
2053 ret = chip->ecc.read_subpage(mtd, chip,
2057 ret = chip->ecc.read_page(mtd, chip, bufpoi,
2058 oob_required, page);
2061 /* Invalidate page cache */
2066 /* Transfer not aligned data */
2068 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
2069 !(mtd->ecc_stats.failed - ecc_failures) &&
2070 (ops->mode != MTD_OPS_RAW)) {
2071 chip->pagebuf = realpage;
2072 chip->pagebuf_bitflips = ret;
2074 /* Invalidate page cache */
2077 memcpy(buf, chip->buffers->databuf + col, bytes);
2080 if (unlikely(oob)) {
2081 int toread = min(oobreadlen, max_oobsize);
2084 oob = nand_transfer_oob(mtd,
2086 oobreadlen -= toread;
2090 if (chip->options & NAND_NEED_READRDY) {
2091 /* Apply delay or wait for ready/busy pin */
2092 if (!chip->dev_ready)
2093 udelay(chip->chip_delay);
2095 nand_wait_ready(mtd);
2098 if (mtd->ecc_stats.failed - ecc_failures) {
2099 if (retry_mode + 1 < chip->read_retries) {
2101 ret = nand_setup_read_retry(mtd,
2106 /* Reset failures; retry */
2107 mtd->ecc_stats.failed = ecc_failures;
2110 /* No more retry modes; real failure */
2116 max_bitflips = max_t(unsigned int, max_bitflips, ret);
2118 memcpy(buf, chip->buffers->databuf + col, bytes);
2120 max_bitflips = max_t(unsigned int, max_bitflips,
2121 chip->pagebuf_bitflips);
2126 /* Reset to retry mode 0 */
2128 ret = nand_setup_read_retry(mtd, 0);
2137 /* For subsequent reads align to page boundary */
2139 /* Increment page address */
2142 page = realpage & chip->pagemask;
2143 /* Check, if we cross a chip boundary */
2146 chip->select_chip(mtd, -1);
2147 chip->select_chip(mtd, chipnr);
2150 chip->select_chip(mtd, -1);
2152 ops->retlen = ops->len - (size_t) readlen;
2154 ops->oobretlen = ops->ooblen - oobreadlen;
2162 return max_bitflips;
2166 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
2167 * @mtd: MTD device structure
2168 * @from: offset to read from
2169 * @len: number of bytes to read
2170 * @retlen: pointer to variable to store the number of read bytes
2171 * @buf: the databuffer to put data
2173 * Get hold of the chip and call nand_do_read.
2175 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
2176 size_t *retlen, uint8_t *buf)
2178 struct mtd_oob_ops ops;
2181 nand_get_device(mtd, FL_READING);
2182 memset(&ops, 0, sizeof(ops));
2185 ops.mode = MTD_OPS_PLACE_OOB;
2186 ret = nand_do_read_ops(mtd, from, &ops);
2187 *retlen = ops.retlen;
2188 nand_release_device(mtd);
2193 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
2194 * @mtd: mtd info structure
2195 * @chip: nand chip info structure
2196 * @page: page number to read
2198 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
2200 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
2201 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
2204 EXPORT_SYMBOL(nand_read_oob_std);
2207 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
2209 * @mtd: mtd info structure
2210 * @chip: nand chip info structure
2211 * @page: page number to read
2213 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2216 int length = mtd->oobsize;
2217 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2218 int eccsize = chip->ecc.size;
2219 uint8_t *bufpoi = chip->oob_poi;
2220 int i, toread, sndrnd = 0, pos;
2222 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
2223 for (i = 0; i < chip->ecc.steps; i++) {
2225 pos = eccsize + i * (eccsize + chunk);
2226 if (mtd->writesize > 512)
2227 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
2229 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
2232 toread = min_t(int, length, chunk);
2233 chip->read_buf(mtd, bufpoi, toread);
2238 chip->read_buf(mtd, bufpoi, length);
2242 EXPORT_SYMBOL(nand_read_oob_syndrome);
2245 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
2246 * @mtd: mtd info structure
2247 * @chip: nand chip info structure
2248 * @page: page number to write
2250 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
2253 const uint8_t *buf = chip->oob_poi;
2254 int length = mtd->oobsize;
2256 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
2257 chip->write_buf(mtd, buf, length);
2258 /* Send command to program the OOB data */
2259 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2261 status = chip->waitfunc(mtd, chip);
2263 return status & NAND_STATUS_FAIL ? -EIO : 0;
2265 EXPORT_SYMBOL(nand_write_oob_std);
2268 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
2269 * with syndrome - only for large page flash
2270 * @mtd: mtd info structure
2271 * @chip: nand chip info structure
2272 * @page: page number to write
2274 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2277 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2278 int eccsize = chip->ecc.size, length = mtd->oobsize;
2279 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
2280 const uint8_t *bufpoi = chip->oob_poi;
2283 * data-ecc-data-ecc ... ecc-oob
2285 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2287 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2288 pos = steps * (eccsize + chunk);
2293 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
2294 for (i = 0; i < steps; i++) {
2296 if (mtd->writesize <= 512) {
2297 uint32_t fill = 0xFFFFFFFF;
2301 int num = min_t(int, len, 4);
2302 chip->write_buf(mtd, (uint8_t *)&fill,
2307 pos = eccsize + i * (eccsize + chunk);
2308 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2312 len = min_t(int, length, chunk);
2313 chip->write_buf(mtd, bufpoi, len);
2318 chip->write_buf(mtd, bufpoi, length);
2320 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2321 status = chip->waitfunc(mtd, chip);
2323 return status & NAND_STATUS_FAIL ? -EIO : 0;
2325 EXPORT_SYMBOL(nand_write_oob_syndrome);
2328 * nand_do_read_oob - [INTERN] NAND read out-of-band
2329 * @mtd: MTD device structure
2330 * @from: offset to read from
2331 * @ops: oob operations description structure
2333 * NAND read out-of-band data from the spare area.
2335 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2336 struct mtd_oob_ops *ops)
2338 int page, realpage, chipnr;
2339 struct nand_chip *chip = mtd_to_nand(mtd);
2340 struct mtd_ecc_stats stats;
2341 int readlen = ops->ooblen;
2343 uint8_t *buf = ops->oobbuf;
2346 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2347 __func__, (unsigned long long)from, readlen);
2349 stats = mtd->ecc_stats;
2351 len = mtd_oobavail(mtd, ops);
2353 if (unlikely(ops->ooboffs >= len)) {
2354 pr_debug("%s: attempt to start read outside oob\n",
2359 /* Do not allow reads past end of device */
2360 if (unlikely(from >= mtd->size ||
2361 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2362 (from >> chip->page_shift)) * len)) {
2363 pr_debug("%s: attempt to read beyond end of device\n",
2368 chipnr = (int)(from >> chip->chip_shift);
2369 chip->select_chip(mtd, chipnr);
2371 /* Shift to get page */
2372 realpage = (int)(from >> chip->page_shift);
2373 page = realpage & chip->pagemask;
2376 if (ops->mode == MTD_OPS_RAW)
2377 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2379 ret = chip->ecc.read_oob(mtd, chip, page);
2384 len = min(len, readlen);
2385 buf = nand_transfer_oob(mtd, buf, ops, len);
2387 if (chip->options & NAND_NEED_READRDY) {
2388 /* Apply delay or wait for ready/busy pin */
2389 if (!chip->dev_ready)
2390 udelay(chip->chip_delay);
2392 nand_wait_ready(mtd);
2399 /* Increment page address */
2402 page = realpage & chip->pagemask;
2403 /* Check, if we cross a chip boundary */
2406 chip->select_chip(mtd, -1);
2407 chip->select_chip(mtd, chipnr);
2410 chip->select_chip(mtd, -1);
2412 ops->oobretlen = ops->ooblen - readlen;
2417 if (mtd->ecc_stats.failed - stats.failed)
2420 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2424 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2425 * @mtd: MTD device structure
2426 * @from: offset to read from
2427 * @ops: oob operation description structure
2429 * NAND read data and/or out-of-band data.
2431 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2432 struct mtd_oob_ops *ops)
2438 /* Do not allow reads past end of device */
2439 if (ops->datbuf && (from + ops->len) > mtd->size) {
2440 pr_debug("%s: attempt to read beyond end of device\n",
2445 if (ops->mode != MTD_OPS_PLACE_OOB &&
2446 ops->mode != MTD_OPS_AUTO_OOB &&
2447 ops->mode != MTD_OPS_RAW)
2450 nand_get_device(mtd, FL_READING);
2453 ret = nand_do_read_oob(mtd, from, ops);
2455 ret = nand_do_read_ops(mtd, from, ops);
2457 nand_release_device(mtd);
2463 * nand_write_page_raw - [INTERN] raw page write function
2464 * @mtd: mtd info structure
2465 * @chip: nand chip info structure
2467 * @oob_required: must write chip->oob_poi to OOB
2468 * @page: page number to write
2470 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2472 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2473 const uint8_t *buf, int oob_required, int page)
2475 chip->write_buf(mtd, buf, mtd->writesize);
2477 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2483 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2484 * @mtd: mtd info structure
2485 * @chip: nand chip info structure
2487 * @oob_required: must write chip->oob_poi to OOB
2488 * @page: page number to write
2490 * We need a special oob layout and handling even when ECC isn't checked.
2492 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2493 struct nand_chip *chip,
2494 const uint8_t *buf, int oob_required,
2497 int eccsize = chip->ecc.size;
2498 int eccbytes = chip->ecc.bytes;
2499 uint8_t *oob = chip->oob_poi;
2502 for (steps = chip->ecc.steps; steps > 0; steps--) {
2503 chip->write_buf(mtd, buf, eccsize);
2506 if (chip->ecc.prepad) {
2507 chip->write_buf(mtd, oob, chip->ecc.prepad);
2508 oob += chip->ecc.prepad;
2511 chip->write_buf(mtd, oob, eccbytes);
2514 if (chip->ecc.postpad) {
2515 chip->write_buf(mtd, oob, chip->ecc.postpad);
2516 oob += chip->ecc.postpad;
2520 size = mtd->oobsize - (oob - chip->oob_poi);
2522 chip->write_buf(mtd, oob, size);
2527 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2528 * @mtd: mtd info structure
2529 * @chip: nand chip info structure
2531 * @oob_required: must write chip->oob_poi to OOB
2532 * @page: page number to write
2534 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2535 const uint8_t *buf, int oob_required,
2538 int i, eccsize = chip->ecc.size, ret;
2539 int eccbytes = chip->ecc.bytes;
2540 int eccsteps = chip->ecc.steps;
2541 uint8_t *ecc_calc = chip->buffers->ecccalc;
2542 const uint8_t *p = buf;
2544 /* Software ECC calculation */
2545 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2546 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2548 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2553 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2557 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2558 * @mtd: mtd info structure
2559 * @chip: nand chip info structure
2561 * @oob_required: must write chip->oob_poi to OOB
2562 * @page: page number to write
2564 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2565 const uint8_t *buf, int oob_required,
2568 int i, eccsize = chip->ecc.size, ret;
2569 int eccbytes = chip->ecc.bytes;
2570 int eccsteps = chip->ecc.steps;
2571 uint8_t *ecc_calc = chip->buffers->ecccalc;
2572 const uint8_t *p = buf;
2574 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2575 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2576 chip->write_buf(mtd, p, eccsize);
2577 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2580 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2585 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2592 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2593 * @mtd: mtd info structure
2594 * @chip: nand chip info structure
2595 * @offset: column address of subpage within the page
2596 * @data_len: data length
2598 * @oob_required: must write chip->oob_poi to OOB
2599 * @page: page number to write
2601 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2602 struct nand_chip *chip, uint32_t offset,
2603 uint32_t data_len, const uint8_t *buf,
2604 int oob_required, int page)
2606 uint8_t *oob_buf = chip->oob_poi;
2607 uint8_t *ecc_calc = chip->buffers->ecccalc;
2608 int ecc_size = chip->ecc.size;
2609 int ecc_bytes = chip->ecc.bytes;
2610 int ecc_steps = chip->ecc.steps;
2611 uint32_t start_step = offset / ecc_size;
2612 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2613 int oob_bytes = mtd->oobsize / ecc_steps;
2616 for (step = 0; step < ecc_steps; step++) {
2617 /* configure controller for WRITE access */
2618 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2620 /* write data (untouched subpages already masked by 0xFF) */
2621 chip->write_buf(mtd, buf, ecc_size);
2623 /* mask ECC of un-touched subpages by padding 0xFF */
2624 if ((step < start_step) || (step > end_step))
2625 memset(ecc_calc, 0xff, ecc_bytes);
2627 chip->ecc.calculate(mtd, buf, ecc_calc);
2629 /* mask OOB of un-touched subpages by padding 0xFF */
2630 /* if oob_required, preserve OOB metadata of written subpage */
2631 if (!oob_required || (step < start_step) || (step > end_step))
2632 memset(oob_buf, 0xff, oob_bytes);
2635 ecc_calc += ecc_bytes;
2636 oob_buf += oob_bytes;
2639 /* copy calculated ECC for whole page to chip->buffer->oob */
2640 /* this include masked-value(0xFF) for unwritten subpages */
2641 ecc_calc = chip->buffers->ecccalc;
2642 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2647 /* write OOB buffer to NAND device */
2648 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2655 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2656 * @mtd: mtd info structure
2657 * @chip: nand chip info structure
2659 * @oob_required: must write chip->oob_poi to OOB
2660 * @page: page number to write
2662 * The hw generator calculates the error syndrome automatically. Therefore we
2663 * need a special oob layout and handling.
2665 static int nand_write_page_syndrome(struct mtd_info *mtd,
2666 struct nand_chip *chip,
2667 const uint8_t *buf, int oob_required,
2670 int i, eccsize = chip->ecc.size;
2671 int eccbytes = chip->ecc.bytes;
2672 int eccsteps = chip->ecc.steps;
2673 const uint8_t *p = buf;
2674 uint8_t *oob = chip->oob_poi;
2676 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2678 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2679 chip->write_buf(mtd, p, eccsize);
2681 if (chip->ecc.prepad) {
2682 chip->write_buf(mtd, oob, chip->ecc.prepad);
2683 oob += chip->ecc.prepad;
2686 chip->ecc.calculate(mtd, p, oob);
2687 chip->write_buf(mtd, oob, eccbytes);
2690 if (chip->ecc.postpad) {
2691 chip->write_buf(mtd, oob, chip->ecc.postpad);
2692 oob += chip->ecc.postpad;
2696 /* Calculate remaining oob bytes */
2697 i = mtd->oobsize - (oob - chip->oob_poi);
2699 chip->write_buf(mtd, oob, i);
2705 * nand_write_page - write one page
2706 * @mtd: MTD device structure
2707 * @chip: NAND chip descriptor
2708 * @offset: address offset within the page
2709 * @data_len: length of actual data to be written
2710 * @buf: the data to write
2711 * @oob_required: must write chip->oob_poi to OOB
2712 * @page: page number to write
2713 * @cached: cached programming
2714 * @raw: use _raw version of write_page
2716 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2717 uint32_t offset, int data_len, const uint8_t *buf,
2718 int oob_required, int page, int cached, int raw)
2720 int status, subpage;
2722 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2723 chip->ecc.write_subpage)
2724 subpage = offset || (data_len < mtd->writesize);
2728 if (nand_standard_page_accessors(&chip->ecc))
2729 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2732 status = chip->ecc.write_page_raw(mtd, chip, buf,
2733 oob_required, page);
2735 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2736 buf, oob_required, page);
2738 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2745 * Cached progamming disabled for now. Not sure if it's worth the
2746 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2750 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2752 if (nand_standard_page_accessors(&chip->ecc))
2753 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2754 status = chip->waitfunc(mtd, chip);
2756 * See if operation failed and additional status checks are
2759 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2760 status = chip->errstat(mtd, chip, FL_WRITING, status,
2763 if (status & NAND_STATUS_FAIL)
2766 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2767 status = chip->waitfunc(mtd, chip);
2774 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2775 * @mtd: MTD device structure
2776 * @oob: oob data buffer
2777 * @len: oob data write length
2778 * @ops: oob ops structure
2780 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2781 struct mtd_oob_ops *ops)
2783 struct nand_chip *chip = mtd_to_nand(mtd);
2787 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2788 * data from a previous OOB read.
2790 memset(chip->oob_poi, 0xff, mtd->oobsize);
2792 switch (ops->mode) {
2794 case MTD_OPS_PLACE_OOB:
2796 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2799 case MTD_OPS_AUTO_OOB:
2800 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
2811 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2814 * nand_do_write_ops - [INTERN] NAND write with ECC
2815 * @mtd: MTD device structure
2816 * @to: offset to write to
2817 * @ops: oob operations description structure
2819 * NAND write with ECC.
2821 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2822 struct mtd_oob_ops *ops)
2824 int chipnr, realpage, page, blockmask, column;
2825 struct nand_chip *chip = mtd_to_nand(mtd);
2826 uint32_t writelen = ops->len;
2828 uint32_t oobwritelen = ops->ooblen;
2829 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
2831 uint8_t *oob = ops->oobbuf;
2832 uint8_t *buf = ops->datbuf;
2834 int oob_required = oob ? 1 : 0;
2840 /* Reject writes, which are not page aligned */
2841 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2842 pr_notice("%s: attempt to write non page aligned data\n",
2847 column = to & (mtd->writesize - 1);
2849 chipnr = (int)(to >> chip->chip_shift);
2850 chip->select_chip(mtd, chipnr);
2852 /* Check, if it is write protected */
2853 if (nand_check_wp(mtd)) {
2858 realpage = (int)(to >> chip->page_shift);
2859 page = realpage & chip->pagemask;
2860 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2862 /* Invalidate the page cache, when we write to the cached page */
2863 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2864 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2867 /* Don't allow multipage oob writes with offset */
2868 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2874 int bytes = mtd->writesize;
2875 int cached = writelen > bytes && page != blockmask;
2876 uint8_t *wbuf = buf;
2878 int part_pagewr = (column || writelen < mtd->writesize);
2882 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2883 use_bufpoi = !virt_addr_valid(buf) ||
2884 !IS_ALIGNED((unsigned long)buf,
2889 /* Partial page write?, or need to use bounce buffer */
2891 pr_debug("%s: using write bounce buffer for buf@%p\n",
2895 bytes = min_t(int, bytes - column, writelen);
2897 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2898 memcpy(&chip->buffers->databuf[column], buf, bytes);
2899 wbuf = chip->buffers->databuf;
2902 if (unlikely(oob)) {
2903 size_t len = min(oobwritelen, oobmaxlen);
2904 oob = nand_fill_oob(mtd, oob, len, ops);
2907 /* We still need to erase leftover OOB data */
2908 memset(chip->oob_poi, 0xff, mtd->oobsize);
2911 ret = nand_write_page(mtd, chip, column, bytes, wbuf,
2912 oob_required, page, cached,
2913 (ops->mode == MTD_OPS_RAW));
2925 page = realpage & chip->pagemask;
2926 /* Check, if we cross a chip boundary */
2929 chip->select_chip(mtd, -1);
2930 chip->select_chip(mtd, chipnr);
2934 ops->retlen = ops->len - writelen;
2936 ops->oobretlen = ops->ooblen;
2939 chip->select_chip(mtd, -1);
2944 * panic_nand_write - [MTD Interface] NAND write with ECC
2945 * @mtd: MTD device structure
2946 * @to: offset to write to
2947 * @len: number of bytes to write
2948 * @retlen: pointer to variable to store the number of written bytes
2949 * @buf: the data to write
2951 * NAND write with ECC. Used when performing writes in interrupt context, this
2952 * may for example be called by mtdoops when writing an oops while in panic.
2954 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2955 size_t *retlen, const uint8_t *buf)
2957 struct nand_chip *chip = mtd_to_nand(mtd);
2958 struct mtd_oob_ops ops;
2961 /* Wait for the device to get ready */
2962 panic_nand_wait(mtd, chip, 400);
2964 /* Grab the device */
2965 panic_nand_get_device(chip, mtd, FL_WRITING);
2967 memset(&ops, 0, sizeof(ops));
2969 ops.datbuf = (uint8_t *)buf;
2970 ops.mode = MTD_OPS_PLACE_OOB;
2972 ret = nand_do_write_ops(mtd, to, &ops);
2974 *retlen = ops.retlen;
2979 * nand_write - [MTD Interface] NAND write with ECC
2980 * @mtd: MTD device structure
2981 * @to: offset to write to
2982 * @len: number of bytes to write
2983 * @retlen: pointer to variable to store the number of written bytes
2984 * @buf: the data to write
2986 * NAND write with ECC.
2988 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2989 size_t *retlen, const uint8_t *buf)
2991 struct mtd_oob_ops ops;
2994 nand_get_device(mtd, FL_WRITING);
2995 memset(&ops, 0, sizeof(ops));
2997 ops.datbuf = (uint8_t *)buf;
2998 ops.mode = MTD_OPS_PLACE_OOB;
2999 ret = nand_do_write_ops(mtd, to, &ops);
3000 *retlen = ops.retlen;
3001 nand_release_device(mtd);
3006 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
3007 * @mtd: MTD device structure
3008 * @to: offset to write to
3009 * @ops: oob operation description structure
3011 * NAND write out-of-band.
3013 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
3014 struct mtd_oob_ops *ops)
3016 int chipnr, page, status, len;
3017 struct nand_chip *chip = mtd_to_nand(mtd);
3019 pr_debug("%s: to = 0x%08x, len = %i\n",
3020 __func__, (unsigned int)to, (int)ops->ooblen);
3022 len = mtd_oobavail(mtd, ops);
3024 /* Do not allow write past end of page */
3025 if ((ops->ooboffs + ops->ooblen) > len) {
3026 pr_debug("%s: attempt to write past end of page\n",
3031 if (unlikely(ops->ooboffs >= len)) {
3032 pr_debug("%s: attempt to start write outside oob\n",
3037 /* Do not allow write past end of device */
3038 if (unlikely(to >= mtd->size ||
3039 ops->ooboffs + ops->ooblen >
3040 ((mtd->size >> chip->page_shift) -
3041 (to >> chip->page_shift)) * len)) {
3042 pr_debug("%s: attempt to write beyond end of device\n",
3047 chipnr = (int)(to >> chip->chip_shift);
3050 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
3051 * of my DiskOnChip 2000 test units) will clear the whole data page too
3052 * if we don't do this. I have no clue why, but I seem to have 'fixed'
3053 * it in the doc2000 driver in August 1999. dwmw2.
3055 nand_reset(chip, chipnr);
3057 chip->select_chip(mtd, chipnr);
3059 /* Shift to get page */
3060 page = (int)(to >> chip->page_shift);
3062 /* Check, if it is write protected */
3063 if (nand_check_wp(mtd)) {
3064 chip->select_chip(mtd, -1);
3068 /* Invalidate the page cache, if we write to the cached page */
3069 if (page == chip->pagebuf)
3072 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
3074 if (ops->mode == MTD_OPS_RAW)
3075 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
3077 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
3079 chip->select_chip(mtd, -1);
3084 ops->oobretlen = ops->ooblen;
3090 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
3091 * @mtd: MTD device structure
3092 * @to: offset to write to
3093 * @ops: oob operation description structure
3095 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
3096 struct mtd_oob_ops *ops)
3098 int ret = -ENOTSUPP;
3102 /* Do not allow writes past end of device */
3103 if (ops->datbuf && (to + ops->len) > mtd->size) {
3104 pr_debug("%s: attempt to write beyond end of device\n",
3109 nand_get_device(mtd, FL_WRITING);
3111 switch (ops->mode) {
3112 case MTD_OPS_PLACE_OOB:
3113 case MTD_OPS_AUTO_OOB:
3122 ret = nand_do_write_oob(mtd, to, ops);
3124 ret = nand_do_write_ops(mtd, to, ops);
3127 nand_release_device(mtd);
3132 * single_erase - [GENERIC] NAND standard block erase command function
3133 * @mtd: MTD device structure
3134 * @page: the page address of the block which will be erased
3136 * Standard erase command for NAND chips. Returns NAND status.
3138 static int single_erase(struct mtd_info *mtd, int page)
3140 struct nand_chip *chip = mtd_to_nand(mtd);
3141 /* Send commands to erase a block */
3142 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
3143 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
3145 return chip->waitfunc(mtd, chip);
3149 * nand_erase - [MTD Interface] erase block(s)
3150 * @mtd: MTD device structure
3151 * @instr: erase instruction
3153 * Erase one ore more blocks.
3155 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
3157 return nand_erase_nand(mtd, instr, 0);
3161 * nand_erase_nand - [INTERN] erase block(s)
3162 * @mtd: MTD device structure
3163 * @instr: erase instruction
3164 * @allowbbt: allow erasing the bbt area
3166 * Erase one ore more blocks.
3168 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
3171 int page, status, pages_per_block, ret, chipnr;
3172 struct nand_chip *chip = mtd_to_nand(mtd);
3175 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3176 __func__, (unsigned long long)instr->addr,
3177 (unsigned long long)instr->len);
3179 if (check_offs_len(mtd, instr->addr, instr->len))
3182 /* Grab the lock and see if the device is available */
3183 nand_get_device(mtd, FL_ERASING);
3185 /* Shift to get first page */
3186 page = (int)(instr->addr >> chip->page_shift);
3187 chipnr = (int)(instr->addr >> chip->chip_shift);
3189 /* Calculate pages in each block */
3190 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3192 /* Select the NAND device */
3193 chip->select_chip(mtd, chipnr);
3195 /* Check, if it is write protected */
3196 if (nand_check_wp(mtd)) {
3197 pr_debug("%s: device is write protected!\n",
3199 instr->state = MTD_ERASE_FAILED;
3203 /* Loop through the pages */
3206 instr->state = MTD_ERASING;
3209 /* Check if we have a bad block, we do not erase bad blocks! */
3210 if (nand_block_checkbad(mtd, ((loff_t) page) <<
3211 chip->page_shift, allowbbt)) {
3212 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3214 instr->state = MTD_ERASE_FAILED;
3219 * Invalidate the page cache, if we erase the block which
3220 * contains the current cached page.
3222 if (page <= chip->pagebuf && chip->pagebuf <
3223 (page + pages_per_block))
3226 status = chip->erase(mtd, page & chip->pagemask);
3229 * See if operation failed and additional status checks are
3232 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
3233 status = chip->errstat(mtd, chip, FL_ERASING,
3236 /* See if block erase succeeded */
3237 if (status & NAND_STATUS_FAIL) {
3238 pr_debug("%s: failed erase, page 0x%08x\n",
3240 instr->state = MTD_ERASE_FAILED;
3242 ((loff_t)page << chip->page_shift);
3246 /* Increment page address and decrement length */
3247 len -= (1ULL << chip->phys_erase_shift);
3248 page += pages_per_block;
3250 /* Check, if we cross a chip boundary */
3251 if (len && !(page & chip->pagemask)) {
3253 chip->select_chip(mtd, -1);
3254 chip->select_chip(mtd, chipnr);
3257 instr->state = MTD_ERASE_DONE;
3261 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
3263 /* Deselect and wake up anyone waiting on the device */
3264 chip->select_chip(mtd, -1);
3265 nand_release_device(mtd);
3267 /* Do call back function */
3269 mtd_erase_callback(instr);
3271 /* Return more or less happy */
3276 * nand_sync - [MTD Interface] sync
3277 * @mtd: MTD device structure
3279 * Sync is actually a wait for chip ready function.
3281 static void nand_sync(struct mtd_info *mtd)
3283 pr_debug("%s: called\n", __func__);
3285 /* Grab the lock and see if the device is available */
3286 nand_get_device(mtd, FL_SYNCING);
3287 /* Release it and go back */
3288 nand_release_device(mtd);
3292 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3293 * @mtd: MTD device structure
3294 * @offs: offset relative to mtd start
3296 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
3298 struct nand_chip *chip = mtd_to_nand(mtd);
3299 int chipnr = (int)(offs >> chip->chip_shift);
3302 /* Select the NAND device */
3303 nand_get_device(mtd, FL_READING);
3304 chip->select_chip(mtd, chipnr);
3306 ret = nand_block_checkbad(mtd, offs, 0);
3308 chip->select_chip(mtd, -1);
3309 nand_release_device(mtd);
3315 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3316 * @mtd: MTD device structure
3317 * @ofs: offset relative to mtd start
3319 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3323 ret = nand_block_isbad(mtd, ofs);
3325 /* If it was bad already, return success and do nothing */
3331 return nand_block_markbad_lowlevel(mtd, ofs);
3335 * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd
3336 * @mtd: MTD device structure
3337 * @ofs: offset relative to mtd start
3338 * @len: length of mtd
3340 static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
3342 struct nand_chip *chip = mtd_to_nand(mtd);
3343 u32 part_start_block;
3349 * max_bb_per_die and blocks_per_die used to determine
3350 * the maximum bad block count.
3352 if (!chip->max_bb_per_die || !chip->blocks_per_die)
3355 /* Get the start and end of the partition in erase blocks. */
3356 part_start_block = mtd_div_by_eb(ofs, mtd);
3357 part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1;
3359 /* Get the start and end LUNs of the partition. */
3360 part_start_die = part_start_block / chip->blocks_per_die;
3361 part_end_die = part_end_block / chip->blocks_per_die;
3364 * Look up the bad blocks per unit and multiply by the number of units
3365 * that the partition spans.
3367 return chip->max_bb_per_die * (part_end_die - part_start_die + 1);
3371 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3372 * @mtd: MTD device structure
3373 * @chip: nand chip info structure
3374 * @addr: feature address.
3375 * @subfeature_param: the subfeature parameters, a four bytes array.
3377 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3378 int addr, uint8_t *subfeature_param)
3383 if (!chip->onfi_version ||
3384 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3385 & ONFI_OPT_CMD_SET_GET_FEATURES))
3388 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3389 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3390 chip->write_byte(mtd, subfeature_param[i]);
3392 status = chip->waitfunc(mtd, chip);
3393 if (status & NAND_STATUS_FAIL)
3399 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3400 * @mtd: MTD device structure
3401 * @chip: nand chip info structure
3402 * @addr: feature address.
3403 * @subfeature_param: the subfeature parameters, a four bytes array.
3405 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3406 int addr, uint8_t *subfeature_param)
3410 if (!chip->onfi_version ||
3411 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3412 & ONFI_OPT_CMD_SET_GET_FEATURES))
3415 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3416 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3417 *subfeature_param++ = chip->read_byte(mtd);
3422 * nand_suspend - [MTD Interface] Suspend the NAND flash
3423 * @mtd: MTD device structure
3425 static int nand_suspend(struct mtd_info *mtd)
3427 return nand_get_device(mtd, FL_PM_SUSPENDED);
3431 * nand_resume - [MTD Interface] Resume the NAND flash
3432 * @mtd: MTD device structure
3434 static void nand_resume(struct mtd_info *mtd)
3436 struct nand_chip *chip = mtd_to_nand(mtd);
3438 if (chip->state == FL_PM_SUSPENDED)
3439 nand_release_device(mtd);
3441 pr_err("%s called for a chip which is not in suspended state\n",
3446 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3447 * prevent further operations
3448 * @mtd: MTD device structure
3450 static void nand_shutdown(struct mtd_info *mtd)
3452 nand_get_device(mtd, FL_PM_SUSPENDED);
3455 /* Set default functions */
3456 static void nand_set_defaults(struct nand_chip *chip)
3458 unsigned int busw = chip->options & NAND_BUSWIDTH_16;
3460 /* check for proper chip_delay setup, set 20us if not */
3461 if (!chip->chip_delay)
3462 chip->chip_delay = 20;
3464 /* check, if a user supplied command function given */
3465 if (chip->cmdfunc == NULL)
3466 chip->cmdfunc = nand_command;
3468 /* check, if a user supplied wait function given */
3469 if (chip->waitfunc == NULL)
3470 chip->waitfunc = nand_wait;
3472 if (!chip->select_chip)
3473 chip->select_chip = nand_select_chip;
3475 /* set for ONFI nand */
3476 if (!chip->onfi_set_features)
3477 chip->onfi_set_features = nand_onfi_set_features;
3478 if (!chip->onfi_get_features)
3479 chip->onfi_get_features = nand_onfi_get_features;
3481 /* If called twice, pointers that depend on busw may need to be reset */
3482 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3483 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3484 if (!chip->read_word)
3485 chip->read_word = nand_read_word;
3486 if (!chip->block_bad)
3487 chip->block_bad = nand_block_bad;
3488 if (!chip->block_markbad)
3489 chip->block_markbad = nand_default_block_markbad;
3490 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3491 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3492 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3493 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3494 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3495 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3496 if (!chip->scan_bbt)
3497 chip->scan_bbt = nand_default_bbt;
3499 if (!chip->controller) {
3500 chip->controller = &chip->hwcontrol;
3501 nand_hw_control_init(chip->controller);
3504 if (!chip->buf_align)
3505 chip->buf_align = 1;
3508 /* Sanitize ONFI strings so we can safely print them */
3509 static void sanitize_string(uint8_t *s, size_t len)
3513 /* Null terminate */
3516 /* Remove non printable chars */
3517 for (i = 0; i < len - 1; i++) {
3518 if (s[i] < ' ' || s[i] > 127)
3522 /* Remove trailing spaces */
3526 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3531 for (i = 0; i < 8; i++)
3532 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3538 /* Parse the Extended Parameter Page. */
3539 static int nand_flash_detect_ext_param_page(struct nand_chip *chip,
3540 struct nand_onfi_params *p)
3542 struct mtd_info *mtd = nand_to_mtd(chip);
3543 struct onfi_ext_param_page *ep;
3544 struct onfi_ext_section *s;
3545 struct onfi_ext_ecc_info *ecc;
3551 len = le16_to_cpu(p->ext_param_page_length) * 16;
3552 ep = kmalloc(len, GFP_KERNEL);
3556 /* Send our own NAND_CMD_PARAM. */
3557 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3559 /* Use the Change Read Column command to skip the ONFI param pages. */
3560 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3561 sizeof(*p) * p->num_of_param_pages , -1);
3563 /* Read out the Extended Parameter Page. */
3564 chip->read_buf(mtd, (uint8_t *)ep, len);
3565 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3566 != le16_to_cpu(ep->crc))) {
3567 pr_debug("fail in the CRC.\n");
3572 * Check the signature.
3573 * Do not strictly follow the ONFI spec, maybe changed in future.
3575 if (strncmp(ep->sig, "EPPS", 4)) {
3576 pr_debug("The signature is invalid.\n");
3580 /* find the ECC section. */
3581 cursor = (uint8_t *)(ep + 1);
3582 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3583 s = ep->sections + i;
3584 if (s->type == ONFI_SECTION_TYPE_2)
3586 cursor += s->length * 16;
3588 if (i == ONFI_EXT_SECTION_MAX) {
3589 pr_debug("We can not find the ECC section.\n");
3593 /* get the info we want. */
3594 ecc = (struct onfi_ext_ecc_info *)cursor;
3596 if (!ecc->codeword_size) {
3597 pr_debug("Invalid codeword size\n");
3601 chip->ecc_strength_ds = ecc->ecc_bits;
3602 chip->ecc_step_ds = 1 << ecc->codeword_size;
3611 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3613 static int nand_flash_detect_onfi(struct nand_chip *chip)
3615 struct mtd_info *mtd = nand_to_mtd(chip);
3616 struct nand_onfi_params *p = &chip->onfi_params;
3620 /* Try ONFI for unknown chip or LP */
3621 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3622 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3623 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3626 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3627 for (i = 0; i < 3; i++) {
3628 for (j = 0; j < sizeof(*p); j++)
3629 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3630 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3631 le16_to_cpu(p->crc)) {
3637 pr_err("Could not find valid ONFI parameter page; aborting\n");
3642 val = le16_to_cpu(p->revision);
3644 chip->onfi_version = 23;
3645 else if (val & (1 << 4))
3646 chip->onfi_version = 22;
3647 else if (val & (1 << 3))
3648 chip->onfi_version = 21;
3649 else if (val & (1 << 2))
3650 chip->onfi_version = 20;
3651 else if (val & (1 << 1))
3652 chip->onfi_version = 10;
3654 if (!chip->onfi_version) {
3655 pr_info("unsupported ONFI version: %d\n", val);
3659 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3660 sanitize_string(p->model, sizeof(p->model));
3662 mtd->name = p->model;
3664 mtd->writesize = le32_to_cpu(p->byte_per_page);
3667 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3668 * (don't ask me who thought of this...). MTD assumes that these
3669 * dimensions will be power-of-2, so just truncate the remaining area.
3671 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3672 mtd->erasesize *= mtd->writesize;
3674 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3676 /* See erasesize comment */
3677 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3678 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3679 chip->bits_per_cell = p->bits_per_cell;
3681 chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun);
3682 chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun);
3684 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3685 chip->options |= NAND_BUSWIDTH_16;
3687 if (p->ecc_bits != 0xff) {
3688 chip->ecc_strength_ds = p->ecc_bits;
3689 chip->ecc_step_ds = 512;
3690 } else if (chip->onfi_version >= 21 &&
3691 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3694 * The nand_flash_detect_ext_param_page() uses the
3695 * Change Read Column command which maybe not supported
3696 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3697 * now. We do not replace user supplied command function.
3699 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3700 chip->cmdfunc = nand_command_lp;
3702 /* The Extended Parameter Page is supported since ONFI 2.1. */
3703 if (nand_flash_detect_ext_param_page(chip, p))
3704 pr_warn("Failed to detect ONFI extended param page\n");
3706 pr_warn("Could not retrieve ONFI ECC requirements\n");
3713 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3715 static int nand_flash_detect_jedec(struct nand_chip *chip)
3717 struct mtd_info *mtd = nand_to_mtd(chip);
3718 struct nand_jedec_params *p = &chip->jedec_params;
3719 struct jedec_ecc_info *ecc;
3723 /* Try JEDEC for unknown chip or LP */
3724 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3725 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3726 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3727 chip->read_byte(mtd) != 'C')
3730 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3731 for (i = 0; i < 3; i++) {
3732 for (j = 0; j < sizeof(*p); j++)
3733 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3735 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3736 le16_to_cpu(p->crc))
3741 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3746 val = le16_to_cpu(p->revision);
3748 chip->jedec_version = 10;
3749 else if (val & (1 << 1))
3750 chip->jedec_version = 1; /* vendor specific version */
3752 if (!chip->jedec_version) {
3753 pr_info("unsupported JEDEC version: %d\n", val);
3757 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3758 sanitize_string(p->model, sizeof(p->model));
3760 mtd->name = p->model;
3762 mtd->writesize = le32_to_cpu(p->byte_per_page);
3764 /* Please reference to the comment for nand_flash_detect_onfi. */
3765 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3766 mtd->erasesize *= mtd->writesize;
3768 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3770 /* Please reference to the comment for nand_flash_detect_onfi. */
3771 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3772 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3773 chip->bits_per_cell = p->bits_per_cell;
3775 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3776 chip->options |= NAND_BUSWIDTH_16;
3779 ecc = &p->ecc_info[0];
3781 if (ecc->codeword_size >= 9) {
3782 chip->ecc_strength_ds = ecc->ecc_bits;
3783 chip->ecc_step_ds = 1 << ecc->codeword_size;
3785 pr_warn("Invalid codeword size\n");
3792 * nand_id_has_period - Check if an ID string has a given wraparound period
3793 * @id_data: the ID string
3794 * @arrlen: the length of the @id_data array
3795 * @period: the period of repitition
3797 * Check if an ID string is repeated within a given sequence of bytes at
3798 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3799 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3800 * if the repetition has a period of @period; otherwise, returns zero.
3802 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3805 for (i = 0; i < period; i++)
3806 for (j = i + period; j < arrlen; j += period)
3807 if (id_data[i] != id_data[j])
3813 * nand_id_len - Get the length of an ID string returned by CMD_READID
3814 * @id_data: the ID string
3815 * @arrlen: the length of the @id_data array
3817 * Returns the length of the ID string, according to known wraparound/trailing
3818 * zero patterns. If no pattern exists, returns the length of the array.
3820 static int nand_id_len(u8 *id_data, int arrlen)
3822 int last_nonzero, period;
3824 /* Find last non-zero byte */
3825 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3826 if (id_data[last_nonzero])
3830 if (last_nonzero < 0)
3833 /* Calculate wraparound period */
3834 for (period = 1; period < arrlen; period++)
3835 if (nand_id_has_period(id_data, arrlen, period))
3838 /* There's a repeated pattern */
3839 if (period < arrlen)
3842 /* There are trailing zeros */
3843 if (last_nonzero < arrlen - 1)
3844 return last_nonzero + 1;
3846 /* No pattern detected */
3850 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3851 static int nand_get_bits_per_cell(u8 cellinfo)
3855 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3856 bits >>= NAND_CI_CELLTYPE_SHIFT;
3861 * Many new NAND share similar device ID codes, which represent the size of the
3862 * chip. The rest of the parameters must be decoded according to generic or
3863 * manufacturer-specific "extended ID" decoding patterns.
3865 void nand_decode_ext_id(struct nand_chip *chip)
3867 struct mtd_info *mtd = nand_to_mtd(chip);
3869 u8 *id_data = chip->id.data;
3870 /* The 3rd id byte holds MLC / multichip data */
3871 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3872 /* The 4th id byte is the important one */
3876 mtd->writesize = 1024 << (extid & 0x03);
3879 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
3881 /* Calc blocksize. Blocksize is multiples of 64KiB */
3882 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3884 /* Get buswidth information */
3886 chip->options |= NAND_BUSWIDTH_16;
3888 EXPORT_SYMBOL_GPL(nand_decode_ext_id);
3891 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3892 * decodes a matching ID table entry and assigns the MTD size parameters for
3895 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
3897 struct mtd_info *mtd = nand_to_mtd(chip);
3899 mtd->erasesize = type->erasesize;
3900 mtd->writesize = type->pagesize;
3901 mtd->oobsize = mtd->writesize / 32;
3903 /* All legacy ID NAND are small-page, SLC */
3904 chip->bits_per_cell = 1;
3908 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3909 * heuristic patterns using various detected parameters (e.g., manufacturer,
3910 * page size, cell-type information).
3912 static void nand_decode_bbm_options(struct nand_chip *chip)
3914 struct mtd_info *mtd = nand_to_mtd(chip);
3916 /* Set the bad block position */
3917 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3918 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3920 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3923 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3925 return type->id_len;
3928 static bool find_full_id_nand(struct nand_chip *chip,
3929 struct nand_flash_dev *type)
3931 struct mtd_info *mtd = nand_to_mtd(chip);
3932 u8 *id_data = chip->id.data;
3934 if (!strncmp(type->id, id_data, type->id_len)) {
3935 mtd->writesize = type->pagesize;
3936 mtd->erasesize = type->erasesize;
3937 mtd->oobsize = type->oobsize;
3939 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3940 chip->chipsize = (uint64_t)type->chipsize << 20;
3941 chip->options |= type->options;
3942 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3943 chip->ecc_step_ds = NAND_ECC_STEP(type);
3944 chip->onfi_timing_mode_default =
3945 type->onfi_timing_mode_default;
3948 mtd->name = type->name;
3956 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
3957 * compliant and does not have a full-id or legacy-id entry in the nand_ids
3960 static void nand_manufacturer_detect(struct nand_chip *chip)
3963 * Try manufacturer detection if available and use
3964 * nand_decode_ext_id() otherwise.
3966 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
3967 chip->manufacturer.desc->ops->detect)
3968 chip->manufacturer.desc->ops->detect(chip);
3970 nand_decode_ext_id(chip);
3974 * Manufacturer initialization. This function is called for all NANDs including
3975 * ONFI and JEDEC compliant ones.
3976 * Manufacturer drivers should put all their specific initialization code in
3977 * their ->init() hook.
3979 static int nand_manufacturer_init(struct nand_chip *chip)
3981 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
3982 !chip->manufacturer.desc->ops->init)
3985 return chip->manufacturer.desc->ops->init(chip);
3989 * Manufacturer cleanup. This function is called for all NANDs including
3990 * ONFI and JEDEC compliant ones.
3991 * Manufacturer drivers should put all their specific cleanup code in their
3994 static void nand_manufacturer_cleanup(struct nand_chip *chip)
3996 /* Release manufacturer private data */
3997 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
3998 chip->manufacturer.desc->ops->cleanup)
3999 chip->manufacturer.desc->ops->cleanup(chip);
4003 * Get the flash and manufacturer id and lookup if the type is supported.
4005 static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
4007 const struct nand_manufacturer *manufacturer;
4008 struct mtd_info *mtd = nand_to_mtd(chip);
4011 u8 *id_data = chip->id.data;
4015 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
4018 nand_reset(chip, 0);
4020 /* Select the device */
4021 chip->select_chip(mtd, 0);
4023 /* Send the command for reading device ID */
4024 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4026 /* Read manufacturer and device IDs */
4027 maf_id = chip->read_byte(mtd);
4028 dev_id = chip->read_byte(mtd);
4031 * Try again to make sure, as some systems the bus-hold or other
4032 * interface concerns can cause random data which looks like a
4033 * possibly credible NAND flash to appear. If the two results do
4034 * not match, ignore the device completely.
4037 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4039 /* Read entire ID string */
4040 for (i = 0; i < 8; i++)
4041 id_data[i] = chip->read_byte(mtd);
4043 if (id_data[0] != maf_id || id_data[1] != dev_id) {
4044 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4045 maf_id, dev_id, id_data[0], id_data[1]);
4049 chip->id.len = nand_id_len(id_data, 8);
4051 /* Try to identify manufacturer */
4052 manufacturer = nand_get_manufacturer(maf_id);
4053 chip->manufacturer.desc = manufacturer;
4056 type = nand_flash_ids;
4059 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
4061 * This is required to make sure initial NAND bus width set by the
4062 * NAND controller driver is coherent with the real NAND bus width
4063 * (extracted by auto-detection code).
4065 busw = chip->options & NAND_BUSWIDTH_16;
4068 * The flag is only set (never cleared), reset it to its default value
4069 * before starting auto-detection.
4071 chip->options &= ~NAND_BUSWIDTH_16;
4073 for (; type->name != NULL; type++) {
4074 if (is_full_id_nand(type)) {
4075 if (find_full_id_nand(chip, type))
4077 } else if (dev_id == type->dev_id) {
4082 chip->onfi_version = 0;
4083 if (!type->name || !type->pagesize) {
4084 /* Check if the chip is ONFI compliant */
4085 if (nand_flash_detect_onfi(chip))
4088 /* Check if the chip is JEDEC compliant */
4089 if (nand_flash_detect_jedec(chip))
4097 mtd->name = type->name;
4099 chip->chipsize = (uint64_t)type->chipsize << 20;
4101 if (!type->pagesize)
4102 nand_manufacturer_detect(chip);
4104 nand_decode_id(chip, type);
4106 /* Get chip options */
4107 chip->options |= type->options;
4111 if (chip->options & NAND_BUSWIDTH_AUTO) {
4112 WARN_ON(busw & NAND_BUSWIDTH_16);
4113 nand_set_defaults(chip);
4114 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
4116 * Check, if buswidth is correct. Hardware drivers should set
4119 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4121 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4123 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
4124 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
4128 nand_decode_bbm_options(chip);
4130 /* Calculate the address shift from the page size */
4131 chip->page_shift = ffs(mtd->writesize) - 1;
4132 /* Convert chipsize to number of pages per chip -1 */
4133 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
4135 chip->bbt_erase_shift = chip->phys_erase_shift =
4136 ffs(mtd->erasesize) - 1;
4137 if (chip->chipsize & 0xffffffff)
4138 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
4140 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4141 chip->chip_shift += 32 - 1;
4144 chip->badblockbits = 8;
4145 chip->erase = single_erase;
4147 /* Do not replace user supplied command function! */
4148 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4149 chip->cmdfunc = nand_command_lp;
4151 ret = nand_manufacturer_init(chip);
4155 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4158 if (chip->onfi_version)
4159 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4160 chip->onfi_params.model);
4161 else if (chip->jedec_version)
4162 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4163 chip->jedec_params.model);
4165 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4168 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4169 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
4170 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4174 static const char * const nand_ecc_modes[] = {
4175 [NAND_ECC_NONE] = "none",
4176 [NAND_ECC_SOFT] = "soft",
4177 [NAND_ECC_HW] = "hw",
4178 [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
4179 [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
4182 static int of_get_nand_ecc_mode(struct device_node *np)
4187 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4191 for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
4192 if (!strcasecmp(pm, nand_ecc_modes[i]))
4196 * For backward compatibility we support few obsoleted values that don't
4197 * have their mappings into nand_ecc_modes_t anymore (they were merged
4198 * with other enums).
4200 if (!strcasecmp(pm, "soft_bch"))
4201 return NAND_ECC_SOFT;
4206 static const char * const nand_ecc_algos[] = {
4207 [NAND_ECC_HAMMING] = "hamming",
4208 [NAND_ECC_BCH] = "bch",
4211 static int of_get_nand_ecc_algo(struct device_node *np)
4216 err = of_property_read_string(np, "nand-ecc-algo", &pm);
4218 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
4219 if (!strcasecmp(pm, nand_ecc_algos[i]))
4225 * For backward compatibility we also read "nand-ecc-mode" checking
4226 * for some obsoleted values that were specifying ECC algorithm.
4228 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4232 if (!strcasecmp(pm, "soft"))
4233 return NAND_ECC_HAMMING;
4234 else if (!strcasecmp(pm, "soft_bch"))
4235 return NAND_ECC_BCH;
4240 static int of_get_nand_ecc_step_size(struct device_node *np)
4245 ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
4246 return ret ? ret : val;
4249 static int of_get_nand_ecc_strength(struct device_node *np)
4254 ret = of_property_read_u32(np, "nand-ecc-strength", &val);
4255 return ret ? ret : val;
4258 static int of_get_nand_bus_width(struct device_node *np)
4262 if (of_property_read_u32(np, "nand-bus-width", &val))
4274 static bool of_get_nand_on_flash_bbt(struct device_node *np)
4276 return of_property_read_bool(np, "nand-on-flash-bbt");
4279 static int nand_dt_init(struct nand_chip *chip)
4281 struct device_node *dn = nand_get_flash_node(chip);
4282 int ecc_mode, ecc_algo, ecc_strength, ecc_step;
4287 if (of_get_nand_bus_width(dn) == 16)
4288 chip->options |= NAND_BUSWIDTH_16;
4290 if (of_get_nand_on_flash_bbt(dn))
4291 chip->bbt_options |= NAND_BBT_USE_FLASH;
4293 ecc_mode = of_get_nand_ecc_mode(dn);
4294 ecc_algo = of_get_nand_ecc_algo(dn);
4295 ecc_strength = of_get_nand_ecc_strength(dn);
4296 ecc_step = of_get_nand_ecc_step_size(dn);
4299 chip->ecc.mode = ecc_mode;
4302 chip->ecc.algo = ecc_algo;
4304 if (ecc_strength >= 0)
4305 chip->ecc.strength = ecc_strength;
4308 chip->ecc.size = ecc_step;
4310 if (of_property_read_bool(dn, "nand-ecc-maximize"))
4311 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4317 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4318 * @mtd: MTD device structure
4319 * @maxchips: number of chips to scan for
4320 * @table: alternative NAND ID table
4322 * This is the first phase of the normal nand_scan() function. It reads the
4323 * flash ID and sets up MTD fields accordingly.
4326 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4327 struct nand_flash_dev *table)
4329 int i, nand_maf_id, nand_dev_id;
4330 struct nand_chip *chip = mtd_to_nand(mtd);
4333 ret = nand_dt_init(chip);
4337 if (!mtd->name && mtd->dev.parent)
4338 mtd->name = dev_name(mtd->dev.parent);
4340 if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
4342 * Default functions assigned for chip_select() and
4343 * cmdfunc() both expect cmd_ctrl() to be populated,
4344 * so we need to check that that's the case
4346 pr_err("chip.cmd_ctrl() callback is not provided");
4349 /* Set the default functions */
4350 nand_set_defaults(chip);
4352 /* Read the flash type */
4353 ret = nand_detect(chip, table);
4355 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4356 pr_warn("No NAND device found\n");
4357 chip->select_chip(mtd, -1);
4361 /* Initialize the ->data_interface field. */
4362 ret = nand_init_data_interface(chip);
4367 * Setup the data interface correctly on the chip and controller side.
4368 * This explicit call to nand_setup_data_interface() is only required
4369 * for the first die, because nand_reset() has been called before
4370 * ->data_interface and ->default_onfi_timing_mode were set.
4371 * For the other dies, nand_reset() will automatically switch to the
4374 ret = nand_setup_data_interface(chip);
4378 nand_maf_id = chip->id.data[0];
4379 nand_dev_id = chip->id.data[1];
4381 chip->select_chip(mtd, -1);
4383 /* Check for a chip array */
4384 for (i = 1; i < maxchips; i++) {
4385 /* See comment in nand_get_flash_type for reset */
4386 nand_reset(chip, i);
4388 chip->select_chip(mtd, i);
4389 /* Send the command for reading device ID */
4390 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4391 /* Read manufacturer and device IDs */
4392 if (nand_maf_id != chip->read_byte(mtd) ||
4393 nand_dev_id != chip->read_byte(mtd)) {
4394 chip->select_chip(mtd, -1);
4397 chip->select_chip(mtd, -1);
4400 pr_info("%d chips detected\n", i);
4402 /* Store the number of chips and calc total size for mtd */
4404 mtd->size = i * chip->chipsize;
4408 EXPORT_SYMBOL(nand_scan_ident);
4410 static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
4412 struct nand_chip *chip = mtd_to_nand(mtd);
4413 struct nand_ecc_ctrl *ecc = &chip->ecc;
4415 if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
4418 switch (ecc->algo) {
4419 case NAND_ECC_HAMMING:
4420 ecc->calculate = nand_calculate_ecc;
4421 ecc->correct = nand_correct_data;
4422 ecc->read_page = nand_read_page_swecc;
4423 ecc->read_subpage = nand_read_subpage;
4424 ecc->write_page = nand_write_page_swecc;
4425 ecc->read_page_raw = nand_read_page_raw;
4426 ecc->write_page_raw = nand_write_page_raw;
4427 ecc->read_oob = nand_read_oob_std;
4428 ecc->write_oob = nand_write_oob_std;
4435 if (!mtd_nand_has_bch()) {
4436 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4439 ecc->calculate = nand_bch_calculate_ecc;
4440 ecc->correct = nand_bch_correct_data;
4441 ecc->read_page = nand_read_page_swecc;
4442 ecc->read_subpage = nand_read_subpage;
4443 ecc->write_page = nand_write_page_swecc;
4444 ecc->read_page_raw = nand_read_page_raw;
4445 ecc->write_page_raw = nand_write_page_raw;
4446 ecc->read_oob = nand_read_oob_std;
4447 ecc->write_oob = nand_write_oob_std;
4450 * Board driver should supply ecc.size and ecc.strength
4451 * values to select how many bits are correctable.
4452 * Otherwise, default to 4 bits for large page devices.
4454 if (!ecc->size && (mtd->oobsize >= 64)) {
4460 * if no ecc placement scheme was provided pickup the default
4463 if (!mtd->ooblayout) {
4464 /* handle large page devices only */
4465 if (mtd->oobsize < 64) {
4466 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4470 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
4475 * We can only maximize ECC config when the default layout is
4476 * used, otherwise we don't know how many bytes can really be
4479 if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
4480 ecc->options & NAND_ECC_MAXIMIZE) {
4483 /* Always prefer 1k blocks over 512bytes ones */
4485 steps = mtd->writesize / ecc->size;
4487 /* Reserve 2 bytes for the BBM */
4488 bytes = (mtd->oobsize - 2) / steps;
4489 ecc->strength = bytes * 8 / fls(8 * ecc->size);
4492 /* See nand_bch_init() for details. */
4494 ecc->priv = nand_bch_init(mtd);
4496 WARN(1, "BCH ECC initialization failed!\n");
4501 WARN(1, "Unsupported ECC algorithm!\n");
4507 * Check if the chip configuration meet the datasheet requirements.
4509 * If our configuration corrects A bits per B bytes and the minimum
4510 * required correction level is X bits per Y bytes, then we must ensure
4511 * both of the following are true:
4513 * (1) A / B >= X / Y
4516 * Requirement (1) ensures we can correct for the required bitflip density.
4517 * Requirement (2) ensures we can correct even when all bitflips are clumped
4518 * in the same sector.
4520 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4522 struct nand_chip *chip = mtd_to_nand(mtd);
4523 struct nand_ecc_ctrl *ecc = &chip->ecc;
4526 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4527 /* Not enough information */
4531 * We get the number of corrected bits per page to compare
4532 * the correction density.
4534 corr = (mtd->writesize * ecc->strength) / ecc->size;
4535 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4537 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4540 static bool invalid_ecc_page_accessors(struct nand_chip *chip)
4542 struct nand_ecc_ctrl *ecc = &chip->ecc;
4544 if (nand_standard_page_accessors(ecc))
4548 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4549 * controller driver implements all the page accessors because
4550 * default helpers are not suitable when the core does not
4551 * send the READ0/PAGEPROG commands.
4553 return (!ecc->read_page || !ecc->write_page ||
4554 !ecc->read_page_raw || !ecc->write_page_raw ||
4555 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
4556 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
4557 ecc->hwctl && ecc->calculate));
4561 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4562 * @mtd: MTD device structure
4564 * This is the second phase of the normal nand_scan() function. It fills out
4565 * all the uninitialized function pointers with the defaults and scans for a
4566 * bad block table if appropriate.
4568 int nand_scan_tail(struct mtd_info *mtd)
4570 struct nand_chip *chip = mtd_to_nand(mtd);
4571 struct nand_ecc_ctrl *ecc = &chip->ecc;
4572 struct nand_buffers *nbuf = NULL;
4575 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4576 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4577 !(chip->bbt_options & NAND_BBT_USE_FLASH)))
4580 if (invalid_ecc_page_accessors(chip)) {
4581 pr_err("Invalid ECC page accessors setup\n");
4585 if (!(chip->options & NAND_OWN_BUFFERS)) {
4586 nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL);
4590 nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL);
4591 if (!nbuf->ecccalc) {
4596 nbuf->ecccode = kmalloc(mtd->oobsize, GFP_KERNEL);
4597 if (!nbuf->ecccode) {
4602 nbuf->databuf = kmalloc(mtd->writesize + mtd->oobsize,
4604 if (!nbuf->databuf) {
4609 chip->buffers = nbuf;
4615 /* Set the internal oob buffer location, just after the page data */
4616 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4619 * If no default placement scheme is given, select an appropriate one.
4621 if (!mtd->ooblayout &&
4622 !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
4623 switch (mtd->oobsize) {
4626 mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
4630 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
4633 WARN(1, "No oob scheme defined for oobsize %d\n",
4641 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4642 * selected and we have 256 byte pagesize fallback to software ECC
4645 switch (ecc->mode) {
4646 case NAND_ECC_HW_OOB_FIRST:
4647 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4648 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4649 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4653 if (!ecc->read_page)
4654 ecc->read_page = nand_read_page_hwecc_oob_first;
4657 /* Use standard hwecc read page function? */
4658 if (!ecc->read_page)
4659 ecc->read_page = nand_read_page_hwecc;
4660 if (!ecc->write_page)
4661 ecc->write_page = nand_write_page_hwecc;
4662 if (!ecc->read_page_raw)
4663 ecc->read_page_raw = nand_read_page_raw;
4664 if (!ecc->write_page_raw)
4665 ecc->write_page_raw = nand_write_page_raw;
4667 ecc->read_oob = nand_read_oob_std;
4668 if (!ecc->write_oob)
4669 ecc->write_oob = nand_write_oob_std;
4670 if (!ecc->read_subpage)
4671 ecc->read_subpage = nand_read_subpage;
4672 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
4673 ecc->write_subpage = nand_write_subpage_hwecc;
4675 case NAND_ECC_HW_SYNDROME:
4676 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4678 ecc->read_page == nand_read_page_hwecc ||
4680 ecc->write_page == nand_write_page_hwecc)) {
4681 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4685 /* Use standard syndrome read/write page function? */
4686 if (!ecc->read_page)
4687 ecc->read_page = nand_read_page_syndrome;
4688 if (!ecc->write_page)
4689 ecc->write_page = nand_write_page_syndrome;
4690 if (!ecc->read_page_raw)
4691 ecc->read_page_raw = nand_read_page_raw_syndrome;
4692 if (!ecc->write_page_raw)
4693 ecc->write_page_raw = nand_write_page_raw_syndrome;
4695 ecc->read_oob = nand_read_oob_syndrome;
4696 if (!ecc->write_oob)
4697 ecc->write_oob = nand_write_oob_syndrome;
4699 if (mtd->writesize >= ecc->size) {
4700 if (!ecc->strength) {
4701 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4707 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4708 ecc->size, mtd->writesize);
4709 ecc->mode = NAND_ECC_SOFT;
4710 ecc->algo = NAND_ECC_HAMMING;
4713 ret = nand_set_ecc_soft_ops(mtd);
4721 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4722 ecc->read_page = nand_read_page_raw;
4723 ecc->write_page = nand_write_page_raw;
4724 ecc->read_oob = nand_read_oob_std;
4725 ecc->read_page_raw = nand_read_page_raw;
4726 ecc->write_page_raw = nand_write_page_raw;
4727 ecc->write_oob = nand_write_oob_std;
4728 ecc->size = mtd->writesize;
4734 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
4739 /* For many systems, the standard OOB write also works for raw */
4740 if (!ecc->read_oob_raw)
4741 ecc->read_oob_raw = ecc->read_oob;
4742 if (!ecc->write_oob_raw)
4743 ecc->write_oob_raw = ecc->write_oob;
4745 /* propagate ecc info to mtd_info */
4746 mtd->ecc_strength = ecc->strength;
4747 mtd->ecc_step_size = ecc->size;
4750 * Set the number of read / write steps for one page depending on ECC
4753 ecc->steps = mtd->writesize / ecc->size;
4754 if (ecc->steps * ecc->size != mtd->writesize) {
4755 WARN(1, "Invalid ECC parameters\n");
4759 ecc->total = ecc->steps * ecc->bytes;
4762 * The number of bytes available for a client to place data into
4763 * the out of band area.
4765 ret = mtd_ooblayout_count_freebytes(mtd);
4769 mtd->oobavail = ret;
4771 /* ECC sanity check: warn if it's too weak */
4772 if (!nand_ecc_strength_good(mtd))
4773 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4776 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4777 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4778 switch (ecc->steps) {
4780 mtd->subpage_sft = 1;
4785 mtd->subpage_sft = 2;
4789 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4791 /* Initialize state */
4792 chip->state = FL_READY;
4794 /* Invalidate the pagebuffer reference */
4797 /* Large page NAND with SOFT_ECC should support subpage reads */
4798 switch (ecc->mode) {
4800 if (chip->page_shift > 9)
4801 chip->options |= NAND_SUBPAGE_READ;
4808 /* Fill in remaining MTD driver data */
4809 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4810 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4812 mtd->_erase = nand_erase;
4814 mtd->_unpoint = NULL;
4815 mtd->_read = nand_read;
4816 mtd->_write = nand_write;
4817 mtd->_panic_write = panic_nand_write;
4818 mtd->_read_oob = nand_read_oob;
4819 mtd->_write_oob = nand_write_oob;
4820 mtd->_sync = nand_sync;
4822 mtd->_unlock = NULL;
4823 mtd->_suspend = nand_suspend;
4824 mtd->_resume = nand_resume;
4825 mtd->_reboot = nand_shutdown;
4826 mtd->_block_isreserved = nand_block_isreserved;
4827 mtd->_block_isbad = nand_block_isbad;
4828 mtd->_block_markbad = nand_block_markbad;
4829 mtd->_max_bad_blocks = nand_max_bad_blocks;
4830 mtd->writebufsize = mtd->writesize;
4833 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4834 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4837 if (!mtd->bitflip_threshold)
4838 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4840 /* Check, if we should skip the bad block table scan */
4841 if (chip->options & NAND_SKIP_BBTSCAN)
4844 /* Build bad block table */
4845 return chip->scan_bbt(mtd);
4848 kfree(nbuf->databuf);
4849 kfree(nbuf->ecccode);
4850 kfree(nbuf->ecccalc);
4855 EXPORT_SYMBOL(nand_scan_tail);
4858 * is_module_text_address() isn't exported, and it's mostly a pointless
4859 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4860 * to call us from in-kernel code if the core NAND support is modular.
4863 #define caller_is_module() (1)
4865 #define caller_is_module() \
4866 is_module_text_address((unsigned long)__builtin_return_address(0))
4870 * nand_scan - [NAND Interface] Scan for the NAND device
4871 * @mtd: MTD device structure
4872 * @maxchips: number of chips to scan for
4874 * This fills out all the uninitialized function pointers with the defaults.
4875 * The flash ID is read and the mtd/chip structures are filled with the
4876 * appropriate values.
4878 int nand_scan(struct mtd_info *mtd, int maxchips)
4882 ret = nand_scan_ident(mtd, maxchips, NULL);
4884 ret = nand_scan_tail(mtd);
4887 EXPORT_SYMBOL(nand_scan);
4890 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
4891 * @chip: NAND chip object
4893 void nand_cleanup(struct nand_chip *chip)
4895 if (chip->ecc.mode == NAND_ECC_SOFT &&
4896 chip->ecc.algo == NAND_ECC_BCH)
4897 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4899 nand_release_data_interface(chip);
4901 /* Free bad block table memory */
4903 if (!(chip->options & NAND_OWN_BUFFERS) && chip->buffers) {
4904 kfree(chip->buffers->databuf);
4905 kfree(chip->buffers->ecccode);
4906 kfree(chip->buffers->ecccalc);
4907 kfree(chip->buffers);
4910 /* Free bad block descriptor memory */
4911 if (chip->badblock_pattern && chip->badblock_pattern->options
4912 & NAND_BBT_DYNAMICSTRUCT)
4913 kfree(chip->badblock_pattern);
4915 /* Free manufacturer priv data. */
4916 nand_manufacturer_cleanup(chip);
4918 EXPORT_SYMBOL_GPL(nand_cleanup);
4921 * nand_release - [NAND Interface] Unregister the MTD device and free resources
4922 * held by the NAND device
4923 * @mtd: MTD device structure
4925 void nand_release(struct mtd_info *mtd)
4927 mtd_device_unregister(mtd);
4928 nand_cleanup(mtd_to_nand(mtd));
4930 EXPORT_SYMBOL_GPL(nand_release);
4932 MODULE_LICENSE("GPL");
4933 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4934 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4935 MODULE_DESCRIPTION("Generic NAND flash driver code");