drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/sched.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #include <plat/dma.h>
  24 #include <plat/gpmc.h>
  25 #include <plat/nand.h>
  26
  27 #define DRIVER_NAME     "omap2-nand"
  28 #define OMAP_NAND_TIMEOUT_MS    5000
  29
  30 #define NAND_Ecc_P1e            (1 << 0)
  31 #define NAND_Ecc_P2e            (1 << 1)
  32 #define NAND_Ecc_P4e            (1 << 2)
  33 #define NAND_Ecc_P8e            (1 << 3)
  34 #define NAND_Ecc_P16e           (1 << 4)
  35 #define NAND_Ecc_P32e           (1 << 5)
  36 #define NAND_Ecc_P64e           (1 << 6)
  37 #define NAND_Ecc_P128e          (1 << 7)
  38 #define NAND_Ecc_P256e          (1 << 8)
  39 #define NAND_Ecc_P512e          (1 << 9)
  40 #define NAND_Ecc_P1024e         (1 << 10)
  41 #define NAND_Ecc_P2048e         (1 << 11)
  42
  43 #define NAND_Ecc_P1o            (1 << 16)
  44 #define NAND_Ecc_P2o            (1 << 17)
  45 #define NAND_Ecc_P4o            (1 << 18)
  46 #define NAND_Ecc_P8o            (1 << 19)
  47 #define NAND_Ecc_P16o           (1 << 20)
  48 #define NAND_Ecc_P32o           (1 << 21)
  49 #define NAND_Ecc_P64o           (1 << 22)
  50 #define NAND_Ecc_P128o          (1 << 23)
  51 #define NAND_Ecc_P256o          (1 << 24)
  52 #define NAND_Ecc_P512o          (1 << 25)
  53 #define NAND_Ecc_P1024o         (1 << 26)
  54 #define NAND_Ecc_P2048o         (1 << 27)
  55
  56 #define TF(value)       (value ? 1 : 0)
  57
  58 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  59 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  60 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  61 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  62 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  63 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  64 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  65 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  66
  67 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  68 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  69 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  70 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  71 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  72 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  73 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  74 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  75
  76 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  77 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  78 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  79 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  80 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  81 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  82 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  83 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  84
  85 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  86 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  87 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  88 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  89 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  90 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  91 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  92 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  93
  94 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
  95 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
  96
  97 #ifdef CONFIG_MTD_PARTITIONS
  98 static const char *part_probes[] = { "cmdlinepart", NULL };
  99 #endif
 100
 101 /* oob info generated runtime depending on ecc algorithm and layout selected */
 102 static struct nand_ecclayout omap_oobinfo;
 103 /* Define some generic bad / good block scan pattern which are used
 104  * while scanning a device for factory marked good / bad blocks
 105  */
 106 static uint8_t scan_ff_pattern[] = { 0xff };
 107 static struct nand_bbt_descr bb_descrip_flashbased = {
 108         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 109         .offs = 0,
 110         .len = 1,
 111         .pattern = scan_ff_pattern,
 112 };
 113
 114
 115 struct omap_nand_info {
 116         struct nand_hw_control          controller;
 117         struct omap_nand_platform_data  *pdata;
 118         struct mtd_info                 mtd;
 119         struct mtd_partition            *parts;
 120         struct nand_chip                nand;
 121         struct platform_device          *pdev;
 122
 123         int                             gpmc_cs;
 124         unsigned long                   phys_base;
 125         struct completion               comp;
 126         int                             dma_ch;
 127         int                             gpmc_irq;
 128         enum {
 129                 OMAP_NAND_IO_READ = 0,  /* read */
 130                 OMAP_NAND_IO_WRITE,     /* write */
 131         } iomode;
 132         u_char                          *buf;
 133         int                                     buf_len;
 134 };
 135
 136 /**
 137  * omap_hwcontrol - hardware specific access to control-lines
 138  * @mtd: MTD device structure
 139  * @cmd: command to device
 140  * @ctrl:
 141  * NAND_NCE: bit 0 -> don't care
 142  * NAND_CLE: bit 1 -> Command Latch
 143  * NAND_ALE: bit 2 -> Address Latch
 144  *
 145  * NOTE: boards may use different bits for these!!
 146  */
 147 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 148 {
 149         struct omap_nand_info *info = container_of(mtd,
 150                                         struct omap_nand_info, mtd);
 151
 152         if (cmd != NAND_CMD_NONE) {
 153                 if (ctrl & NAND_CLE)
 154                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
 155
 156                 else if (ctrl & NAND_ALE)
 157                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
 158
 159                 else /* NAND_NCE */
 160                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
 161         }
 162 }
 163
 164 /**
 165  * omap_read_buf8 - read data from NAND controller into buffer
 166  * @mtd: MTD device structure
 167  * @buf: buffer to store date
 168  * @len: number of bytes to read
 169  */
 170 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 171 {
 172         struct nand_chip *nand = mtd->priv;
 173
 174         ioread8_rep(nand->IO_ADDR_R, buf, len);
 175 }
 176
 177 /**
 178  * omap_write_buf8 - write buffer to NAND controller
 179  * @mtd: MTD device structure
 180  * @buf: data buffer
 181  * @len: number of bytes to write
 182  */
 183 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 184 {
 185         struct omap_nand_info *info = container_of(mtd,
 186                                                 struct omap_nand_info, mtd);
 187         u_char *p = (u_char *)buf;
 188         u32     status = 0;
 189
 190         while (len--) {
 191                 iowrite8(*p++, info->nand.IO_ADDR_W);
 192                 /* wait until buffer is available for write */
 193                 do {
 194                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 195                 } while (!status);
 196         }
 197 }
 198
 199 /**
 200  * omap_read_buf16 - read data from NAND controller into buffer
 201  * @mtd: MTD device structure
 202  * @buf: buffer to store date
 203  * @len: number of bytes to read
 204  */
 205 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 206 {
 207         struct nand_chip *nand = mtd->priv;
 208
 209         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 210 }
 211
 212 /**
 213  * omap_write_buf16 - write buffer to NAND controller
 214  * @mtd: MTD device structure
 215  * @buf: data buffer
 216  * @len: number of bytes to write
 217  */
 218 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 219 {
 220         struct omap_nand_info *info = container_of(mtd,
 221                                                 struct omap_nand_info, mtd);
 222         u16 *p = (u16 *) buf;
 223         u32     status = 0;
 224         /* FIXME try bursts of writesw() or DMA ... */
 225         len >>= 1;
 226
 227         while (len--) {
 228                 iowrite16(*p++, info->nand.IO_ADDR_W);
 229                 /* wait until buffer is available for write */
 230                 do {
 231                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 232                 } while (!status);
 233         }
 234 }
 235
 236 /**
 237  * omap_read_buf_pref - read data from NAND controller into buffer
 238  * @mtd: MTD device structure
 239  * @buf: buffer to store date
 240  * @len: number of bytes to read
 241  */
 242 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 243 {
 244         struct omap_nand_info *info = container_of(mtd,
 245                                                 struct omap_nand_info, mtd);
 246         uint32_t r_count = 0;
 247         int ret = 0;
 248         u32 *p = (u32 *)buf;
 249
 250         /* take care of subpage reads */
 251         if (len % 4) {
 252                 if (info->nand.options & NAND_BUSWIDTH_16)
 253                         omap_read_buf16(mtd, buf, len % 4);
 254                 else
 255                         omap_read_buf8(mtd, buf, len % 4);
 256                 p = (u32 *) (buf + len % 4);
 257                 len -= len % 4;
 258         }
 259
 260         /* configure and start prefetch transfer */
 261         ret = gpmc_prefetch_enable(info->gpmc_cs,
 262                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
 263         if (ret) {
 264                 /* PFPW engine is busy, use cpu copy method */
 265                 if (info->nand.options & NAND_BUSWIDTH_16)
 266                         omap_read_buf16(mtd, (u_char *)p, len);
 267                 else
 268                         omap_read_buf8(mtd, (u_char *)p, len);
 269         } else {
 270                 do {
 271                         r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 272                         r_count = r_count >> 2;
 273                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 274                         p += r_count;
 275                         len -= r_count << 2;
 276                 } while (len);
 277                 /* disable and stop the PFPW engine */
 278                 gpmc_prefetch_reset(info->gpmc_cs);
 279         }
 280 }
 281
 282 /**
 283  * omap_write_buf_pref - write buffer to NAND controller
 284  * @mtd: MTD device structure
 285  * @buf: data buffer
 286  * @len: number of bytes to write
 287  */
 288 static void omap_write_buf_pref(struct mtd_info *mtd,
 289                                         const u_char *buf, int len)
 290 {
 291         struct omap_nand_info *info = container_of(mtd,
 292                                                 struct omap_nand_info, mtd);
 293         uint32_t w_count = 0;
 294         int i = 0, ret = 0;
 295         u16 *p = (u16 *)buf;
 296         unsigned long tim, limit;
 297
 298         /* take care of subpage writes */
 299         if (len % 2 != 0) {
 300                 writeb(*buf, info->nand.IO_ADDR_W);
 301                 p = (u16 *)(buf + 1);
 302                 len--;
 303         }
 304
 305         /*  configure and start prefetch transfer */
 306         ret = gpmc_prefetch_enable(info->gpmc_cs,
 307                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
 308         if (ret) {
 309                 /* PFPW engine is busy, use cpu copy method */
 310                 if (info->nand.options & NAND_BUSWIDTH_16)
 311                         omap_write_buf16(mtd, (u_char *)p, len);
 312                 else
 313                         omap_write_buf8(mtd, (u_char *)p, len);
 314         } else {
 315                 while (len) {
 316                         w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 317                         w_count = w_count >> 1;
 318                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 319                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 320                 }
 321                 /* wait for data to flushed-out before reset the prefetch */
 322                 tim = 0;
 323                 limit = (loops_per_jiffy *
 324                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 325                 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 326                         cpu_relax();
 327
 328                 /* disable and stop the PFPW engine */
 329                 gpmc_prefetch_reset(info->gpmc_cs);
 330         }
 331 }
 332
 333 /*
 334  * omap_nand_dma_cb: callback on the completion of dma transfer
 335  * @lch: logical channel
 336  * @ch_satuts: channel status
 337  * @data: pointer to completion data structure
 338  */
 339 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
 340 {
 341         complete((struct completion *) data);
 342 }
 343
 344 /*
 345  * omap_nand_dma_transfer: configer and start dma transfer
 346  * @mtd: MTD device structure
 347  * @addr: virtual address in RAM of source/destination
 348  * @len: number of data bytes to be transferred
 349  * @is_write: flag for read/write operation
 350  */
 351 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 352                                         unsigned int len, int is_write)
 353 {
 354         struct omap_nand_info *info = container_of(mtd,
 355                                         struct omap_nand_info, mtd);
 356         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 357                                                         DMA_FROM_DEVICE;
 358         dma_addr_t dma_addr;
 359         int ret;
 360         unsigned long tim, limit;
 361
 362         /* The fifo depth is 64 bytes max.
 363          * But configure the FIFO-threahold to 32 to get a sync at each frame
 364          * and frame length is 32 bytes.
 365          */
 366         int buf_len = len >> 6;
 367
 368         if (addr >= high_memory) {
 369                 struct page *p1;
 370
 371                 if (((size_t)addr & PAGE_MASK) !=
 372                         ((size_t)(addr + len - 1) & PAGE_MASK))
 373                         goto out_copy;
 374                 p1 = vmalloc_to_page(addr);
 375                 if (!p1)
 376                         goto out_copy;
 377                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 378         }
 379
 380         dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
 381         if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
 382                 dev_err(&info->pdev->dev,
 383                         "Couldn't DMA map a %d byte buffer\n", len);
 384                 goto out_copy;
 385         }
 386
 387         if (is_write) {
 388             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 389                                                 info->phys_base, 0, 0);
 390             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 391                                                         dma_addr, 0, 0);
 392             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 393                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 394                                         OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
 395         } else {
 396             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 397                                                 info->phys_base, 0, 0);
 398             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 399                                                         dma_addr, 0, 0);
 400             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 401                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 402                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
 403         }
 404         /*  configure and start prefetch transfer */
 405         ret = gpmc_prefetch_enable(info->gpmc_cs,
 406                         PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
 407         if (ret)
 408                 /* PFPW engine is busy, use cpu copy method */
 409                 goto out_copy;
 410
 411         init_completion(&info->comp);
 412
 413         omap_start_dma(info->dma_ch);
 414
 415         /* setup and start DMA using dma_addr */
 416         wait_for_completion(&info->comp);
 417         tim = 0;
 418         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 419         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 420                 cpu_relax();
 421
 422         /* disable and stop the PFPW engine */
 423         gpmc_prefetch_reset(info->gpmc_cs);
 424
 425         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 426         return 0;
 427
 428 out_copy:
 429         if (info->nand.options & NAND_BUSWIDTH_16)
 430                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 431                         : omap_write_buf16(mtd, (u_char *) addr, len);
 432         else
 433                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 434                         : omap_write_buf8(mtd, (u_char *) addr, len);
 435         return 0;
 436 }
 437
 438 /**
 439  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 440  * @mtd: MTD device structure
 441  * @buf: buffer to store date
 442  * @len: number of bytes to read
 443  */
 444 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 445 {
 446         if (len <= mtd->oobsize)
 447                 omap_read_buf_pref(mtd, buf, len);
 448         else
 449                 /* start transfer in DMA mode */
 450                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 451 }
 452
 453 /**
 454  * omap_write_buf_dma_pref - write buffer to NAND controller
 455  * @mtd: MTD device structure
 456  * @buf: data buffer
 457  * @len: number of bytes to write
 458  */
 459 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 460                                         const u_char *buf, int len)
 461 {
 462         if (len <= mtd->oobsize)
 463                 omap_write_buf_pref(mtd, buf, len);
 464         else
 465                 /* start transfer in DMA mode */
 466                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 467 }
 468
 469 /*
 470  * omap_nand_irq - GMPC irq handler
 471  * @this_irq: gpmc irq number
 472  * @dev: omap_nand_info structure pointer is passed here
 473  */
 474 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 475 {
 476         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 477         u32 bytes;
 478         u32 irq_stat;
 479
 480         irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 481         bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 482         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 483         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 484                 if (irq_stat & 0x2)
 485                         goto done;
 486
 487                 if (info->buf_len && (info->buf_len < bytes))
 488                         bytes = info->buf_len;
 489                 else if (!info->buf_len)
 490                         bytes = 0;
 491                 iowrite32_rep(info->nand.IO_ADDR_W,
 492                                                 (u32 *)info->buf, bytes >> 2);
 493                 info->buf = info->buf + bytes;
 494                 info->buf_len -= bytes;
 495
 496         } else {
 497                 ioread32_rep(info->nand.IO_ADDR_R,
 498                                                 (u32 *)info->buf, bytes >> 2);
 499                 info->buf = info->buf + bytes;
 500
 501                 if (irq_stat & 0x2)
 502                         goto done;
 503         }
 504         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 505
 506         return IRQ_HANDLED;
 507
 508 done:
 509         complete(&info->comp);
 510         /* disable irq */
 511         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 512
 513         /* clear status */
 514         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 515
 516         return IRQ_HANDLED;
 517 }
 518
 519 /*
 520  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 521  * @mtd: MTD device structure
 522  * @buf: buffer to store date
 523  * @len: number of bytes to read
 524  */
 525 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 526 {
 527         struct omap_nand_info *info = container_of(mtd,
 528                                                 struct omap_nand_info, mtd);
 529         int ret = 0;
 530
 531         if (len <= mtd->oobsize) {
 532                 omap_read_buf_pref(mtd, buf, len);
 533                 return;
 534         }
 535
 536         info->iomode = OMAP_NAND_IO_READ;
 537         info->buf = buf;
 538         init_completion(&info->comp);
 539
 540         /*  configure and start prefetch transfer */
 541         ret = gpmc_prefetch_enable(info->gpmc_cs,
 542                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
 543         if (ret)
 544                 /* PFPW engine is busy, use cpu copy method */
 545                 goto out_copy;
 546
 547         info->buf_len = len;
 548         /* enable irq */
 549         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 550                 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 551
 552         /* waiting for read to complete */
 553         wait_for_completion(&info->comp);
 554
 555         /* disable and stop the PFPW engine */
 556         gpmc_prefetch_reset(info->gpmc_cs);
 557         return;
 558
 559 out_copy:
 560         if (info->nand.options & NAND_BUSWIDTH_16)
 561                 omap_read_buf16(mtd, buf, len);
 562         else
 563                 omap_read_buf8(mtd, buf, len);
 564 }
 565
 566 /*
 567  * omap_write_buf_irq_pref - write buffer to NAND controller
 568  * @mtd: MTD device structure
 569  * @buf: data buffer
 570  * @len: number of bytes to write
 571  */
 572 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 573                                         const u_char *buf, int len)
 574 {
 575         struct omap_nand_info *info = container_of(mtd,
 576                                                 struct omap_nand_info, mtd);
 577         int ret = 0;
 578         unsigned long tim, limit;
 579
 580         if (len <= mtd->oobsize) {
 581                 omap_write_buf_pref(mtd, buf, len);
 582                 return;
 583         }
 584
 585         info->iomode = OMAP_NAND_IO_WRITE;
 586         info->buf = (u_char *) buf;
 587         init_completion(&info->comp);
 588
 589         /* configure and start prefetch transfer : size=24 */
 590         ret = gpmc_prefetch_enable(info->gpmc_cs,
 591                         (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
 592         if (ret)
 593                 /* PFPW engine is busy, use cpu copy method */
 594                 goto out_copy;
 595
 596         info->buf_len = len;
 597         /* enable irq */
 598         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 599                         (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 600
 601         /* waiting for write to complete */
 602         wait_for_completion(&info->comp);
 603         /* wait for data to flushed-out before reset the prefetch */
 604         tim = 0;
 605         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 606         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 607                 cpu_relax();
 608
 609         /* disable and stop the PFPW engine */
 610         gpmc_prefetch_reset(info->gpmc_cs);
 611         return;
 612
 613 out_copy:
 614         if (info->nand.options & NAND_BUSWIDTH_16)
 615                 omap_write_buf16(mtd, buf, len);
 616         else
 617                 omap_write_buf8(mtd, buf, len);
 618 }
 619
 620 /**
 621  * omap_verify_buf - Verify chip data against buffer
 622  * @mtd: MTD device structure
 623  * @buf: buffer containing the data to compare
 624  * @len: number of bytes to compare
 625  */
 626 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 627 {
 628         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 629                                                         mtd);
 630         u16 *p = (u16 *) buf;
 631
 632         len >>= 1;
 633         while (len--) {
 634                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 635                         return -EFAULT;
 636         }
 637
 638         return 0;
 639 }
 640
 641 /**
 642  * gen_true_ecc - This function will generate true ECC value
 643  * @ecc_buf: buffer to store ecc code
 644  *
 645  * This generated true ECC value can be used when correcting
 646  * data read from NAND flash memory core
 647  */
 648 static void gen_true_ecc(u8 *ecc_buf)
 649 {
 650         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 651                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 652
 653         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 654                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 655         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 656                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 657         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 658                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 659 }
 660
 661 /**
 662  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 663  * @ecc_data1:  ecc code from nand spare area
 664  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 665  * @page_data:  page data
 666  *
 667  * This function compares two ECC's and indicates if there is an error.
 668  * If the error can be corrected it will be corrected to the buffer.
 669  * If there is no error, %0 is returned. If there is an error but it
 670  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 671  */
 672 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 673                             u8 *ecc_data2,      /* read from register */
 674                             u8 *page_data)
 675 {
 676         uint    i;
 677         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 678         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 679         u8      ecc_bit[24];
 680         u8      ecc_sum = 0;
 681         u8      find_bit = 0;
 682         uint    find_byte = 0;
 683         int     isEccFF;
 684
 685         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 686
 687         gen_true_ecc(ecc_data1);
 688         gen_true_ecc(ecc_data2);
 689
 690         for (i = 0; i <= 2; i++) {
 691                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 692                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 693         }
 694
 695         for (i = 0; i < 8; i++) {
 696                 tmp0_bit[i]     = *ecc_data1 % 2;
 697                 *ecc_data1      = *ecc_data1 / 2;
 698         }
 699
 700         for (i = 0; i < 8; i++) {
 701                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 702                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 703         }
 704
 705         for (i = 0; i < 8; i++) {
 706                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 707                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 708         }
 709
 710         for (i = 0; i < 8; i++) {
 711                 comp0_bit[i]     = *ecc_data2 % 2;
 712                 *ecc_data2       = *ecc_data2 / 2;
 713         }
 714
 715         for (i = 0; i < 8; i++) {
 716                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 717                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 718         }
 719
 720         for (i = 0; i < 8; i++) {
 721                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 722                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 723         }
 724
 725         for (i = 0; i < 6; i++)
 726                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 727
 728         for (i = 0; i < 8; i++)
 729                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 730
 731         for (i = 0; i < 8; i++)
 732                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 733
 734         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 735         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 736
 737         for (i = 0; i < 24; i++)
 738                 ecc_sum += ecc_bit[i];
 739
 740         switch (ecc_sum) {
 741         case 0:
 742                 /* Not reached because this function is not called if
 743                  *  ECC values are equal
 744                  */
 745                 return 0;
 746
 747         case 1:
 748                 /* Uncorrectable error */
 749                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 750                 return -1;
 751
 752         case 11:
 753                 /* UN-Correctable error */
 754                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
 755                 return -1;
 756
 757         case 12:
 758                 /* Correctable error */
 759                 find_byte = (ecc_bit[23] << 8) +
 760                             (ecc_bit[21] << 7) +
 761                             (ecc_bit[19] << 6) +
 762                             (ecc_bit[17] << 5) +
 763                             (ecc_bit[15] << 4) +
 764                             (ecc_bit[13] << 3) +
 765                             (ecc_bit[11] << 2) +
 766                             (ecc_bit[9]  << 1) +
 767                             ecc_bit[7];
 768
 769                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 770
 771                 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
 772                                 "offset: %d, bit: %d\n", find_byte, find_bit);
 773
 774                 page_data[find_byte] ^= (1 << find_bit);
 775
 776                 return 1;
 777         default:
 778                 if (isEccFF) {
 779                         if (ecc_data2[0] == 0 &&
 780                             ecc_data2[1] == 0 &&
 781                             ecc_data2[2] == 0)
 782                                 return 0;
 783                 }
 784                 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
 785                 return -1;
 786         }
 787 }
 788
 789 /**
 790  * omap_correct_data - Compares the ECC read with HW generated ECC
 791  * @mtd: MTD device structure
 792  * @dat: page data
 793  * @read_ecc: ecc read from nand flash
 794  * @calc_ecc: ecc read from HW ECC registers
 795  *
 796  * Compares the ecc read from nand spare area with ECC registers values
 797  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 798  * detection and correction. If there are no errors, %0 is returned. If
 799  * there were errors and all of the errors were corrected, the number of
 800  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 801  * returned.
 802  */
 803 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 804                                 u_char *read_ecc, u_char *calc_ecc)
 805 {
 806         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 807                                                         mtd);
 808         int blockCnt = 0, i = 0, ret = 0;
 809         int stat = 0;
 810
 811         /* Ex NAND_ECC_HW12_2048 */
 812         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 813                         (info->nand.ecc.size  == 2048))
 814                 blockCnt = 4;
 815         else
 816                 blockCnt = 1;
 817
 818         for (i = 0; i < blockCnt; i++) {
 819                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 820                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 821                         if (ret < 0)
 822                                 return ret;
 823                         /* keep track of the number of corrected errors */
 824                         stat += ret;
 825                 }
 826                 read_ecc += 3;
 827                 calc_ecc += 3;
 828                 dat      += 512;
 829         }
 830         return stat;
 831 }
 832
 833 /**
 834  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 835  * @mtd: MTD device structure
 836  * @dat: The pointer to data on which ecc is computed
 837  * @ecc_code: The ecc_code buffer
 838  *
 839  * Using noninverted ECC can be considered ugly since writing a blank
 840  * page ie. padding will clear the ECC bytes. This is no problem as long
 841  * nobody is trying to write data on the seemingly unused page. Reading
 842  * an erased page will produce an ECC mismatch between generated and read
 843  * ECC bytes that has to be dealt with separately.
 844  */
 845 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 846                                 u_char *ecc_code)
 847 {
 848         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 849                                                         mtd);
 850         return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 851 }
 852
 853 /**
 854  * omap_enable_hwecc - This function enables the hardware ecc functionality
 855  * @mtd: MTD device structure
 856  * @mode: Read/Write mode
 857  */
 858 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 859 {
 860         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 861                                                         mtd);
 862         struct nand_chip *chip = mtd->priv;
 863         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 864
 865         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 866 }
 867
 868 /**
 869  * omap_wait - wait until the command is done
 870  * @mtd: MTD device structure
 871  * @chip: NAND Chip structure
 872  *
 873  * Wait function is called during Program and erase operations and
 874  * the way it is called from MTD layer, we should wait till the NAND
 875  * chip is ready after the programming/erase operation has completed.
 876  *
 877  * Erase can take up to 400ms and program up to 20ms according to
 878  * general NAND and SmartMedia specs
 879  */
 880 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 881 {
 882         struct nand_chip *this = mtd->priv;
 883         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 884                                                         mtd);
 885         unsigned long timeo = jiffies;
 886         int status = NAND_STATUS_FAIL, state = this->state;
 887
 888         if (state == FL_ERASING)
 889                 timeo += (HZ * 400) / 1000;
 890         else
 891                 timeo += (HZ * 20) / 1000;
 892
 893         gpmc_nand_write(info->gpmc_cs,
 894                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 895         while (time_before(jiffies, timeo)) {
 896                 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 897                 if (status & NAND_STATUS_READY)
 898                         break;
 899                 cond_resched();
 900         }
 901         return status;
 902 }
 903
 904 /**
 905  * omap_dev_ready - calls the platform specific dev_ready function
 906  * @mtd: MTD device structure
 907  */
 908 static int omap_dev_ready(struct mtd_info *mtd)
 909 {
 910         unsigned int val = 0;
 911         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 912                                                         mtd);
 913
 914         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 915         if ((val & 0x100) == 0x100) {
 916                 /* Clear IRQ Interrupt */
 917                 val |= 0x100;
 918                 val &= ~(0x0);
 919                 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
 920         } else {
 921                 unsigned int cnt = 0;
 922                 while (cnt++ < 0x1FF) {
 923                         if  ((val & 0x100) == 0x100)
 924                                 return 0;
 925                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 926                 }
 927         }
 928
 929         return 1;
 930 }
 931
 932 static int __devinit omap_nand_probe(struct platform_device *pdev)
 933 {
 934         struct omap_nand_info           *info;
 935         struct omap_nand_platform_data  *pdata;
 936         int                             err;
 937         int                             i, offset;
 938
 939         pdata = pdev->dev.platform_data;
 940         if (pdata == NULL) {
 941                 dev_err(&pdev->dev, "platform data missing\n");
 942                 return -ENODEV;
 943         }
 944
 945         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
 946         if (!info)
 947                 return -ENOMEM;
 948
 949         platform_set_drvdata(pdev, info);
 950
 951         spin_lock_init(&info->controller.lock);
 952         init_waitqueue_head(&info->controller.wq);
 953
 954         info->pdev = pdev;
 955
 956         info->gpmc_cs           = pdata->cs;
 957         info->phys_base         = pdata->phys_base;
 958
 959         info->mtd.priv          = &info->nand;
 960         info->mtd.name          = dev_name(&pdev->dev);
 961         info->mtd.owner         = THIS_MODULE;
 962
 963         info->nand.options      = pdata->devsize;
 964         info->nand.options      |= NAND_SKIP_BBTSCAN;
 965
 966         /* NAND write protect off */
 967         gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 968
 969         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
 970                                 pdev->dev.driver->name)) {
 971                 err = -EBUSY;
 972                 goto out_free_info;
 973         }
 974
 975         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
 976         if (!info->nand.IO_ADDR_R) {
 977                 err = -ENOMEM;
 978                 goto out_release_mem_region;
 979         }
 980
 981         info->nand.controller = &info->controller;
 982
 983         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
 984         info->nand.cmd_ctrl  = omap_hwcontrol;
 985
 986         /*
 987          * If RDY/BSY line is connected to OMAP then use the omap ready
 988          * funcrtion and the generic nand_wait function which reads the status
 989          * register after monitoring the RDY/BSY line.Otherwise use a standard
 990          * chip delay which is slightly more than tR (AC Timing) of the NAND
 991          * device and read status register until you get a failure or success
 992          */
 993         if (pdata->dev_ready) {
 994                 info->nand.dev_ready = omap_dev_ready;
 995                 info->nand.chip_delay = 0;
 996         } else {
 997                 info->nand.waitfunc = omap_wait;
 998                 info->nand.chip_delay = 50;
 999         }
1000
1001         switch (pdata->xfer_type) {
1002         case NAND_OMAP_PREFETCH_POLLED:
1003                 info->nand.read_buf   = omap_read_buf_pref;
1004                 info->nand.write_buf  = omap_write_buf_pref;
1005                 break;
1006
1007         case NAND_OMAP_POLLED:
1008                 if (info->nand.options & NAND_BUSWIDTH_16) {
1009                         info->nand.read_buf   = omap_read_buf16;
1010                         info->nand.write_buf  = omap_write_buf16;
1011                 } else {
1012                         info->nand.read_buf   = omap_read_buf8;
1013                         info->nand.write_buf  = omap_write_buf8;
1014                 }
1015                 break;
1016
1017         case NAND_OMAP_PREFETCH_DMA:
1018                 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1019                                 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1020                 if (err < 0) {
1021                         info->dma_ch = -1;
1022                         dev_err(&pdev->dev, "DMA request failed!\n");
1023                         goto out_release_mem_region;
1024                 } else {
1025                         omap_set_dma_dest_burst_mode(info->dma_ch,
1026                                         OMAP_DMA_DATA_BURST_16);
1027                         omap_set_dma_src_burst_mode(info->dma_ch,
1028                                         OMAP_DMA_DATA_BURST_16);
1029
1030                         info->nand.read_buf   = omap_read_buf_dma_pref;
1031                         info->nand.write_buf  = omap_write_buf_dma_pref;
1032                 }
1033                 break;
1034
1035         case NAND_OMAP_PREFETCH_IRQ:
1036                 err = request_irq(pdata->gpmc_irq,
1037                                 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1038                 if (err) {
1039                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1040                                                         pdata->gpmc_irq, err);
1041                         goto out_release_mem_region;
1042                 } else {
1043                         info->gpmc_irq       = pdata->gpmc_irq;
1044                         info->nand.read_buf  = omap_read_buf_irq_pref;
1045                         info->nand.write_buf = omap_write_buf_irq_pref;
1046                 }
1047                 break;
1048
1049         default:
1050                 dev_err(&pdev->dev,
1051                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1052                 err = -EINVAL;
1053                 goto out_release_mem_region;
1054         }
1055
1056         info->nand.verify_buf = omap_verify_buf;
1057
1058         /* selsect the ecc type */
1059         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1060                 info->nand.ecc.mode = NAND_ECC_SOFT;
1061         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1062                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1063                 info->nand.ecc.bytes            = 3;
1064                 info->nand.ecc.size             = 512;
1065                 info->nand.ecc.calculate        = omap_calculate_ecc;
1066                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1067                 info->nand.ecc.correct          = omap_correct_data;
1068                 info->nand.ecc.mode             = NAND_ECC_HW;
1069         }
1070
1071         /* DIP switches on some boards change between 8 and 16 bit
1072          * bus widths for flash.  Try the other width if the first try fails.
1073          */
1074         if (nand_scan_ident(&info->mtd, 1, NULL)) {
1075                 info->nand.options ^= NAND_BUSWIDTH_16;
1076                 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1077                         err = -ENXIO;
1078                         goto out_release_mem_region;
1079                 }
1080         }
1081
1082         /* rom code layout */
1083         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1084
1085                 if (info->nand.options & NAND_BUSWIDTH_16)
1086                         offset = 2;
1087                 else {
1088                         offset = 1;
1089                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1090                 }
1091                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1092                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1093                         omap_oobinfo.eccpos[i] = i+offset;
1094
1095                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1096                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1097                                         (offset + omap_oobinfo.eccbytes);
1098
1099                 info->nand.ecc.layout = &omap_oobinfo;
1100         }
1101
1102         /* second phase scan */
1103         if (nand_scan_tail(&info->mtd)) {
1104                 err = -ENXIO;
1105                 goto out_release_mem_region;
1106         }
1107
1108 #ifdef CONFIG_MTD_PARTITIONS
1109         err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
1110         if (err > 0)
1111                 add_mtd_partitions(&info->mtd, info->parts, err);
1112         else if (pdata->parts)
1113                 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
1114         else
1115 #endif
1116                 add_mtd_device(&info->mtd);
1117
1118         platform_set_drvdata(pdev, &info->mtd);
1119
1120         return 0;
1121
1122 out_release_mem_region:
1123         release_mem_region(info->phys_base, NAND_IO_SIZE);
1124 out_free_info:
1125         kfree(info);
1126
1127         return err;
1128 }
1129
1130 static int omap_nand_remove(struct platform_device *pdev)
1131 {
1132         struct mtd_info *mtd = platform_get_drvdata(pdev);
1133         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1134                                                         mtd);
1135
1136         platform_set_drvdata(pdev, NULL);
1137         if (info->dma_ch != -1)
1138                 omap_free_dma(info->dma_ch);
1139
1140         if (info->gpmc_irq)
1141                 free_irq(info->gpmc_irq, info);
1142
1143         /* Release NAND device, its internal structures and partitions */
1144         nand_release(&info->mtd);
1145         iounmap(info->nand.IO_ADDR_R);
1146         kfree(&info->mtd);
1147         return 0;
1148 }
1149
1150 static struct platform_driver omap_nand_driver = {
1151         .probe          = omap_nand_probe,
1152         .remove         = omap_nand_remove,
1153         .driver         = {
1154                 .name   = DRIVER_NAME,
1155                 .owner  = THIS_MODULE,
1156         },
1157 };
1158
1159 static int __init omap_nand_init(void)
1160 {
1161         pr_info("%s driver initializing\n", DRIVER_NAME);
1162
1163         return platform_driver_register(&omap_nand_driver);
1164 }
1165
1166 static void __exit omap_nand_exit(void)
1167 {
1168         platform_driver_unregister(&omap_nand_driver);
1169 }
1170
1171 module_init(omap_nand_init);
1172 module_exit(omap_nand_exit);
1173
1174 MODULE_ALIAS("platform:" DRIVER_NAME);
1175 MODULE_LICENSE("GPL");
1176 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");