2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #define CONFIG_MTD_NAND_OMAP_HWECC
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/jiffies.h>
16 #include <linux/sched.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/partitions.h>
21 #include <linux/slab.h>
24 #include <plat/gpmc.h>
25 #include <plat/nand.h>
27 #define DRIVER_NAME "omap2-nand"
29 #define NAND_Ecc_P1e (1 << 0)
30 #define NAND_Ecc_P2e (1 << 1)
31 #define NAND_Ecc_P4e (1 << 2)
32 #define NAND_Ecc_P8e (1 << 3)
33 #define NAND_Ecc_P16e (1 << 4)
34 #define NAND_Ecc_P32e (1 << 5)
35 #define NAND_Ecc_P64e (1 << 6)
36 #define NAND_Ecc_P128e (1 << 7)
37 #define NAND_Ecc_P256e (1 << 8)
38 #define NAND_Ecc_P512e (1 << 9)
39 #define NAND_Ecc_P1024e (1 << 10)
40 #define NAND_Ecc_P2048e (1 << 11)
42 #define NAND_Ecc_P1o (1 << 16)
43 #define NAND_Ecc_P2o (1 << 17)
44 #define NAND_Ecc_P4o (1 << 18)
45 #define NAND_Ecc_P8o (1 << 19)
46 #define NAND_Ecc_P16o (1 << 20)
47 #define NAND_Ecc_P32o (1 << 21)
48 #define NAND_Ecc_P64o (1 << 22)
49 #define NAND_Ecc_P128o (1 << 23)
50 #define NAND_Ecc_P256o (1 << 24)
51 #define NAND_Ecc_P512o (1 << 25)
52 #define NAND_Ecc_P1024o (1 << 26)
53 #define NAND_Ecc_P2048o (1 << 27)
55 #define TF(value) (value ? 1 : 0)
57 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
58 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
59 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
60 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
61 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
62 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
63 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
64 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
66 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
67 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
68 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
69 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
70 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
71 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
72 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
73 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
75 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
76 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
77 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
78 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
79 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
80 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
81 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
82 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
84 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
85 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
86 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
87 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
88 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
89 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
90 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
91 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
93 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
94 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
96 #ifdef CONFIG_MTD_PARTITIONS
97 static const char *part_probes[] = { "cmdlinepart", NULL };
100 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
101 static int use_prefetch = 1;
103 /* "modprobe ... use_prefetch=0" etc */
104 module_param(use_prefetch, bool, 0);
105 MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH");
107 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
108 static int use_dma = 1;
110 /* "modprobe ... use_dma=0" etc */
111 module_param(use_dma, bool, 0);
112 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
117 const int use_prefetch;
121 struct omap_nand_info {
122 struct nand_hw_control controller;
123 struct omap_nand_platform_data *pdata;
125 struct mtd_partition *parts;
126 struct nand_chip nand;
127 struct platform_device *pdev;
130 unsigned long phys_base;
131 struct completion comp;
136 * omap_hwcontrol - hardware specific access to control-lines
137 * @mtd: MTD device structure
138 * @cmd: command to device
140 * NAND_NCE: bit 0 -> don't care
141 * NAND_CLE: bit 1 -> Command Latch
142 * NAND_ALE: bit 2 -> Address Latch
144 * NOTE: boards may use different bits for these!!
146 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
148 struct omap_nand_info *info = container_of(mtd,
149 struct omap_nand_info, mtd);
151 if (cmd != NAND_CMD_NONE) {
153 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
155 else if (ctrl & NAND_ALE)
156 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
159 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
164 * omap_read_buf8 - read data from NAND controller into buffer
165 * @mtd: MTD device structure
166 * @buf: buffer to store date
167 * @len: number of bytes to read
169 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
171 struct nand_chip *nand = mtd->priv;
173 ioread8_rep(nand->IO_ADDR_R, buf, len);
177 * omap_write_buf8 - write buffer to NAND controller
178 * @mtd: MTD device structure
180 * @len: number of bytes to write
182 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
184 struct omap_nand_info *info = container_of(mtd,
185 struct omap_nand_info, mtd);
186 u_char *p = (u_char *)buf;
190 iowrite8(*p++, info->nand.IO_ADDR_W);
191 /* wait until buffer is available for write */
193 status = gpmc_read_status(GPMC_STATUS_BUFFER);
199 * omap_read_buf16 - read data from NAND controller into buffer
200 * @mtd: MTD device structure
201 * @buf: buffer to store date
202 * @len: number of bytes to read
204 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
206 struct nand_chip *nand = mtd->priv;
208 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
212 * omap_write_buf16 - write buffer to NAND controller
213 * @mtd: MTD device structure
215 * @len: number of bytes to write
217 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
219 struct omap_nand_info *info = container_of(mtd,
220 struct omap_nand_info, mtd);
221 u16 *p = (u16 *) buf;
223 /* FIXME try bursts of writesw() or DMA ... */
227 iowrite16(*p++, info->nand.IO_ADDR_W);
228 /* wait until buffer is available for write */
230 status = gpmc_read_status(GPMC_STATUS_BUFFER);
236 * omap_read_buf_pref - read data from NAND controller into buffer
237 * @mtd: MTD device structure
238 * @buf: buffer to store date
239 * @len: number of bytes to read
241 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
243 struct omap_nand_info *info = container_of(mtd,
244 struct omap_nand_info, mtd);
245 uint32_t r_count = 0;
249 /* take care of subpage reads */
251 if (info->nand.options & NAND_BUSWIDTH_16)
252 omap_read_buf16(mtd, buf, len % 4);
254 omap_read_buf8(mtd, buf, len % 4);
255 p = (u32 *) (buf + len % 4);
259 /* configure and start prefetch transfer */
260 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
262 /* PFPW engine is busy, use cpu copy method */
263 if (info->nand.options & NAND_BUSWIDTH_16)
264 omap_read_buf16(mtd, buf, len);
266 omap_read_buf8(mtd, buf, len);
270 r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
271 r_count = r_count >> 2;
272 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
276 /* disable and stop the PFPW engine */
277 gpmc_prefetch_reset(info->gpmc_cs);
282 * omap_write_buf_pref - write buffer to NAND controller
283 * @mtd: MTD device structure
285 * @len: number of bytes to write
287 static void omap_write_buf_pref(struct mtd_info *mtd,
288 const u_char *buf, int len)
290 struct omap_nand_info *info = container_of(mtd,
291 struct omap_nand_info, mtd);
292 uint32_t pref_count = 0, w_count = 0;
296 /* take care of subpage writes */
298 writeb(*buf, info->nand.IO_ADDR_W);
299 p = (u16 *)(buf + 1);
303 /* configure and start prefetch transfer */
304 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
306 /* PFPW engine is busy, use cpu copy method */
307 if (info->nand.options & NAND_BUSWIDTH_16)
308 omap_write_buf16(mtd, buf, len);
310 omap_write_buf8(mtd, buf, len);
314 w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
315 w_count = w_count >> 1;
316 for (i = 0; (i < w_count) && len; i++, len -= 2)
317 iowrite16(*p++, info->nand.IO_ADDR_W);
319 /* wait for data to flushed-out before reset the prefetch */
321 pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT);
322 } while (pref_count);
323 /* disable and stop the PFPW engine */
324 gpmc_prefetch_reset(info->gpmc_cs);
328 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
330 * omap_nand_dma_cb: callback on the completion of dma transfer
331 * @lch: logical channel
332 * @ch_satuts: channel status
333 * @data: pointer to completion data structure
335 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
337 complete((struct completion *) data);
341 * omap_nand_dma_transfer: configer and start dma transfer
342 * @mtd: MTD device structure
343 * @addr: virtual address in RAM of source/destination
344 * @len: number of data bytes to be transferred
345 * @is_write: flag for read/write operation
347 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
348 unsigned int len, int is_write)
350 struct omap_nand_info *info = container_of(mtd,
351 struct omap_nand_info, mtd);
352 uint32_t prefetch_status = 0;
353 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
358 /* The fifo depth is 64 bytes. We have a sync at each frame and frame
359 * length is 64 bytes.
361 int buf_len = len >> 6;
363 if (addr >= high_memory) {
366 if (((size_t)addr & PAGE_MASK) !=
367 ((size_t)(addr + len - 1) & PAGE_MASK))
369 p1 = vmalloc_to_page(addr);
372 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
375 dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
376 if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
377 dev_err(&info->pdev->dev,
378 "Couldn't DMA map a %d byte buffer\n", len);
383 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
384 info->phys_base, 0, 0);
385 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
387 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
388 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
389 OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
391 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
392 info->phys_base, 0, 0);
393 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
395 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
396 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
397 OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
399 /* configure and start prefetch transfer */
400 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
402 /* PFPW engine is busy, use cpu copy methode */
405 init_completion(&info->comp);
407 omap_start_dma(info->dma_ch);
409 /* setup and start DMA using dma_addr */
410 wait_for_completion(&info->comp);
413 prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT);
414 } while (prefetch_status);
415 /* disable and stop the PFPW engine */
416 gpmc_prefetch_reset(info->gpmc_cs);
418 dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
422 if (info->nand.options & NAND_BUSWIDTH_16)
423 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
424 : omap_write_buf16(mtd, (u_char *) addr, len);
426 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
427 : omap_write_buf8(mtd, (u_char *) addr, len);
431 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {}
432 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
433 unsigned int len, int is_write)
440 * omap_read_buf_dma_pref - read data from NAND controller into buffer
441 * @mtd: MTD device structure
442 * @buf: buffer to store date
443 * @len: number of bytes to read
445 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
447 if (len <= mtd->oobsize)
448 omap_read_buf_pref(mtd, buf, len);
450 /* start transfer in DMA mode */
451 omap_nand_dma_transfer(mtd, buf, len, 0x0);
455 * omap_write_buf_dma_pref - write buffer to NAND controller
456 * @mtd: MTD device structure
458 * @len: number of bytes to write
460 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
461 const u_char *buf, int len)
463 if (len <= mtd->oobsize)
464 omap_write_buf_pref(mtd, buf, len);
466 /* start transfer in DMA mode */
467 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
471 * omap_verify_buf - Verify chip data against buffer
472 * @mtd: MTD device structure
473 * @buf: buffer containing the data to compare
474 * @len: number of bytes to compare
476 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
478 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
480 u16 *p = (u16 *) buf;
484 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
491 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
494 * gen_true_ecc - This function will generate true ECC value
495 * @ecc_buf: buffer to store ecc code
497 * This generated true ECC value can be used when correcting
498 * data read from NAND flash memory core
500 static void gen_true_ecc(u8 *ecc_buf)
502 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
503 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
505 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
506 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
507 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
508 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
509 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
510 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
514 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
515 * @ecc_data1: ecc code from nand spare area
516 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
517 * @page_data: page data
519 * This function compares two ECC's and indicates if there is an error.
520 * If the error can be corrected it will be corrected to the buffer.
522 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
523 u8 *ecc_data2, /* read from register */
527 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
528 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
535 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
537 gen_true_ecc(ecc_data1);
538 gen_true_ecc(ecc_data2);
540 for (i = 0; i <= 2; i++) {
541 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
542 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
545 for (i = 0; i < 8; i++) {
546 tmp0_bit[i] = *ecc_data1 % 2;
547 *ecc_data1 = *ecc_data1 / 2;
550 for (i = 0; i < 8; i++) {
551 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
552 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
555 for (i = 0; i < 8; i++) {
556 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
557 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
560 for (i = 0; i < 8; i++) {
561 comp0_bit[i] = *ecc_data2 % 2;
562 *ecc_data2 = *ecc_data2 / 2;
565 for (i = 0; i < 8; i++) {
566 comp1_bit[i] = *(ecc_data2 + 1) % 2;
567 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
570 for (i = 0; i < 8; i++) {
571 comp2_bit[i] = *(ecc_data2 + 2) % 2;
572 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
575 for (i = 0; i < 6; i++)
576 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
578 for (i = 0; i < 8; i++)
579 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
581 for (i = 0; i < 8; i++)
582 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
584 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
585 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
587 for (i = 0; i < 24; i++)
588 ecc_sum += ecc_bit[i];
592 /* Not reached because this function is not called if
593 * ECC values are equal
598 /* Uncorrectable error */
599 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
603 /* UN-Correctable error */
604 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
608 /* Correctable error */
609 find_byte = (ecc_bit[23] << 8) +
619 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
621 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
622 "offset: %d, bit: %d\n", find_byte, find_bit);
624 page_data[find_byte] ^= (1 << find_bit);
629 if (ecc_data2[0] == 0 &&
634 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
640 * omap_correct_data - Compares the ECC read with HW generated ECC
641 * @mtd: MTD device structure
643 * @read_ecc: ecc read from nand flash
644 * @calc_ecc: ecc read from HW ECC registers
646 * Compares the ecc read from nand spare area with ECC registers values
647 * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection
650 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
651 u_char *read_ecc, u_char *calc_ecc)
653 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
655 int blockCnt = 0, i = 0, ret = 0;
657 /* Ex NAND_ECC_HW12_2048 */
658 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
659 (info->nand.ecc.size == 2048))
664 for (i = 0; i < blockCnt; i++) {
665 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
666 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
678 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
679 * @mtd: MTD device structure
680 * @dat: The pointer to data on which ecc is computed
681 * @ecc_code: The ecc_code buffer
683 * Using noninverted ECC can be considered ugly since writing a blank
684 * page ie. padding will clear the ECC bytes. This is no problem as long
685 * nobody is trying to write data on the seemingly unused page. Reading
686 * an erased page will produce an ECC mismatch between generated and read
687 * ECC bytes that has to be dealt with separately.
689 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
692 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
694 return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
698 * omap_enable_hwecc - This function enables the hardware ecc functionality
699 * @mtd: MTD device structure
700 * @mode: Read/Write mode
702 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
704 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
706 struct nand_chip *chip = mtd->priv;
707 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
709 gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
715 * omap_wait - wait until the command is done
716 * @mtd: MTD device structure
717 * @chip: NAND Chip structure
719 * Wait function is called during Program and erase operations and
720 * the way it is called from MTD layer, we should wait till the NAND
721 * chip is ready after the programming/erase operation has completed.
723 * Erase can take up to 400ms and program up to 20ms according to
724 * general NAND and SmartMedia specs
726 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
728 struct nand_chip *this = mtd->priv;
729 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
731 unsigned long timeo = jiffies;
732 int status = NAND_STATUS_FAIL, state = this->state;
734 if (state == FL_ERASING)
735 timeo += (HZ * 400) / 1000;
737 timeo += (HZ * 20) / 1000;
739 gpmc_nand_write(info->gpmc_cs,
740 GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
741 while (time_before(jiffies, timeo)) {
742 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
743 if (status & NAND_STATUS_READY)
751 * omap_dev_ready - calls the platform specific dev_ready function
752 * @mtd: MTD device structure
754 static int omap_dev_ready(struct mtd_info *mtd)
756 unsigned int val = 0;
757 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
760 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
761 if ((val & 0x100) == 0x100) {
762 /* Clear IRQ Interrupt */
765 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
767 unsigned int cnt = 0;
768 while (cnt++ < 0x1FF) {
769 if ((val & 0x100) == 0x100)
771 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
778 static int __devinit omap_nand_probe(struct platform_device *pdev)
780 struct omap_nand_info *info;
781 struct omap_nand_platform_data *pdata;
784 pdata = pdev->dev.platform_data;
786 dev_err(&pdev->dev, "platform data missing\n");
790 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
794 platform_set_drvdata(pdev, info);
796 spin_lock_init(&info->controller.lock);
797 init_waitqueue_head(&info->controller.wq);
801 info->gpmc_cs = pdata->cs;
802 info->phys_base = pdata->phys_base;
804 info->mtd.priv = &info->nand;
805 info->mtd.name = dev_name(&pdev->dev);
806 info->mtd.owner = THIS_MODULE;
808 info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
809 info->nand.options |= NAND_SKIP_BBTSCAN;
811 /* NAND write protect off */
812 gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
814 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
815 pdev->dev.driver->name)) {
820 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
821 if (!info->nand.IO_ADDR_R) {
823 goto out_release_mem_region;
826 info->nand.controller = &info->controller;
828 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
829 info->nand.cmd_ctrl = omap_hwcontrol;
832 * If RDY/BSY line is connected to OMAP then use the omap ready
833 * funcrtion and the generic nand_wait function which reads the status
834 * register after monitoring the RDY/BSY line.Otherwise use a standard
835 * chip delay which is slightly more than tR (AC Timing) of the NAND
836 * device and read status register until you get a failure or success
838 if (pdata->dev_ready) {
839 info->nand.dev_ready = omap_dev_ready;
840 info->nand.chip_delay = 0;
842 info->nand.waitfunc = omap_wait;
843 info->nand.chip_delay = 50;
848 info->nand.read_buf = omap_read_buf_pref;
849 info->nand.write_buf = omap_write_buf_pref;
851 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
852 omap_nand_dma_cb, &info->comp, &info->dma_ch);
855 printk(KERN_WARNING "DMA request failed."
856 " Non-dma data transfer mode\n");
858 omap_set_dma_dest_burst_mode(info->dma_ch,
859 OMAP_DMA_DATA_BURST_16);
860 omap_set_dma_src_burst_mode(info->dma_ch,
861 OMAP_DMA_DATA_BURST_16);
863 info->nand.read_buf = omap_read_buf_dma_pref;
864 info->nand.write_buf = omap_write_buf_dma_pref;
868 if (info->nand.options & NAND_BUSWIDTH_16) {
869 info->nand.read_buf = omap_read_buf16;
870 info->nand.write_buf = omap_write_buf16;
872 info->nand.read_buf = omap_read_buf8;
873 info->nand.write_buf = omap_write_buf8;
876 info->nand.verify_buf = omap_verify_buf;
878 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
879 info->nand.ecc.bytes = 3;
880 info->nand.ecc.size = 512;
881 info->nand.ecc.calculate = omap_calculate_ecc;
882 info->nand.ecc.hwctl = omap_enable_hwecc;
883 info->nand.ecc.correct = omap_correct_data;
884 info->nand.ecc.mode = NAND_ECC_HW;
887 info->nand.ecc.mode = NAND_ECC_SOFT;
890 /* DIP switches on some boards change between 8 and 16 bit
891 * bus widths for flash. Try the other width if the first try fails.
893 if (nand_scan(&info->mtd, 1)) {
894 info->nand.options ^= NAND_BUSWIDTH_16;
895 if (nand_scan(&info->mtd, 1)) {
897 goto out_release_mem_region;
901 #ifdef CONFIG_MTD_PARTITIONS
902 err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
904 add_mtd_partitions(&info->mtd, info->parts, err);
905 else if (pdata->parts)
906 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
909 add_mtd_device(&info->mtd);
911 platform_set_drvdata(pdev, &info->mtd);
915 out_release_mem_region:
916 release_mem_region(info->phys_base, NAND_IO_SIZE);
923 static int omap_nand_remove(struct platform_device *pdev)
925 struct mtd_info *mtd = platform_get_drvdata(pdev);
926 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
929 platform_set_drvdata(pdev, NULL);
931 omap_free_dma(info->dma_ch);
933 /* Release NAND device, its internal structures and partitions */
934 nand_release(&info->mtd);
935 iounmap(info->nand.IO_ADDR_R);
940 static struct platform_driver omap_nand_driver = {
941 .probe = omap_nand_probe,
942 .remove = omap_nand_remove,
945 .owner = THIS_MODULE,
949 static int __init omap_nand_init(void)
951 printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
953 /* This check is required if driver is being
954 * loaded run time as a module
956 if ((1 == use_dma) && (0 == use_prefetch)) {
957 printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 "
958 "without use_prefetch'. Prefetch will not be"
959 " used in either mode (mpu or dma)\n");
961 return platform_driver_register(&omap_nand_driver);
964 static void __exit omap_nand_exit(void)
966 platform_driver_unregister(&omap_nand_driver);
969 module_init(omap_nand_init);
970 module_exit(omap_nand_exit);
972 MODULE_ALIAS(DRIVER_NAME);
973 MODULE_LICENSE("GPL");
974 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");