2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/delay.h>
14 #include <linux/jiffies.h>
15 #include <linux/sched.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
20 #include <linux/slab.h>
23 #include <plat/gpmc.h>
24 #include <plat/nand.h>
26 #define GPMC_IRQ_STATUS 0x18
27 #define GPMC_ECC_CONFIG 0x1F4
28 #define GPMC_ECC_CONTROL 0x1F8
29 #define GPMC_ECC_SIZE_CONFIG 0x1FC
30 #define GPMC_ECC1_RESULT 0x200
32 #define DRIVER_NAME "omap2-nand"
35 #define NAND_WP_BIT 0x00000010
37 #define GPMC_BUF_FULL 0x00000001
38 #define GPMC_BUF_EMPTY 0x00000000
40 #define NAND_Ecc_P1e (1 << 0)
41 #define NAND_Ecc_P2e (1 << 1)
42 #define NAND_Ecc_P4e (1 << 2)
43 #define NAND_Ecc_P8e (1 << 3)
44 #define NAND_Ecc_P16e (1 << 4)
45 #define NAND_Ecc_P32e (1 << 5)
46 #define NAND_Ecc_P64e (1 << 6)
47 #define NAND_Ecc_P128e (1 << 7)
48 #define NAND_Ecc_P256e (1 << 8)
49 #define NAND_Ecc_P512e (1 << 9)
50 #define NAND_Ecc_P1024e (1 << 10)
51 #define NAND_Ecc_P2048e (1 << 11)
53 #define NAND_Ecc_P1o (1 << 16)
54 #define NAND_Ecc_P2o (1 << 17)
55 #define NAND_Ecc_P4o (1 << 18)
56 #define NAND_Ecc_P8o (1 << 19)
57 #define NAND_Ecc_P16o (1 << 20)
58 #define NAND_Ecc_P32o (1 << 21)
59 #define NAND_Ecc_P64o (1 << 22)
60 #define NAND_Ecc_P128o (1 << 23)
61 #define NAND_Ecc_P256o (1 << 24)
62 #define NAND_Ecc_P512o (1 << 25)
63 #define NAND_Ecc_P1024o (1 << 26)
64 #define NAND_Ecc_P2048o (1 << 27)
66 #define TF(value) (value ? 1 : 0)
68 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
69 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
70 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
71 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
72 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
73 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
74 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
75 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
77 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
78 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
79 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
80 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
81 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
82 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
83 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
84 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
86 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
87 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
88 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
89 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
90 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
91 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
92 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
93 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
95 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
96 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
97 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
98 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
99 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
100 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
101 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
102 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
104 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
105 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
107 #ifdef CONFIG_MTD_PARTITIONS
108 static const char *part_probes[] = { "cmdlinepart", NULL };
111 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
112 static int use_prefetch = 1;
114 /* "modprobe ... use_prefetch=0" etc */
115 module_param(use_prefetch, bool, 0);
116 MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH");
118 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
119 static int use_dma = 1;
121 /* "modprobe ... use_dma=0" etc */
122 module_param(use_dma, bool, 0);
123 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
128 const int use_prefetch;
132 struct omap_nand_info {
133 struct nand_hw_control controller;
134 struct omap_nand_platform_data *pdata;
136 struct mtd_partition *parts;
137 struct nand_chip nand;
138 struct platform_device *pdev;
141 unsigned long phys_base;
142 void __iomem *gpmc_cs_baseaddr;
143 void __iomem *gpmc_baseaddr;
144 void __iomem *nand_pref_fifo_add;
145 struct completion comp;
150 * omap_nand_wp - This function enable or disable the Write Protect feature
151 * @mtd: MTD device structure
154 static void omap_nand_wp(struct mtd_info *mtd, int mode)
156 struct omap_nand_info *info = container_of(mtd,
157 struct omap_nand_info, mtd);
159 unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG);
162 config &= ~(NAND_WP_BIT); /* WP is ON */
164 config |= (NAND_WP_BIT); /* WP is OFF */
166 __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG));
170 * omap_hwcontrol - hardware specific access to control-lines
171 * @mtd: MTD device structure
172 * @cmd: command to device
174 * NAND_NCE: bit 0 -> don't care
175 * NAND_CLE: bit 1 -> Command Latch
176 * NAND_ALE: bit 2 -> Address Latch
178 * NOTE: boards may use different bits for these!!
180 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
182 struct omap_nand_info *info = container_of(mtd,
183 struct omap_nand_info, mtd);
185 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
186 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
187 GPMC_CS_NAND_COMMAND;
188 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
192 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
193 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
194 GPMC_CS_NAND_ADDRESS;
195 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
199 case NAND_CTRL_CHANGE | NAND_NCE:
200 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
202 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
207 if (cmd != NAND_CMD_NONE)
208 __raw_writeb(cmd, info->nand.IO_ADDR_W);
212 * omap_read_buf8 - read data from NAND controller into buffer
213 * @mtd: MTD device structure
214 * @buf: buffer to store date
215 * @len: number of bytes to read
217 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
219 struct nand_chip *nand = mtd->priv;
221 ioread8_rep(nand->IO_ADDR_R, buf, len);
225 * omap_write_buf8 - write buffer to NAND controller
226 * @mtd: MTD device structure
228 * @len: number of bytes to write
230 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
232 struct omap_nand_info *info = container_of(mtd,
233 struct omap_nand_info, mtd);
234 u_char *p = (u_char *)buf;
237 iowrite8(*p++, info->nand.IO_ADDR_W);
238 while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
239 GPMC_STATUS) & GPMC_BUF_FULL));
244 * omap_read_buf16 - read data from NAND controller into buffer
245 * @mtd: MTD device structure
246 * @buf: buffer to store date
247 * @len: number of bytes to read
249 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
251 struct nand_chip *nand = mtd->priv;
253 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
257 * omap_write_buf16 - write buffer to NAND controller
258 * @mtd: MTD device structure
260 * @len: number of bytes to write
262 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
264 struct omap_nand_info *info = container_of(mtd,
265 struct omap_nand_info, mtd);
266 u16 *p = (u16 *) buf;
268 /* FIXME try bursts of writesw() or DMA ... */
272 iowrite16(*p++, info->nand.IO_ADDR_W);
274 while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
275 GPMC_STATUS) & GPMC_BUF_FULL))
281 * omap_read_buf_pref - read data from NAND controller into buffer
282 * @mtd: MTD device structure
283 * @buf: buffer to store date
284 * @len: number of bytes to read
286 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
288 struct omap_nand_info *info = container_of(mtd,
289 struct omap_nand_info, mtd);
290 uint32_t pfpw_status = 0, r_count = 0;
294 /* take care of subpage reads */
295 for (; len % 4 != 0; ) {
296 *buf++ = __raw_readb(info->nand.IO_ADDR_R);
301 /* configure and start prefetch transfer */
302 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
304 /* PFPW engine is busy, use cpu copy method */
305 if (info->nand.options & NAND_BUSWIDTH_16)
306 omap_read_buf16(mtd, buf, len);
308 omap_read_buf8(mtd, buf, len);
311 pfpw_status = gpmc_prefetch_status();
312 r_count = ((pfpw_status >> 24) & 0x7F) >> 2;
313 ioread32_rep(info->nand_pref_fifo_add, p, r_count);
318 /* disable and stop the PFPW engine */
319 gpmc_prefetch_reset();
324 * omap_write_buf_pref - write buffer to NAND controller
325 * @mtd: MTD device structure
327 * @len: number of bytes to write
329 static void omap_write_buf_pref(struct mtd_info *mtd,
330 const u_char *buf, int len)
332 struct omap_nand_info *info = container_of(mtd,
333 struct omap_nand_info, mtd);
334 uint32_t pfpw_status = 0, w_count = 0;
336 u16 *p = (u16 *) buf;
338 /* take care of subpage writes */
340 writeb(*buf, info->nand.IO_ADDR_R);
341 p = (u16 *)(buf + 1);
345 /* configure and start prefetch transfer */
346 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
348 /* PFPW engine is busy, use cpu copy method */
349 if (info->nand.options & NAND_BUSWIDTH_16)
350 omap_write_buf16(mtd, buf, len);
352 omap_write_buf8(mtd, buf, len);
354 pfpw_status = gpmc_prefetch_status();
355 while (pfpw_status & 0x3FFF) {
356 w_count = ((pfpw_status >> 24) & 0x7F) >> 1;
357 for (i = 0; (i < w_count) && len; i++, len -= 2)
358 iowrite16(*p++, info->nand_pref_fifo_add);
359 pfpw_status = gpmc_prefetch_status();
362 /* disable and stop the PFPW engine */
363 gpmc_prefetch_reset();
367 #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
369 * omap_nand_dma_cb: callback on the completion of dma transfer
370 * @lch: logical channel
371 * @ch_satuts: channel status
372 * @data: pointer to completion data structure
374 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
376 complete((struct completion *) data);
380 * omap_nand_dma_transfer: configer and start dma transfer
381 * @mtd: MTD device structure
382 * @addr: virtual address in RAM of source/destination
383 * @len: number of data bytes to be transferred
384 * @is_write: flag for read/write operation
386 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
387 unsigned int len, int is_write)
389 struct omap_nand_info *info = container_of(mtd,
390 struct omap_nand_info, mtd);
391 uint32_t prefetch_status = 0;
392 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
397 /* The fifo depth is 64 bytes. We have a sync at each frame and frame
398 * length is 64 bytes.
400 int buf_len = len >> 6;
402 if (addr >= high_memory) {
405 if (((size_t)addr & PAGE_MASK) !=
406 ((size_t)(addr + len - 1) & PAGE_MASK))
408 p1 = vmalloc_to_page(addr);
411 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
414 dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
415 if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
416 dev_err(&info->pdev->dev,
417 "Couldn't DMA map a %d byte buffer\n", len);
422 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
423 info->phys_base, 0, 0);
424 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
426 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
427 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
428 OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
430 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
431 info->phys_base, 0, 0);
432 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
434 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
435 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
436 OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
438 /* configure and start prefetch transfer */
439 ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
441 /* PFPW engine is busy, use cpu copy methode */
444 init_completion(&info->comp);
446 omap_start_dma(info->dma_ch);
448 /* setup and start DMA using dma_addr */
449 wait_for_completion(&info->comp);
451 while (0x3fff & (prefetch_status = gpmc_prefetch_status()))
453 /* disable and stop the PFPW engine */
454 gpmc_prefetch_reset();
456 dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
460 if (info->nand.options & NAND_BUSWIDTH_16)
461 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
462 : omap_write_buf16(mtd, (u_char *) addr, len);
464 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
465 : omap_write_buf8(mtd, (u_char *) addr, len);
469 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {}
470 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
471 unsigned int len, int is_write)
478 * omap_read_buf_dma_pref - read data from NAND controller into buffer
479 * @mtd: MTD device structure
480 * @buf: buffer to store date
481 * @len: number of bytes to read
483 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
485 if (len <= mtd->oobsize)
486 omap_read_buf_pref(mtd, buf, len);
488 /* start transfer in DMA mode */
489 omap_nand_dma_transfer(mtd, buf, len, 0x0);
493 * omap_write_buf_dma_pref - write buffer to NAND controller
494 * @mtd: MTD device structure
496 * @len: number of bytes to write
498 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
499 const u_char *buf, int len)
501 if (len <= mtd->oobsize)
502 omap_write_buf_pref(mtd, buf, len);
504 /* start transfer in DMA mode */
505 omap_nand_dma_transfer(mtd, buf, len, 0x1);
509 * omap_verify_buf - Verify chip data against buffer
510 * @mtd: MTD device structure
511 * @buf: buffer containing the data to compare
512 * @len: number of bytes to compare
514 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
516 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
518 u16 *p = (u16 *) buf;
522 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
529 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
531 * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller
532 * @mtd: MTD device structure
534 static void omap_hwecc_init(struct mtd_info *mtd)
536 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
538 struct nand_chip *chip = mtd->priv;
539 unsigned long val = 0x0;
541 /* Read from ECC Control Register */
542 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL);
543 /* Clear all ECC | Enable Reg1 */
544 val = ((0x00000001<<8) | 0x00000001);
545 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
547 /* Read from ECC Size Config Register */
548 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
549 /* ECCSIZE1=512 | Select eccResultsize[0-3] */
550 val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
551 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
555 * gen_true_ecc - This function will generate true ECC value
556 * @ecc_buf: buffer to store ecc code
558 * This generated true ECC value can be used when correcting
559 * data read from NAND flash memory core
561 static void gen_true_ecc(u8 *ecc_buf)
563 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
564 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
566 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
567 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
568 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
569 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
570 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
571 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
575 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
576 * @ecc_data1: ecc code from nand spare area
577 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
578 * @page_data: page data
580 * This function compares two ECC's and indicates if there is an error.
581 * If the error can be corrected it will be corrected to the buffer.
583 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
584 u8 *ecc_data2, /* read from register */
588 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
589 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
596 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
598 gen_true_ecc(ecc_data1);
599 gen_true_ecc(ecc_data2);
601 for (i = 0; i <= 2; i++) {
602 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
603 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
606 for (i = 0; i < 8; i++) {
607 tmp0_bit[i] = *ecc_data1 % 2;
608 *ecc_data1 = *ecc_data1 / 2;
611 for (i = 0; i < 8; i++) {
612 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
613 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
616 for (i = 0; i < 8; i++) {
617 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
618 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
621 for (i = 0; i < 8; i++) {
622 comp0_bit[i] = *ecc_data2 % 2;
623 *ecc_data2 = *ecc_data2 / 2;
626 for (i = 0; i < 8; i++) {
627 comp1_bit[i] = *(ecc_data2 + 1) % 2;
628 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
631 for (i = 0; i < 8; i++) {
632 comp2_bit[i] = *(ecc_data2 + 2) % 2;
633 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
636 for (i = 0; i < 6; i++)
637 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
639 for (i = 0; i < 8; i++)
640 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
642 for (i = 0; i < 8; i++)
643 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
645 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
646 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
648 for (i = 0; i < 24; i++)
649 ecc_sum += ecc_bit[i];
653 /* Not reached because this function is not called if
654 * ECC values are equal
659 /* Uncorrectable error */
660 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
664 /* UN-Correctable error */
665 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
669 /* Correctable error */
670 find_byte = (ecc_bit[23] << 8) +
680 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
682 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
683 "offset: %d, bit: %d\n", find_byte, find_bit);
685 page_data[find_byte] ^= (1 << find_bit);
690 if (ecc_data2[0] == 0 &&
695 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
701 * omap_correct_data - Compares the ECC read with HW generated ECC
702 * @mtd: MTD device structure
704 * @read_ecc: ecc read from nand flash
705 * @calc_ecc: ecc read from HW ECC registers
707 * Compares the ecc read from nand spare area with ECC registers values
708 * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection
711 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
712 u_char *read_ecc, u_char *calc_ecc)
714 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
716 int blockCnt = 0, i = 0, ret = 0;
718 /* Ex NAND_ECC_HW12_2048 */
719 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
720 (info->nand.ecc.size == 2048))
725 for (i = 0; i < blockCnt; i++) {
726 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
727 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
739 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
740 * @mtd: MTD device structure
741 * @dat: The pointer to data on which ecc is computed
742 * @ecc_code: The ecc_code buffer
744 * Using noninverted ECC can be considered ugly since writing a blank
745 * page ie. padding will clear the ECC bytes. This is no problem as long
746 * nobody is trying to write data on the seemingly unused page. Reading
747 * an erased page will produce an ECC mismatch between generated and read
748 * ECC bytes that has to be dealt with separately.
750 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
753 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
755 unsigned long val = 0x0;
758 /* Start Reading from HW ECC1_Result = 0x200 */
759 reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
760 val = __raw_readl(reg);
761 *ecc_code++ = val; /* P128e, ..., P1e */
762 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
763 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
764 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
771 * omap_enable_hwecc - This function enables the hardware ecc functionality
772 * @mtd: MTD device structure
773 * @mode: Read/Write mode
775 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
777 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
779 struct nand_chip *chip = mtd->priv;
780 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
781 unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
785 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
786 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
787 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
789 case NAND_ECC_READSYN:
790 __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
791 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
792 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
795 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
796 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
797 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
800 DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
805 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
810 * omap_wait - wait until the command is done
811 * @mtd: MTD device structure
812 * @chip: NAND Chip structure
814 * Wait function is called during Program and erase operations and
815 * the way it is called from MTD layer, we should wait till the NAND
816 * chip is ready after the programming/erase operation has completed.
818 * Erase can take up to 400ms and program up to 20ms according to
819 * general NAND and SmartMedia specs
821 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
823 struct nand_chip *this = mtd->priv;
824 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
826 unsigned long timeo = jiffies;
827 int status = NAND_STATUS_FAIL, state = this->state;
829 if (state == FL_ERASING)
830 timeo += (HZ * 400) / 1000;
832 timeo += (HZ * 20) / 1000;
834 this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
835 GPMC_CS_NAND_COMMAND;
836 this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
838 __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
840 while (time_before(jiffies, timeo)) {
841 status = __raw_readb(this->IO_ADDR_R);
842 if (status & NAND_STATUS_READY)
850 * omap_dev_ready - calls the platform specific dev_ready function
851 * @mtd: MTD device structure
853 static int omap_dev_ready(struct mtd_info *mtd)
855 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
857 unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS);
859 if ((val & 0x100) == 0x100) {
860 /* Clear IRQ Interrupt */
863 __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS);
865 unsigned int cnt = 0;
866 while (cnt++ < 0x1FF) {
867 if ((val & 0x100) == 0x100)
869 val = __raw_readl(info->gpmc_baseaddr +
877 static int __devinit omap_nand_probe(struct platform_device *pdev)
879 struct omap_nand_info *info;
880 struct omap_nand_platform_data *pdata;
883 pdata = pdev->dev.platform_data;
885 dev_err(&pdev->dev, "platform data missing\n");
889 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
893 platform_set_drvdata(pdev, info);
895 spin_lock_init(&info->controller.lock);
896 init_waitqueue_head(&info->controller.wq);
900 info->gpmc_cs = pdata->cs;
901 info->gpmc_baseaddr = pdata->gpmc_baseaddr;
902 info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr;
903 info->phys_base = pdata->phys_base;
905 info->mtd.priv = &info->nand;
906 info->mtd.name = dev_name(&pdev->dev);
907 info->mtd.owner = THIS_MODULE;
909 info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
910 info->nand.options |= NAND_SKIP_BBTSCAN;
912 /* NAND write protect off */
913 omap_nand_wp(&info->mtd, NAND_WP_OFF);
915 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
916 pdev->dev.driver->name)) {
921 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
922 if (!info->nand.IO_ADDR_R) {
924 goto out_release_mem_region;
927 info->nand.controller = &info->controller;
929 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
930 info->nand.cmd_ctrl = omap_hwcontrol;
933 * If RDY/BSY line is connected to OMAP then use the omap ready
934 * funcrtion and the generic nand_wait function which reads the status
935 * register after monitoring the RDY/BSY line.Otherwise use a standard
936 * chip delay which is slightly more than tR (AC Timing) of the NAND
937 * device and read status register until you get a failure or success
939 if (pdata->dev_ready) {
940 info->nand.dev_ready = omap_dev_ready;
941 info->nand.chip_delay = 0;
943 info->nand.waitfunc = omap_wait;
944 info->nand.chip_delay = 50;
948 /* copy the virtual address of nand base for fifo access */
949 info->nand_pref_fifo_add = info->nand.IO_ADDR_R;
951 info->nand.read_buf = omap_read_buf_pref;
952 info->nand.write_buf = omap_write_buf_pref;
954 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
955 omap_nand_dma_cb, &info->comp, &info->dma_ch);
958 printk(KERN_WARNING "DMA request failed."
959 " Non-dma data transfer mode\n");
961 omap_set_dma_dest_burst_mode(info->dma_ch,
962 OMAP_DMA_DATA_BURST_16);
963 omap_set_dma_src_burst_mode(info->dma_ch,
964 OMAP_DMA_DATA_BURST_16);
966 info->nand.read_buf = omap_read_buf_dma_pref;
967 info->nand.write_buf = omap_write_buf_dma_pref;
971 if (info->nand.options & NAND_BUSWIDTH_16) {
972 info->nand.read_buf = omap_read_buf16;
973 info->nand.write_buf = omap_write_buf16;
975 info->nand.read_buf = omap_read_buf8;
976 info->nand.write_buf = omap_write_buf8;
979 info->nand.verify_buf = omap_verify_buf;
981 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
982 info->nand.ecc.bytes = 3;
983 info->nand.ecc.size = 512;
984 info->nand.ecc.calculate = omap_calculate_ecc;
985 info->nand.ecc.hwctl = omap_enable_hwecc;
986 info->nand.ecc.correct = omap_correct_data;
987 info->nand.ecc.mode = NAND_ECC_HW;
990 omap_hwecc_init(&info->mtd);
992 info->nand.ecc.mode = NAND_ECC_SOFT;
995 /* DIP switches on some boards change between 8 and 16 bit
996 * bus widths for flash. Try the other width if the first try fails.
998 if (nand_scan(&info->mtd, 1)) {
999 info->nand.options ^= NAND_BUSWIDTH_16;
1000 if (nand_scan(&info->mtd, 1)) {
1002 goto out_release_mem_region;
1006 #ifdef CONFIG_MTD_PARTITIONS
1007 err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
1009 add_mtd_partitions(&info->mtd, info->parts, err);
1010 else if (pdata->parts)
1011 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
1014 add_mtd_device(&info->mtd);
1016 platform_set_drvdata(pdev, &info->mtd);
1020 out_release_mem_region:
1021 release_mem_region(info->phys_base, NAND_IO_SIZE);
1028 static int omap_nand_remove(struct platform_device *pdev)
1030 struct mtd_info *mtd = platform_get_drvdata(pdev);
1031 struct omap_nand_info *info = mtd->priv;
1033 platform_set_drvdata(pdev, NULL);
1035 omap_free_dma(info->dma_ch);
1037 /* Release NAND device, its internal structures and partitions */
1038 nand_release(&info->mtd);
1039 iounmap(info->nand_pref_fifo_add);
1044 static struct platform_driver omap_nand_driver = {
1045 .probe = omap_nand_probe,
1046 .remove = omap_nand_remove,
1048 .name = DRIVER_NAME,
1049 .owner = THIS_MODULE,
1053 static int __init omap_nand_init(void)
1055 printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
1057 /* This check is required if driver is being
1058 * loaded run time as a module
1060 if ((1 == use_dma) && (0 == use_prefetch)) {
1061 printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 "
1062 "without use_prefetch'. Prefetch will not be"
1063 " used in either mode (mpu or dma)\n");
1065 return platform_driver_register(&omap_nand_driver);
1068 static void __exit omap_nand_exit(void)
1070 platform_driver_unregister(&omap_nand_driver);
1073 module_init(omap_nand_init);
1074 module_exit(omap_nand_exit);
1076 MODULE_ALIAS(DRIVER_NAME);
1077 MODULE_LICENSE("GPL");
1078 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");