drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/sched.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #include <plat/dma.h>
  24 #include <plat/gpmc.h>
  25 #include <plat/nand.h>
  26
  27 #define DRIVER_NAME     "omap2-nand"
  28 #define OMAP_NAND_TIMEOUT_MS    5000
  29
  30 #define NAND_Ecc_P1e            (1 << 0)
  31 #define NAND_Ecc_P2e            (1 << 1)
  32 #define NAND_Ecc_P4e            (1 << 2)
  33 #define NAND_Ecc_P8e            (1 << 3)
  34 #define NAND_Ecc_P16e           (1 << 4)
  35 #define NAND_Ecc_P32e           (1 << 5)
  36 #define NAND_Ecc_P64e           (1 << 6)
  37 #define NAND_Ecc_P128e          (1 << 7)
  38 #define NAND_Ecc_P256e          (1 << 8)
  39 #define NAND_Ecc_P512e          (1 << 9)
  40 #define NAND_Ecc_P1024e         (1 << 10)
  41 #define NAND_Ecc_P2048e         (1 << 11)
  42
  43 #define NAND_Ecc_P1o            (1 << 16)
  44 #define NAND_Ecc_P2o            (1 << 17)
  45 #define NAND_Ecc_P4o            (1 << 18)
  46 #define NAND_Ecc_P8o            (1 << 19)
  47 #define NAND_Ecc_P16o           (1 << 20)
  48 #define NAND_Ecc_P32o           (1 << 21)
  49 #define NAND_Ecc_P64o           (1 << 22)
  50 #define NAND_Ecc_P128o          (1 << 23)
  51 #define NAND_Ecc_P256o          (1 << 24)
  52 #define NAND_Ecc_P512o          (1 << 25)
  53 #define NAND_Ecc_P1024o         (1 << 26)
  54 #define NAND_Ecc_P2048o         (1 << 27)
  55
  56 #define TF(value)       (value ? 1 : 0)
  57
  58 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  59 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  60 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  61 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  62 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  63 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  64 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  65 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  66
  67 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  68 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  69 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  70 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  71 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  72 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  73 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  74 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  75
  76 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  77 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  78 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  79 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  80 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  81 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  82 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  83 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  84
  85 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  86 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  87 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  88 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  89 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  90 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  91 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  92 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  93
  94 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
  95 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
  96
  97 #ifdef CONFIG_MTD_PARTITIONS
  98 static const char *part_probes[] = { "cmdlinepart", NULL };
  99 #endif
 100
 101 /* oob info generated runtime depending on ecc algorithm and layout selected */
 102 static struct nand_ecclayout omap_oobinfo;
 103 /* Define some generic bad / good block scan pattern which are used
 104  * while scanning a device for factory marked good / bad blocks
 105  */
 106 static uint8_t scan_ff_pattern[] = { 0xff };
 107 static struct nand_bbt_descr bb_descrip_flashbased = {
 108         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 109         .offs = 0,
 110         .len = 1,
 111         .pattern = scan_ff_pattern,
 112 };
 113
 114
 115 struct omap_nand_info {
 116         struct nand_hw_control          controller;
 117         struct omap_nand_platform_data  *pdata;
 118         struct mtd_info                 mtd;
 119         struct mtd_partition            *parts;
 120         struct nand_chip                nand;
 121         struct platform_device          *pdev;
 122
 123         int                             gpmc_cs;
 124         unsigned long                   phys_base;
 125         struct completion               comp;
 126         int                             dma_ch;
 127         int                             gpmc_irq;
 128         enum {
 129                 OMAP_NAND_IO_READ = 0,  /* read */
 130                 OMAP_NAND_IO_WRITE,     /* write */
 131         } iomode;
 132         u_char                          *buf;
 133         int                                     buf_len;
 134 };
 135
 136 /**
 137  * omap_hwcontrol - hardware specific access to control-lines
 138  * @mtd: MTD device structure
 139  * @cmd: command to device
 140  * @ctrl:
 141  * NAND_NCE: bit 0 -> don't care
 142  * NAND_CLE: bit 1 -> Command Latch
 143  * NAND_ALE: bit 2 -> Address Latch
 144  *
 145  * NOTE: boards may use different bits for these!!
 146  */
 147 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 148 {
 149         struct omap_nand_info *info = container_of(mtd,
 150                                         struct omap_nand_info, mtd);
 151
 152         if (cmd != NAND_CMD_NONE) {
 153                 if (ctrl & NAND_CLE)
 154                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
 155
 156                 else if (ctrl & NAND_ALE)
 157                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
 158
 159                 else /* NAND_NCE */
 160                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
 161         }
 162 }
 163
 164 /**
 165  * omap_read_buf8 - read data from NAND controller into buffer
 166  * @mtd: MTD device structure
 167  * @buf: buffer to store date
 168  * @len: number of bytes to read
 169  */
 170 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 171 {
 172         struct nand_chip *nand = mtd->priv;
 173
 174         ioread8_rep(nand->IO_ADDR_R, buf, len);
 175 }
 176
 177 /**
 178  * omap_write_buf8 - write buffer to NAND controller
 179  * @mtd: MTD device structure
 180  * @buf: data buffer
 181  * @len: number of bytes to write
 182  */
 183 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 184 {
 185         struct omap_nand_info *info = container_of(mtd,
 186                                                 struct omap_nand_info, mtd);
 187         u_char *p = (u_char *)buf;
 188         u32     status = 0;
 189
 190         while (len--) {
 191                 iowrite8(*p++, info->nand.IO_ADDR_W);
 192                 /* wait until buffer is available for write */
 193                 do {
 194                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 195                 } while (!status);
 196         }
 197 }
 198
 199 /**
 200  * omap_read_buf16 - read data from NAND controller into buffer
 201  * @mtd: MTD device structure
 202  * @buf: buffer to store date
 203  * @len: number of bytes to read
 204  */
 205 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 206 {
 207         struct nand_chip *nand = mtd->priv;
 208
 209         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 210 }
 211
 212 /**
 213  * omap_write_buf16 - write buffer to NAND controller
 214  * @mtd: MTD device structure
 215  * @buf: data buffer
 216  * @len: number of bytes to write
 217  */
 218 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 219 {
 220         struct omap_nand_info *info = container_of(mtd,
 221                                                 struct omap_nand_info, mtd);
 222         u16 *p = (u16 *) buf;
 223         u32     status = 0;
 224         /* FIXME try bursts of writesw() or DMA ... */
 225         len >>= 1;
 226
 227         while (len--) {
 228                 iowrite16(*p++, info->nand.IO_ADDR_W);
 229                 /* wait until buffer is available for write */
 230                 do {
 231                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 232                 } while (!status);
 233         }
 234 }
 235
 236 /**
 237  * omap_read_buf_pref - read data from NAND controller into buffer
 238  * @mtd: MTD device structure
 239  * @buf: buffer to store date
 240  * @len: number of bytes to read
 241  */
 242 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 243 {
 244         struct omap_nand_info *info = container_of(mtd,
 245                                                 struct omap_nand_info, mtd);
 246         uint32_t r_count = 0;
 247         int ret = 0;
 248         u32 *p = (u32 *)buf;
 249
 250         /* take care of subpage reads */
 251         if (len % 4) {
 252                 if (info->nand.options & NAND_BUSWIDTH_16)
 253                         omap_read_buf16(mtd, buf, len % 4);
 254                 else
 255                         omap_read_buf8(mtd, buf, len % 4);
 256                 p = (u32 *) (buf + len % 4);
 257                 len -= len % 4;
 258         }
 259
 260         /* configure and start prefetch transfer */
 261         ret = gpmc_prefetch_enable(info->gpmc_cs,
 262                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
 263         if (ret) {
 264                 /* PFPW engine is busy, use cpu copy method */
 265                 if (info->nand.options & NAND_BUSWIDTH_16)
 266                         omap_read_buf16(mtd, buf, len);
 267                 else
 268                         omap_read_buf8(mtd, buf, len);
 269         } else {
 270                 p = (u32 *) buf;
 271                 do {
 272                         r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 273                         r_count = r_count >> 2;
 274                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 275                         p += r_count;
 276                         len -= r_count << 2;
 277                 } while (len);
 278                 /* disable and stop the PFPW engine */
 279                 gpmc_prefetch_reset(info->gpmc_cs);
 280         }
 281 }
 282
 283 /**
 284  * omap_write_buf_pref - write buffer to NAND controller
 285  * @mtd: MTD device structure
 286  * @buf: data buffer
 287  * @len: number of bytes to write
 288  */
 289 static void omap_write_buf_pref(struct mtd_info *mtd,
 290                                         const u_char *buf, int len)
 291 {
 292         struct omap_nand_info *info = container_of(mtd,
 293                                                 struct omap_nand_info, mtd);
 294         uint32_t w_count = 0;
 295         int i = 0, ret = 0;
 296         u16 *p;
 297         unsigned long tim, limit;
 298
 299         /* take care of subpage writes */
 300         if (len % 2 != 0) {
 301                 writeb(*buf, info->nand.IO_ADDR_W);
 302                 p = (u16 *)(buf + 1);
 303                 len--;
 304         }
 305
 306         /*  configure and start prefetch transfer */
 307         ret = gpmc_prefetch_enable(info->gpmc_cs,
 308                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
 309         if (ret) {
 310                 /* PFPW engine is busy, use cpu copy method */
 311                 if (info->nand.options & NAND_BUSWIDTH_16)
 312                         omap_write_buf16(mtd, buf, len);
 313                 else
 314                         omap_write_buf8(mtd, buf, len);
 315         } else {
 316                 p = (u16 *) buf;
 317                 while (len) {
 318                         w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 319                         w_count = w_count >> 1;
 320                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 321                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 322                 }
 323                 /* wait for data to flushed-out before reset the prefetch */
 324                 tim = 0;
 325                 limit = (loops_per_jiffy *
 326                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 327                 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 328                         cpu_relax();
 329
 330                 /* disable and stop the PFPW engine */
 331                 gpmc_prefetch_reset(info->gpmc_cs);
 332         }
 333 }
 334
 335 /*
 336  * omap_nand_dma_cb: callback on the completion of dma transfer
 337  * @lch: logical channel
 338  * @ch_satuts: channel status
 339  * @data: pointer to completion data structure
 340  */
 341 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
 342 {
 343         complete((struct completion *) data);
 344 }
 345
 346 /*
 347  * omap_nand_dma_transfer: configer and start dma transfer
 348  * @mtd: MTD device structure
 349  * @addr: virtual address in RAM of source/destination
 350  * @len: number of data bytes to be transferred
 351  * @is_write: flag for read/write operation
 352  */
 353 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 354                                         unsigned int len, int is_write)
 355 {
 356         struct omap_nand_info *info = container_of(mtd,
 357                                         struct omap_nand_info, mtd);
 358         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 359                                                         DMA_FROM_DEVICE;
 360         dma_addr_t dma_addr;
 361         int ret;
 362         unsigned long tim, limit;
 363
 364         /* The fifo depth is 64 bytes max.
 365          * But configure the FIFO-threahold to 32 to get a sync at each frame
 366          * and frame length is 32 bytes.
 367          */
 368         int buf_len = len >> 6;
 369
 370         if (addr >= high_memory) {
 371                 struct page *p1;
 372
 373                 if (((size_t)addr & PAGE_MASK) !=
 374                         ((size_t)(addr + len - 1) & PAGE_MASK))
 375                         goto out_copy;
 376                 p1 = vmalloc_to_page(addr);
 377                 if (!p1)
 378                         goto out_copy;
 379                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 380         }
 381
 382         dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
 383         if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
 384                 dev_err(&info->pdev->dev,
 385                         "Couldn't DMA map a %d byte buffer\n", len);
 386                 goto out_copy;
 387         }
 388
 389         if (is_write) {
 390             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 391                                                 info->phys_base, 0, 0);
 392             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 393                                                         dma_addr, 0, 0);
 394             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 395                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 396                                         OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
 397         } else {
 398             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 399                                                 info->phys_base, 0, 0);
 400             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 401                                                         dma_addr, 0, 0);
 402             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 403                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 404                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
 405         }
 406         /*  configure and start prefetch transfer */
 407         ret = gpmc_prefetch_enable(info->gpmc_cs,
 408                         PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
 409         if (ret)
 410                 /* PFPW engine is busy, use cpu copy method */
 411                 goto out_copy;
 412
 413         init_completion(&info->comp);
 414
 415         omap_start_dma(info->dma_ch);
 416
 417         /* setup and start DMA using dma_addr */
 418         wait_for_completion(&info->comp);
 419         tim = 0;
 420         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 421         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 422                 cpu_relax();
 423
 424         /* disable and stop the PFPW engine */
 425         gpmc_prefetch_reset(info->gpmc_cs);
 426
 427         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 428         return 0;
 429
 430 out_copy:
 431         if (info->nand.options & NAND_BUSWIDTH_16)
 432                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 433                         : omap_write_buf16(mtd, (u_char *) addr, len);
 434         else
 435                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 436                         : omap_write_buf8(mtd, (u_char *) addr, len);
 437         return 0;
 438 }
 439
 440 /**
 441  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 442  * @mtd: MTD device structure
 443  * @buf: buffer to store date
 444  * @len: number of bytes to read
 445  */
 446 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 447 {
 448         if (len <= mtd->oobsize)
 449                 omap_read_buf_pref(mtd, buf, len);
 450         else
 451                 /* start transfer in DMA mode */
 452                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 453 }
 454
 455 /**
 456  * omap_write_buf_dma_pref - write buffer to NAND controller
 457  * @mtd: MTD device structure
 458  * @buf: data buffer
 459  * @len: number of bytes to write
 460  */
 461 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 462                                         const u_char *buf, int len)
 463 {
 464         if (len <= mtd->oobsize)
 465                 omap_write_buf_pref(mtd, buf, len);
 466         else
 467                 /* start transfer in DMA mode */
 468                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 469 }
 470
 471 /*
 472  * omap_nand_irq - GMPC irq handler
 473  * @this_irq: gpmc irq number
 474  * @dev: omap_nand_info structure pointer is passed here
 475  */
 476 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 477 {
 478         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 479         u32 bytes;
 480         u32 irq_stat;
 481
 482         irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 483         bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 484         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 485         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 486                 if (irq_stat & 0x2)
 487                         goto done;
 488
 489                 if (info->buf_len && (info->buf_len < bytes))
 490                         bytes = info->buf_len;
 491                 else if (!info->buf_len)
 492                         bytes = 0;
 493                 iowrite32_rep(info->nand.IO_ADDR_W,
 494                                                 (u32 *)info->buf, bytes >> 2);
 495                 info->buf = info->buf + bytes;
 496                 info->buf_len -= bytes;
 497
 498         } else {
 499                 ioread32_rep(info->nand.IO_ADDR_R,
 500                                                 (u32 *)info->buf, bytes >> 2);
 501                 info->buf = info->buf + bytes;
 502
 503                 if (irq_stat & 0x2)
 504                         goto done;
 505         }
 506         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 507
 508         return IRQ_HANDLED;
 509
 510 done:
 511         complete(&info->comp);
 512         /* disable irq */
 513         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 514
 515         /* clear status */
 516         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 517
 518         return IRQ_HANDLED;
 519 }
 520
 521 /*
 522  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 523  * @mtd: MTD device structure
 524  * @buf: buffer to store date
 525  * @len: number of bytes to read
 526  */
 527 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 528 {
 529         struct omap_nand_info *info = container_of(mtd,
 530                                                 struct omap_nand_info, mtd);
 531         int ret = 0;
 532
 533         if (len <= mtd->oobsize) {
 534                 omap_read_buf_pref(mtd, buf, len);
 535                 return;
 536         }
 537
 538         info->iomode = OMAP_NAND_IO_READ;
 539         info->buf = buf;
 540         init_completion(&info->comp);
 541
 542         /*  configure and start prefetch transfer */
 543         ret = gpmc_prefetch_enable(info->gpmc_cs,
 544                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
 545         if (ret)
 546                 /* PFPW engine is busy, use cpu copy method */
 547                 goto out_copy;
 548
 549         info->buf_len = len;
 550         /* enable irq */
 551         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 552                 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 553
 554         /* waiting for read to complete */
 555         wait_for_completion(&info->comp);
 556
 557         /* disable and stop the PFPW engine */
 558         gpmc_prefetch_reset(info->gpmc_cs);
 559         return;
 560
 561 out_copy:
 562         if (info->nand.options & NAND_BUSWIDTH_16)
 563                 omap_read_buf16(mtd, buf, len);
 564         else
 565                 omap_read_buf8(mtd, buf, len);
 566 }
 567
 568 /*
 569  * omap_write_buf_irq_pref - write buffer to NAND controller
 570  * @mtd: MTD device structure
 571  * @buf: data buffer
 572  * @len: number of bytes to write
 573  */
 574 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 575                                         const u_char *buf, int len)
 576 {
 577         struct omap_nand_info *info = container_of(mtd,
 578                                                 struct omap_nand_info, mtd);
 579         int ret = 0;
 580         unsigned long tim, limit;
 581
 582         if (len <= mtd->oobsize) {
 583                 omap_write_buf_pref(mtd, buf, len);
 584                 return;
 585         }
 586
 587         info->iomode = OMAP_NAND_IO_WRITE;
 588         info->buf = (u_char *) buf;
 589         init_completion(&info->comp);
 590
 591         /* configure and start prefetch transfer : size=24 */
 592         ret = gpmc_prefetch_enable(info->gpmc_cs,
 593                         (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
 594         if (ret)
 595                 /* PFPW engine is busy, use cpu copy method */
 596                 goto out_copy;
 597
 598         info->buf_len = len;
 599         /* enable irq */
 600         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 601                         (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 602
 603         /* waiting for write to complete */
 604         wait_for_completion(&info->comp);
 605         /* wait for data to flushed-out before reset the prefetch */
 606         tim = 0;
 607         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 608         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 609                 cpu_relax();
 610
 611         /* disable and stop the PFPW engine */
 612         gpmc_prefetch_reset(info->gpmc_cs);
 613         return;
 614
 615 out_copy:
 616         if (info->nand.options & NAND_BUSWIDTH_16)
 617                 omap_write_buf16(mtd, buf, len);
 618         else
 619                 omap_write_buf8(mtd, buf, len);
 620 }
 621
 622 /**
 623  * omap_verify_buf - Verify chip data against buffer
 624  * @mtd: MTD device structure
 625  * @buf: buffer containing the data to compare
 626  * @len: number of bytes to compare
 627  */
 628 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 629 {
 630         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 631                                                         mtd);
 632         u16 *p = (u16 *) buf;
 633
 634         len >>= 1;
 635         while (len--) {
 636                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 637                         return -EFAULT;
 638         }
 639
 640         return 0;
 641 }
 642
 643 /**
 644  * gen_true_ecc - This function will generate true ECC value
 645  * @ecc_buf: buffer to store ecc code
 646  *
 647  * This generated true ECC value can be used when correcting
 648  * data read from NAND flash memory core
 649  */
 650 static void gen_true_ecc(u8 *ecc_buf)
 651 {
 652         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 653                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 654
 655         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 656                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 657         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 658                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 659         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 660                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 661 }
 662
 663 /**
 664  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 665  * @ecc_data1:  ecc code from nand spare area
 666  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 667  * @page_data:  page data
 668  *
 669  * This function compares two ECC's and indicates if there is an error.
 670  * If the error can be corrected it will be corrected to the buffer.
 671  */
 672 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 673                             u8 *ecc_data2,      /* read from register */
 674                             u8 *page_data)
 675 {
 676         uint    i;
 677         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 678         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 679         u8      ecc_bit[24];
 680         u8      ecc_sum = 0;
 681         u8      find_bit = 0;
 682         uint    find_byte = 0;
 683         int     isEccFF;
 684
 685         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 686
 687         gen_true_ecc(ecc_data1);
 688         gen_true_ecc(ecc_data2);
 689
 690         for (i = 0; i <= 2; i++) {
 691                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 692                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 693         }
 694
 695         for (i = 0; i < 8; i++) {
 696                 tmp0_bit[i]     = *ecc_data1 % 2;
 697                 *ecc_data1      = *ecc_data1 / 2;
 698         }
 699
 700         for (i = 0; i < 8; i++) {
 701                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 702                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 703         }
 704
 705         for (i = 0; i < 8; i++) {
 706                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 707                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 708         }
 709
 710         for (i = 0; i < 8; i++) {
 711                 comp0_bit[i]     = *ecc_data2 % 2;
 712                 *ecc_data2       = *ecc_data2 / 2;
 713         }
 714
 715         for (i = 0; i < 8; i++) {
 716                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 717                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 718         }
 719
 720         for (i = 0; i < 8; i++) {
 721                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 722                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 723         }
 724
 725         for (i = 0; i < 6; i++)
 726                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 727
 728         for (i = 0; i < 8; i++)
 729                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 730
 731         for (i = 0; i < 8; i++)
 732                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 733
 734         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 735         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 736
 737         for (i = 0; i < 24; i++)
 738                 ecc_sum += ecc_bit[i];
 739
 740         switch (ecc_sum) {
 741         case 0:
 742                 /* Not reached because this function is not called if
 743                  *  ECC values are equal
 744                  */
 745                 return 0;
 746
 747         case 1:
 748                 /* Uncorrectable error */
 749                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 750                 return -1;
 751
 752         case 11:
 753                 /* UN-Correctable error */
 754                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
 755                 return -1;
 756
 757         case 12:
 758                 /* Correctable error */
 759                 find_byte = (ecc_bit[23] << 8) +
 760                             (ecc_bit[21] << 7) +
 761                             (ecc_bit[19] << 6) +
 762                             (ecc_bit[17] << 5) +
 763                             (ecc_bit[15] << 4) +
 764                             (ecc_bit[13] << 3) +
 765                             (ecc_bit[11] << 2) +
 766                             (ecc_bit[9]  << 1) +
 767                             ecc_bit[7];
 768
 769                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 770
 771                 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
 772                                 "offset: %d, bit: %d\n", find_byte, find_bit);
 773
 774                 page_data[find_byte] ^= (1 << find_bit);
 775
 776                 return 0;
 777         default:
 778                 if (isEccFF) {
 779                         if (ecc_data2[0] == 0 &&
 780                             ecc_data2[1] == 0 &&
 781                             ecc_data2[2] == 0)
 782                                 return 0;
 783                 }
 784                 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
 785                 return -1;
 786         }
 787 }
 788
 789 /**
 790  * omap_correct_data - Compares the ECC read with HW generated ECC
 791  * @mtd: MTD device structure
 792  * @dat: page data
 793  * @read_ecc: ecc read from nand flash
 794  * @calc_ecc: ecc read from HW ECC registers
 795  *
 796  * Compares the ecc read from nand spare area with ECC registers values
 797  * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection
 798  * and correction.
 799  */
 800 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 801                                 u_char *read_ecc, u_char *calc_ecc)
 802 {
 803         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 804                                                         mtd);
 805         int blockCnt = 0, i = 0, ret = 0;
 806
 807         /* Ex NAND_ECC_HW12_2048 */
 808         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 809                         (info->nand.ecc.size  == 2048))
 810                 blockCnt = 4;
 811         else
 812                 blockCnt = 1;
 813
 814         for (i = 0; i < blockCnt; i++) {
 815                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 816                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 817                         if (ret < 0)
 818                                 return ret;
 819                 }
 820                 read_ecc += 3;
 821                 calc_ecc += 3;
 822                 dat      += 512;
 823         }
 824         return 0;
 825 }
 826
 827 /**
 828  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 829  * @mtd: MTD device structure
 830  * @dat: The pointer to data on which ecc is computed
 831  * @ecc_code: The ecc_code buffer
 832  *
 833  * Using noninverted ECC can be considered ugly since writing a blank
 834  * page ie. padding will clear the ECC bytes. This is no problem as long
 835  * nobody is trying to write data on the seemingly unused page. Reading
 836  * an erased page will produce an ECC mismatch between generated and read
 837  * ECC bytes that has to be dealt with separately.
 838  */
 839 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 840                                 u_char *ecc_code)
 841 {
 842         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 843                                                         mtd);
 844         return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 845 }
 846
 847 /**
 848  * omap_enable_hwecc - This function enables the hardware ecc functionality
 849  * @mtd: MTD device structure
 850  * @mode: Read/Write mode
 851  */
 852 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 853 {
 854         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 855                                                         mtd);
 856         struct nand_chip *chip = mtd->priv;
 857         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 858
 859         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 860 }
 861
 862 /**
 863  * omap_wait - wait until the command is done
 864  * @mtd: MTD device structure
 865  * @chip: NAND Chip structure
 866  *
 867  * Wait function is called during Program and erase operations and
 868  * the way it is called from MTD layer, we should wait till the NAND
 869  * chip is ready after the programming/erase operation has completed.
 870  *
 871  * Erase can take up to 400ms and program up to 20ms according to
 872  * general NAND and SmartMedia specs
 873  */
 874 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 875 {
 876         struct nand_chip *this = mtd->priv;
 877         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 878                                                         mtd);
 879         unsigned long timeo = jiffies;
 880         int status = NAND_STATUS_FAIL, state = this->state;
 881
 882         if (state == FL_ERASING)
 883                 timeo += (HZ * 400) / 1000;
 884         else
 885                 timeo += (HZ * 20) / 1000;
 886
 887         gpmc_nand_write(info->gpmc_cs,
 888                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 889         while (time_before(jiffies, timeo)) {
 890                 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 891                 if (status & NAND_STATUS_READY)
 892                         break;
 893                 cond_resched();
 894         }
 895         return status;
 896 }
 897
 898 /**
 899  * omap_dev_ready - calls the platform specific dev_ready function
 900  * @mtd: MTD device structure
 901  */
 902 static int omap_dev_ready(struct mtd_info *mtd)
 903 {
 904         unsigned int val = 0;
 905         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 906                                                         mtd);
 907
 908         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 909         if ((val & 0x100) == 0x100) {
 910                 /* Clear IRQ Interrupt */
 911                 val |= 0x100;
 912                 val &= ~(0x0);
 913                 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
 914         } else {
 915                 unsigned int cnt = 0;
 916                 while (cnt++ < 0x1FF) {
 917                         if  ((val & 0x100) == 0x100)
 918                                 return 0;
 919                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 920                 }
 921         }
 922
 923         return 1;
 924 }
 925
 926 static int __devinit omap_nand_probe(struct platform_device *pdev)
 927 {
 928         struct omap_nand_info           *info;
 929         struct omap_nand_platform_data  *pdata;
 930         int                             err;
 931         int                             i, offset;
 932
 933         pdata = pdev->dev.platform_data;
 934         if (pdata == NULL) {
 935                 dev_err(&pdev->dev, "platform data missing\n");
 936                 return -ENODEV;
 937         }
 938
 939         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
 940         if (!info)
 941                 return -ENOMEM;
 942
 943         platform_set_drvdata(pdev, info);
 944
 945         spin_lock_init(&info->controller.lock);
 946         init_waitqueue_head(&info->controller.wq);
 947
 948         info->pdev = pdev;
 949
 950         info->gpmc_cs           = pdata->cs;
 951         info->phys_base         = pdata->phys_base;
 952
 953         info->mtd.priv          = &info->nand;
 954         info->mtd.name          = dev_name(&pdev->dev);
 955         info->mtd.owner         = THIS_MODULE;
 956
 957         info->nand.options      = pdata->devsize;
 958         info->nand.options      |= NAND_SKIP_BBTSCAN;
 959
 960         /* NAND write protect off */
 961         gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 962
 963         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
 964                                 pdev->dev.driver->name)) {
 965                 err = -EBUSY;
 966                 goto out_free_info;
 967         }
 968
 969         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
 970         if (!info->nand.IO_ADDR_R) {
 971                 err = -ENOMEM;
 972                 goto out_release_mem_region;
 973         }
 974
 975         info->nand.controller = &info->controller;
 976
 977         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
 978         info->nand.cmd_ctrl  = omap_hwcontrol;
 979
 980         /*
 981          * If RDY/BSY line is connected to OMAP then use the omap ready
 982          * funcrtion and the generic nand_wait function which reads the status
 983          * register after monitoring the RDY/BSY line.Otherwise use a standard
 984          * chip delay which is slightly more than tR (AC Timing) of the NAND
 985          * device and read status register until you get a failure or success
 986          */
 987         if (pdata->dev_ready) {
 988                 info->nand.dev_ready = omap_dev_ready;
 989                 info->nand.chip_delay = 0;
 990         } else {
 991                 info->nand.waitfunc = omap_wait;
 992                 info->nand.chip_delay = 50;
 993         }
 994
 995         switch (pdata->xfer_type) {
 996         case NAND_OMAP_PREFETCH_POLLED:
 997                 info->nand.read_buf   = omap_read_buf_pref;
 998                 info->nand.write_buf  = omap_write_buf_pref;
 999                 break;
1000
1001         case NAND_OMAP_POLLED:
1002                 if (info->nand.options & NAND_BUSWIDTH_16) {
1003                         info->nand.read_buf   = omap_read_buf16;
1004                         info->nand.write_buf  = omap_write_buf16;
1005                 } else {
1006                         info->nand.read_buf   = omap_read_buf8;
1007                         info->nand.write_buf  = omap_write_buf8;
1008                 }
1009                 break;
1010
1011         case NAND_OMAP_PREFETCH_DMA:
1012                 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1013                                 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1014                 if (err < 0) {
1015                         info->dma_ch = -1;
1016                         dev_err(&pdev->dev, "DMA request failed!\n");
1017                         goto out_release_mem_region;
1018                 } else {
1019                         omap_set_dma_dest_burst_mode(info->dma_ch,
1020                                         OMAP_DMA_DATA_BURST_16);
1021                         omap_set_dma_src_burst_mode(info->dma_ch,
1022                                         OMAP_DMA_DATA_BURST_16);
1023
1024                         info->nand.read_buf   = omap_read_buf_dma_pref;
1025                         info->nand.write_buf  = omap_write_buf_dma_pref;
1026                 }
1027                 break;
1028
1029         case NAND_OMAP_PREFETCH_IRQ:
1030                 err = request_irq(pdata->gpmc_irq,
1031                                 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1032                 if (err) {
1033                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1034                                                         pdata->gpmc_irq, err);
1035                         goto out_release_mem_region;
1036                 } else {
1037                         info->gpmc_irq       = pdata->gpmc_irq;
1038                         info->nand.read_buf  = omap_read_buf_irq_pref;
1039                         info->nand.write_buf = omap_write_buf_irq_pref;
1040                 }
1041                 break;
1042
1043         default:
1044                 dev_err(&pdev->dev,
1045                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1046                 err = -EINVAL;
1047                 goto out_release_mem_region;
1048         }
1049
1050         info->nand.verify_buf = omap_verify_buf;
1051
1052         /* selsect the ecc type */
1053         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1054                 info->nand.ecc.mode = NAND_ECC_SOFT;
1055         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1056                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1057                 info->nand.ecc.bytes            = 3;
1058                 info->nand.ecc.size             = 512;
1059                 info->nand.ecc.calculate        = omap_calculate_ecc;
1060                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1061                 info->nand.ecc.correct          = omap_correct_data;
1062                 info->nand.ecc.mode             = NAND_ECC_HW;
1063         }
1064
1065         /* DIP switches on some boards change between 8 and 16 bit
1066          * bus widths for flash.  Try the other width if the first try fails.
1067          */
1068         if (nand_scan(&info->mtd, 1)) {
1069                 info->nand.options ^= NAND_BUSWIDTH_16;
1070                 if (nand_scan(&info->mtd, 1)) {
1071                         err = -ENXIO;
1072                         goto out_release_mem_region;
1073                 }
1074         }
1075
1076         /* rom code layout */
1077         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1078
1079                 if (info->nand.options & NAND_BUSWIDTH_16)
1080                         offset = 2;
1081                 else {
1082                         offset = 1;
1083                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1084                 }
1085                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1086                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1087                         omap_oobinfo.eccpos[i] = i+offset;
1088
1089                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1090                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1091                                         (offset + omap_oobinfo.eccbytes);
1092
1093                 info->nand.ecc.layout = &omap_oobinfo;
1094         }
1095
1096 #ifdef CONFIG_MTD_PARTITIONS
1097         err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
1098         if (err > 0)
1099                 add_mtd_partitions(&info->mtd, info->parts, err);
1100         else if (pdata->parts)
1101                 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
1102         else
1103 #endif
1104                 add_mtd_device(&info->mtd);
1105
1106         platform_set_drvdata(pdev, &info->mtd);
1107
1108         return 0;
1109
1110 out_release_mem_region:
1111         release_mem_region(info->phys_base, NAND_IO_SIZE);
1112 out_free_info:
1113         kfree(info);
1114
1115         return err;
1116 }
1117
1118 static int omap_nand_remove(struct platform_device *pdev)
1119 {
1120         struct mtd_info *mtd = platform_get_drvdata(pdev);
1121         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1122                                                         mtd);
1123
1124         platform_set_drvdata(pdev, NULL);
1125         if (info->dma_ch != -1)
1126                 omap_free_dma(info->dma_ch);
1127
1128         if (info->gpmc_irq)
1129                 free_irq(info->gpmc_irq, info);
1130
1131         /* Release NAND device, its internal structures and partitions */
1132         nand_release(&info->mtd);
1133         iounmap(info->nand.IO_ADDR_R);
1134         kfree(&info->mtd);
1135         return 0;
1136 }
1137
1138 static struct platform_driver omap_nand_driver = {
1139         .probe          = omap_nand_probe,
1140         .remove         = omap_nand_remove,
1141         .driver         = {
1142                 .name   = DRIVER_NAME,
1143                 .owner  = THIS_MODULE,
1144         },
1145 };
1146
1147 static int __init omap_nand_init(void)
1148 {
1149         pr_info("%s driver initializing\n", DRIVER_NAME);
1150
1151         return platform_driver_register(&omap_nand_driver);
1152 }
1153
1154 static void __exit omap_nand_exit(void)
1155 {
1156         platform_driver_unregister(&omap_nand_driver);
1157 }
1158
1159 module_init(omap_nand_init);
1160 module_exit(omap_nand_exit);
1161
1162 MODULE_ALIAS("platform:" DRIVER_NAME);
1163 MODULE_LICENSE("GPL");
1164 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");