drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/sched.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/nand.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23
  24 #ifdef CONFIG_MTD_NAND_OMAP_BCH
  25 #include <linux/bch.h>
  26 #endif
  27
  28 #include <plat/dma.h>
  29 #include <plat/gpmc.h>
  30 #include <plat/nand.h>
  31
  32 #define DRIVER_NAME     "omap2-nand"
  33 #define OMAP_NAND_TIMEOUT_MS    5000
  34
  35 #define NAND_Ecc_P1e            (1 << 0)
  36 #define NAND_Ecc_P2e            (1 << 1)
  37 #define NAND_Ecc_P4e            (1 << 2)
  38 #define NAND_Ecc_P8e            (1 << 3)
  39 #define NAND_Ecc_P16e           (1 << 4)
  40 #define NAND_Ecc_P32e           (1 << 5)
  41 #define NAND_Ecc_P64e           (1 << 6)
  42 #define NAND_Ecc_P128e          (1 << 7)
  43 #define NAND_Ecc_P256e          (1 << 8)
  44 #define NAND_Ecc_P512e          (1 << 9)
  45 #define NAND_Ecc_P1024e         (1 << 10)
  46 #define NAND_Ecc_P2048e         (1 << 11)
  47
  48 #define NAND_Ecc_P1o            (1 << 16)
  49 #define NAND_Ecc_P2o            (1 << 17)
  50 #define NAND_Ecc_P4o            (1 << 18)
  51 #define NAND_Ecc_P8o            (1 << 19)
  52 #define NAND_Ecc_P16o           (1 << 20)
  53 #define NAND_Ecc_P32o           (1 << 21)
  54 #define NAND_Ecc_P64o           (1 << 22)
  55 #define NAND_Ecc_P128o          (1 << 23)
  56 #define NAND_Ecc_P256o          (1 << 24)
  57 #define NAND_Ecc_P512o          (1 << 25)
  58 #define NAND_Ecc_P1024o         (1 << 26)
  59 #define NAND_Ecc_P2048o         (1 << 27)
  60
  61 #define TF(value)       (value ? 1 : 0)
  62
  63 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  64 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  65 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  66 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  67 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  68 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  69 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  70 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  71
  72 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  73 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  74 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  75 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  76 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  77 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  78 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  79 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  80
  81 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  82 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  83 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  84 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  85 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  86 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  87 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  88 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  89
  90 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  91 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  92 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  93 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  94 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  95 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  96 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  97 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  98
  99 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 100 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 101
 102 /* oob info generated runtime depending on ecc algorithm and layout selected */
 103 static struct nand_ecclayout omap_oobinfo;
 104 /* Define some generic bad / good block scan pattern which are used
 105  * while scanning a device for factory marked good / bad blocks
 106  */
 107 static uint8_t scan_ff_pattern[] = { 0xff };
 108 static struct nand_bbt_descr bb_descrip_flashbased = {
 109         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 110         .offs = 0,
 111         .len = 1,
 112         .pattern = scan_ff_pattern,
 113 };
 114
 115
 116 struct omap_nand_info {
 117         struct nand_hw_control          controller;
 118         struct omap_nand_platform_data  *pdata;
 119         struct mtd_info                 mtd;
 120         struct nand_chip                nand;
 121         struct platform_device          *pdev;
 122
 123         int                             gpmc_cs;
 124         unsigned long                   phys_base;
 125         struct completion               comp;
 126         int                             dma_ch;
 127         int                             gpmc_irq;
 128         enum {
 129                 OMAP_NAND_IO_READ = 0,  /* read */
 130                 OMAP_NAND_IO_WRITE,     /* write */
 131         } iomode;
 132         u_char                          *buf;
 133         int                                     buf_len;
 134
 135 #ifdef CONFIG_MTD_NAND_OMAP_BCH
 136         struct bch_control             *bch;
 137         struct nand_ecclayout           ecclayout;
 138 #endif
 139 };
 140
 141 /**
 142  * omap_hwcontrol - hardware specific access to control-lines
 143  * @mtd: MTD device structure
 144  * @cmd: command to device
 145  * @ctrl:
 146  * NAND_NCE: bit 0 -> don't care
 147  * NAND_CLE: bit 1 -> Command Latch
 148  * NAND_ALE: bit 2 -> Address Latch
 149  *
 150  * NOTE: boards may use different bits for these!!
 151  */
 152 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 153 {
 154         struct omap_nand_info *info = container_of(mtd,
 155                                         struct omap_nand_info, mtd);
 156
 157         if (cmd != NAND_CMD_NONE) {
 158                 if (ctrl & NAND_CLE)
 159                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
 160
 161                 else if (ctrl & NAND_ALE)
 162                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
 163
 164                 else /* NAND_NCE */
 165                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
 166         }
 167 }
 168
 169 /**
 170  * omap_read_buf8 - read data from NAND controller into buffer
 171  * @mtd: MTD device structure
 172  * @buf: buffer to store date
 173  * @len: number of bytes to read
 174  */
 175 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 176 {
 177         struct nand_chip *nand = mtd->priv;
 178
 179         ioread8_rep(nand->IO_ADDR_R, buf, len);
 180 }
 181
 182 /**
 183  * omap_write_buf8 - write buffer to NAND controller
 184  * @mtd: MTD device structure
 185  * @buf: data buffer
 186  * @len: number of bytes to write
 187  */
 188 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 189 {
 190         struct omap_nand_info *info = container_of(mtd,
 191                                                 struct omap_nand_info, mtd);
 192         u_char *p = (u_char *)buf;
 193         u32     status = 0;
 194
 195         while (len--) {
 196                 iowrite8(*p++, info->nand.IO_ADDR_W);
 197                 /* wait until buffer is available for write */
 198                 do {
 199                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 200                 } while (!status);
 201         }
 202 }
 203
 204 /**
 205  * omap_read_buf16 - read data from NAND controller into buffer
 206  * @mtd: MTD device structure
 207  * @buf: buffer to store date
 208  * @len: number of bytes to read
 209  */
 210 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 211 {
 212         struct nand_chip *nand = mtd->priv;
 213
 214         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 215 }
 216
 217 /**
 218  * omap_write_buf16 - write buffer to NAND controller
 219  * @mtd: MTD device structure
 220  * @buf: data buffer
 221  * @len: number of bytes to write
 222  */
 223 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 224 {
 225         struct omap_nand_info *info = container_of(mtd,
 226                                                 struct omap_nand_info, mtd);
 227         u16 *p = (u16 *) buf;
 228         u32     status = 0;
 229         /* FIXME try bursts of writesw() or DMA ... */
 230         len >>= 1;
 231
 232         while (len--) {
 233                 iowrite16(*p++, info->nand.IO_ADDR_W);
 234                 /* wait until buffer is available for write */
 235                 do {
 236                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 237                 } while (!status);
 238         }
 239 }
 240
 241 /**
 242  * omap_read_buf_pref - read data from NAND controller into buffer
 243  * @mtd: MTD device structure
 244  * @buf: buffer to store date
 245  * @len: number of bytes to read
 246  */
 247 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 248 {
 249         struct omap_nand_info *info = container_of(mtd,
 250                                                 struct omap_nand_info, mtd);
 251         uint32_t r_count = 0;
 252         int ret = 0;
 253         u32 *p = (u32 *)buf;
 254
 255         /* take care of subpage reads */
 256         if (len % 4) {
 257                 if (info->nand.options & NAND_BUSWIDTH_16)
 258                         omap_read_buf16(mtd, buf, len % 4);
 259                 else
 260                         omap_read_buf8(mtd, buf, len % 4);
 261                 p = (u32 *) (buf + len % 4);
 262                 len -= len % 4;
 263         }
 264
 265         /* configure and start prefetch transfer */
 266         ret = gpmc_prefetch_enable(info->gpmc_cs,
 267                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
 268         if (ret) {
 269                 /* PFPW engine is busy, use cpu copy method */
 270                 if (info->nand.options & NAND_BUSWIDTH_16)
 271                         omap_read_buf16(mtd, (u_char *)p, len);
 272                 else
 273                         omap_read_buf8(mtd, (u_char *)p, len);
 274         } else {
 275                 do {
 276                         r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 277                         r_count = r_count >> 2;
 278                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 279                         p += r_count;
 280                         len -= r_count << 2;
 281                 } while (len);
 282                 /* disable and stop the PFPW engine */
 283                 gpmc_prefetch_reset(info->gpmc_cs);
 284         }
 285 }
 286
 287 /**
 288  * omap_write_buf_pref - write buffer to NAND controller
 289  * @mtd: MTD device structure
 290  * @buf: data buffer
 291  * @len: number of bytes to write
 292  */
 293 static void omap_write_buf_pref(struct mtd_info *mtd,
 294                                         const u_char *buf, int len)
 295 {
 296         struct omap_nand_info *info = container_of(mtd,
 297                                                 struct omap_nand_info, mtd);
 298         uint32_t w_count = 0;
 299         int i = 0, ret = 0;
 300         u16 *p = (u16 *)buf;
 301         unsigned long tim, limit;
 302
 303         /* take care of subpage writes */
 304         if (len % 2 != 0) {
 305                 writeb(*buf, info->nand.IO_ADDR_W);
 306                 p = (u16 *)(buf + 1);
 307                 len--;
 308         }
 309
 310         /*  configure and start prefetch transfer */
 311         ret = gpmc_prefetch_enable(info->gpmc_cs,
 312                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
 313         if (ret) {
 314                 /* PFPW engine is busy, use cpu copy method */
 315                 if (info->nand.options & NAND_BUSWIDTH_16)
 316                         omap_write_buf16(mtd, (u_char *)p, len);
 317                 else
 318                         omap_write_buf8(mtd, (u_char *)p, len);
 319         } else {
 320                 while (len) {
 321                         w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 322                         w_count = w_count >> 1;
 323                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 324                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 325                 }
 326                 /* wait for data to flushed-out before reset the prefetch */
 327                 tim = 0;
 328                 limit = (loops_per_jiffy *
 329                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 330                 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 331                         cpu_relax();
 332
 333                 /* disable and stop the PFPW engine */
 334                 gpmc_prefetch_reset(info->gpmc_cs);
 335         }
 336 }
 337
 338 /*
 339  * omap_nand_dma_cb: callback on the completion of dma transfer
 340  * @lch: logical channel
 341  * @ch_satuts: channel status
 342  * @data: pointer to completion data structure
 343  */
 344 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
 345 {
 346         complete((struct completion *) data);
 347 }
 348
 349 /*
 350  * omap_nand_dma_transfer: configer and start dma transfer
 351  * @mtd: MTD device structure
 352  * @addr: virtual address in RAM of source/destination
 353  * @len: number of data bytes to be transferred
 354  * @is_write: flag for read/write operation
 355  */
 356 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 357                                         unsigned int len, int is_write)
 358 {
 359         struct omap_nand_info *info = container_of(mtd,
 360                                         struct omap_nand_info, mtd);
 361         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 362                                                         DMA_FROM_DEVICE;
 363         dma_addr_t dma_addr;
 364         int ret;
 365         unsigned long tim, limit;
 366
 367         /* The fifo depth is 64 bytes max.
 368          * But configure the FIFO-threahold to 32 to get a sync at each frame
 369          * and frame length is 32 bytes.
 370          */
 371         int buf_len = len >> 6;
 372
 373         if (addr >= high_memory) {
 374                 struct page *p1;
 375
 376                 if (((size_t)addr & PAGE_MASK) !=
 377                         ((size_t)(addr + len - 1) & PAGE_MASK))
 378                         goto out_copy;
 379                 p1 = vmalloc_to_page(addr);
 380                 if (!p1)
 381                         goto out_copy;
 382                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 383         }
 384
 385         dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
 386         if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
 387                 dev_err(&info->pdev->dev,
 388                         "Couldn't DMA map a %d byte buffer\n", len);
 389                 goto out_copy;
 390         }
 391
 392         if (is_write) {
 393             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 394                                                 info->phys_base, 0, 0);
 395             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 396                                                         dma_addr, 0, 0);
 397             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 398                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 399                                         OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
 400         } else {
 401             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 402                                                 info->phys_base, 0, 0);
 403             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 404                                                         dma_addr, 0, 0);
 405             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 406                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 407                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
 408         }
 409         /*  configure and start prefetch transfer */
 410         ret = gpmc_prefetch_enable(info->gpmc_cs,
 411                         PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
 412         if (ret)
 413                 /* PFPW engine is busy, use cpu copy method */
 414                 goto out_copy_unmap;
 415
 416         init_completion(&info->comp);
 417
 418         omap_start_dma(info->dma_ch);
 419
 420         /* setup and start DMA using dma_addr */
 421         wait_for_completion(&info->comp);
 422         tim = 0;
 423         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 424         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 425                 cpu_relax();
 426
 427         /* disable and stop the PFPW engine */
 428         gpmc_prefetch_reset(info->gpmc_cs);
 429
 430         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 431         return 0;
 432
 433 out_copy_unmap:
 434         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 435 out_copy:
 436         if (info->nand.options & NAND_BUSWIDTH_16)
 437                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 438                         : omap_write_buf16(mtd, (u_char *) addr, len);
 439         else
 440                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 441                         : omap_write_buf8(mtd, (u_char *) addr, len);
 442         return 0;
 443 }
 444
 445 /**
 446  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 447  * @mtd: MTD device structure
 448  * @buf: buffer to store date
 449  * @len: number of bytes to read
 450  */
 451 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 452 {
 453         if (len <= mtd->oobsize)
 454                 omap_read_buf_pref(mtd, buf, len);
 455         else
 456                 /* start transfer in DMA mode */
 457                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 458 }
 459
 460 /**
 461  * omap_write_buf_dma_pref - write buffer to NAND controller
 462  * @mtd: MTD device structure
 463  * @buf: data buffer
 464  * @len: number of bytes to write
 465  */
 466 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 467                                         const u_char *buf, int len)
 468 {
 469         if (len <= mtd->oobsize)
 470                 omap_write_buf_pref(mtd, buf, len);
 471         else
 472                 /* start transfer in DMA mode */
 473                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 474 }
 475
 476 /*
 477  * omap_nand_irq - GMPC irq handler
 478  * @this_irq: gpmc irq number
 479  * @dev: omap_nand_info structure pointer is passed here
 480  */
 481 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 482 {
 483         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 484         u32 bytes;
 485         u32 irq_stat;
 486
 487         irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 488         bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 489         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 490         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 491                 if (irq_stat & 0x2)
 492                         goto done;
 493
 494                 if (info->buf_len && (info->buf_len < bytes))
 495                         bytes = info->buf_len;
 496                 else if (!info->buf_len)
 497                         bytes = 0;
 498                 iowrite32_rep(info->nand.IO_ADDR_W,
 499                                                 (u32 *)info->buf, bytes >> 2);
 500                 info->buf = info->buf + bytes;
 501                 info->buf_len -= bytes;
 502
 503         } else {
 504                 ioread32_rep(info->nand.IO_ADDR_R,
 505                                                 (u32 *)info->buf, bytes >> 2);
 506                 info->buf = info->buf + bytes;
 507
 508                 if (irq_stat & 0x2)
 509                         goto done;
 510         }
 511         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 512
 513         return IRQ_HANDLED;
 514
 515 done:
 516         complete(&info->comp);
 517         /* disable irq */
 518         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 519
 520         /* clear status */
 521         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 522
 523         return IRQ_HANDLED;
 524 }
 525
 526 /*
 527  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 528  * @mtd: MTD device structure
 529  * @buf: buffer to store date
 530  * @len: number of bytes to read
 531  */
 532 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 533 {
 534         struct omap_nand_info *info = container_of(mtd,
 535                                                 struct omap_nand_info, mtd);
 536         int ret = 0;
 537
 538         if (len <= mtd->oobsize) {
 539                 omap_read_buf_pref(mtd, buf, len);
 540                 return;
 541         }
 542
 543         info->iomode = OMAP_NAND_IO_READ;
 544         info->buf = buf;
 545         init_completion(&info->comp);
 546
 547         /*  configure and start prefetch transfer */
 548         ret = gpmc_prefetch_enable(info->gpmc_cs,
 549                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
 550         if (ret)
 551                 /* PFPW engine is busy, use cpu copy method */
 552                 goto out_copy;
 553
 554         info->buf_len = len;
 555         /* enable irq */
 556         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 557                 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 558
 559         /* waiting for read to complete */
 560         wait_for_completion(&info->comp);
 561
 562         /* disable and stop the PFPW engine */
 563         gpmc_prefetch_reset(info->gpmc_cs);
 564         return;
 565
 566 out_copy:
 567         if (info->nand.options & NAND_BUSWIDTH_16)
 568                 omap_read_buf16(mtd, buf, len);
 569         else
 570                 omap_read_buf8(mtd, buf, len);
 571 }
 572
 573 /*
 574  * omap_write_buf_irq_pref - write buffer to NAND controller
 575  * @mtd: MTD device structure
 576  * @buf: data buffer
 577  * @len: number of bytes to write
 578  */
 579 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 580                                         const u_char *buf, int len)
 581 {
 582         struct omap_nand_info *info = container_of(mtd,
 583                                                 struct omap_nand_info, mtd);
 584         int ret = 0;
 585         unsigned long tim, limit;
 586
 587         if (len <= mtd->oobsize) {
 588                 omap_write_buf_pref(mtd, buf, len);
 589                 return;
 590         }
 591
 592         info->iomode = OMAP_NAND_IO_WRITE;
 593         info->buf = (u_char *) buf;
 594         init_completion(&info->comp);
 595
 596         /* configure and start prefetch transfer : size=24 */
 597         ret = gpmc_prefetch_enable(info->gpmc_cs,
 598                         (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
 599         if (ret)
 600                 /* PFPW engine is busy, use cpu copy method */
 601                 goto out_copy;
 602
 603         info->buf_len = len;
 604         /* enable irq */
 605         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 606                         (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 607
 608         /* waiting for write to complete */
 609         wait_for_completion(&info->comp);
 610         /* wait for data to flushed-out before reset the prefetch */
 611         tim = 0;
 612         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 613         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 614                 cpu_relax();
 615
 616         /* disable and stop the PFPW engine */
 617         gpmc_prefetch_reset(info->gpmc_cs);
 618         return;
 619
 620 out_copy:
 621         if (info->nand.options & NAND_BUSWIDTH_16)
 622                 omap_write_buf16(mtd, buf, len);
 623         else
 624                 omap_write_buf8(mtd, buf, len);
 625 }
 626
 627 /**
 628  * omap_verify_buf - Verify chip data against buffer
 629  * @mtd: MTD device structure
 630  * @buf: buffer containing the data to compare
 631  * @len: number of bytes to compare
 632  */
 633 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 634 {
 635         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 636                                                         mtd);
 637         u16 *p = (u16 *) buf;
 638
 639         len >>= 1;
 640         while (len--) {
 641                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 642                         return -EFAULT;
 643         }
 644
 645         return 0;
 646 }
 647
 648 /**
 649  * gen_true_ecc - This function will generate true ECC value
 650  * @ecc_buf: buffer to store ecc code
 651  *
 652  * This generated true ECC value can be used when correcting
 653  * data read from NAND flash memory core
 654  */
 655 static void gen_true_ecc(u8 *ecc_buf)
 656 {
 657         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 658                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 659
 660         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 661                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 662         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 663                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 664         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 665                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 666 }
 667
 668 /**
 669  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 670  * @ecc_data1:  ecc code from nand spare area
 671  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 672  * @page_data:  page data
 673  *
 674  * This function compares two ECC's and indicates if there is an error.
 675  * If the error can be corrected it will be corrected to the buffer.
 676  * If there is no error, %0 is returned. If there is an error but it
 677  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 678  */
 679 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 680                             u8 *ecc_data2,      /* read from register */
 681                             u8 *page_data)
 682 {
 683         uint    i;
 684         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 685         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 686         u8      ecc_bit[24];
 687         u8      ecc_sum = 0;
 688         u8      find_bit = 0;
 689         uint    find_byte = 0;
 690         int     isEccFF;
 691
 692         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 693
 694         gen_true_ecc(ecc_data1);
 695         gen_true_ecc(ecc_data2);
 696
 697         for (i = 0; i <= 2; i++) {
 698                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 699                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 700         }
 701
 702         for (i = 0; i < 8; i++) {
 703                 tmp0_bit[i]     = *ecc_data1 % 2;
 704                 *ecc_data1      = *ecc_data1 / 2;
 705         }
 706
 707         for (i = 0; i < 8; i++) {
 708                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 709                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 710         }
 711
 712         for (i = 0; i < 8; i++) {
 713                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 714                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 715         }
 716
 717         for (i = 0; i < 8; i++) {
 718                 comp0_bit[i]     = *ecc_data2 % 2;
 719                 *ecc_data2       = *ecc_data2 / 2;
 720         }
 721
 722         for (i = 0; i < 8; i++) {
 723                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 724                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 725         }
 726
 727         for (i = 0; i < 8; i++) {
 728                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 729                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 730         }
 731
 732         for (i = 0; i < 6; i++)
 733                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 734
 735         for (i = 0; i < 8; i++)
 736                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 737
 738         for (i = 0; i < 8; i++)
 739                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 740
 741         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 742         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 743
 744         for (i = 0; i < 24; i++)
 745                 ecc_sum += ecc_bit[i];
 746
 747         switch (ecc_sum) {
 748         case 0:
 749                 /* Not reached because this function is not called if
 750                  *  ECC values are equal
 751                  */
 752                 return 0;
 753
 754         case 1:
 755                 /* Uncorrectable error */
 756                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 757                 return -1;
 758
 759         case 11:
 760                 /* UN-Correctable error */
 761                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 762                 return -1;
 763
 764         case 12:
 765                 /* Correctable error */
 766                 find_byte = (ecc_bit[23] << 8) +
 767                             (ecc_bit[21] << 7) +
 768                             (ecc_bit[19] << 6) +
 769                             (ecc_bit[17] << 5) +
 770                             (ecc_bit[15] << 4) +
 771                             (ecc_bit[13] << 3) +
 772                             (ecc_bit[11] << 2) +
 773                             (ecc_bit[9]  << 1) +
 774                             ecc_bit[7];
 775
 776                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 777
 778                 pr_debug("Correcting single bit ECC error at offset: "
 779                                 "%d, bit: %d\n", find_byte, find_bit);
 780
 781                 page_data[find_byte] ^= (1 << find_bit);
 782
 783                 return 1;
 784         default:
 785                 if (isEccFF) {
 786                         if (ecc_data2[0] == 0 &&
 787                             ecc_data2[1] == 0 &&
 788                             ecc_data2[2] == 0)
 789                                 return 0;
 790                 }
 791                 pr_debug("UNCORRECTED_ERROR default\n");
 792                 return -1;
 793         }
 794 }
 795
 796 /**
 797  * omap_correct_data - Compares the ECC read with HW generated ECC
 798  * @mtd: MTD device structure
 799  * @dat: page data
 800  * @read_ecc: ecc read from nand flash
 801  * @calc_ecc: ecc read from HW ECC registers
 802  *
 803  * Compares the ecc read from nand spare area with ECC registers values
 804  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 805  * detection and correction. If there are no errors, %0 is returned. If
 806  * there were errors and all of the errors were corrected, the number of
 807  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 808  * returned.
 809  */
 810 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 811                                 u_char *read_ecc, u_char *calc_ecc)
 812 {
 813         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 814                                                         mtd);
 815         int blockCnt = 0, i = 0, ret = 0;
 816         int stat = 0;
 817
 818         /* Ex NAND_ECC_HW12_2048 */
 819         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 820                         (info->nand.ecc.size  == 2048))
 821                 blockCnt = 4;
 822         else
 823                 blockCnt = 1;
 824
 825         for (i = 0; i < blockCnt; i++) {
 826                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 827                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 828                         if (ret < 0)
 829                                 return ret;
 830                         /* keep track of the number of corrected errors */
 831                         stat += ret;
 832                 }
 833                 read_ecc += 3;
 834                 calc_ecc += 3;
 835                 dat      += 512;
 836         }
 837         return stat;
 838 }
 839
 840 /**
 841  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 842  * @mtd: MTD device structure
 843  * @dat: The pointer to data on which ecc is computed
 844  * @ecc_code: The ecc_code buffer
 845  *
 846  * Using noninverted ECC can be considered ugly since writing a blank
 847  * page ie. padding will clear the ECC bytes. This is no problem as long
 848  * nobody is trying to write data on the seemingly unused page. Reading
 849  * an erased page will produce an ECC mismatch between generated and read
 850  * ECC bytes that has to be dealt with separately.
 851  */
 852 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 853                                 u_char *ecc_code)
 854 {
 855         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 856                                                         mtd);
 857         return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 858 }
 859
 860 /**
 861  * omap_enable_hwecc - This function enables the hardware ecc functionality
 862  * @mtd: MTD device structure
 863  * @mode: Read/Write mode
 864  */
 865 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 866 {
 867         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 868                                                         mtd);
 869         struct nand_chip *chip = mtd->priv;
 870         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 871
 872         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 873 }
 874
 875 /**
 876  * omap_wait - wait until the command is done
 877  * @mtd: MTD device structure
 878  * @chip: NAND Chip structure
 879  *
 880  * Wait function is called during Program and erase operations and
 881  * the way it is called from MTD layer, we should wait till the NAND
 882  * chip is ready after the programming/erase operation has completed.
 883  *
 884  * Erase can take up to 400ms and program up to 20ms according to
 885  * general NAND and SmartMedia specs
 886  */
 887 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 888 {
 889         struct nand_chip *this = mtd->priv;
 890         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 891                                                         mtd);
 892         unsigned long timeo = jiffies;
 893         int status, state = this->state;
 894
 895         if (state == FL_ERASING)
 896                 timeo += (HZ * 400) / 1000;
 897         else
 898                 timeo += (HZ * 20) / 1000;
 899
 900         gpmc_nand_write(info->gpmc_cs,
 901                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 902         while (time_before(jiffies, timeo)) {
 903                 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 904                 if (status & NAND_STATUS_READY)
 905                         break;
 906                 cond_resched();
 907         }
 908
 909         status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 910         return status;
 911 }
 912
 913 /**
 914  * omap_dev_ready - calls the platform specific dev_ready function
 915  * @mtd: MTD device structure
 916  */
 917 static int omap_dev_ready(struct mtd_info *mtd)
 918 {
 919         unsigned int val = 0;
 920         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 921                                                         mtd);
 922
 923         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 924         if ((val & 0x100) == 0x100) {
 925                 /* Clear IRQ Interrupt */
 926                 val |= 0x100;
 927                 val &= ~(0x0);
 928                 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
 929         } else {
 930                 unsigned int cnt = 0;
 931                 while (cnt++ < 0x1FF) {
 932                         if  ((val & 0x100) == 0x100)
 933                                 return 0;
 934                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 935                 }
 936         }
 937
 938         return 1;
 939 }
 940
 941 #ifdef CONFIG_MTD_NAND_OMAP_BCH
 942
 943 /**
 944  * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
 945  * @mtd: MTD device structure
 946  * @mode: Read/Write mode
 947  */
 948 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
 949 {
 950         int nerrors;
 951         unsigned int dev_width;
 952         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 953                                                    mtd);
 954         struct nand_chip *chip = mtd->priv;
 955
 956         nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4;
 957         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 958         /*
 959          * Program GPMC to perform correction on one 512-byte sector at a time.
 960          * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
 961          * gives a slight (5%) performance gain (but requires additional code).
 962          */
 963         (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors);
 964 }
 965
 966 /**
 967  * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
 968  * @mtd: MTD device structure
 969  * @dat: The pointer to data on which ecc is computed
 970  * @ecc_code: The ecc_code buffer
 971  */
 972 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
 973                                     u_char *ecc_code)
 974 {
 975         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 976                                                    mtd);
 977         return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code);
 978 }
 979
 980 /**
 981  * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
 982  * @mtd: MTD device structure
 983  * @dat: The pointer to data on which ecc is computed
 984  * @ecc_code: The ecc_code buffer
 985  */
 986 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
 987                                     u_char *ecc_code)
 988 {
 989         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 990                                                    mtd);
 991         return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code);
 992 }
 993
 994 /**
 995  * omap3_correct_data_bch - Decode received data and correct errors
 996  * @mtd: MTD device structure
 997  * @data: page data
 998  * @read_ecc: ecc read from nand flash
 999  * @calc_ecc: ecc read from HW ECC registers
1000  */
1001 static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
1002                                   u_char *read_ecc, u_char *calc_ecc)
1003 {
1004         int i, count;
1005         /* cannot correct more than 8 errors */
1006         unsigned int errloc[8];
1007         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1008                                                    mtd);
1009
1010         count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL,
1011                            errloc);
1012         if (count > 0) {
1013                 /* correct errors */
1014                 for (i = 0; i < count; i++) {
1015                         /* correct data only, not ecc bytes */
1016                         if (errloc[i] < 8*512)
1017                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
1018                         pr_debug("corrected bitflip %u\n", errloc[i]);
1019                 }
1020         } else if (count < 0) {
1021                 pr_err("ecc unrecoverable error\n");
1022         }
1023         return count;
1024 }
1025
1026 /**
1027  * omap3_free_bch - Release BCH ecc resources
1028  * @mtd: MTD device structure
1029  */
1030 static void omap3_free_bch(struct mtd_info *mtd)
1031 {
1032         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1033                                                    mtd);
1034         if (info->bch) {
1035                 free_bch(info->bch);
1036                 info->bch = NULL;
1037         }
1038 }
1039
1040 /**
1041  * omap3_init_bch - Initialize BCH ECC
1042  * @mtd: MTD device structure
1043  * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
1044  */
1045 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1046 {
1047         int ret, max_errors;
1048         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1049                                                    mtd);
1050 #ifdef CONFIG_MTD_NAND_OMAP_BCH8
1051         const int hw_errors = 8;
1052 #else
1053         const int hw_errors = 4;
1054 #endif
1055         info->bch = NULL;
1056
1057         max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4;
1058         if (max_errors != hw_errors) {
1059                 pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
1060                        max_errors, hw_errors);
1061                 goto fail;
1062         }
1063
1064         /* initialize GPMC BCH engine */
1065         ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors);
1066         if (ret)
1067                 goto fail;
1068
1069         /* software bch library is only used to detect and locate errors */
1070         info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */);
1071         if (!info->bch)
1072                 goto fail;
1073
1074         info->nand.ecc.size    = 512;
1075         info->nand.ecc.hwctl   = omap3_enable_hwecc_bch;
1076         info->nand.ecc.correct = omap3_correct_data_bch;
1077         info->nand.ecc.mode    = NAND_ECC_HW;
1078
1079         /*
1080          * The number of corrected errors in an ecc block that will trigger
1081          * block scrubbing defaults to the ecc strength (4 or 8).
1082          * Set mtd->bitflip_threshold here to define a custom threshold.
1083          */
1084
1085         if (max_errors == 8) {
1086                 info->nand.ecc.strength  = 8;
1087                 info->nand.ecc.bytes     = 13;
1088                 info->nand.ecc.calculate = omap3_calculate_ecc_bch8;
1089         } else {
1090                 info->nand.ecc.strength  = 4;
1091                 info->nand.ecc.bytes     = 7;
1092                 info->nand.ecc.calculate = omap3_calculate_ecc_bch4;
1093         }
1094
1095         pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors);
1096         return 0;
1097 fail:
1098         omap3_free_bch(mtd);
1099         return -1;
1100 }
1101
1102 /**
1103  * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
1104  * @mtd: MTD device structure
1105  */
1106 static int omap3_init_bch_tail(struct mtd_info *mtd)
1107 {
1108         int i, steps;
1109         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1110                                                    mtd);
1111         struct nand_ecclayout *layout = &info->ecclayout;
1112
1113         /* build oob layout */
1114         steps = mtd->writesize/info->nand.ecc.size;
1115         layout->eccbytes = steps*info->nand.ecc.bytes;
1116
1117         /* do not bother creating special oob layouts for small page devices */
1118         if (mtd->oobsize < 64) {
1119                 pr_err("BCH ecc is not supported on small page devices\n");
1120                 goto fail;
1121         }
1122
1123         /* reserve 2 bytes for bad block marker */
1124         if (layout->eccbytes+2 > mtd->oobsize) {
1125                 pr_err("no oob layout available for oobsize %d eccbytes %u\n",
1126                        mtd->oobsize, layout->eccbytes);
1127                 goto fail;
1128         }
1129
1130         /* put ecc bytes at oob tail */
1131         for (i = 0; i < layout->eccbytes; i++)
1132                 layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i;
1133
1134         layout->oobfree[0].offset = 2;
1135         layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
1136         info->nand.ecc.layout = layout;
1137
1138         if (!(info->nand.options & NAND_BUSWIDTH_16))
1139                 info->nand.badblock_pattern = &bb_descrip_flashbased;
1140         return 0;
1141 fail:
1142         omap3_free_bch(mtd);
1143         return -1;
1144 }
1145
1146 #else
1147 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1148 {
1149         pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
1150         return -1;
1151 }
1152 static int omap3_init_bch_tail(struct mtd_info *mtd)
1153 {
1154         return -1;
1155 }
1156 static void omap3_free_bch(struct mtd_info *mtd)
1157 {
1158 }
1159 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
1160
1161 static int __devinit omap_nand_probe(struct platform_device *pdev)
1162 {
1163         struct omap_nand_info           *info;
1164         struct omap_nand_platform_data  *pdata;
1165         int                             err;
1166         int                             i, offset;
1167
1168         pdata = pdev->dev.platform_data;
1169         if (pdata == NULL) {
1170                 dev_err(&pdev->dev, "platform data missing\n");
1171                 return -ENODEV;
1172         }
1173
1174         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
1175         if (!info)
1176                 return -ENOMEM;
1177
1178         platform_set_drvdata(pdev, info);
1179
1180         spin_lock_init(&info->controller.lock);
1181         init_waitqueue_head(&info->controller.wq);
1182
1183         info->pdev = pdev;
1184
1185         info->gpmc_cs           = pdata->cs;
1186         info->phys_base         = pdata->phys_base;
1187
1188         info->mtd.priv          = &info->nand;
1189         info->mtd.name          = dev_name(&pdev->dev);
1190         info->mtd.owner         = THIS_MODULE;
1191
1192         info->nand.options      = pdata->devsize;
1193         info->nand.options      |= NAND_SKIP_BBTSCAN;
1194
1195         /* NAND write protect off */
1196         gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
1197
1198         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
1199                                 pdev->dev.driver->name)) {
1200                 err = -EBUSY;
1201                 goto out_free_info;
1202         }
1203
1204         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
1205         if (!info->nand.IO_ADDR_R) {
1206                 err = -ENOMEM;
1207                 goto out_release_mem_region;
1208         }
1209
1210         info->nand.controller = &info->controller;
1211
1212         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
1213         info->nand.cmd_ctrl  = omap_hwcontrol;
1214
1215         /*
1216          * If RDY/BSY line is connected to OMAP then use the omap ready
1217          * funcrtion and the generic nand_wait function which reads the status
1218          * register after monitoring the RDY/BSY line.Otherwise use a standard
1219          * chip delay which is slightly more than tR (AC Timing) of the NAND
1220          * device and read status register until you get a failure or success
1221          */
1222         if (pdata->dev_ready) {
1223                 info->nand.dev_ready = omap_dev_ready;
1224                 info->nand.chip_delay = 0;
1225         } else {
1226                 info->nand.waitfunc = omap_wait;
1227                 info->nand.chip_delay = 50;
1228         }
1229
1230         switch (pdata->xfer_type) {
1231         case NAND_OMAP_PREFETCH_POLLED:
1232                 info->nand.read_buf   = omap_read_buf_pref;
1233                 info->nand.write_buf  = omap_write_buf_pref;
1234                 break;
1235
1236         case NAND_OMAP_POLLED:
1237                 if (info->nand.options & NAND_BUSWIDTH_16) {
1238                         info->nand.read_buf   = omap_read_buf16;
1239                         info->nand.write_buf  = omap_write_buf16;
1240                 } else {
1241                         info->nand.read_buf   = omap_read_buf8;
1242                         info->nand.write_buf  = omap_write_buf8;
1243                 }
1244                 break;
1245
1246         case NAND_OMAP_PREFETCH_DMA:
1247                 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1248                                 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1249                 if (err < 0) {
1250                         info->dma_ch = -1;
1251                         dev_err(&pdev->dev, "DMA request failed!\n");
1252                         goto out_release_mem_region;
1253                 } else {
1254                         omap_set_dma_dest_burst_mode(info->dma_ch,
1255                                         OMAP_DMA_DATA_BURST_16);
1256                         omap_set_dma_src_burst_mode(info->dma_ch,
1257                                         OMAP_DMA_DATA_BURST_16);
1258
1259                         info->nand.read_buf   = omap_read_buf_dma_pref;
1260                         info->nand.write_buf  = omap_write_buf_dma_pref;
1261                 }
1262                 break;
1263
1264         case NAND_OMAP_PREFETCH_IRQ:
1265                 err = request_irq(pdata->gpmc_irq,
1266                                 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1267                 if (err) {
1268                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1269                                                         pdata->gpmc_irq, err);
1270                         goto out_release_mem_region;
1271                 } else {
1272                         info->gpmc_irq       = pdata->gpmc_irq;
1273                         info->nand.read_buf  = omap_read_buf_irq_pref;
1274                         info->nand.write_buf = omap_write_buf_irq_pref;
1275                 }
1276                 break;
1277
1278         default:
1279                 dev_err(&pdev->dev,
1280                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1281                 err = -EINVAL;
1282                 goto out_release_mem_region;
1283         }
1284
1285         info->nand.verify_buf = omap_verify_buf;
1286
1287         /* selsect the ecc type */
1288         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1289                 info->nand.ecc.mode = NAND_ECC_SOFT;
1290         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1291                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1292                 info->nand.ecc.bytes            = 3;
1293                 info->nand.ecc.size             = 512;
1294                 info->nand.ecc.strength         = 1;
1295                 info->nand.ecc.calculate        = omap_calculate_ecc;
1296                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1297                 info->nand.ecc.correct          = omap_correct_data;
1298                 info->nand.ecc.mode             = NAND_ECC_HW;
1299         } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1300                    (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1301                 err = omap3_init_bch(&info->mtd, pdata->ecc_opt);
1302                 if (err) {
1303                         err = -EINVAL;
1304                         goto out_release_mem_region;
1305                 }
1306         }
1307
1308         /* DIP switches on some boards change between 8 and 16 bit
1309          * bus widths for flash.  Try the other width if the first try fails.
1310          */
1311         if (nand_scan_ident(&info->mtd, 1, NULL)) {
1312                 info->nand.options ^= NAND_BUSWIDTH_16;
1313                 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1314                         err = -ENXIO;
1315                         goto out_release_mem_region;
1316                 }
1317         }
1318
1319         /* rom code layout */
1320         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1321
1322                 if (info->nand.options & NAND_BUSWIDTH_16)
1323                         offset = 2;
1324                 else {
1325                         offset = 1;
1326                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1327                 }
1328                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1329                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1330                         omap_oobinfo.eccpos[i] = i+offset;
1331
1332                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1333                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1334                                         (offset + omap_oobinfo.eccbytes);
1335
1336                 info->nand.ecc.layout = &omap_oobinfo;
1337         } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1338                    (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1339                 /* build OOB layout for BCH ECC correction */
1340                 err = omap3_init_bch_tail(&info->mtd);
1341                 if (err) {
1342                         err = -EINVAL;
1343                         goto out_release_mem_region;
1344                 }
1345         }
1346
1347         /* second phase scan */
1348         if (nand_scan_tail(&info->mtd)) {
1349                 err = -ENXIO;
1350                 goto out_release_mem_region;
1351         }
1352
1353         mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
1354                                   pdata->nr_parts);
1355
1356         platform_set_drvdata(pdev, &info->mtd);
1357
1358         return 0;
1359
1360 out_release_mem_region:
1361         release_mem_region(info->phys_base, NAND_IO_SIZE);
1362 out_free_info:
1363         kfree(info);
1364
1365         return err;
1366 }
1367
1368 static int omap_nand_remove(struct platform_device *pdev)
1369 {
1370         struct mtd_info *mtd = platform_get_drvdata(pdev);
1371         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1372                                                         mtd);
1373         omap3_free_bch(&info->mtd);
1374
1375         platform_set_drvdata(pdev, NULL);
1376         if (info->dma_ch != -1)
1377                 omap_free_dma(info->dma_ch);
1378
1379         if (info->gpmc_irq)
1380                 free_irq(info->gpmc_irq, info);
1381
1382         /* Release NAND device, its internal structures and partitions */
1383         nand_release(&info->mtd);
1384         iounmap(info->nand.IO_ADDR_R);
1385         kfree(&info->mtd);
1386         return 0;
1387 }
1388
1389 static struct platform_driver omap_nand_driver = {
1390         .probe          = omap_nand_probe,
1391         .remove         = omap_nand_remove,
1392         .driver         = {
1393                 .name   = DRIVER_NAME,
1394                 .owner  = THIS_MODULE,
1395         },
1396 };
1397
1398 module_platform_driver(omap_nand_driver);
1399
1400 MODULE_ALIAS("platform:" DRIVER_NAME);
1401 MODULE_LICENSE("GPL");
1402 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");