drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/sched.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #include <plat/dma.h>
  24 #include <plat/gpmc.h>
  25 #include <plat/nand.h>
  26
  27 #define DRIVER_NAME     "omap2-nand"
  28 #define OMAP_NAND_TIMEOUT_MS    5000
  29
  30 #define NAND_Ecc_P1e            (1 << 0)
  31 #define NAND_Ecc_P2e            (1 << 1)
  32 #define NAND_Ecc_P4e            (1 << 2)
  33 #define NAND_Ecc_P8e            (1 << 3)
  34 #define NAND_Ecc_P16e           (1 << 4)
  35 #define NAND_Ecc_P32e           (1 << 5)
  36 #define NAND_Ecc_P64e           (1 << 6)
  37 #define NAND_Ecc_P128e          (1 << 7)
  38 #define NAND_Ecc_P256e          (1 << 8)
  39 #define NAND_Ecc_P512e          (1 << 9)
  40 #define NAND_Ecc_P1024e         (1 << 10)
  41 #define NAND_Ecc_P2048e         (1 << 11)
  42
  43 #define NAND_Ecc_P1o            (1 << 16)
  44 #define NAND_Ecc_P2o            (1 << 17)
  45 #define NAND_Ecc_P4o            (1 << 18)
  46 #define NAND_Ecc_P8o            (1 << 19)
  47 #define NAND_Ecc_P16o           (1 << 20)
  48 #define NAND_Ecc_P32o           (1 << 21)
  49 #define NAND_Ecc_P64o           (1 << 22)
  50 #define NAND_Ecc_P128o          (1 << 23)
  51 #define NAND_Ecc_P256o          (1 << 24)
  52 #define NAND_Ecc_P512o          (1 << 25)
  53 #define NAND_Ecc_P1024o         (1 << 26)
  54 #define NAND_Ecc_P2048o         (1 << 27)
  55
  56 #define TF(value)       (value ? 1 : 0)
  57
  58 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  59 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  60 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  61 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  62 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  63 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  64 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  65 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  66
  67 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  68 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  69 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  70 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  71 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  72 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  73 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  74 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  75
  76 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  77 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  78 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  79 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  80 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  81 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  82 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  83 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  84
  85 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  86 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  87 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  88 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  89 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  90 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  91 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  92 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  93
  94 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
  95 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
  96
  97 #ifdef CONFIG_MTD_PARTITIONS
  98 static const char *part_probes[] = { "cmdlinepart", NULL };
  99 #endif
 100
 101 /* oob info generated runtime depending on ecc algorithm and layout selected */
 102 static struct nand_ecclayout omap_oobinfo;
 103 /* Define some generic bad / good block scan pattern which are used
 104  * while scanning a device for factory marked good / bad blocks
 105  */
 106 static uint8_t scan_ff_pattern[] = { 0xff };
 107 static struct nand_bbt_descr bb_descrip_flashbased = {
 108         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 109         .offs = 0,
 110         .len = 1,
 111         .pattern = scan_ff_pattern,
 112 };
 113
 114
 115 struct omap_nand_info {
 116         struct nand_hw_control          controller;
 117         struct omap_nand_platform_data  *pdata;
 118         struct mtd_info                 mtd;
 119         struct mtd_partition            *parts;
 120         struct nand_chip                nand;
 121         struct platform_device          *pdev;
 122
 123         int                             gpmc_cs;
 124         unsigned long                   phys_base;
 125         struct completion               comp;
 126         int                             dma_ch;
 127         int                             gpmc_irq;
 128         enum {
 129                 OMAP_NAND_IO_READ = 0,  /* read */
 130                 OMAP_NAND_IO_WRITE,     /* write */
 131         } iomode;
 132         u_char                          *buf;
 133         int                                     buf_len;
 134 };
 135
 136 /**
 137  * omap_hwcontrol - hardware specific access to control-lines
 138  * @mtd: MTD device structure
 139  * @cmd: command to device
 140  * @ctrl:
 141  * NAND_NCE: bit 0 -> don't care
 142  * NAND_CLE: bit 1 -> Command Latch
 143  * NAND_ALE: bit 2 -> Address Latch
 144  *
 145  * NOTE: boards may use different bits for these!!
 146  */
 147 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 148 {
 149         struct omap_nand_info *info = container_of(mtd,
 150                                         struct omap_nand_info, mtd);
 151
 152         if (cmd != NAND_CMD_NONE) {
 153                 if (ctrl & NAND_CLE)
 154                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
 155
 156                 else if (ctrl & NAND_ALE)
 157                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
 158
 159                 else /* NAND_NCE */
 160                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
 161         }
 162 }
 163
 164 /**
 165  * omap_read_buf8 - read data from NAND controller into buffer
 166  * @mtd: MTD device structure
 167  * @buf: buffer to store date
 168  * @len: number of bytes to read
 169  */
 170 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 171 {
 172         struct nand_chip *nand = mtd->priv;
 173
 174         ioread8_rep(nand->IO_ADDR_R, buf, len);
 175 }
 176
 177 /**
 178  * omap_write_buf8 - write buffer to NAND controller
 179  * @mtd: MTD device structure
 180  * @buf: data buffer
 181  * @len: number of bytes to write
 182  */
 183 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 184 {
 185         struct omap_nand_info *info = container_of(mtd,
 186                                                 struct omap_nand_info, mtd);
 187         u_char *p = (u_char *)buf;
 188         u32     status = 0;
 189
 190         while (len--) {
 191                 iowrite8(*p++, info->nand.IO_ADDR_W);
 192                 /* wait until buffer is available for write */
 193                 do {
 194                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 195                 } while (!status);
 196         }
 197 }
 198
 199 /**
 200  * omap_read_buf16 - read data from NAND controller into buffer
 201  * @mtd: MTD device structure
 202  * @buf: buffer to store date
 203  * @len: number of bytes to read
 204  */
 205 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 206 {
 207         struct nand_chip *nand = mtd->priv;
 208
 209         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 210 }
 211
 212 /**
 213  * omap_write_buf16 - write buffer to NAND controller
 214  * @mtd: MTD device structure
 215  * @buf: data buffer
 216  * @len: number of bytes to write
 217  */
 218 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 219 {
 220         struct omap_nand_info *info = container_of(mtd,
 221                                                 struct omap_nand_info, mtd);
 222         u16 *p = (u16 *) buf;
 223         u32     status = 0;
 224         /* FIXME try bursts of writesw() or DMA ... */
 225         len >>= 1;
 226
 227         while (len--) {
 228                 iowrite16(*p++, info->nand.IO_ADDR_W);
 229                 /* wait until buffer is available for write */
 230                 do {
 231                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 232                 } while (!status);
 233         }
 234 }
 235
 236 /**
 237  * omap_read_buf_pref - read data from NAND controller into buffer
 238  * @mtd: MTD device structure
 239  * @buf: buffer to store date
 240  * @len: number of bytes to read
 241  */
 242 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 243 {
 244         struct omap_nand_info *info = container_of(mtd,
 245                                                 struct omap_nand_info, mtd);
 246         uint32_t r_count = 0;
 247         int ret = 0;
 248         u32 *p = (u32 *)buf;
 249
 250         /* take care of subpage reads */
 251         if (len % 4) {
 252                 if (info->nand.options & NAND_BUSWIDTH_16)
 253                         omap_read_buf16(mtd, buf, len % 4);
 254                 else
 255                         omap_read_buf8(mtd, buf, len % 4);
 256                 p = (u32 *) (buf + len % 4);
 257                 len -= len % 4;
 258         }
 259
 260         /* configure and start prefetch transfer */
 261         ret = gpmc_prefetch_enable(info->gpmc_cs,
 262                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
 263         if (ret) {
 264                 /* PFPW engine is busy, use cpu copy method */
 265                 if (info->nand.options & NAND_BUSWIDTH_16)
 266                         omap_read_buf16(mtd, buf, len);
 267                 else
 268                         omap_read_buf8(mtd, buf, len);
 269         } else {
 270                 p = (u32 *) buf;
 271                 do {
 272                         r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 273                         r_count = r_count >> 2;
 274                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 275                         p += r_count;
 276                         len -= r_count << 2;
 277                 } while (len);
 278                 /* disable and stop the PFPW engine */
 279                 gpmc_prefetch_reset(info->gpmc_cs);
 280         }
 281 }
 282
 283 /**
 284  * omap_write_buf_pref - write buffer to NAND controller
 285  * @mtd: MTD device structure
 286  * @buf: data buffer
 287  * @len: number of bytes to write
 288  */
 289 static void omap_write_buf_pref(struct mtd_info *mtd,
 290                                         const u_char *buf, int len)
 291 {
 292         struct omap_nand_info *info = container_of(mtd,
 293                                                 struct omap_nand_info, mtd);
 294         uint32_t w_count = 0;
 295         int i = 0, ret = 0;
 296         u16 *p;
 297         unsigned long tim, limit;
 298
 299         /* take care of subpage writes */
 300         if (len % 2 != 0) {
 301                 writeb(*buf, info->nand.IO_ADDR_W);
 302                 p = (u16 *)(buf + 1);
 303                 len--;
 304         }
 305
 306         /*  configure and start prefetch transfer */
 307         ret = gpmc_prefetch_enable(info->gpmc_cs,
 308                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
 309         if (ret) {
 310                 /* PFPW engine is busy, use cpu copy method */
 311                 if (info->nand.options & NAND_BUSWIDTH_16)
 312                         omap_write_buf16(mtd, buf, len);
 313                 else
 314                         omap_write_buf8(mtd, buf, len);
 315         } else {
 316                 p = (u16 *) buf;
 317                 while (len) {
 318                         w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 319                         w_count = w_count >> 1;
 320                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 321                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 322                 }
 323                 /* wait for data to flushed-out before reset the prefetch */
 324                 tim = 0;
 325                 limit = (loops_per_jiffy *
 326                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 327                 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 328                         cpu_relax();
 329
 330                 /* disable and stop the PFPW engine */
 331                 gpmc_prefetch_reset(info->gpmc_cs);
 332         }
 333 }
 334
 335 /*
 336  * omap_nand_dma_cb: callback on the completion of dma transfer
 337  * @lch: logical channel
 338  * @ch_satuts: channel status
 339  * @data: pointer to completion data structure
 340  */
 341 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
 342 {
 343         complete((struct completion *) data);
 344 }
 345
 346 /*
 347  * omap_nand_dma_transfer: configer and start dma transfer
 348  * @mtd: MTD device structure
 349  * @addr: virtual address in RAM of source/destination
 350  * @len: number of data bytes to be transferred
 351  * @is_write: flag for read/write operation
 352  */
 353 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 354                                         unsigned int len, int is_write)
 355 {
 356         struct omap_nand_info *info = container_of(mtd,
 357                                         struct omap_nand_info, mtd);
 358         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 359                                                         DMA_FROM_DEVICE;
 360         dma_addr_t dma_addr;
 361         int ret;
 362         unsigned long tim, limit;
 363
 364         /* The fifo depth is 64 bytes max.
 365          * But configure the FIFO-threahold to 32 to get a sync at each frame
 366          * and frame length is 32 bytes.
 367          */
 368         int buf_len = len >> 6;
 369
 370         if (addr >= high_memory) {
 371                 struct page *p1;
 372
 373                 if (((size_t)addr & PAGE_MASK) !=
 374                         ((size_t)(addr + len - 1) & PAGE_MASK))
 375                         goto out_copy;
 376                 p1 = vmalloc_to_page(addr);
 377                 if (!p1)
 378                         goto out_copy;
 379                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 380         }
 381
 382         dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
 383         if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
 384                 dev_err(&info->pdev->dev,
 385                         "Couldn't DMA map a %d byte buffer\n", len);
 386                 goto out_copy;
 387         }
 388
 389         if (is_write) {
 390             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 391                                                 info->phys_base, 0, 0);
 392             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 393                                                         dma_addr, 0, 0);
 394             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 395                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 396                                         OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
 397         } else {
 398             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 399                                                 info->phys_base, 0, 0);
 400             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 401                                                         dma_addr, 0, 0);
 402             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 403                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 404                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
 405         }
 406         /*  configure and start prefetch transfer */
 407         ret = gpmc_prefetch_enable(info->gpmc_cs,
 408                         PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
 409         if (ret)
 410                 /* PFPW engine is busy, use cpu copy method */
 411                 goto out_copy;
 412
 413         init_completion(&info->comp);
 414
 415         omap_start_dma(info->dma_ch);
 416
 417         /* setup and start DMA using dma_addr */
 418         wait_for_completion(&info->comp);
 419         tim = 0;
 420         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 421         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 422                 cpu_relax();
 423
 424         /* disable and stop the PFPW engine */
 425         gpmc_prefetch_reset(info->gpmc_cs);
 426
 427         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 428         return 0;
 429
 430 out_copy:
 431         if (info->nand.options & NAND_BUSWIDTH_16)
 432                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 433                         : omap_write_buf16(mtd, (u_char *) addr, len);
 434         else
 435                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 436                         : omap_write_buf8(mtd, (u_char *) addr, len);
 437         return 0;
 438 }
 439
 440 /**
 441  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 442  * @mtd: MTD device structure
 443  * @buf: buffer to store date
 444  * @len: number of bytes to read
 445  */
 446 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 447 {
 448         if (len <= mtd->oobsize)
 449                 omap_read_buf_pref(mtd, buf, len);
 450         else
 451                 /* start transfer in DMA mode */
 452                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 453 }
 454
 455 /**
 456  * omap_write_buf_dma_pref - write buffer to NAND controller
 457  * @mtd: MTD device structure
 458  * @buf: data buffer
 459  * @len: number of bytes to write
 460  */
 461 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 462                                         const u_char *buf, int len)
 463 {
 464         if (len <= mtd->oobsize)
 465                 omap_write_buf_pref(mtd, buf, len);
 466         else
 467                 /* start transfer in DMA mode */
 468                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 469 }
 470
 471 /*
 472  * omap_nand_irq - GMPC irq handler
 473  * @this_irq: gpmc irq number
 474  * @dev: omap_nand_info structure pointer is passed here
 475  */
 476 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 477 {
 478         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 479         u32 bytes;
 480         u32 irq_stat;
 481
 482         irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 483         bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 484         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 485         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 486                 if (irq_stat & 0x2)
 487                         goto done;
 488
 489                 if (info->buf_len && (info->buf_len < bytes))
 490                         bytes = info->buf_len;
 491                 else if (!info->buf_len)
 492                         bytes = 0;
 493                 iowrite32_rep(info->nand.IO_ADDR_W,
 494                                                 (u32 *)info->buf, bytes >> 2);
 495                 info->buf = info->buf + bytes;
 496                 info->buf_len -= bytes;
 497
 498         } else {
 499                 ioread32_rep(info->nand.IO_ADDR_R,
 500                                                 (u32 *)info->buf, bytes >> 2);
 501                 info->buf = info->buf + bytes;
 502
 503                 if (irq_stat & 0x2)
 504                         goto done;
 505         }
 506         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 507
 508         return IRQ_HANDLED;
 509
 510 done:
 511         complete(&info->comp);
 512         /* disable irq */
 513         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 514
 515         /* clear status */
 516         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 517
 518         return IRQ_HANDLED;
 519 }
 520
 521 /*
 522  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 523  * @mtd: MTD device structure
 524  * @buf: buffer to store date
 525  * @len: number of bytes to read
 526  */
 527 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 528 {
 529         struct omap_nand_info *info = container_of(mtd,
 530                                                 struct omap_nand_info, mtd);
 531         int ret = 0;
 532
 533         if (len <= mtd->oobsize) {
 534                 omap_read_buf_pref(mtd, buf, len);
 535                 return;
 536         }
 537
 538         info->iomode = OMAP_NAND_IO_READ;
 539         info->buf = buf;
 540         init_completion(&info->comp);
 541
 542         /*  configure and start prefetch transfer */
 543         ret = gpmc_prefetch_enable(info->gpmc_cs,
 544                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
 545         if (ret)
 546                 /* PFPW engine is busy, use cpu copy method */
 547                 goto out_copy;
 548
 549         info->buf_len = len;
 550         /* enable irq */
 551         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 552                 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 553
 554         /* waiting for read to complete */
 555         wait_for_completion(&info->comp);
 556
 557         /* disable and stop the PFPW engine */
 558         gpmc_prefetch_reset(info->gpmc_cs);
 559         return;
 560
 561 out_copy:
 562         if (info->nand.options & NAND_BUSWIDTH_16)
 563                 omap_read_buf16(mtd, buf, len);
 564         else
 565                 omap_read_buf8(mtd, buf, len);
 566 }
 567
 568 /*
 569  * omap_write_buf_irq_pref - write buffer to NAND controller
 570  * @mtd: MTD device structure
 571  * @buf: data buffer
 572  * @len: number of bytes to write
 573  */
 574 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 575                                         const u_char *buf, int len)
 576 {
 577         struct omap_nand_info *info = container_of(mtd,
 578                                                 struct omap_nand_info, mtd);
 579         int ret = 0;
 580         unsigned long tim, limit;
 581
 582         if (len <= mtd->oobsize) {
 583                 omap_write_buf_pref(mtd, buf, len);
 584                 return;
 585         }
 586
 587         info->iomode = OMAP_NAND_IO_WRITE;
 588         info->buf = (u_char *) buf;
 589         init_completion(&info->comp);
 590
 591         /* configure and start prefetch transfer : size=24 */
 592         ret = gpmc_prefetch_enable(info->gpmc_cs,
 593                         (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
 594         if (ret)
 595                 /* PFPW engine is busy, use cpu copy method */
 596                 goto out_copy;
 597
 598         info->buf_len = len;
 599         /* enable irq */
 600         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 601                         (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 602
 603         /* waiting for write to complete */
 604         wait_for_completion(&info->comp);
 605         /* wait for data to flushed-out before reset the prefetch */
 606         tim = 0;
 607         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 608         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 609                 cpu_relax();
 610
 611         /* disable and stop the PFPW engine */
 612         gpmc_prefetch_reset(info->gpmc_cs);
 613         return;
 614
 615 out_copy:
 616         if (info->nand.options & NAND_BUSWIDTH_16)
 617                 omap_write_buf16(mtd, buf, len);
 618         else
 619                 omap_write_buf8(mtd, buf, len);
 620 }
 621
 622 /**
 623  * omap_verify_buf - Verify chip data against buffer
 624  * @mtd: MTD device structure
 625  * @buf: buffer containing the data to compare
 626  * @len: number of bytes to compare
 627  */
 628 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 629 {
 630         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 631                                                         mtd);
 632         u16 *p = (u16 *) buf;
 633
 634         len >>= 1;
 635         while (len--) {
 636                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 637                         return -EFAULT;
 638         }
 639
 640         return 0;
 641 }
 642
 643 /**
 644  * gen_true_ecc - This function will generate true ECC value
 645  * @ecc_buf: buffer to store ecc code
 646  *
 647  * This generated true ECC value can be used when correcting
 648  * data read from NAND flash memory core
 649  */
 650 static void gen_true_ecc(u8 *ecc_buf)
 651 {
 652         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 653                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 654
 655         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 656                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 657         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 658                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 659         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 660                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 661 }
 662
 663 /**
 664  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 665  * @ecc_data1:  ecc code from nand spare area
 666  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 667  * @page_data:  page data
 668  *
 669  * This function compares two ECC's and indicates if there is an error.
 670  * If the error can be corrected it will be corrected to the buffer.
 671  * If there is no error, %0 is returned. If there is an error but it
 672  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 673  */
 674 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 675                             u8 *ecc_data2,      /* read from register */
 676                             u8 *page_data)
 677 {
 678         uint    i;
 679         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 680         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 681         u8      ecc_bit[24];
 682         u8      ecc_sum = 0;
 683         u8      find_bit = 0;
 684         uint    find_byte = 0;
 685         int     isEccFF;
 686
 687         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 688
 689         gen_true_ecc(ecc_data1);
 690         gen_true_ecc(ecc_data2);
 691
 692         for (i = 0; i <= 2; i++) {
 693                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 694                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 695         }
 696
 697         for (i = 0; i < 8; i++) {
 698                 tmp0_bit[i]     = *ecc_data1 % 2;
 699                 *ecc_data1      = *ecc_data1 / 2;
 700         }
 701
 702         for (i = 0; i < 8; i++) {
 703                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 704                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 705         }
 706
 707         for (i = 0; i < 8; i++) {
 708                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 709                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 710         }
 711
 712         for (i = 0; i < 8; i++) {
 713                 comp0_bit[i]     = *ecc_data2 % 2;
 714                 *ecc_data2       = *ecc_data2 / 2;
 715         }
 716
 717         for (i = 0; i < 8; i++) {
 718                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 719                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 720         }
 721
 722         for (i = 0; i < 8; i++) {
 723                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 724                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 725         }
 726
 727         for (i = 0; i < 6; i++)
 728                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 729
 730         for (i = 0; i < 8; i++)
 731                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 732
 733         for (i = 0; i < 8; i++)
 734                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 735
 736         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 737         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 738
 739         for (i = 0; i < 24; i++)
 740                 ecc_sum += ecc_bit[i];
 741
 742         switch (ecc_sum) {
 743         case 0:
 744                 /* Not reached because this function is not called if
 745                  *  ECC values are equal
 746                  */
 747                 return 0;
 748
 749         case 1:
 750                 /* Uncorrectable error */
 751                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 752                 return -1;
 753
 754         case 11:
 755                 /* UN-Correctable error */
 756                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
 757                 return -1;
 758
 759         case 12:
 760                 /* Correctable error */
 761                 find_byte = (ecc_bit[23] << 8) +
 762                             (ecc_bit[21] << 7) +
 763                             (ecc_bit[19] << 6) +
 764                             (ecc_bit[17] << 5) +
 765                             (ecc_bit[15] << 4) +
 766                             (ecc_bit[13] << 3) +
 767                             (ecc_bit[11] << 2) +
 768                             (ecc_bit[9]  << 1) +
 769                             ecc_bit[7];
 770
 771                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 772
 773                 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
 774                                 "offset: %d, bit: %d\n", find_byte, find_bit);
 775
 776                 page_data[find_byte] ^= (1 << find_bit);
 777
 778                 return 1;
 779         default:
 780                 if (isEccFF) {
 781                         if (ecc_data2[0] == 0 &&
 782                             ecc_data2[1] == 0 &&
 783                             ecc_data2[2] == 0)
 784                                 return 0;
 785                 }
 786                 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
 787                 return -1;
 788         }
 789 }
 790
 791 /**
 792  * omap_correct_data - Compares the ECC read with HW generated ECC
 793  * @mtd: MTD device structure
 794  * @dat: page data
 795  * @read_ecc: ecc read from nand flash
 796  * @calc_ecc: ecc read from HW ECC registers
 797  *
 798  * Compares the ecc read from nand spare area with ECC registers values
 799  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 800  * detection and correction. If there are no errors, %0 is returned. If
 801  * there were errors and all of the errors were corrected, the number of
 802  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 803  * returned.
 804  */
 805 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 806                                 u_char *read_ecc, u_char *calc_ecc)
 807 {
 808         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 809                                                         mtd);
 810         int blockCnt = 0, i = 0, ret = 0;
 811         int stat = 0;
 812
 813         /* Ex NAND_ECC_HW12_2048 */
 814         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 815                         (info->nand.ecc.size  == 2048))
 816                 blockCnt = 4;
 817         else
 818                 blockCnt = 1;
 819
 820         for (i = 0; i < blockCnt; i++) {
 821                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 822                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 823                         if (ret < 0)
 824                                 return ret;
 825                         /* keep track of the number of corrected errors */
 826                         stat += ret;
 827                 }
 828                 read_ecc += 3;
 829                 calc_ecc += 3;
 830                 dat      += 512;
 831         }
 832         return stat;
 833 }
 834
 835 /**
 836  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 837  * @mtd: MTD device structure
 838  * @dat: The pointer to data on which ecc is computed
 839  * @ecc_code: The ecc_code buffer
 840  *
 841  * Using noninverted ECC can be considered ugly since writing a blank
 842  * page ie. padding will clear the ECC bytes. This is no problem as long
 843  * nobody is trying to write data on the seemingly unused page. Reading
 844  * an erased page will produce an ECC mismatch between generated and read
 845  * ECC bytes that has to be dealt with separately.
 846  */
 847 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 848                                 u_char *ecc_code)
 849 {
 850         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 851                                                         mtd);
 852         return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 853 }
 854
 855 /**
 856  * omap_enable_hwecc - This function enables the hardware ecc functionality
 857  * @mtd: MTD device structure
 858  * @mode: Read/Write mode
 859  */
 860 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 861 {
 862         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 863                                                         mtd);
 864         struct nand_chip *chip = mtd->priv;
 865         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 866
 867         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 868 }
 869
 870 /**
 871  * omap_wait - wait until the command is done
 872  * @mtd: MTD device structure
 873  * @chip: NAND Chip structure
 874  *
 875  * Wait function is called during Program and erase operations and
 876  * the way it is called from MTD layer, we should wait till the NAND
 877  * chip is ready after the programming/erase operation has completed.
 878  *
 879  * Erase can take up to 400ms and program up to 20ms according to
 880  * general NAND and SmartMedia specs
 881  */
 882 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 883 {
 884         struct nand_chip *this = mtd->priv;
 885         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 886                                                         mtd);
 887         unsigned long timeo = jiffies;
 888         int status = NAND_STATUS_FAIL, state = this->state;
 889
 890         if (state == FL_ERASING)
 891                 timeo += (HZ * 400) / 1000;
 892         else
 893                 timeo += (HZ * 20) / 1000;
 894
 895         gpmc_nand_write(info->gpmc_cs,
 896                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 897         while (time_before(jiffies, timeo)) {
 898                 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 899                 if (status & NAND_STATUS_READY)
 900                         break;
 901                 cond_resched();
 902         }
 903         return status;
 904 }
 905
 906 /**
 907  * omap_dev_ready - calls the platform specific dev_ready function
 908  * @mtd: MTD device structure
 909  */
 910 static int omap_dev_ready(struct mtd_info *mtd)
 911 {
 912         unsigned int val = 0;
 913         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 914                                                         mtd);
 915
 916         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 917         if ((val & 0x100) == 0x100) {
 918                 /* Clear IRQ Interrupt */
 919                 val |= 0x100;
 920                 val &= ~(0x0);
 921                 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
 922         } else {
 923                 unsigned int cnt = 0;
 924                 while (cnt++ < 0x1FF) {
 925                         if  ((val & 0x100) == 0x100)
 926                                 return 0;
 927                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 928                 }
 929         }
 930
 931         return 1;
 932 }
 933
 934 static int __devinit omap_nand_probe(struct platform_device *pdev)
 935 {
 936         struct omap_nand_info           *info;
 937         struct omap_nand_platform_data  *pdata;
 938         int                             err;
 939         int                             i, offset;
 940
 941         pdata = pdev->dev.platform_data;
 942         if (pdata == NULL) {
 943                 dev_err(&pdev->dev, "platform data missing\n");
 944                 return -ENODEV;
 945         }
 946
 947         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
 948         if (!info)
 949                 return -ENOMEM;
 950
 951         platform_set_drvdata(pdev, info);
 952
 953         spin_lock_init(&info->controller.lock);
 954         init_waitqueue_head(&info->controller.wq);
 955
 956         info->pdev = pdev;
 957
 958         info->gpmc_cs           = pdata->cs;
 959         info->phys_base         = pdata->phys_base;
 960
 961         info->mtd.priv          = &info->nand;
 962         info->mtd.name          = dev_name(&pdev->dev);
 963         info->mtd.owner         = THIS_MODULE;
 964
 965         info->nand.options      = pdata->devsize;
 966         info->nand.options      |= NAND_SKIP_BBTSCAN;
 967
 968         /* NAND write protect off */
 969         gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 970
 971         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
 972                                 pdev->dev.driver->name)) {
 973                 err = -EBUSY;
 974                 goto out_free_info;
 975         }
 976
 977         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
 978         if (!info->nand.IO_ADDR_R) {
 979                 err = -ENOMEM;
 980                 goto out_release_mem_region;
 981         }
 982
 983         info->nand.controller = &info->controller;
 984
 985         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
 986         info->nand.cmd_ctrl  = omap_hwcontrol;
 987
 988         /*
 989          * If RDY/BSY line is connected to OMAP then use the omap ready
 990          * funcrtion and the generic nand_wait function which reads the status
 991          * register after monitoring the RDY/BSY line.Otherwise use a standard
 992          * chip delay which is slightly more than tR (AC Timing) of the NAND
 993          * device and read status register until you get a failure or success
 994          */
 995         if (pdata->dev_ready) {
 996                 info->nand.dev_ready = omap_dev_ready;
 997                 info->nand.chip_delay = 0;
 998         } else {
 999                 info->nand.waitfunc = omap_wait;
1000                 info->nand.chip_delay = 50;
1001         }
1002
1003         switch (pdata->xfer_type) {
1004         case NAND_OMAP_PREFETCH_POLLED:
1005                 info->nand.read_buf   = omap_read_buf_pref;
1006                 info->nand.write_buf  = omap_write_buf_pref;
1007                 break;
1008
1009         case NAND_OMAP_POLLED:
1010                 if (info->nand.options & NAND_BUSWIDTH_16) {
1011                         info->nand.read_buf   = omap_read_buf16;
1012                         info->nand.write_buf  = omap_write_buf16;
1013                 } else {
1014                         info->nand.read_buf   = omap_read_buf8;
1015                         info->nand.write_buf  = omap_write_buf8;
1016                 }
1017                 break;
1018
1019         case NAND_OMAP_PREFETCH_DMA:
1020                 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1021                                 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1022                 if (err < 0) {
1023                         info->dma_ch = -1;
1024                         dev_err(&pdev->dev, "DMA request failed!\n");
1025                         goto out_release_mem_region;
1026                 } else {
1027                         omap_set_dma_dest_burst_mode(info->dma_ch,
1028                                         OMAP_DMA_DATA_BURST_16);
1029                         omap_set_dma_src_burst_mode(info->dma_ch,
1030                                         OMAP_DMA_DATA_BURST_16);
1031
1032                         info->nand.read_buf   = omap_read_buf_dma_pref;
1033                         info->nand.write_buf  = omap_write_buf_dma_pref;
1034                 }
1035                 break;
1036
1037         case NAND_OMAP_PREFETCH_IRQ:
1038                 err = request_irq(pdata->gpmc_irq,
1039                                 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1040                 if (err) {
1041                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1042                                                         pdata->gpmc_irq, err);
1043                         goto out_release_mem_region;
1044                 } else {
1045                         info->gpmc_irq       = pdata->gpmc_irq;
1046                         info->nand.read_buf  = omap_read_buf_irq_pref;
1047                         info->nand.write_buf = omap_write_buf_irq_pref;
1048                 }
1049                 break;
1050
1051         default:
1052                 dev_err(&pdev->dev,
1053                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1054                 err = -EINVAL;
1055                 goto out_release_mem_region;
1056         }
1057
1058         info->nand.verify_buf = omap_verify_buf;
1059
1060         /* selsect the ecc type */
1061         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1062                 info->nand.ecc.mode = NAND_ECC_SOFT;
1063         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1064                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1065                 info->nand.ecc.bytes            = 3;
1066                 info->nand.ecc.size             = 512;
1067                 info->nand.ecc.calculate        = omap_calculate_ecc;
1068                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1069                 info->nand.ecc.correct          = omap_correct_data;
1070                 info->nand.ecc.mode             = NAND_ECC_HW;
1071         }
1072
1073         /* DIP switches on some boards change between 8 and 16 bit
1074          * bus widths for flash.  Try the other width if the first try fails.
1075          */
1076         if (nand_scan(&info->mtd, 1)) {
1077                 info->nand.options ^= NAND_BUSWIDTH_16;
1078                 if (nand_scan(&info->mtd, 1)) {
1079                         err = -ENXIO;
1080                         goto out_release_mem_region;
1081                 }
1082         }
1083
1084         /* rom code layout */
1085         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1086
1087                 if (info->nand.options & NAND_BUSWIDTH_16)
1088                         offset = 2;
1089                 else {
1090                         offset = 1;
1091                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1092                 }
1093                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1094                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1095                         omap_oobinfo.eccpos[i] = i+offset;
1096
1097                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1098                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1099                                         (offset + omap_oobinfo.eccbytes);
1100
1101                 info->nand.ecc.layout = &omap_oobinfo;
1102         }
1103
1104 #ifdef CONFIG_MTD_PARTITIONS
1105         err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
1106         if (err > 0)
1107                 add_mtd_partitions(&info->mtd, info->parts, err);
1108         else if (pdata->parts)
1109                 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
1110         else
1111 #endif
1112                 add_mtd_device(&info->mtd);
1113
1114         platform_set_drvdata(pdev, &info->mtd);
1115
1116         return 0;
1117
1118 out_release_mem_region:
1119         release_mem_region(info->phys_base, NAND_IO_SIZE);
1120 out_free_info:
1121         kfree(info);
1122
1123         return err;
1124 }
1125
1126 static int omap_nand_remove(struct platform_device *pdev)
1127 {
1128         struct mtd_info *mtd = platform_get_drvdata(pdev);
1129         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1130                                                         mtd);
1131
1132         platform_set_drvdata(pdev, NULL);
1133         if (info->dma_ch != -1)
1134                 omap_free_dma(info->dma_ch);
1135
1136         if (info->gpmc_irq)
1137                 free_irq(info->gpmc_irq, info);
1138
1139         /* Release NAND device, its internal structures and partitions */
1140         nand_release(&info->mtd);
1141         iounmap(info->nand.IO_ADDR_R);
1142         kfree(&info->mtd);
1143         return 0;
1144 }
1145
1146 static struct platform_driver omap_nand_driver = {
1147         .probe          = omap_nand_probe,
1148         .remove         = omap_nand_remove,
1149         .driver         = {
1150                 .name   = DRIVER_NAME,
1151                 .owner  = THIS_MODULE,
1152         },
1153 };
1154
1155 static int __init omap_nand_init(void)
1156 {
1157         pr_info("%s driver initializing\n", DRIVER_NAME);
1158
1159         return platform_driver_register(&omap_nand_driver);
1160 }
1161
1162 static void __exit omap_nand_exit(void)
1163 {
1164         platform_driver_unregister(&omap_nand_driver);
1165 }
1166
1167 module_init(omap_nand_init);
1168 module_exit(omap_nand_exit);
1169
1170 MODULE_ALIAS("platform:" DRIVER_NAME);
1171 MODULE_LICENSE("GPL");
1172 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");