2 * drivers/mtd/nand/ppchameleonevb.c
4 * Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
6 * Derived from drivers/mtd/nand/edb7312.c
9 * $Id: ppchameleonevb.c,v 1.7 2005/11/07 11:14:31 gleixner Exp $
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 * This is a device driver for the NAND flash devices found on the
17 * PPChameleon/PPChameleonEVB system.
18 * PPChameleon options (autodetected):
20 * - ME model: 32MB (Samsung K9F5608U0B)
21 * - HI model: 128MB (Samsung K9F1G08UOM)
22 * PPChameleonEVB options:
23 * - 32MB (Samsung K9F5608U0B)
26 #include <linux/init.h>
27 #include <linux/slab.h>
28 #include <linux/module.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/mtd/partitions.h>
33 #include <platforms/PPChameleonEVB.h>
35 #undef USE_READY_BUSY_PIN
36 #define USE_READY_BUSY_PIN
37 /* see datasheets (tR) */
38 #define NAND_BIG_DELAY_US 25
39 #define NAND_SMALL_DELAY_US 10
42 #define SZ_4M 0x00400000
43 #define NAND_SMALL_SIZE 0x02000000
44 #define NAND_MTD_NAME "ppchameleon-nand"
45 #define NAND_EVB_MTD_NAME "ppchameleonevb-nand"
47 /* GPIO pins used to drive NAND chip mounted on processor module */
48 #define NAND_nCE_GPIO_PIN (0x80000000 >> 1)
49 #define NAND_CLE_GPIO_PIN (0x80000000 >> 2)
50 #define NAND_ALE_GPIO_PIN (0x80000000 >> 3)
51 #define NAND_RB_GPIO_PIN (0x80000000 >> 4)
52 /* GPIO pins used to drive NAND chip mounted on EVB */
53 #define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14)
54 #define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15)
55 #define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16)
56 #define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31)
59 * MTD structure for PPChameleonEVB board
61 static struct mtd_info *ppchameleon_mtd = NULL;
62 static struct mtd_info *ppchameleonevb_mtd = NULL;
67 static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
68 static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;
71 module_param(ppchameleon_fio_pbase, ulong, 0);
72 module_param(ppchameleonevb_fio_pbase, ulong, 0);
74 __setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase);
75 __setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase);
78 #ifdef CONFIG_MTD_PARTITIONS
80 * Define static partitions for flash devices
82 static struct mtd_partition partition_info_hi[] = {
83 { .name = "PPChameleon HI Nand Flash",
85 .size = 128 * 1024 * 1024
89 static struct mtd_partition partition_info_me[] = {
90 { .name = "PPChameleon ME Nand Flash",
92 .size = 32 * 1024 * 1024
96 static struct mtd_partition partition_info_evb[] = {
97 { .name = "PPChameleonEVB Nand Flash",
99 .size = 32 * 1024 * 1024
103 #define NUM_PARTITIONS 1
105 extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partition **pparts, const char *mtd_id);
109 * hardware specific access to control-lines
111 static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd)
115 case NAND_CTL_SETCLE:
116 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
118 case NAND_CTL_CLRCLE:
119 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
121 case NAND_CTL_SETALE:
122 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
124 case NAND_CTL_CLRALE:
125 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
127 case NAND_CTL_SETNCE:
128 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
130 case NAND_CTL_CLRNCE:
131 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
136 static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
140 case NAND_CTL_SETCLE:
141 MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
143 case NAND_CTL_CLRCLE:
144 MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
146 case NAND_CTL_SETALE:
147 MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
149 case NAND_CTL_CLRALE:
150 MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
152 case NAND_CTL_SETNCE:
153 MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
155 case NAND_CTL_CLRNCE:
156 MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
161 #ifdef USE_READY_BUSY_PIN
163 * read device ready pin
165 static int ppchameleon_device_ready(struct mtd_info *minfo)
167 if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN)
172 static int ppchameleonevb_device_ready(struct mtd_info *minfo)
174 if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN)
180 #ifdef CONFIG_MTD_PARTITIONS
181 const char *part_probes[] = { "cmdlinepart", NULL };
182 const char *part_probes_evb[] = { "cmdlinepart", NULL };
186 * Main initialization routine
188 static int __init ppchameleonevb_init(void)
190 struct nand_chip *this;
191 const char *part_type = 0;
192 int mtd_parts_nb = 0;
193 struct mtd_partition *mtd_parts = 0;
194 void __iomem *ppchameleon_fio_base;
195 void __iomem *ppchameleonevb_fio_base;
197 /*********************************
198 * Processor module NAND (if any) *
199 *********************************/
200 /* Allocate memory for MTD device structure and private data */
201 ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
202 if (!ppchameleon_mtd) {
203 printk("Unable to allocate PPChameleon NAND MTD device structure.\n");
207 /* map physical address */
208 ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M);
209 if (!ppchameleon_fio_base) {
210 printk("ioremap PPChameleon NAND flash failed\n");
211 kfree(ppchameleon_mtd);
215 /* Get pointer to private data */
216 this = (struct nand_chip *)(&ppchameleon_mtd[1]);
218 /* Initialize structures */
219 memset(ppchameleon_mtd, 0, sizeof(struct mtd_info));
220 memset(this, 0, sizeof(struct nand_chip));
222 /* Link the private data with the MTD structure */
223 ppchameleon_mtd->priv = this;
225 /* Initialize GPIOs */
226 /* Pin mapping for NAND chip */
234 out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xC0FFFFFF);
235 /* three-state select */
236 out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xC0FFFFFF);
237 /* enable output driver */
238 out_be32((volatile unsigned *)GPIO0_TCR,
239 in_be32((volatile unsigned *)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN);
240 #ifdef USE_READY_BUSY_PIN
241 /* three-state select */
242 out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFF3FFFFF);
243 /* high-impedecence */
244 out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_RB_GPIO_PIN));
246 out_be32((volatile unsigned *)GPIO0_ISR1H,
247 (in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000);
250 /* insert callbacks */
251 this->IO_ADDR_R = ppchameleon_fio_base;
252 this->IO_ADDR_W = ppchameleon_fio_base;
253 this->hwcontrol = ppchameleon_hwcontrol;
254 #ifdef USE_READY_BUSY_PIN
255 this->dev_ready = ppchameleon_device_ready;
257 this->chip_delay = NAND_BIG_DELAY_US;
259 this->eccmode = NAND_ECC_SOFT;
261 /* Scan to find existence of the device (it could not be mounted) */
262 if (nand_scan(ppchameleon_mtd, 1)) {
263 iounmap((void *)ppchameleon_fio_base);
264 kfree(ppchameleon_mtd);
267 #ifndef USE_READY_BUSY_PIN
268 /* Adjust delay if necessary */
269 if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
270 this->chip_delay = NAND_SMALL_DELAY_US;
273 #ifdef CONFIG_MTD_PARTITIONS
274 ppchameleon_mtd->name = "ppchameleon-nand";
275 mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0);
276 if (mtd_parts_nb > 0)
277 part_type = "command line";
281 if (mtd_parts_nb == 0) {
282 if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
283 mtd_parts = partition_info_me;
285 mtd_parts = partition_info_hi;
286 mtd_parts_nb = NUM_PARTITIONS;
287 part_type = "static";
290 /* Register the partitions */
291 printk(KERN_NOTICE "Using %s partition definition\n", part_type);
292 add_mtd_partitions(ppchameleon_mtd, mtd_parts, mtd_parts_nb);
295 /****************************
296 * EVB NAND (always present) *
297 ****************************/
298 /* Allocate memory for MTD device structure and private data */
299 ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
300 if (!ppchameleonevb_mtd) {
301 printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
305 /* map physical address */
306 ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M);
307 if (!ppchameleonevb_fio_base) {
308 printk("ioremap PPChameleonEVB NAND flash failed\n");
309 kfree(ppchameleonevb_mtd);
313 /* Get pointer to private data */
314 this = (struct nand_chip *)(&ppchameleonevb_mtd[1]);
316 /* Initialize structures */
317 memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info));
318 memset(this, 0, sizeof(struct nand_chip));
320 /* Link the private data with the MTD structure */
321 ppchameleonevb_mtd->priv = this;
323 /* Initialize GPIOs */
324 /* Pin mapping for NAND chip */
332 out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xFFFFFFF0);
333 out_be32((volatile unsigned *)GPIO0_OSRL, in_be32((volatile unsigned *)GPIO0_OSRL) & 0x3FFFFFFF);
334 /* three-state select */
335 out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFFFFFFF0);
336 out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0x3FFFFFFF);
337 /* enable output driver */
338 out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN |
339 NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN);
340 #ifdef USE_READY_BUSY_PIN
341 /* three-state select */
342 out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0xFFFFFFFC);
343 /* high-impedecence */
344 out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN));
346 out_be32((volatile unsigned *)GPIO0_ISR1L,
347 (in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001);
350 /* insert callbacks */
351 this->IO_ADDR_R = ppchameleonevb_fio_base;
352 this->IO_ADDR_W = ppchameleonevb_fio_base;
353 this->hwcontrol = ppchameleonevb_hwcontrol;
354 #ifdef USE_READY_BUSY_PIN
355 this->dev_ready = ppchameleonevb_device_ready;
357 this->chip_delay = NAND_SMALL_DELAY_US;
360 this->eccmode = NAND_ECC_SOFT;
362 /* Scan to find existence of the device */
363 if (nand_scan(ppchameleonevb_mtd, 1)) {
364 iounmap((void *)ppchameleonevb_fio_base);
365 kfree(ppchameleonevb_mtd);
368 #ifdef CONFIG_MTD_PARTITIONS
369 ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
370 mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0);
371 if (mtd_parts_nb > 0)
372 part_type = "command line";
376 if (mtd_parts_nb == 0) {
377 mtd_parts = partition_info_evb;
378 mtd_parts_nb = NUM_PARTITIONS;
379 part_type = "static";
382 /* Register the partitions */
383 printk(KERN_NOTICE "Using %s partition definition\n", part_type);
384 add_mtd_partitions(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb);
390 module_init(ppchameleonevb_init);
395 static void __exit ppchameleonevb_cleanup(void)
397 struct nand_chip *this;
399 /* Release resources, unregister device(s) */
400 nand_release(ppchameleon_mtd);
401 nand_release(ppchameleonevb_mtd);
404 this = (struct nand_chip *) &ppchameleon_mtd[1];
405 iounmap((void *) this->IO_ADDR_R;
406 this = (struct nand_chip *) &ppchameleonevb_mtd[1];
407 iounmap((void *) this->IO_ADDR_R;
409 /* Free the MTD device structure */
410 kfree (ppchameleon_mtd);
411 kfree (ppchameleonevb_mtd);
413 module_exit(ppchameleonevb_cleanup);
415 MODULE_LICENSE("GPL");
416 MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
417 MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");