drivers/mtd/nand/pxa3xx_nand.c

   1 /*
   2  * drivers/mtd/nand/pxa3xx_nand.c
   3  *
   4  * Copyright © 2005 Intel Corporation
   5  * Copyright © 2006 Marvell International Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/slab.h>
  25
  26 #include <mach/dma.h>
  27 #include <plat/pxa3xx_nand.h>
  28
  29 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
  30 #define NAND_STOP_DELAY         (2 * HZ/50)
  31 #define PAGE_CHUNK_SIZE         (2048)
  32
  33 /* registers and bit definitions */
  34 #define NDCR            (0x00) /* Control register */
  35 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
  36 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
  37 #define NDSR            (0x14) /* Status Register */
  38 #define NDPCR           (0x18) /* Page Count Register */
  39 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
  40 #define NDBDR1          (0x20) /* Bad Block Register 1 */
  41 #define NDDB            (0x40) /* Data Buffer */
  42 #define NDCB0           (0x48) /* Command Buffer0 */
  43 #define NDCB1           (0x4C) /* Command Buffer1 */
  44 #define NDCB2           (0x50) /* Command Buffer2 */
  45
  46 #define NDCR_SPARE_EN           (0x1 << 31)
  47 #define NDCR_ECC_EN             (0x1 << 30)
  48 #define NDCR_DMA_EN             (0x1 << 29)
  49 #define NDCR_ND_RUN             (0x1 << 28)
  50 #define NDCR_DWIDTH_C           (0x1 << 27)
  51 #define NDCR_DWIDTH_M           (0x1 << 26)
  52 #define NDCR_PAGE_SZ            (0x1 << 24)
  53 #define NDCR_NCSX               (0x1 << 23)
  54 #define NDCR_ND_MODE            (0x3 << 21)
  55 #define NDCR_NAND_MODE          (0x0)
  56 #define NDCR_CLR_PG_CNT         (0x1 << 20)
  57 #define NDCR_STOP_ON_UNCOR      (0x1 << 19)
  58 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
  59 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  60
  61 #define NDCR_RA_START           (0x1 << 15)
  62 #define NDCR_PG_PER_BLK         (0x1 << 14)
  63 #define NDCR_ND_ARB_EN          (0x1 << 12)
  64 #define NDCR_INT_MASK           (0xFFF)
  65
  66 #define NDSR_MASK               (0xfff)
  67 #define NDSR_RDY                (0x1 << 12)
  68 #define NDSR_FLASH_RDY          (0x1 << 11)
  69 #define NDSR_CS0_PAGED          (0x1 << 10)
  70 #define NDSR_CS1_PAGED          (0x1 << 9)
  71 #define NDSR_CS0_CMDD           (0x1 << 8)
  72 #define NDSR_CS1_CMDD           (0x1 << 7)
  73 #define NDSR_CS0_BBD            (0x1 << 6)
  74 #define NDSR_CS1_BBD            (0x1 << 5)
  75 #define NDSR_DBERR              (0x1 << 4)
  76 #define NDSR_SBERR              (0x1 << 3)
  77 #define NDSR_WRDREQ             (0x1 << 2)
  78 #define NDSR_RDDREQ             (0x1 << 1)
  79 #define NDSR_WRCMDREQ           (0x1)
  80
  81 #define NDCB0_ST_ROW_EN         (0x1 << 26)
  82 #define NDCB0_AUTO_RS           (0x1 << 25)
  83 #define NDCB0_CSEL              (0x1 << 24)
  84 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
  85 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  86 #define NDCB0_NC                (0x1 << 20)
  87 #define NDCB0_DBC               (0x1 << 19)
  88 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
  89 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  90 #define NDCB0_CMD2_MASK         (0xff << 8)
  91 #define NDCB0_CMD1_MASK         (0xff)
  92 #define NDCB0_ADDR_CYC_SHIFT    (16)
  93
  94 /* macros for registers read/write */
  95 #define nand_writel(info, off, val)     \
  96         __raw_writel((val), (info)->mmio_base + (off))
  97
  98 #define nand_readl(info, off)           \
  99         __raw_readl((info)->mmio_base + (off))
 100
 101 /* error code and state */
 102 enum {
 103         ERR_NONE        = 0,
 104         ERR_DMABUSERR   = -1,
 105         ERR_SENDCMD     = -2,
 106         ERR_DBERR       = -3,
 107         ERR_BBERR       = -4,
 108         ERR_SBERR       = -5,
 109 };
 110
 111 enum {
 112         STATE_IDLE = 0,
 113         STATE_PREPARED,
 114         STATE_CMD_HANDLE,
 115         STATE_DMA_READING,
 116         STATE_DMA_WRITING,
 117         STATE_DMA_DONE,
 118         STATE_PIO_READING,
 119         STATE_PIO_WRITING,
 120         STATE_CMD_DONE,
 121         STATE_READY,
 122 };
 123
 124 struct pxa3xx_nand_host {
 125         struct nand_chip        chip;
 126         struct pxa3xx_nand_cmdset *cmdset;
 127         struct mtd_info         *mtd;
 128         void                    *info_data;
 129
 130         /* page size of attached chip */
 131         unsigned int            page_size;
 132         int                     use_ecc;
 133         int                     cs;
 134
 135         /* calculated from pxa3xx_nand_flash data */
 136         unsigned int            col_addr_cycles;
 137         unsigned int            row_addr_cycles;
 138         size_t                  read_id_bytes;
 139
 140         /* cached register value */
 141         uint32_t                reg_ndcr;
 142         uint32_t                ndtr0cs0;
 143         uint32_t                ndtr1cs0;
 144 };
 145
 146 struct pxa3xx_nand_info {
 147         struct nand_hw_control  controller;
 148         struct platform_device   *pdev;
 149
 150         struct clk              *clk;
 151         void __iomem            *mmio_base;
 152         unsigned long           mmio_phys;
 153         struct completion       cmd_complete;
 154
 155         unsigned int            buf_start;
 156         unsigned int            buf_count;
 157
 158         /* DMA information */
 159         int                     drcmr_dat;
 160         int                     drcmr_cmd;
 161
 162         unsigned char           *data_buff;
 163         unsigned char           *oob_buff;
 164         dma_addr_t              data_buff_phys;
 165         int                     data_dma_ch;
 166         struct pxa_dma_desc     *data_desc;
 167         dma_addr_t              data_desc_addr;
 168
 169         struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
 170         unsigned int            state;
 171
 172         int                     cs;
 173         int                     use_ecc;        /* use HW ECC ? */
 174         int                     use_dma;        /* use DMA ? */
 175         int                     is_ready;
 176
 177         unsigned int            page_size;      /* page size of attached chip */
 178         unsigned int            data_size;      /* data size in FIFO */
 179         unsigned int            oob_size;
 180         int                     retcode;
 181
 182         /* generated NDCBx register values */
 183         uint32_t                ndcb0;
 184         uint32_t                ndcb1;
 185         uint32_t                ndcb2;
 186 };
 187
 188 static bool use_dma = 1;
 189 module_param(use_dma, bool, 0444);
 190 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
 191
 192 /*
 193  * Default NAND flash controller configuration setup by the
 194  * bootloader. This configuration is used only when pdata->keep_config is set
 195  */
 196 static struct pxa3xx_nand_cmdset default_cmdset = {
 197         .read1          = 0x3000,
 198         .read2          = 0x0050,
 199         .program        = 0x1080,
 200         .read_status    = 0x0070,
 201         .read_id        = 0x0090,
 202         .erase          = 0xD060,
 203         .reset          = 0x00FF,
 204         .lock           = 0x002A,
 205         .unlock         = 0x2423,
 206         .lock_status    = 0x007A,
 207 };
 208
 209 static struct pxa3xx_nand_timing timing[] = {
 210         { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 211         { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 212         { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 213         { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 214 };
 215
 216 static struct pxa3xx_nand_flash builtin_flash_types[] = {
 217 { "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },
 218 { "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },
 219 { "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },
 220 { "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },
 221 { "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },
 222 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },
 223 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },
 224 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },
 225 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },
 226 };
 227
 228 /* Define a default flash type setting serve as flash detecting only */
 229 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 230
 231 const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
 232
 233 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 234 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 235 #define NDTR0_tWH(c)    (min((c), 7) << 11)
 236 #define NDTR0_tWP(c)    (min((c), 7) << 8)
 237 #define NDTR0_tRH(c)    (min((c), 7) << 3)
 238 #define NDTR0_tRP(c)    (min((c), 7) << 0)
 239
 240 #define NDTR1_tR(c)     (min((c), 65535) << 16)
 241 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 242 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 243
 244 /* convert nano-seconds to nand flash controller clock cycles */
 245 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 246
 247 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
 248                                    const struct pxa3xx_nand_timing *t)
 249 {
 250         struct pxa3xx_nand_info *info = host->info_data;
 251         unsigned long nand_clk = clk_get_rate(info->clk);
 252         uint32_t ndtr0, ndtr1;
 253
 254         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 255                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 256                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
 257                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
 258                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
 259                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
 260
 261         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
 262                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 263                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 264
 265         host->ndtr0cs0 = ndtr0;
 266         host->ndtr1cs0 = ndtr1;
 267         nand_writel(info, NDTR0CS0, ndtr0);
 268         nand_writel(info, NDTR1CS0, ndtr1);
 269 }
 270
 271 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 272 {
 273         struct pxa3xx_nand_host *host = info->host[info->cs];
 274         int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
 275
 276         info->data_size = host->page_size;
 277         if (!oob_enable) {
 278                 info->oob_size = 0;
 279                 return;
 280         }
 281
 282         switch (host->page_size) {
 283         case 2048:
 284                 info->oob_size = (info->use_ecc) ? 40 : 64;
 285                 break;
 286         case 512:
 287                 info->oob_size = (info->use_ecc) ? 8 : 16;
 288                 break;
 289         }
 290 }
 291
 292 /**
 293  * NOTE: it is a must to set ND_RUN firstly, then write
 294  * command buffer, otherwise, it does not work.
 295  * We enable all the interrupt at the same time, and
 296  * let pxa3xx_nand_irq to handle all logic.
 297  */
 298 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
 299 {
 300         struct pxa3xx_nand_host *host = info->host[info->cs];
 301         uint32_t ndcr;
 302
 303         ndcr = host->reg_ndcr;
 304         ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
 305         ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
 306         ndcr |= NDCR_ND_RUN;
 307
 308         /* clear status bits and run */
 309         nand_writel(info, NDCR, 0);
 310         nand_writel(info, NDSR, NDSR_MASK);
 311         nand_writel(info, NDCR, ndcr);
 312 }
 313
 314 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 315 {
 316         uint32_t ndcr;
 317         int timeout = NAND_STOP_DELAY;
 318
 319         /* wait RUN bit in NDCR become 0 */
 320         ndcr = nand_readl(info, NDCR);
 321         while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
 322                 ndcr = nand_readl(info, NDCR);
 323                 udelay(1);
 324         }
 325
 326         if (timeout <= 0) {
 327                 ndcr &= ~NDCR_ND_RUN;
 328                 nand_writel(info, NDCR, ndcr);
 329         }
 330         /* clear status bits */
 331         nand_writel(info, NDSR, NDSR_MASK);
 332 }
 333
 334 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 335 {
 336         uint32_t ndcr;
 337
 338         ndcr = nand_readl(info, NDCR);
 339         nand_writel(info, NDCR, ndcr & ~int_mask);
 340 }
 341
 342 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 343 {
 344         uint32_t ndcr;
 345
 346         ndcr = nand_readl(info, NDCR);
 347         nand_writel(info, NDCR, ndcr | int_mask);
 348 }
 349
 350 static void handle_data_pio(struct pxa3xx_nand_info *info)
 351 {
 352         switch (info->state) {
 353         case STATE_PIO_WRITING:
 354                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
 355                                 DIV_ROUND_UP(info->data_size, 4));
 356                 if (info->oob_size > 0)
 357                         __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 358                                         DIV_ROUND_UP(info->oob_size, 4));
 359                 break;
 360         case STATE_PIO_READING:
 361                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
 362                                 DIV_ROUND_UP(info->data_size, 4));
 363                 if (info->oob_size > 0)
 364                         __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 365                                         DIV_ROUND_UP(info->oob_size, 4));
 366                 break;
 367         default:
 368                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 369                                 info->state);
 370                 BUG();
 371         }
 372 }
 373
 374 static void start_data_dma(struct pxa3xx_nand_info *info)
 375 {
 376         struct pxa_dma_desc *desc = info->data_desc;
 377         int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 378
 379         desc->ddadr = DDADR_STOP;
 380         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
 381
 382         switch (info->state) {
 383         case STATE_DMA_WRITING:
 384                 desc->dsadr = info->data_buff_phys;
 385                 desc->dtadr = info->mmio_phys + NDDB;
 386                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 387                 break;
 388         case STATE_DMA_READING:
 389                 desc->dtadr = info->data_buff_phys;
 390                 desc->dsadr = info->mmio_phys + NDDB;
 391                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 392                 break;
 393         default:
 394                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 395                                 info->state);
 396                 BUG();
 397         }
 398
 399         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
 400         DDADR(info->data_dma_ch) = info->data_desc_addr;
 401         DCSR(info->data_dma_ch) |= DCSR_RUN;
 402 }
 403
 404 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 405 {
 406         struct pxa3xx_nand_info *info = data;
 407         uint32_t dcsr;
 408
 409         dcsr = DCSR(channel);
 410         DCSR(channel) = dcsr;
 411
 412         if (dcsr & DCSR_BUSERR) {
 413                 info->retcode = ERR_DMABUSERR;
 414         }
 415
 416         info->state = STATE_DMA_DONE;
 417         enable_int(info, NDCR_INT_MASK);
 418         nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 419 }
 420
 421 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 422 {
 423         struct pxa3xx_nand_info *info = devid;
 424         unsigned int status, is_completed = 0;
 425         unsigned int ready, cmd_done;
 426
 427         if (info->cs == 0) {
 428                 ready           = NDSR_FLASH_RDY;
 429                 cmd_done        = NDSR_CS0_CMDD;
 430         } else {
 431                 ready           = NDSR_RDY;
 432                 cmd_done        = NDSR_CS1_CMDD;
 433         }
 434
 435         status = nand_readl(info, NDSR);
 436
 437         if (status & NDSR_DBERR)
 438                 info->retcode = ERR_DBERR;
 439         if (status & NDSR_SBERR)
 440                 info->retcode = ERR_SBERR;
 441         if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 442                 /* whether use dma to transfer data */
 443                 if (info->use_dma) {
 444                         disable_int(info, NDCR_INT_MASK);
 445                         info->state = (status & NDSR_RDDREQ) ?
 446                                       STATE_DMA_READING : STATE_DMA_WRITING;
 447                         start_data_dma(info);
 448                         goto NORMAL_IRQ_EXIT;
 449                 } else {
 450                         info->state = (status & NDSR_RDDREQ) ?
 451                                       STATE_PIO_READING : STATE_PIO_WRITING;
 452                         handle_data_pio(info);
 453                 }
 454         }
 455         if (status & cmd_done) {
 456                 info->state = STATE_CMD_DONE;
 457                 is_completed = 1;
 458         }
 459         if (status & ready) {
 460                 info->is_ready = 1;
 461                 info->state = STATE_READY;
 462         }
 463
 464         if (status & NDSR_WRCMDREQ) {
 465                 nand_writel(info, NDSR, NDSR_WRCMDREQ);
 466                 status &= ~NDSR_WRCMDREQ;
 467                 info->state = STATE_CMD_HANDLE;
 468                 nand_writel(info, NDCB0, info->ndcb0);
 469                 nand_writel(info, NDCB0, info->ndcb1);
 470                 nand_writel(info, NDCB0, info->ndcb2);
 471         }
 472
 473         /* clear NDSR to let the controller exit the IRQ */
 474         nand_writel(info, NDSR, status);
 475         if (is_completed)
 476                 complete(&info->cmd_complete);
 477 NORMAL_IRQ_EXIT:
 478         return IRQ_HANDLED;
 479 }
 480
 481 static inline int is_buf_blank(uint8_t *buf, size_t len)
 482 {
 483         for (; len > 0; len--)
 484                 if (*buf++ != 0xff)
 485                         return 0;
 486         return 1;
 487 }
 488
 489 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
 490                 uint16_t column, int page_addr)
 491 {
 492         uint16_t cmd;
 493         int addr_cycle, exec_cmd;
 494         struct pxa3xx_nand_host *host;
 495         struct mtd_info *mtd;
 496
 497         host = info->host[info->cs];
 498         mtd = host->mtd;
 499         addr_cycle = 0;
 500         exec_cmd = 1;
 501
 502         /* reset data and oob column point to handle data */
 503         info->buf_start         = 0;
 504         info->buf_count         = 0;
 505         info->oob_size          = 0;
 506         info->use_ecc           = 0;
 507         info->is_ready          = 0;
 508         info->retcode           = ERR_NONE;
 509         if (info->cs != 0)
 510                 info->ndcb0 = NDCB0_CSEL;
 511         else
 512                 info->ndcb0 = 0;
 513
 514         switch (command) {
 515         case NAND_CMD_READ0:
 516         case NAND_CMD_PAGEPROG:
 517                 info->use_ecc = 1;
 518         case NAND_CMD_READOOB:
 519                 pxa3xx_set_datasize(info);
 520                 break;
 521         case NAND_CMD_SEQIN:
 522                 exec_cmd = 0;
 523                 break;
 524         default:
 525                 info->ndcb1 = 0;
 526                 info->ndcb2 = 0;
 527                 break;
 528         }
 529
 530         addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
 531                                     + host->col_addr_cycles);
 532
 533         switch (command) {
 534         case NAND_CMD_READOOB:
 535         case NAND_CMD_READ0:
 536                 cmd = host->cmdset->read1;
 537                 if (command == NAND_CMD_READOOB)
 538                         info->buf_start = mtd->writesize + column;
 539                 else
 540                         info->buf_start = column;
 541
 542                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
 543                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 544                                         | addr_cycle
 545                                         | (cmd & NDCB0_CMD1_MASK);
 546                 else
 547                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 548                                         | NDCB0_DBC
 549                                         | addr_cycle
 550                                         | cmd;
 551
 552         case NAND_CMD_SEQIN:
 553                 /* small page addr setting */
 554                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
 555                         info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 556                                         | (column & 0xFF);
 557
 558                         info->ndcb2 = 0;
 559                 } else {
 560                         info->ndcb1 = ((page_addr & 0xFFFF) << 16)
 561                                         | (column & 0xFFFF);
 562
 563                         if (page_addr & 0xFF0000)
 564                                 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
 565                         else
 566                                 info->ndcb2 = 0;
 567                 }
 568
 569                 info->buf_count = mtd->writesize + mtd->oobsize;
 570                 memset(info->data_buff, 0xFF, info->buf_count);
 571
 572                 break;
 573
 574         case NAND_CMD_PAGEPROG:
 575                 if (is_buf_blank(info->data_buff,
 576                                         (mtd->writesize + mtd->oobsize))) {
 577                         exec_cmd = 0;
 578                         break;
 579                 }
 580
 581                 cmd = host->cmdset->program;
 582                 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 583                                 | NDCB0_AUTO_RS
 584                                 | NDCB0_ST_ROW_EN
 585                                 | NDCB0_DBC
 586                                 | cmd
 587                                 | addr_cycle;
 588                 break;
 589
 590         case NAND_CMD_READID:
 591                 cmd = host->cmdset->read_id;
 592                 info->buf_count = host->read_id_bytes;
 593                 info->ndcb0 |= NDCB0_CMD_TYPE(3)
 594                                 | NDCB0_ADDR_CYC(1)
 595                                 | cmd;
 596
 597                 info->data_size = 8;
 598                 break;
 599         case NAND_CMD_STATUS:
 600                 cmd = host->cmdset->read_status;
 601                 info->buf_count = 1;
 602                 info->ndcb0 |= NDCB0_CMD_TYPE(4)
 603                                 | NDCB0_ADDR_CYC(1)
 604                                 | cmd;
 605
 606                 info->data_size = 8;
 607                 break;
 608
 609         case NAND_CMD_ERASE1:
 610                 cmd = host->cmdset->erase;
 611                 info->ndcb0 |= NDCB0_CMD_TYPE(2)
 612                                 | NDCB0_AUTO_RS
 613                                 | NDCB0_ADDR_CYC(3)
 614                                 | NDCB0_DBC
 615                                 | cmd;
 616                 info->ndcb1 = page_addr;
 617                 info->ndcb2 = 0;
 618
 619                 break;
 620         case NAND_CMD_RESET:
 621                 cmd = host->cmdset->reset;
 622                 info->ndcb0 |= NDCB0_CMD_TYPE(5)
 623                                 | cmd;
 624
 625                 break;
 626
 627         case NAND_CMD_ERASE2:
 628                 exec_cmd = 0;
 629                 break;
 630
 631         default:
 632                 exec_cmd = 0;
 633                 dev_err(&info->pdev->dev, "non-supported command %x\n",
 634                                 command);
 635                 break;
 636         }
 637
 638         return exec_cmd;
 639 }
 640
 641 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 642                                 int column, int page_addr)
 643 {
 644         struct pxa3xx_nand_host *host = mtd->priv;
 645         struct pxa3xx_nand_info *info = host->info_data;
 646         int ret, exec_cmd;
 647
 648         /*
 649          * if this is a x16 device ,then convert the input
 650          * "byte" address into a "word" address appropriate
 651          * for indexing a word-oriented device
 652          */
 653         if (host->reg_ndcr & NDCR_DWIDTH_M)
 654                 column /= 2;
 655
 656         /*
 657          * There may be different NAND chip hooked to
 658          * different chip select, so check whether
 659          * chip select has been changed, if yes, reset the timing
 660          */
 661         if (info->cs != host->cs) {
 662                 info->cs = host->cs;
 663                 nand_writel(info, NDTR0CS0, host->ndtr0cs0);
 664                 nand_writel(info, NDTR1CS0, host->ndtr1cs0);
 665         }
 666
 667         info->state = STATE_PREPARED;
 668         exec_cmd = prepare_command_pool(info, command, column, page_addr);
 669         if (exec_cmd) {
 670                 init_completion(&info->cmd_complete);
 671                 pxa3xx_nand_start(info);
 672
 673                 ret = wait_for_completion_timeout(&info->cmd_complete,
 674                                 CHIP_DELAY_TIMEOUT);
 675                 if (!ret) {
 676                         dev_err(&info->pdev->dev, "Wait time out!!!\n");
 677                         /* Stop State Machine for next command cycle */
 678                         pxa3xx_nand_stop(info);
 679                 }
 680         }
 681         info->state = STATE_IDLE;
 682 }
 683
 684 static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 685                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 686 {
 687         chip->write_buf(mtd, buf, mtd->writesize);
 688         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 689 }
 690
 691 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 692                 struct nand_chip *chip, uint8_t *buf, int oob_required,
 693                 int page)
 694 {
 695         struct pxa3xx_nand_host *host = mtd->priv;
 696         struct pxa3xx_nand_info *info = host->info_data;
 697
 698         chip->read_buf(mtd, buf, mtd->writesize);
 699         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 700
 701         if (info->retcode == ERR_SBERR) {
 702                 switch (info->use_ecc) {
 703                 case 1:
 704                         mtd->ecc_stats.corrected++;
 705                         break;
 706                 case 0:
 707                 default:
 708                         break;
 709                 }
 710         } else if (info->retcode == ERR_DBERR) {
 711                 /*
 712                  * for blank page (all 0xff), HW will calculate its ECC as
 713                  * 0, which is different from the ECC information within
 714                  * OOB, ignore such double bit errors
 715                  */
 716                 if (is_buf_blank(buf, mtd->writesize))
 717                         info->retcode = ERR_NONE;
 718                 else
 719                         mtd->ecc_stats.failed++;
 720         }
 721
 722         return 0;
 723 }
 724
 725 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 726 {
 727         struct pxa3xx_nand_host *host = mtd->priv;
 728         struct pxa3xx_nand_info *info = host->info_data;
 729         char retval = 0xFF;
 730
 731         if (info->buf_start < info->buf_count)
 732                 /* Has just send a new command? */
 733                 retval = info->data_buff[info->buf_start++];
 734
 735         return retval;
 736 }
 737
 738 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 739 {
 740         struct pxa3xx_nand_host *host = mtd->priv;
 741         struct pxa3xx_nand_info *info = host->info_data;
 742         u16 retval = 0xFFFF;
 743
 744         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
 745                 retval = *((u16 *)(info->data_buff+info->buf_start));
 746                 info->buf_start += 2;
 747         }
 748         return retval;
 749 }
 750
 751 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 752 {
 753         struct pxa3xx_nand_host *host = mtd->priv;
 754         struct pxa3xx_nand_info *info = host->info_data;
 755         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 756
 757         memcpy(buf, info->data_buff + info->buf_start, real_len);
 758         info->buf_start += real_len;
 759 }
 760
 761 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 762                 const uint8_t *buf, int len)
 763 {
 764         struct pxa3xx_nand_host *host = mtd->priv;
 765         struct pxa3xx_nand_info *info = host->info_data;
 766         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 767
 768         memcpy(info->data_buff + info->buf_start, buf, real_len);
 769         info->buf_start += real_len;
 770 }
 771
 772 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
 773                 const uint8_t *buf, int len)
 774 {
 775         return 0;
 776 }
 777
 778 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 779 {
 780         return;
 781 }
 782
 783 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 784 {
 785         struct pxa3xx_nand_host *host = mtd->priv;
 786         struct pxa3xx_nand_info *info = host->info_data;
 787
 788         /* pxa3xx_nand_send_command has waited for command complete */
 789         if (this->state == FL_WRITING || this->state == FL_ERASING) {
 790                 if (info->retcode == ERR_NONE)
 791                         return 0;
 792                 else {
 793                         /*
 794                          * any error make it return 0x01 which will tell
 795                          * the caller the erase and write fail
 796                          */
 797                         return 0x01;
 798                 }
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 805                                     const struct pxa3xx_nand_flash *f)
 806 {
 807         struct platform_device *pdev = info->pdev;
 808         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 809         struct pxa3xx_nand_host *host = info->host[info->cs];
 810         uint32_t ndcr = 0x0; /* enable all interrupts */
 811
 812         if (f->page_size != 2048 && f->page_size != 512) {
 813                 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
 814                 return -EINVAL;
 815         }
 816
 817         if (f->flash_width != 16 && f->flash_width != 8) {
 818                 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
 819                 return -EINVAL;
 820         }
 821
 822         /* calculate flash information */
 823         host->cmdset = &default_cmdset;
 824         host->page_size = f->page_size;
 825         host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 826
 827         /* calculate addressing information */
 828         host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
 829
 830         if (f->num_blocks * f->page_per_block > 65536)
 831                 host->row_addr_cycles = 3;
 832         else
 833                 host->row_addr_cycles = 2;
 834
 835         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
 836         ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 837         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 838         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 839         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 840         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
 841
 842         ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 843         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 844
 845         host->reg_ndcr = ndcr;
 846
 847         pxa3xx_nand_set_timing(host, f->timing);
 848         return 0;
 849 }
 850
 851 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 852 {
 853         /*
 854          * We set 0 by hard coding here, for we don't support keep_config
 855          * when there is more than one chip attached to the controller
 856          */
 857         struct pxa3xx_nand_host *host = info->host[0];
 858         uint32_t ndcr = nand_readl(info, NDCR);
 859
 860         if (ndcr & NDCR_PAGE_SZ) {
 861                 host->page_size = 2048;
 862                 host->read_id_bytes = 4;
 863         } else {
 864                 host->page_size = 512;
 865                 host->read_id_bytes = 2;
 866         }
 867
 868         host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 869         host->cmdset = &default_cmdset;
 870
 871         host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 872         host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 873
 874         return 0;
 875 }
 876
 877 /* the maximum possible buffer size for large page with OOB data
 878  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
 879  * data buffer and the DMA descriptor
 880  */
 881 #define MAX_BUFF_SIZE   PAGE_SIZE
 882
 883 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 884 {
 885         struct platform_device *pdev = info->pdev;
 886         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
 887
 888         if (use_dma == 0) {
 889                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 890                 if (info->data_buff == NULL)
 891                         return -ENOMEM;
 892                 return 0;
 893         }
 894
 895         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
 896                                 &info->data_buff_phys, GFP_KERNEL);
 897         if (info->data_buff == NULL) {
 898                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 899                 return -ENOMEM;
 900         }
 901
 902         info->data_desc = (void *)info->data_buff + data_desc_offset;
 903         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 904
 905         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 906                                 pxa3xx_nand_data_dma_irq, info);
 907         if (info->data_dma_ch < 0) {
 908                 dev_err(&pdev->dev, "failed to request data dma\n");
 909                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 910                                 info->data_buff, info->data_buff_phys);
 911                 return info->data_dma_ch;
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 918 {
 919         struct mtd_info *mtd;
 920         int ret;
 921         mtd = info->host[info->cs]->mtd;
 922         /* use the common timing to make a try */
 923         ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
 924         if (ret)
 925                 return ret;
 926
 927         pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 928         if (info->is_ready)
 929                 return 0;
 930
 931         return -ENODEV;
 932 }
 933
 934 static int pxa3xx_nand_scan(struct mtd_info *mtd)
 935 {
 936         struct pxa3xx_nand_host *host = mtd->priv;
 937         struct pxa3xx_nand_info *info = host->info_data;
 938         struct platform_device *pdev = info->pdev;
 939         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 940         struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
 941         const struct pxa3xx_nand_flash *f = NULL;
 942         struct nand_chip *chip = mtd->priv;
 943         uint32_t id = -1;
 944         uint64_t chipsize;
 945         int i, ret, num;
 946
 947         if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
 948                 goto KEEP_CONFIG;
 949
 950         ret = pxa3xx_nand_sensing(info);
 951         if (ret) {
 952                 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
 953                          info->cs);
 954
 955                 return ret;
 956         }
 957
 958         chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
 959         id = *((uint16_t *)(info->data_buff));
 960         if (id != 0)
 961                 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
 962         else {
 963                 dev_warn(&info->pdev->dev,
 964                          "Read out ID 0, potential timing set wrong!!\n");
 965
 966                 return -EINVAL;
 967         }
 968
 969         num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
 970         for (i = 0; i < num; i++) {
 971                 if (i < pdata->num_flash)
 972                         f = pdata->flash + i;
 973                 else
 974                         f = &builtin_flash_types[i - pdata->num_flash + 1];
 975
 976                 /* find the chip in default list */
 977                 if (f->chip_id == id)
 978                         break;
 979         }
 980
 981         if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
 982                 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
 983
 984                 return -EINVAL;
 985         }
 986
 987         ret = pxa3xx_nand_config_flash(info, f);
 988         if (ret) {
 989                 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
 990                 return ret;
 991         }
 992
 993         pxa3xx_flash_ids[0].name = f->name;
 994         pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
 995         pxa3xx_flash_ids[0].pagesize = f->page_size;
 996         chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
 997         pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
 998         pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
 999         if (f->flash_width == 16)
1000                 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
1001         pxa3xx_flash_ids[1].name = NULL;
1002         def = pxa3xx_flash_ids;
1003 KEEP_CONFIG:
1004         chip->ecc.mode = NAND_ECC_HW;
1005         chip->ecc.size = host->page_size;
1006         chip->ecc.strength = 1;
1007
1008         chip->options |= NAND_NO_READRDY;
1009         if (host->reg_ndcr & NDCR_DWIDTH_M)
1010                 chip->options |= NAND_BUSWIDTH_16;
1011
1012         if (nand_scan_ident(mtd, 1, def))
1013                 return -ENODEV;
1014         /* calculate addressing information */
1015         if (mtd->writesize >= 2048)
1016                 host->col_addr_cycles = 2;
1017         else
1018                 host->col_addr_cycles = 1;
1019
1020         info->oob_buff = info->data_buff + mtd->writesize;
1021         if ((mtd->size >> chip->page_shift) > 65536)
1022                 host->row_addr_cycles = 3;
1023         else
1024                 host->row_addr_cycles = 2;
1025
1026         mtd->name = mtd_names[0];
1027         return nand_scan_tail(mtd);
1028 }
1029
1030 static int alloc_nand_resource(struct platform_device *pdev)
1031 {
1032         struct pxa3xx_nand_platform_data *pdata;
1033         struct pxa3xx_nand_info *info;
1034         struct pxa3xx_nand_host *host;
1035         struct nand_chip *chip;
1036         struct mtd_info *mtd;
1037         struct resource *r;
1038         int ret, irq, cs;
1039
1040         pdata = pdev->dev.platform_data;
1041         info = kzalloc(sizeof(*info) + (sizeof(*mtd) +
1042                        sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1043         if (!info) {
1044                 dev_err(&pdev->dev, "failed to allocate memory\n");
1045                 return -ENOMEM;
1046         }
1047
1048         info->pdev = pdev;
1049         for (cs = 0; cs < pdata->num_cs; cs++) {
1050                 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1051                       (sizeof(*mtd) + sizeof(*host)) * cs);
1052                 chip = (struct nand_chip *)(&mtd[1]);
1053                 host = (struct pxa3xx_nand_host *)chip;
1054                 info->host[cs] = host;
1055                 host->mtd = mtd;
1056                 host->cs = cs;
1057                 host->info_data = info;
1058                 mtd->priv = host;
1059                 mtd->owner = THIS_MODULE;
1060
1061                 chip->ecc.read_page     = pxa3xx_nand_read_page_hwecc;
1062                 chip->ecc.write_page    = pxa3xx_nand_write_page_hwecc;
1063                 chip->controller        = &info->controller;
1064                 chip->waitfunc          = pxa3xx_nand_waitfunc;
1065                 chip->select_chip       = pxa3xx_nand_select_chip;
1066                 chip->cmdfunc           = pxa3xx_nand_cmdfunc;
1067                 chip->read_word         = pxa3xx_nand_read_word;
1068                 chip->read_byte         = pxa3xx_nand_read_byte;
1069                 chip->read_buf          = pxa3xx_nand_read_buf;
1070                 chip->write_buf         = pxa3xx_nand_write_buf;
1071                 chip->verify_buf        = pxa3xx_nand_verify_buf;
1072         }
1073
1074         spin_lock_init(&chip->controller->lock);
1075         init_waitqueue_head(&chip->controller->wq);
1076         info->clk = clk_get(&pdev->dev, NULL);
1077         if (IS_ERR(info->clk)) {
1078                 dev_err(&pdev->dev, "failed to get nand clock\n");
1079                 ret = PTR_ERR(info->clk);
1080                 goto fail_free_mtd;
1081         }
1082         clk_enable(info->clk);
1083
1084         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1085         if (r == NULL) {
1086                 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1087                 ret = -ENXIO;
1088                 goto fail_put_clk;
1089         }
1090         info->drcmr_dat = r->start;
1091
1092         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1093         if (r == NULL) {
1094                 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1095                 ret = -ENXIO;
1096                 goto fail_put_clk;
1097         }
1098         info->drcmr_cmd = r->start;
1099
1100         irq = platform_get_irq(pdev, 0);
1101         if (irq < 0) {
1102                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1103                 ret = -ENXIO;
1104                 goto fail_put_clk;
1105         }
1106
1107         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108         if (r == NULL) {
1109                 dev_err(&pdev->dev, "no IO memory resource defined\n");
1110                 ret = -ENODEV;
1111                 goto fail_put_clk;
1112         }
1113
1114         r = request_mem_region(r->start, resource_size(r), pdev->name);
1115         if (r == NULL) {
1116                 dev_err(&pdev->dev, "failed to request memory resource\n");
1117                 ret = -EBUSY;
1118                 goto fail_put_clk;
1119         }
1120
1121         info->mmio_base = ioremap(r->start, resource_size(r));
1122         if (info->mmio_base == NULL) {
1123                 dev_err(&pdev->dev, "ioremap() failed\n");
1124                 ret = -ENODEV;
1125                 goto fail_free_res;
1126         }
1127         info->mmio_phys = r->start;
1128
1129         ret = pxa3xx_nand_init_buff(info);
1130         if (ret)
1131                 goto fail_free_io;
1132
1133         /* initialize all interrupts to be disabled */
1134         disable_int(info, NDSR_MASK);
1135
1136         ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1137                           pdev->name, info);
1138         if (ret < 0) {
1139                 dev_err(&pdev->dev, "failed to request IRQ\n");
1140                 goto fail_free_buf;
1141         }
1142
1143         platform_set_drvdata(pdev, info);
1144
1145         return 0;
1146
1147 fail_free_buf:
1148         free_irq(irq, info);
1149         if (use_dma) {
1150                 pxa_free_dma(info->data_dma_ch);
1151                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
1152                         info->data_buff, info->data_buff_phys);
1153         } else
1154                 kfree(info->data_buff);
1155 fail_free_io:
1156         iounmap(info->mmio_base);
1157 fail_free_res:
1158         release_mem_region(r->start, resource_size(r));
1159 fail_put_clk:
1160         clk_disable(info->clk);
1161         clk_put(info->clk);
1162 fail_free_mtd:
1163         kfree(info);
1164         return ret;
1165 }
1166
1167 static int pxa3xx_nand_remove(struct platform_device *pdev)
1168 {
1169         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1170         struct pxa3xx_nand_platform_data *pdata;
1171         struct resource *r;
1172         int irq, cs;
1173
1174         if (!info)
1175                 return 0;
1176
1177         pdata = pdev->dev.platform_data;
1178         platform_set_drvdata(pdev, NULL);
1179
1180         irq = platform_get_irq(pdev, 0);
1181         if (irq >= 0)
1182                 free_irq(irq, info);
1183         if (use_dma) {
1184                 pxa_free_dma(info->data_dma_ch);
1185                 dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE,
1186                                 info->data_buff, info->data_buff_phys);
1187         } else
1188                 kfree(info->data_buff);
1189
1190         iounmap(info->mmio_base);
1191         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1192         release_mem_region(r->start, resource_size(r));
1193
1194         clk_disable(info->clk);
1195         clk_put(info->clk);
1196
1197         for (cs = 0; cs < pdata->num_cs; cs++)
1198                 nand_release(info->host[cs]->mtd);
1199         kfree(info);
1200         return 0;
1201 }
1202
1203 static int pxa3xx_nand_probe(struct platform_device *pdev)
1204 {
1205         struct pxa3xx_nand_platform_data *pdata;
1206         struct pxa3xx_nand_info *info;
1207         int ret, cs, probe_success;
1208
1209         pdata = pdev->dev.platform_data;
1210         if (!pdata) {
1211                 dev_err(&pdev->dev, "no platform data defined\n");
1212                 return -ENODEV;
1213         }
1214
1215         ret = alloc_nand_resource(pdev);
1216         if (ret) {
1217                 dev_err(&pdev->dev, "alloc nand resource failed\n");
1218                 return ret;
1219         }
1220
1221         info = platform_get_drvdata(pdev);
1222         probe_success = 0;
1223         for (cs = 0; cs < pdata->num_cs; cs++) {
1224                 info->cs = cs;
1225                 ret = pxa3xx_nand_scan(info->host[cs]->mtd);
1226                 if (ret) {
1227                         dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1228                                 cs);
1229                         continue;
1230                 }
1231
1232                 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1233                                                 NULL, pdata->parts[cs],
1234                                                 pdata->nr_parts[cs]);
1235                 if (!ret)
1236                         probe_success = 1;
1237         }
1238
1239         if (!probe_success) {
1240                 pxa3xx_nand_remove(pdev);
1241                 return -ENODEV;
1242         }
1243
1244         return 0;
1245 }
1246
1247 #ifdef CONFIG_PM
1248 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1249 {
1250         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1251         struct pxa3xx_nand_platform_data *pdata;
1252         struct mtd_info *mtd;
1253         int cs;
1254
1255         pdata = pdev->dev.platform_data;
1256         if (info->state) {
1257                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1258                 return -EAGAIN;
1259         }
1260
1261         for (cs = 0; cs < pdata->num_cs; cs++) {
1262                 mtd = info->host[cs]->mtd;
1263                 mtd_suspend(mtd);
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int pxa3xx_nand_resume(struct platform_device *pdev)
1270 {
1271         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1272         struct pxa3xx_nand_platform_data *pdata;
1273         struct mtd_info *mtd;
1274         int cs;
1275
1276         pdata = pdev->dev.platform_data;
1277         /* We don't want to handle interrupt without calling mtd routine */
1278         disable_int(info, NDCR_INT_MASK);
1279
1280         /*
1281          * Directly set the chip select to a invalid value,
1282          * then the driver would reset the timing according
1283          * to current chip select at the beginning of cmdfunc
1284          */
1285         info->cs = 0xff;
1286
1287         /*
1288          * As the spec says, the NDSR would be updated to 0x1800 when
1289          * doing the nand_clk disable/enable.
1290          * To prevent it damaging state machine of the driver, clear
1291          * all status before resume
1292          */
1293         nand_writel(info, NDSR, NDSR_MASK);
1294         for (cs = 0; cs < pdata->num_cs; cs++) {
1295                 mtd = info->host[cs]->mtd;
1296                 mtd_resume(mtd);
1297         }
1298
1299         return 0;
1300 }
1301 #else
1302 #define pxa3xx_nand_suspend     NULL
1303 #define pxa3xx_nand_resume      NULL
1304 #endif
1305
1306 static struct platform_driver pxa3xx_nand_driver = {
1307         .driver = {
1308                 .name   = "pxa3xx-nand",
1309         },
1310         .probe          = pxa3xx_nand_probe,
1311         .remove         = pxa3xx_nand_remove,
1312         .suspend        = pxa3xx_nand_suspend,
1313         .resume         = pxa3xx_nand_resume,
1314 };
1315
1316 module_platform_driver(pxa3xx_nand_driver);
1317
1318 MODULE_LICENSE("GPL");
1319 MODULE_DESCRIPTION("PXA3xx NAND controller driver");