2 * drivers/mtd/nand/pxa3xx_nand.c
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
23 #include <linux/irq.h>
24 #include <linux/slab.h>
26 #include <linux/of_device.h>
28 #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
36 #include <linux/platform_data/mtd-nand-pxa3xx.h>
38 #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
39 #define NAND_STOP_DELAY (2 * HZ/50)
40 #define PAGE_CHUNK_SIZE (2048)
42 /* registers and bit definitions */
43 #define NDCR (0x00) /* Control register */
44 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
45 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
46 #define NDSR (0x14) /* Status Register */
47 #define NDPCR (0x18) /* Page Count Register */
48 #define NDBDR0 (0x1C) /* Bad Block Register 0 */
49 #define NDBDR1 (0x20) /* Bad Block Register 1 */
50 #define NDDB (0x40) /* Data Buffer */
51 #define NDCB0 (0x48) /* Command Buffer0 */
52 #define NDCB1 (0x4C) /* Command Buffer1 */
53 #define NDCB2 (0x50) /* Command Buffer2 */
55 #define NDCR_SPARE_EN (0x1 << 31)
56 #define NDCR_ECC_EN (0x1 << 30)
57 #define NDCR_DMA_EN (0x1 << 29)
58 #define NDCR_ND_RUN (0x1 << 28)
59 #define NDCR_DWIDTH_C (0x1 << 27)
60 #define NDCR_DWIDTH_M (0x1 << 26)
61 #define NDCR_PAGE_SZ (0x1 << 24)
62 #define NDCR_NCSX (0x1 << 23)
63 #define NDCR_ND_MODE (0x3 << 21)
64 #define NDCR_NAND_MODE (0x0)
65 #define NDCR_CLR_PG_CNT (0x1 << 20)
66 #define NDCR_STOP_ON_UNCOR (0x1 << 19)
67 #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
68 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
70 #define NDCR_RA_START (0x1 << 15)
71 #define NDCR_PG_PER_BLK (0x1 << 14)
72 #define NDCR_ND_ARB_EN (0x1 << 12)
73 #define NDCR_INT_MASK (0xFFF)
75 #define NDSR_MASK (0xfff)
76 #define NDSR_RDY (0x1 << 12)
77 #define NDSR_FLASH_RDY (0x1 << 11)
78 #define NDSR_CS0_PAGED (0x1 << 10)
79 #define NDSR_CS1_PAGED (0x1 << 9)
80 #define NDSR_CS0_CMDD (0x1 << 8)
81 #define NDSR_CS1_CMDD (0x1 << 7)
82 #define NDSR_CS0_BBD (0x1 << 6)
83 #define NDSR_CS1_BBD (0x1 << 5)
84 #define NDSR_DBERR (0x1 << 4)
85 #define NDSR_SBERR (0x1 << 3)
86 #define NDSR_WRDREQ (0x1 << 2)
87 #define NDSR_RDDREQ (0x1 << 1)
88 #define NDSR_WRCMDREQ (0x1)
90 #define NDCB0_LEN_OVRD (0x1 << 28)
91 #define NDCB0_ST_ROW_EN (0x1 << 26)
92 #define NDCB0_AUTO_RS (0x1 << 25)
93 #define NDCB0_CSEL (0x1 << 24)
94 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
95 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
96 #define NDCB0_NC (0x1 << 20)
97 #define NDCB0_DBC (0x1 << 19)
98 #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
99 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
100 #define NDCB0_CMD2_MASK (0xff << 8)
101 #define NDCB0_CMD1_MASK (0xff)
102 #define NDCB0_ADDR_CYC_SHIFT (16)
104 /* macros for registers read/write */
105 #define nand_writel(info, off, val) \
106 __raw_writel((val), (info)->mmio_base + (off))
108 #define nand_readl(info, off) \
109 __raw_readl((info)->mmio_base + (off))
111 /* error code and state */
134 enum pxa3xx_nand_variant {
135 PXA3XX_NAND_VARIANT_PXA,
136 PXA3XX_NAND_VARIANT_ARMADA370,
139 struct pxa3xx_nand_host {
140 struct nand_chip chip;
141 struct mtd_info *mtd;
144 /* page size of attached chip */
145 unsigned int page_size;
149 /* calculated from pxa3xx_nand_flash data */
150 unsigned int col_addr_cycles;
151 unsigned int row_addr_cycles;
152 size_t read_id_bytes;
156 struct pxa3xx_nand_info {
157 struct nand_hw_control controller;
158 struct platform_device *pdev;
161 void __iomem *mmio_base;
162 unsigned long mmio_phys;
163 struct completion cmd_complete;
165 unsigned int buf_start;
166 unsigned int buf_count;
168 /* DMA information */
172 unsigned char *data_buff;
173 unsigned char *oob_buff;
174 dma_addr_t data_buff_phys;
176 struct pxa_dma_desc *data_desc;
177 dma_addr_t data_desc_addr;
179 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
183 * This driver supports NFCv1 (as found in PXA SoC)
184 * and NFCv2 (as found in Armada 370/XP SoC).
186 enum pxa3xx_nand_variant variant;
189 int use_ecc; /* use HW ECC ? */
190 int use_dma; /* use DMA ? */
191 int use_spare; /* use spare ? */
194 unsigned int page_size; /* page size of attached chip */
195 unsigned int data_size; /* data size in FIFO */
196 unsigned int oob_size;
199 /* cached register value */
204 /* generated NDCBx register values */
211 static bool use_dma = 1;
212 module_param(use_dma, bool, 0444);
213 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
215 static struct pxa3xx_nand_timing timing[] = {
216 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
217 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
218 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
219 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
222 static struct pxa3xx_nand_flash builtin_flash_types[] = {
223 { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
224 { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
225 { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
226 { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
227 { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
228 { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
229 { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
230 { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
231 { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
234 /* Define a default flash type setting serve as flash detecting only */
235 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
237 #define NDTR0_tCH(c) (min((c), 7) << 19)
238 #define NDTR0_tCS(c) (min((c), 7) << 16)
239 #define NDTR0_tWH(c) (min((c), 7) << 11)
240 #define NDTR0_tWP(c) (min((c), 7) << 8)
241 #define NDTR0_tRH(c) (min((c), 7) << 3)
242 #define NDTR0_tRP(c) (min((c), 7) << 0)
244 #define NDTR1_tR(c) (min((c), 65535) << 16)
245 #define NDTR1_tWHR(c) (min((c), 15) << 4)
246 #define NDTR1_tAR(c) (min((c), 15) << 0)
248 /* convert nano-seconds to nand flash controller clock cycles */
249 #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
251 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
252 const struct pxa3xx_nand_timing *t)
254 struct pxa3xx_nand_info *info = host->info_data;
255 unsigned long nand_clk = clk_get_rate(info->clk);
256 uint32_t ndtr0, ndtr1;
258 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
259 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
260 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
261 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
262 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
263 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
265 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
266 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
267 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
269 info->ndtr0cs0 = ndtr0;
270 info->ndtr1cs0 = ndtr1;
271 nand_writel(info, NDTR0CS0, ndtr0);
272 nand_writel(info, NDTR1CS0, ndtr1);
275 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
277 struct pxa3xx_nand_host *host = info->host[info->cs];
278 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
280 info->data_size = host->page_size;
286 switch (host->page_size) {
288 info->oob_size = (info->use_ecc) ? 40 : 64;
291 info->oob_size = (info->use_ecc) ? 8 : 16;
297 * NOTE: it is a must to set ND_RUN firstly, then write
298 * command buffer, otherwise, it does not work.
299 * We enable all the interrupt at the same time, and
300 * let pxa3xx_nand_irq to handle all logic.
302 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
306 ndcr = info->reg_ndcr;
311 ndcr &= ~NDCR_ECC_EN;
316 ndcr &= ~NDCR_DMA_EN;
319 ndcr |= NDCR_SPARE_EN;
321 ndcr &= ~NDCR_SPARE_EN;
325 /* clear status bits and run */
326 nand_writel(info, NDCR, 0);
327 nand_writel(info, NDSR, NDSR_MASK);
328 nand_writel(info, NDCR, ndcr);
331 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
334 int timeout = NAND_STOP_DELAY;
336 /* wait RUN bit in NDCR become 0 */
337 ndcr = nand_readl(info, NDCR);
338 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
339 ndcr = nand_readl(info, NDCR);
344 ndcr &= ~NDCR_ND_RUN;
345 nand_writel(info, NDCR, ndcr);
347 /* clear status bits */
348 nand_writel(info, NDSR, NDSR_MASK);
351 static void __maybe_unused
352 enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
356 ndcr = nand_readl(info, NDCR);
357 nand_writel(info, NDCR, ndcr & ~int_mask);
360 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
364 ndcr = nand_readl(info, NDCR);
365 nand_writel(info, NDCR, ndcr | int_mask);
368 static void handle_data_pio(struct pxa3xx_nand_info *info)
370 switch (info->state) {
371 case STATE_PIO_WRITING:
372 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
373 DIV_ROUND_UP(info->data_size, 4));
374 if (info->oob_size > 0)
375 __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
376 DIV_ROUND_UP(info->oob_size, 4));
378 case STATE_PIO_READING:
379 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
380 DIV_ROUND_UP(info->data_size, 4));
381 if (info->oob_size > 0)
382 __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
383 DIV_ROUND_UP(info->oob_size, 4));
386 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
393 static void start_data_dma(struct pxa3xx_nand_info *info)
395 struct pxa_dma_desc *desc = info->data_desc;
396 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
398 desc->ddadr = DDADR_STOP;
399 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
401 switch (info->state) {
402 case STATE_DMA_WRITING:
403 desc->dsadr = info->data_buff_phys;
404 desc->dtadr = info->mmio_phys + NDDB;
405 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
407 case STATE_DMA_READING:
408 desc->dtadr = info->data_buff_phys;
409 desc->dsadr = info->mmio_phys + NDDB;
410 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
413 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
418 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
419 DDADR(info->data_dma_ch) = info->data_desc_addr;
420 DCSR(info->data_dma_ch) |= DCSR_RUN;
423 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
425 struct pxa3xx_nand_info *info = data;
428 dcsr = DCSR(channel);
429 DCSR(channel) = dcsr;
431 if (dcsr & DCSR_BUSERR) {
432 info->retcode = ERR_DMABUSERR;
435 info->state = STATE_DMA_DONE;
436 enable_int(info, NDCR_INT_MASK);
437 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
440 static void start_data_dma(struct pxa3xx_nand_info *info)
444 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
446 struct pxa3xx_nand_info *info = devid;
447 unsigned int status, is_completed = 0;
448 unsigned int ready, cmd_done;
451 ready = NDSR_FLASH_RDY;
452 cmd_done = NDSR_CS0_CMDD;
455 cmd_done = NDSR_CS1_CMDD;
458 status = nand_readl(info, NDSR);
460 if (status & NDSR_DBERR)
461 info->retcode = ERR_DBERR;
462 if (status & NDSR_SBERR)
463 info->retcode = ERR_SBERR;
464 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
465 /* whether use dma to transfer data */
467 disable_int(info, NDCR_INT_MASK);
468 info->state = (status & NDSR_RDDREQ) ?
469 STATE_DMA_READING : STATE_DMA_WRITING;
470 start_data_dma(info);
471 goto NORMAL_IRQ_EXIT;
473 info->state = (status & NDSR_RDDREQ) ?
474 STATE_PIO_READING : STATE_PIO_WRITING;
475 handle_data_pio(info);
478 if (status & cmd_done) {
479 info->state = STATE_CMD_DONE;
482 if (status & ready) {
484 info->state = STATE_READY;
487 if (status & NDSR_WRCMDREQ) {
488 nand_writel(info, NDSR, NDSR_WRCMDREQ);
489 status &= ~NDSR_WRCMDREQ;
490 info->state = STATE_CMD_HANDLE;
493 * Command buffer registers NDCB{0-2} (and optionally NDCB3)
494 * must be loaded by writing directly either 12 or 16
495 * bytes directly to NDCB0, four bytes at a time.
497 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
498 * but each NDCBx register can be read.
500 nand_writel(info, NDCB0, info->ndcb0);
501 nand_writel(info, NDCB0, info->ndcb1);
502 nand_writel(info, NDCB0, info->ndcb2);
504 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
505 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
506 nand_writel(info, NDCB0, info->ndcb3);
509 /* clear NDSR to let the controller exit the IRQ */
510 nand_writel(info, NDSR, status);
512 complete(&info->cmd_complete);
517 static inline int is_buf_blank(uint8_t *buf, size_t len)
519 for (; len > 0; len--)
525 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
526 uint16_t column, int page_addr)
528 int addr_cycle, exec_cmd;
529 struct pxa3xx_nand_host *host;
530 struct mtd_info *mtd;
532 host = info->host[info->cs];
537 /* reset data and oob column point to handle data */
543 info->use_dma = (use_dma) ? 1 : 0;
545 info->retcode = ERR_NONE;
547 info->ndcb0 = NDCB0_CSEL;
553 case NAND_CMD_PAGEPROG:
555 case NAND_CMD_READOOB:
556 pxa3xx_set_datasize(info);
571 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
572 + host->col_addr_cycles);
575 case NAND_CMD_READOOB:
577 info->buf_start = column;
578 info->ndcb0 |= NDCB0_CMD_TYPE(0)
582 if (command == NAND_CMD_READOOB)
583 info->buf_start += mtd->writesize;
585 /* Second command setting for large pages */
586 if (host->page_size >= PAGE_CHUNK_SIZE)
587 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
590 /* small page addr setting */
591 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
592 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
597 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
600 if (page_addr & 0xFF0000)
601 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
606 info->buf_count = mtd->writesize + mtd->oobsize;
607 memset(info->data_buff, 0xFF, info->buf_count);
611 case NAND_CMD_PAGEPROG:
612 if (is_buf_blank(info->data_buff,
613 (mtd->writesize + mtd->oobsize))) {
618 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
622 | (NAND_CMD_PAGEPROG << 8)
628 info->buf_count = 256;
629 info->ndcb0 |= NDCB0_CMD_TYPE(0)
633 info->ndcb1 = (column & 0xFF);
635 info->data_size = 256;
638 case NAND_CMD_READID:
639 info->buf_count = host->read_id_bytes;
640 info->ndcb0 |= NDCB0_CMD_TYPE(3)
643 info->ndcb1 = (column & 0xFF);
647 case NAND_CMD_STATUS:
649 info->ndcb0 |= NDCB0_CMD_TYPE(4)
656 case NAND_CMD_ERASE1:
657 info->ndcb0 |= NDCB0_CMD_TYPE(2)
661 | (NAND_CMD_ERASE2 << 8)
663 info->ndcb1 = page_addr;
668 info->ndcb0 |= NDCB0_CMD_TYPE(5)
673 case NAND_CMD_ERASE2:
679 dev_err(&info->pdev->dev, "non-supported command %x\n",
687 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
688 int column, int page_addr)
690 struct pxa3xx_nand_host *host = mtd->priv;
691 struct pxa3xx_nand_info *info = host->info_data;
695 * if this is a x16 device ,then convert the input
696 * "byte" address into a "word" address appropriate
697 * for indexing a word-oriented device
699 if (info->reg_ndcr & NDCR_DWIDTH_M)
703 * There may be different NAND chip hooked to
704 * different chip select, so check whether
705 * chip select has been changed, if yes, reset the timing
707 if (info->cs != host->cs) {
709 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
710 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
713 info->state = STATE_PREPARED;
714 exec_cmd = prepare_command_pool(info, command, column, page_addr);
716 init_completion(&info->cmd_complete);
717 pxa3xx_nand_start(info);
719 ret = wait_for_completion_timeout(&info->cmd_complete,
722 dev_err(&info->pdev->dev, "Wait time out!!!\n");
723 /* Stop State Machine for next command cycle */
724 pxa3xx_nand_stop(info);
727 info->state = STATE_IDLE;
730 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
731 struct nand_chip *chip, const uint8_t *buf, int oob_required)
733 chip->write_buf(mtd, buf, mtd->writesize);
734 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
739 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
740 struct nand_chip *chip, uint8_t *buf, int oob_required,
743 struct pxa3xx_nand_host *host = mtd->priv;
744 struct pxa3xx_nand_info *info = host->info_data;
746 chip->read_buf(mtd, buf, mtd->writesize);
747 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
749 if (info->retcode == ERR_SBERR) {
750 switch (info->use_ecc) {
752 mtd->ecc_stats.corrected++;
758 } else if (info->retcode == ERR_DBERR) {
760 * for blank page (all 0xff), HW will calculate its ECC as
761 * 0, which is different from the ECC information within
762 * OOB, ignore such double bit errors
764 if (is_buf_blank(buf, mtd->writesize))
765 info->retcode = ERR_NONE;
767 mtd->ecc_stats.failed++;
773 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
775 struct pxa3xx_nand_host *host = mtd->priv;
776 struct pxa3xx_nand_info *info = host->info_data;
779 if (info->buf_start < info->buf_count)
780 /* Has just send a new command? */
781 retval = info->data_buff[info->buf_start++];
786 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
788 struct pxa3xx_nand_host *host = mtd->priv;
789 struct pxa3xx_nand_info *info = host->info_data;
792 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
793 retval = *((u16 *)(info->data_buff+info->buf_start));
794 info->buf_start += 2;
799 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
801 struct pxa3xx_nand_host *host = mtd->priv;
802 struct pxa3xx_nand_info *info = host->info_data;
803 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
805 memcpy(buf, info->data_buff + info->buf_start, real_len);
806 info->buf_start += real_len;
809 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
810 const uint8_t *buf, int len)
812 struct pxa3xx_nand_host *host = mtd->priv;
813 struct pxa3xx_nand_info *info = host->info_data;
814 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
816 memcpy(info->data_buff + info->buf_start, buf, real_len);
817 info->buf_start += real_len;
820 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
825 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
827 struct pxa3xx_nand_host *host = mtd->priv;
828 struct pxa3xx_nand_info *info = host->info_data;
830 /* pxa3xx_nand_send_command has waited for command complete */
831 if (this->state == FL_WRITING || this->state == FL_ERASING) {
832 if (info->retcode == ERR_NONE)
836 * any error make it return 0x01 which will tell
837 * the caller the erase and write fail
846 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
847 const struct pxa3xx_nand_flash *f)
849 struct platform_device *pdev = info->pdev;
850 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
851 struct pxa3xx_nand_host *host = info->host[info->cs];
852 uint32_t ndcr = 0x0; /* enable all interrupts */
854 if (f->page_size != 2048 && f->page_size != 512) {
855 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
859 if (f->flash_width != 16 && f->flash_width != 8) {
860 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
864 /* calculate flash information */
865 host->page_size = f->page_size;
866 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
868 /* calculate addressing information */
869 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
871 if (f->num_blocks * f->page_per_block > 65536)
872 host->row_addr_cycles = 3;
874 host->row_addr_cycles = 2;
876 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
877 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
878 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
879 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
880 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
881 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
883 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
884 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
886 info->reg_ndcr = ndcr;
888 pxa3xx_nand_set_timing(host, f->timing);
892 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
895 * We set 0 by hard coding here, for we don't support keep_config
896 * when there is more than one chip attached to the controller
898 struct pxa3xx_nand_host *host = info->host[0];
899 uint32_t ndcr = nand_readl(info, NDCR);
901 if (ndcr & NDCR_PAGE_SZ) {
902 host->page_size = 2048;
903 host->read_id_bytes = 4;
905 host->page_size = 512;
906 host->read_id_bytes = 2;
909 info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
910 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
911 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
915 /* the maximum possible buffer size for large page with OOB data
916 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
917 * data buffer and the DMA descriptor
919 #define MAX_BUFF_SIZE PAGE_SIZE
922 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
924 struct platform_device *pdev = info->pdev;
925 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
928 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
929 if (info->data_buff == NULL)
934 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
935 &info->data_buff_phys, GFP_KERNEL);
936 if (info->data_buff == NULL) {
937 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
941 info->data_desc = (void *)info->data_buff + data_desc_offset;
942 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
944 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
945 pxa3xx_nand_data_dma_irq, info);
946 if (info->data_dma_ch < 0) {
947 dev_err(&pdev->dev, "failed to request data dma\n");
948 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
949 info->data_buff, info->data_buff_phys);
950 return info->data_dma_ch;
956 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
958 struct platform_device *pdev = info->pdev;
960 pxa_free_dma(info->data_dma_ch);
961 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
962 info->data_buff, info->data_buff_phys);
964 kfree(info->data_buff);
968 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
970 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
971 if (info->data_buff == NULL)
976 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
978 kfree(info->data_buff);
982 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
984 struct mtd_info *mtd;
986 mtd = info->host[info->cs]->mtd;
987 /* use the common timing to make a try */
988 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
992 pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
999 static int pxa3xx_nand_scan(struct mtd_info *mtd)
1001 struct pxa3xx_nand_host *host = mtd->priv;
1002 struct pxa3xx_nand_info *info = host->info_data;
1003 struct platform_device *pdev = info->pdev;
1004 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
1005 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
1006 const struct pxa3xx_nand_flash *f = NULL;
1007 struct nand_chip *chip = mtd->priv;
1012 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
1015 ret = pxa3xx_nand_sensing(info);
1017 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
1023 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
1024 id = *((uint16_t *)(info->data_buff));
1026 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
1028 dev_warn(&info->pdev->dev,
1029 "Read out ID 0, potential timing set wrong!!\n");
1034 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1035 for (i = 0; i < num; i++) {
1036 if (i < pdata->num_flash)
1037 f = pdata->flash + i;
1039 f = &builtin_flash_types[i - pdata->num_flash + 1];
1041 /* find the chip in default list */
1042 if (f->chip_id == id)
1046 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
1047 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
1052 ret = pxa3xx_nand_config_flash(info, f);
1054 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1058 pxa3xx_flash_ids[0].name = f->name;
1059 pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
1060 pxa3xx_flash_ids[0].pagesize = f->page_size;
1061 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1062 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1063 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1064 if (f->flash_width == 16)
1065 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
1066 pxa3xx_flash_ids[1].name = NULL;
1067 def = pxa3xx_flash_ids;
1069 chip->ecc.mode = NAND_ECC_HW;
1070 chip->ecc.size = host->page_size;
1071 chip->ecc.strength = 1;
1073 if (info->reg_ndcr & NDCR_DWIDTH_M)
1074 chip->options |= NAND_BUSWIDTH_16;
1076 if (nand_scan_ident(mtd, 1, def))
1078 /* calculate addressing information */
1079 if (mtd->writesize >= 2048)
1080 host->col_addr_cycles = 2;
1082 host->col_addr_cycles = 1;
1084 info->oob_buff = info->data_buff + mtd->writesize;
1085 if ((mtd->size >> chip->page_shift) > 65536)
1086 host->row_addr_cycles = 3;
1088 host->row_addr_cycles = 2;
1089 return nand_scan_tail(mtd);
1092 static int alloc_nand_resource(struct platform_device *pdev)
1094 struct pxa3xx_nand_platform_data *pdata;
1095 struct pxa3xx_nand_info *info;
1096 struct pxa3xx_nand_host *host;
1097 struct nand_chip *chip = NULL;
1098 struct mtd_info *mtd;
1102 pdata = dev_get_platdata(&pdev->dev);
1103 info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1104 sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1109 for (cs = 0; cs < pdata->num_cs; cs++) {
1110 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1111 (sizeof(*mtd) + sizeof(*host)) * cs);
1112 chip = (struct nand_chip *)(&mtd[1]);
1113 host = (struct pxa3xx_nand_host *)chip;
1114 info->host[cs] = host;
1117 host->info_data = info;
1119 mtd->owner = THIS_MODULE;
1121 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1122 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1123 chip->controller = &info->controller;
1124 chip->waitfunc = pxa3xx_nand_waitfunc;
1125 chip->select_chip = pxa3xx_nand_select_chip;
1126 chip->cmdfunc = pxa3xx_nand_cmdfunc;
1127 chip->read_word = pxa3xx_nand_read_word;
1128 chip->read_byte = pxa3xx_nand_read_byte;
1129 chip->read_buf = pxa3xx_nand_read_buf;
1130 chip->write_buf = pxa3xx_nand_write_buf;
1133 spin_lock_init(&chip->controller->lock);
1134 init_waitqueue_head(&chip->controller->wq);
1135 info->clk = devm_clk_get(&pdev->dev, NULL);
1136 if (IS_ERR(info->clk)) {
1137 dev_err(&pdev->dev, "failed to get nand clock\n");
1138 return PTR_ERR(info->clk);
1140 ret = clk_prepare_enable(info->clk);
1146 * This is a dirty hack to make this driver work from
1147 * devicetree bindings. It can be removed once we have
1148 * a prober DMA controller framework for DT.
1150 if (pdev->dev.of_node &&
1151 of_machine_is_compatible("marvell,pxa3xx")) {
1152 info->drcmr_dat = 97;
1153 info->drcmr_cmd = 99;
1155 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1158 "no resource defined for data DMA\n");
1160 goto fail_disable_clk;
1162 info->drcmr_dat = r->start;
1164 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1167 "no resource defined for cmd DMA\n");
1169 goto fail_disable_clk;
1171 info->drcmr_cmd = r->start;
1175 irq = platform_get_irq(pdev, 0);
1177 dev_err(&pdev->dev, "no IRQ resource defined\n");
1179 goto fail_disable_clk;
1182 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1184 if (IS_ERR(info->mmio_base)) {
1185 ret = PTR_ERR(info->mmio_base);
1186 goto fail_disable_clk;
1188 info->mmio_phys = r->start;
1190 ret = pxa3xx_nand_init_buff(info);
1192 goto fail_disable_clk;
1194 /* initialize all interrupts to be disabled */
1195 disable_int(info, NDSR_MASK);
1197 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1200 dev_err(&pdev->dev, "failed to request IRQ\n");
1204 platform_set_drvdata(pdev, info);
1209 free_irq(irq, info);
1210 pxa3xx_nand_free_buff(info);
1212 clk_disable_unprepare(info->clk);
1216 static int pxa3xx_nand_remove(struct platform_device *pdev)
1218 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1219 struct pxa3xx_nand_platform_data *pdata;
1225 pdata = dev_get_platdata(&pdev->dev);
1227 irq = platform_get_irq(pdev, 0);
1229 free_irq(irq, info);
1230 pxa3xx_nand_free_buff(info);
1232 clk_disable_unprepare(info->clk);
1234 for (cs = 0; cs < pdata->num_cs; cs++)
1235 nand_release(info->host[cs]->mtd);
1240 static struct of_device_id pxa3xx_nand_dt_ids[] = {
1242 .compatible = "marvell,pxa3xx-nand",
1243 .data = (void *)PXA3XX_NAND_VARIANT_PXA,
1246 .compatible = "marvell,armada370-nand",
1247 .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
1251 MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
1253 static enum pxa3xx_nand_variant
1254 pxa3xx_nand_get_variant(struct platform_device *pdev)
1256 const struct of_device_id *of_id =
1257 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1259 return PXA3XX_NAND_VARIANT_PXA;
1260 return (enum pxa3xx_nand_variant)of_id->data;
1263 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1265 struct pxa3xx_nand_platform_data *pdata;
1266 struct device_node *np = pdev->dev.of_node;
1267 const struct of_device_id *of_id =
1268 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1273 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1277 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1278 pdata->enable_arbiter = 1;
1279 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1280 pdata->keep_config = 1;
1281 of_property_read_u32(np, "num-cs", &pdata->num_cs);
1283 pdev->dev.platform_data = pdata;
1288 static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1294 static int pxa3xx_nand_probe(struct platform_device *pdev)
1296 struct pxa3xx_nand_platform_data *pdata;
1297 struct mtd_part_parser_data ppdata = {};
1298 struct pxa3xx_nand_info *info;
1299 int ret, cs, probe_success;
1301 #ifndef ARCH_HAS_DMA
1304 dev_warn(&pdev->dev,
1305 "This platform can't do DMA on this device\n");
1308 ret = pxa3xx_nand_probe_dt(pdev);
1312 pdata = dev_get_platdata(&pdev->dev);
1314 dev_err(&pdev->dev, "no platform data defined\n");
1318 ret = alloc_nand_resource(pdev);
1320 dev_err(&pdev->dev, "alloc nand resource failed\n");
1324 info = platform_get_drvdata(pdev);
1325 info->variant = pxa3xx_nand_get_variant(pdev);
1327 for (cs = 0; cs < pdata->num_cs; cs++) {
1328 struct mtd_info *mtd = info->host[cs]->mtd;
1330 mtd->name = pdev->name;
1332 ret = pxa3xx_nand_scan(mtd);
1334 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1339 ppdata.of_node = pdev->dev.of_node;
1340 ret = mtd_device_parse_register(mtd, NULL,
1341 &ppdata, pdata->parts[cs],
1342 pdata->nr_parts[cs]);
1347 if (!probe_success) {
1348 pxa3xx_nand_remove(pdev);
1356 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1358 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1359 struct pxa3xx_nand_platform_data *pdata;
1360 struct mtd_info *mtd;
1363 pdata = dev_get_platdata(&pdev->dev);
1365 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1369 for (cs = 0; cs < pdata->num_cs; cs++) {
1370 mtd = info->host[cs]->mtd;
1377 static int pxa3xx_nand_resume(struct platform_device *pdev)
1379 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1380 struct pxa3xx_nand_platform_data *pdata;
1381 struct mtd_info *mtd;
1384 pdata = dev_get_platdata(&pdev->dev);
1385 /* We don't want to handle interrupt without calling mtd routine */
1386 disable_int(info, NDCR_INT_MASK);
1389 * Directly set the chip select to a invalid value,
1390 * then the driver would reset the timing according
1391 * to current chip select at the beginning of cmdfunc
1396 * As the spec says, the NDSR would be updated to 0x1800 when
1397 * doing the nand_clk disable/enable.
1398 * To prevent it damaging state machine of the driver, clear
1399 * all status before resume
1401 nand_writel(info, NDSR, NDSR_MASK);
1402 for (cs = 0; cs < pdata->num_cs; cs++) {
1403 mtd = info->host[cs]->mtd;
1410 #define pxa3xx_nand_suspend NULL
1411 #define pxa3xx_nand_resume NULL
1414 static struct platform_driver pxa3xx_nand_driver = {
1416 .name = "pxa3xx-nand",
1417 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1419 .probe = pxa3xx_nand_probe,
1420 .remove = pxa3xx_nand_remove,
1421 .suspend = pxa3xx_nand_suspend,
1422 .resume = pxa3xx_nand_resume,
1425 module_platform_driver(pxa3xx_nand_driver);
1427 MODULE_LICENSE("GPL");
1428 MODULE_DESCRIPTION("PXA3xx NAND controller driver");