drivers/mtd/nand/pxa3xx_nand.c

   1 /*
   2  * drivers/mtd/nand/pxa3xx_nand.c
   3  *
   4  * Copyright © 2005 Intel Corporation
   5  * Copyright © 2006 Marvell International Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
  29 #define ARCH_HAS_DMA
  30 #endif
  31
  32 #ifdef ARCH_HAS_DMA
  33 #include <mach/dma.h>
  34 #endif
  35
  36 #include <linux/platform_data/mtd-nand-pxa3xx.h>
  37
  38 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
  39 #define NAND_STOP_DELAY         (2 * HZ/50)
  40 #define PAGE_CHUNK_SIZE         (2048)
  41
  42 /* registers and bit definitions */
  43 #define NDCR            (0x00) /* Control register */
  44 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
  45 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
  46 #define NDSR            (0x14) /* Status Register */
  47 #define NDPCR           (0x18) /* Page Count Register */
  48 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
  49 #define NDBDR1          (0x20) /* Bad Block Register 1 */
  50 #define NDDB            (0x40) /* Data Buffer */
  51 #define NDCB0           (0x48) /* Command Buffer0 */
  52 #define NDCB1           (0x4C) /* Command Buffer1 */
  53 #define NDCB2           (0x50) /* Command Buffer2 */
  54
  55 #define NDCR_SPARE_EN           (0x1 << 31)
  56 #define NDCR_ECC_EN             (0x1 << 30)
  57 #define NDCR_DMA_EN             (0x1 << 29)
  58 #define NDCR_ND_RUN             (0x1 << 28)
  59 #define NDCR_DWIDTH_C           (0x1 << 27)
  60 #define NDCR_DWIDTH_M           (0x1 << 26)
  61 #define NDCR_PAGE_SZ            (0x1 << 24)
  62 #define NDCR_NCSX               (0x1 << 23)
  63 #define NDCR_ND_MODE            (0x3 << 21)
  64 #define NDCR_NAND_MODE          (0x0)
  65 #define NDCR_CLR_PG_CNT         (0x1 << 20)
  66 #define NDCR_STOP_ON_UNCOR      (0x1 << 19)
  67 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
  68 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  69
  70 #define NDCR_RA_START           (0x1 << 15)
  71 #define NDCR_PG_PER_BLK         (0x1 << 14)
  72 #define NDCR_ND_ARB_EN          (0x1 << 12)
  73 #define NDCR_INT_MASK           (0xFFF)
  74
  75 #define NDSR_MASK               (0xfff)
  76 #define NDSR_RDY                (0x1 << 12)
  77 #define NDSR_FLASH_RDY          (0x1 << 11)
  78 #define NDSR_CS0_PAGED          (0x1 << 10)
  79 #define NDSR_CS1_PAGED          (0x1 << 9)
  80 #define NDSR_CS0_CMDD           (0x1 << 8)
  81 #define NDSR_CS1_CMDD           (0x1 << 7)
  82 #define NDSR_CS0_BBD            (0x1 << 6)
  83 #define NDSR_CS1_BBD            (0x1 << 5)
  84 #define NDSR_DBERR              (0x1 << 4)
  85 #define NDSR_SBERR              (0x1 << 3)
  86 #define NDSR_WRDREQ             (0x1 << 2)
  87 #define NDSR_RDDREQ             (0x1 << 1)
  88 #define NDSR_WRCMDREQ           (0x1)
  89
  90 #define NDCB0_LEN_OVRD          (0x1 << 28)
  91 #define NDCB0_ST_ROW_EN         (0x1 << 26)
  92 #define NDCB0_AUTO_RS           (0x1 << 25)
  93 #define NDCB0_CSEL              (0x1 << 24)
  94 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
  95 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  96 #define NDCB0_NC                (0x1 << 20)
  97 #define NDCB0_DBC               (0x1 << 19)
  98 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
  99 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
 100 #define NDCB0_CMD2_MASK         (0xff << 8)
 101 #define NDCB0_CMD1_MASK         (0xff)
 102 #define NDCB0_ADDR_CYC_SHIFT    (16)
 103
 104 /* macros for registers read/write */
 105 #define nand_writel(info, off, val)     \
 106         __raw_writel((val), (info)->mmio_base + (off))
 107
 108 #define nand_readl(info, off)           \
 109         __raw_readl((info)->mmio_base + (off))
 110
 111 /* error code and state */
 112 enum {
 113         ERR_NONE        = 0,
 114         ERR_DMABUSERR   = -1,
 115         ERR_SENDCMD     = -2,
 116         ERR_DBERR       = -3,
 117         ERR_BBERR       = -4,
 118         ERR_SBERR       = -5,
 119 };
 120
 121 enum {
 122         STATE_IDLE = 0,
 123         STATE_PREPARED,
 124         STATE_CMD_HANDLE,
 125         STATE_DMA_READING,
 126         STATE_DMA_WRITING,
 127         STATE_DMA_DONE,
 128         STATE_PIO_READING,
 129         STATE_PIO_WRITING,
 130         STATE_CMD_DONE,
 131         STATE_READY,
 132 };
 133
 134 enum pxa3xx_nand_variant {
 135         PXA3XX_NAND_VARIANT_PXA,
 136         PXA3XX_NAND_VARIANT_ARMADA370,
 137 };
 138
 139 struct pxa3xx_nand_host {
 140         struct nand_chip        chip;
 141         struct mtd_info         *mtd;
 142         void                    *info_data;
 143
 144         /* page size of attached chip */
 145         unsigned int            page_size;
 146         int                     use_ecc;
 147         int                     cs;
 148
 149         /* calculated from pxa3xx_nand_flash data */
 150         unsigned int            col_addr_cycles;
 151         unsigned int            row_addr_cycles;
 152         size_t                  read_id_bytes;
 153
 154 };
 155
 156 struct pxa3xx_nand_info {
 157         struct nand_hw_control  controller;
 158         struct platform_device   *pdev;
 159
 160         struct clk              *clk;
 161         void __iomem            *mmio_base;
 162         unsigned long           mmio_phys;
 163         struct completion       cmd_complete;
 164
 165         unsigned int            buf_start;
 166         unsigned int            buf_count;
 167
 168         /* DMA information */
 169         int                     drcmr_dat;
 170         int                     drcmr_cmd;
 171
 172         unsigned char           *data_buff;
 173         unsigned char           *oob_buff;
 174         dma_addr_t              data_buff_phys;
 175         int                     data_dma_ch;
 176         struct pxa_dma_desc     *data_desc;
 177         dma_addr_t              data_desc_addr;
 178
 179         struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
 180         unsigned int            state;
 181
 182         /*
 183          * This driver supports NFCv1 (as found in PXA SoC)
 184          * and NFCv2 (as found in Armada 370/XP SoC).
 185          */
 186         enum pxa3xx_nand_variant variant;
 187
 188         int                     cs;
 189         int                     use_ecc;        /* use HW ECC ? */
 190         int                     use_dma;        /* use DMA ? */
 191         int                     use_spare;      /* use spare ? */
 192         int                     is_ready;
 193
 194         unsigned int            page_size;      /* page size of attached chip */
 195         unsigned int            data_size;      /* data size in FIFO */
 196         unsigned int            oob_size;
 197         int                     retcode;
 198
 199         /* cached register value */
 200         uint32_t                reg_ndcr;
 201         uint32_t                ndtr0cs0;
 202         uint32_t                ndtr1cs0;
 203
 204         /* generated NDCBx register values */
 205         uint32_t                ndcb0;
 206         uint32_t                ndcb1;
 207         uint32_t                ndcb2;
 208         uint32_t                ndcb3;
 209 };
 210
 211 static bool use_dma = 1;
 212 module_param(use_dma, bool, 0444);
 213 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
 214
 215 static struct pxa3xx_nand_timing timing[] = {
 216         { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 217         { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 218         { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 219         { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 220 };
 221
 222 static struct pxa3xx_nand_flash builtin_flash_types[] = {
 223 { "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },
 224 { "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },
 225 { "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },
 226 { "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },
 227 { "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },
 228 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },
 229 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },
 230 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },
 231 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },
 232 };
 233
 234 /* Define a default flash type setting serve as flash detecting only */
 235 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 236
 237 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 238 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 239 #define NDTR0_tWH(c)    (min((c), 7) << 11)
 240 #define NDTR0_tWP(c)    (min((c), 7) << 8)
 241 #define NDTR0_tRH(c)    (min((c), 7) << 3)
 242 #define NDTR0_tRP(c)    (min((c), 7) << 0)
 243
 244 #define NDTR1_tR(c)     (min((c), 65535) << 16)
 245 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 246 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 247
 248 /* convert nano-seconds to nand flash controller clock cycles */
 249 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 250
 251 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
 252                                    const struct pxa3xx_nand_timing *t)
 253 {
 254         struct pxa3xx_nand_info *info = host->info_data;
 255         unsigned long nand_clk = clk_get_rate(info->clk);
 256         uint32_t ndtr0, ndtr1;
 257
 258         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 259                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 260                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
 261                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
 262                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
 263                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
 264
 265         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
 266                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 267                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 268
 269         info->ndtr0cs0 = ndtr0;
 270         info->ndtr1cs0 = ndtr1;
 271         nand_writel(info, NDTR0CS0, ndtr0);
 272         nand_writel(info, NDTR1CS0, ndtr1);
 273 }
 274
 275 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 276 {
 277         struct pxa3xx_nand_host *host = info->host[info->cs];
 278         int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
 279
 280         info->data_size = host->page_size;
 281         if (!oob_enable) {
 282                 info->oob_size = 0;
 283                 return;
 284         }
 285
 286         switch (host->page_size) {
 287         case 2048:
 288                 info->oob_size = (info->use_ecc) ? 40 : 64;
 289                 break;
 290         case 512:
 291                 info->oob_size = (info->use_ecc) ? 8 : 16;
 292                 break;
 293         }
 294 }
 295
 296 /**
 297  * NOTE: it is a must to set ND_RUN firstly, then write
 298  * command buffer, otherwise, it does not work.
 299  * We enable all the interrupt at the same time, and
 300  * let pxa3xx_nand_irq to handle all logic.
 301  */
 302 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
 303 {
 304         uint32_t ndcr;
 305
 306         ndcr = info->reg_ndcr;
 307
 308         if (info->use_ecc)
 309                 ndcr |= NDCR_ECC_EN;
 310         else
 311                 ndcr &= ~NDCR_ECC_EN;
 312
 313         if (info->use_dma)
 314                 ndcr |= NDCR_DMA_EN;
 315         else
 316                 ndcr &= ~NDCR_DMA_EN;
 317
 318         if (info->use_spare)
 319                 ndcr |= NDCR_SPARE_EN;
 320         else
 321                 ndcr &= ~NDCR_SPARE_EN;
 322
 323         ndcr |= NDCR_ND_RUN;
 324
 325         /* clear status bits and run */
 326         nand_writel(info, NDCR, 0);
 327         nand_writel(info, NDSR, NDSR_MASK);
 328         nand_writel(info, NDCR, ndcr);
 329 }
 330
 331 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 332 {
 333         uint32_t ndcr;
 334         int timeout = NAND_STOP_DELAY;
 335
 336         /* wait RUN bit in NDCR become 0 */
 337         ndcr = nand_readl(info, NDCR);
 338         while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
 339                 ndcr = nand_readl(info, NDCR);
 340                 udelay(1);
 341         }
 342
 343         if (timeout <= 0) {
 344                 ndcr &= ~NDCR_ND_RUN;
 345                 nand_writel(info, NDCR, ndcr);
 346         }
 347         /* clear status bits */
 348         nand_writel(info, NDSR, NDSR_MASK);
 349 }
 350
 351 static void __maybe_unused
 352 enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 353 {
 354         uint32_t ndcr;
 355
 356         ndcr = nand_readl(info, NDCR);
 357         nand_writel(info, NDCR, ndcr & ~int_mask);
 358 }
 359
 360 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 361 {
 362         uint32_t ndcr;
 363
 364         ndcr = nand_readl(info, NDCR);
 365         nand_writel(info, NDCR, ndcr | int_mask);
 366 }
 367
 368 static void handle_data_pio(struct pxa3xx_nand_info *info)
 369 {
 370         switch (info->state) {
 371         case STATE_PIO_WRITING:
 372                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
 373                                 DIV_ROUND_UP(info->data_size, 4));
 374                 if (info->oob_size > 0)
 375                         __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 376                                         DIV_ROUND_UP(info->oob_size, 4));
 377                 break;
 378         case STATE_PIO_READING:
 379                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
 380                                 DIV_ROUND_UP(info->data_size, 4));
 381                 if (info->oob_size > 0)
 382                         __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 383                                         DIV_ROUND_UP(info->oob_size, 4));
 384                 break;
 385         default:
 386                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 387                                 info->state);
 388                 BUG();
 389         }
 390 }
 391
 392 #ifdef ARCH_HAS_DMA
 393 static void start_data_dma(struct pxa3xx_nand_info *info)
 394 {
 395         struct pxa_dma_desc *desc = info->data_desc;
 396         int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 397
 398         desc->ddadr = DDADR_STOP;
 399         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
 400
 401         switch (info->state) {
 402         case STATE_DMA_WRITING:
 403                 desc->dsadr = info->data_buff_phys;
 404                 desc->dtadr = info->mmio_phys + NDDB;
 405                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 406                 break;
 407         case STATE_DMA_READING:
 408                 desc->dtadr = info->data_buff_phys;
 409                 desc->dsadr = info->mmio_phys + NDDB;
 410                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 411                 break;
 412         default:
 413                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 414                                 info->state);
 415                 BUG();
 416         }
 417
 418         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
 419         DDADR(info->data_dma_ch) = info->data_desc_addr;
 420         DCSR(info->data_dma_ch) |= DCSR_RUN;
 421 }
 422
 423 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 424 {
 425         struct pxa3xx_nand_info *info = data;
 426         uint32_t dcsr;
 427
 428         dcsr = DCSR(channel);
 429         DCSR(channel) = dcsr;
 430
 431         if (dcsr & DCSR_BUSERR) {
 432                 info->retcode = ERR_DMABUSERR;
 433         }
 434
 435         info->state = STATE_DMA_DONE;
 436         enable_int(info, NDCR_INT_MASK);
 437         nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 438 }
 439 #else
 440 static void start_data_dma(struct pxa3xx_nand_info *info)
 441 {}
 442 #endif
 443
 444 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 445 {
 446         struct pxa3xx_nand_info *info = devid;
 447         unsigned int status, is_completed = 0;
 448         unsigned int ready, cmd_done;
 449
 450         if (info->cs == 0) {
 451                 ready           = NDSR_FLASH_RDY;
 452                 cmd_done        = NDSR_CS0_CMDD;
 453         } else {
 454                 ready           = NDSR_RDY;
 455                 cmd_done        = NDSR_CS1_CMDD;
 456         }
 457
 458         status = nand_readl(info, NDSR);
 459
 460         if (status & NDSR_DBERR)
 461                 info->retcode = ERR_DBERR;
 462         if (status & NDSR_SBERR)
 463                 info->retcode = ERR_SBERR;
 464         if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 465                 /* whether use dma to transfer data */
 466                 if (info->use_dma) {
 467                         disable_int(info, NDCR_INT_MASK);
 468                         info->state = (status & NDSR_RDDREQ) ?
 469                                       STATE_DMA_READING : STATE_DMA_WRITING;
 470                         start_data_dma(info);
 471                         goto NORMAL_IRQ_EXIT;
 472                 } else {
 473                         info->state = (status & NDSR_RDDREQ) ?
 474                                       STATE_PIO_READING : STATE_PIO_WRITING;
 475                         handle_data_pio(info);
 476                 }
 477         }
 478         if (status & cmd_done) {
 479                 info->state = STATE_CMD_DONE;
 480                 is_completed = 1;
 481         }
 482         if (status & ready) {
 483                 info->is_ready = 1;
 484                 info->state = STATE_READY;
 485         }
 486
 487         if (status & NDSR_WRCMDREQ) {
 488                 nand_writel(info, NDSR, NDSR_WRCMDREQ);
 489                 status &= ~NDSR_WRCMDREQ;
 490                 info->state = STATE_CMD_HANDLE;
 491
 492                 /*
 493                  * Command buffer registers NDCB{0-2} (and optionally NDCB3)
 494                  * must be loaded by writing directly either 12 or 16
 495                  * bytes directly to NDCB0, four bytes at a time.
 496                  *
 497                  * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
 498                  * but each NDCBx register can be read.
 499                  */
 500                 nand_writel(info, NDCB0, info->ndcb0);
 501                 nand_writel(info, NDCB0, info->ndcb1);
 502                 nand_writel(info, NDCB0, info->ndcb2);
 503
 504                 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
 505                 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
 506                         nand_writel(info, NDCB0, info->ndcb3);
 507         }
 508
 509         /* clear NDSR to let the controller exit the IRQ */
 510         nand_writel(info, NDSR, status);
 511         if (is_completed)
 512                 complete(&info->cmd_complete);
 513 NORMAL_IRQ_EXIT:
 514         return IRQ_HANDLED;
 515 }
 516
 517 static inline int is_buf_blank(uint8_t *buf, size_t len)
 518 {
 519         for (; len > 0; len--)
 520                 if (*buf++ != 0xff)
 521                         return 0;
 522         return 1;
 523 }
 524
 525 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
 526                 uint16_t column, int page_addr)
 527 {
 528         int addr_cycle, exec_cmd;
 529         struct pxa3xx_nand_host *host;
 530         struct mtd_info *mtd;
 531
 532         host = info->host[info->cs];
 533         mtd = host->mtd;
 534         addr_cycle = 0;
 535         exec_cmd = 1;
 536
 537         /* reset data and oob column point to handle data */
 538         info->buf_start         = 0;
 539         info->buf_count         = 0;
 540         info->oob_size          = 0;
 541         info->use_ecc           = 0;
 542         info->use_spare         = 1;
 543         info->use_dma           = (use_dma) ? 1 : 0;
 544         info->is_ready          = 0;
 545         info->retcode           = ERR_NONE;
 546         if (info->cs != 0)
 547                 info->ndcb0 = NDCB0_CSEL;
 548         else
 549                 info->ndcb0 = 0;
 550
 551         switch (command) {
 552         case NAND_CMD_READ0:
 553         case NAND_CMD_PAGEPROG:
 554                 info->use_ecc = 1;
 555         case NAND_CMD_READOOB:
 556                 pxa3xx_set_datasize(info);
 557                 break;
 558         case NAND_CMD_PARAM:
 559                 info->use_spare = 0;
 560                 break;
 561         case NAND_CMD_SEQIN:
 562                 exec_cmd = 0;
 563                 break;
 564         default:
 565                 info->ndcb1 = 0;
 566                 info->ndcb2 = 0;
 567                 info->ndcb3 = 0;
 568                 break;
 569         }
 570
 571         addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
 572                                     + host->col_addr_cycles);
 573
 574         switch (command) {
 575         case NAND_CMD_READOOB:
 576         case NAND_CMD_READ0:
 577                 info->buf_start = column;
 578                 info->ndcb0 |= NDCB0_CMD_TYPE(0)
 579                                 | addr_cycle
 580                                 | NAND_CMD_READ0;
 581
 582                 if (command == NAND_CMD_READOOB)
 583                         info->buf_start += mtd->writesize;
 584
 585                 /* Second command setting for large pages */
 586                 if (host->page_size >= PAGE_CHUNK_SIZE)
 587                         info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
 588
 589         case NAND_CMD_SEQIN:
 590                 /* small page addr setting */
 591                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
 592                         info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 593                                         | (column & 0xFF);
 594
 595                         info->ndcb2 = 0;
 596                 } else {
 597                         info->ndcb1 = ((page_addr & 0xFFFF) << 16)
 598                                         | (column & 0xFFFF);
 599
 600                         if (page_addr & 0xFF0000)
 601                                 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
 602                         else
 603                                 info->ndcb2 = 0;
 604                 }
 605
 606                 info->buf_count = mtd->writesize + mtd->oobsize;
 607                 memset(info->data_buff, 0xFF, info->buf_count);
 608
 609                 break;
 610
 611         case NAND_CMD_PAGEPROG:
 612                 if (is_buf_blank(info->data_buff,
 613                                         (mtd->writesize + mtd->oobsize))) {
 614                         exec_cmd = 0;
 615                         break;
 616                 }
 617
 618                 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 619                                 | NDCB0_AUTO_RS
 620                                 | NDCB0_ST_ROW_EN
 621                                 | NDCB0_DBC
 622                                 | (NAND_CMD_PAGEPROG << 8)
 623                                 | NAND_CMD_SEQIN
 624                                 | addr_cycle;
 625                 break;
 626
 627         case NAND_CMD_PARAM:
 628                 info->buf_count = 256;
 629                 info->ndcb0 |= NDCB0_CMD_TYPE(0)
 630                                 | NDCB0_ADDR_CYC(1)
 631                                 | NDCB0_LEN_OVRD
 632                                 | command;
 633                 info->ndcb1 = (column & 0xFF);
 634                 info->ndcb3 = 256;
 635                 info->data_size = 256;
 636                 break;
 637
 638         case NAND_CMD_READID:
 639                 info->buf_count = host->read_id_bytes;
 640                 info->ndcb0 |= NDCB0_CMD_TYPE(3)
 641                                 | NDCB0_ADDR_CYC(1)
 642                                 | command;
 643                 info->ndcb1 = (column & 0xFF);
 644
 645                 info->data_size = 8;
 646                 break;
 647         case NAND_CMD_STATUS:
 648                 info->buf_count = 1;
 649                 info->ndcb0 |= NDCB0_CMD_TYPE(4)
 650                                 | NDCB0_ADDR_CYC(1)
 651                                 | command;
 652
 653                 info->data_size = 8;
 654                 break;
 655
 656         case NAND_CMD_ERASE1:
 657                 info->ndcb0 |= NDCB0_CMD_TYPE(2)
 658                                 | NDCB0_AUTO_RS
 659                                 | NDCB0_ADDR_CYC(3)
 660                                 | NDCB0_DBC
 661                                 | (NAND_CMD_ERASE2 << 8)
 662                                 | NAND_CMD_ERASE1;
 663                 info->ndcb1 = page_addr;
 664                 info->ndcb2 = 0;
 665
 666                 break;
 667         case NAND_CMD_RESET:
 668                 info->ndcb0 |= NDCB0_CMD_TYPE(5)
 669                                 | command;
 670
 671                 break;
 672
 673         case NAND_CMD_ERASE2:
 674                 exec_cmd = 0;
 675                 break;
 676
 677         default:
 678                 exec_cmd = 0;
 679                 dev_err(&info->pdev->dev, "non-supported command %x\n",
 680                                 command);
 681                 break;
 682         }
 683
 684         return exec_cmd;
 685 }
 686
 687 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 688                                 int column, int page_addr)
 689 {
 690         struct pxa3xx_nand_host *host = mtd->priv;
 691         struct pxa3xx_nand_info *info = host->info_data;
 692         int ret, exec_cmd;
 693
 694         /*
 695          * if this is a x16 device ,then convert the input
 696          * "byte" address into a "word" address appropriate
 697          * for indexing a word-oriented device
 698          */
 699         if (info->reg_ndcr & NDCR_DWIDTH_M)
 700                 column /= 2;
 701
 702         /*
 703          * There may be different NAND chip hooked to
 704          * different chip select, so check whether
 705          * chip select has been changed, if yes, reset the timing
 706          */
 707         if (info->cs != host->cs) {
 708                 info->cs = host->cs;
 709                 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
 710                 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
 711         }
 712
 713         info->state = STATE_PREPARED;
 714         exec_cmd = prepare_command_pool(info, command, column, page_addr);
 715         if (exec_cmd) {
 716                 init_completion(&info->cmd_complete);
 717                 pxa3xx_nand_start(info);
 718
 719                 ret = wait_for_completion_timeout(&info->cmd_complete,
 720                                 CHIP_DELAY_TIMEOUT);
 721                 if (!ret) {
 722                         dev_err(&info->pdev->dev, "Wait time out!!!\n");
 723                         /* Stop State Machine for next command cycle */
 724                         pxa3xx_nand_stop(info);
 725                 }
 726         }
 727         info->state = STATE_IDLE;
 728 }
 729
 730 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 731                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 732 {
 733         chip->write_buf(mtd, buf, mtd->writesize);
 734         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 735
 736         return 0;
 737 }
 738
 739 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 740                 struct nand_chip *chip, uint8_t *buf, int oob_required,
 741                 int page)
 742 {
 743         struct pxa3xx_nand_host *host = mtd->priv;
 744         struct pxa3xx_nand_info *info = host->info_data;
 745
 746         chip->read_buf(mtd, buf, mtd->writesize);
 747         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 748
 749         if (info->retcode == ERR_SBERR) {
 750                 switch (info->use_ecc) {
 751                 case 1:
 752                         mtd->ecc_stats.corrected++;
 753                         break;
 754                 case 0:
 755                 default:
 756                         break;
 757                 }
 758         } else if (info->retcode == ERR_DBERR) {
 759                 /*
 760                  * for blank page (all 0xff), HW will calculate its ECC as
 761                  * 0, which is different from the ECC information within
 762                  * OOB, ignore such double bit errors
 763                  */
 764                 if (is_buf_blank(buf, mtd->writesize))
 765                         info->retcode = ERR_NONE;
 766                 else
 767                         mtd->ecc_stats.failed++;
 768         }
 769
 770         return 0;
 771 }
 772
 773 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 774 {
 775         struct pxa3xx_nand_host *host = mtd->priv;
 776         struct pxa3xx_nand_info *info = host->info_data;
 777         char retval = 0xFF;
 778
 779         if (info->buf_start < info->buf_count)
 780                 /* Has just send a new command? */
 781                 retval = info->data_buff[info->buf_start++];
 782
 783         return retval;
 784 }
 785
 786 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 787 {
 788         struct pxa3xx_nand_host *host = mtd->priv;
 789         struct pxa3xx_nand_info *info = host->info_data;
 790         u16 retval = 0xFFFF;
 791
 792         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
 793                 retval = *((u16 *)(info->data_buff+info->buf_start));
 794                 info->buf_start += 2;
 795         }
 796         return retval;
 797 }
 798
 799 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 800 {
 801         struct pxa3xx_nand_host *host = mtd->priv;
 802         struct pxa3xx_nand_info *info = host->info_data;
 803         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 804
 805         memcpy(buf, info->data_buff + info->buf_start, real_len);
 806         info->buf_start += real_len;
 807 }
 808
 809 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 810                 const uint8_t *buf, int len)
 811 {
 812         struct pxa3xx_nand_host *host = mtd->priv;
 813         struct pxa3xx_nand_info *info = host->info_data;
 814         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 815
 816         memcpy(info->data_buff + info->buf_start, buf, real_len);
 817         info->buf_start += real_len;
 818 }
 819
 820 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 821 {
 822         return;
 823 }
 824
 825 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 826 {
 827         struct pxa3xx_nand_host *host = mtd->priv;
 828         struct pxa3xx_nand_info *info = host->info_data;
 829
 830         /* pxa3xx_nand_send_command has waited for command complete */
 831         if (this->state == FL_WRITING || this->state == FL_ERASING) {
 832                 if (info->retcode == ERR_NONE)
 833                         return 0;
 834                 else {
 835                         /*
 836                          * any error make it return 0x01 which will tell
 837                          * the caller the erase and write fail
 838                          */
 839                         return 0x01;
 840                 }
 841         }
 842
 843         return 0;
 844 }
 845
 846 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 847                                     const struct pxa3xx_nand_flash *f)
 848 {
 849         struct platform_device *pdev = info->pdev;
 850         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 851         struct pxa3xx_nand_host *host = info->host[info->cs];
 852         uint32_t ndcr = 0x0; /* enable all interrupts */
 853
 854         if (f->page_size != 2048 && f->page_size != 512) {
 855                 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
 856                 return -EINVAL;
 857         }
 858
 859         if (f->flash_width != 16 && f->flash_width != 8) {
 860                 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
 861                 return -EINVAL;
 862         }
 863
 864         /* calculate flash information */
 865         host->page_size = f->page_size;
 866         host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 867
 868         /* calculate addressing information */
 869         host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
 870
 871         if (f->num_blocks * f->page_per_block > 65536)
 872                 host->row_addr_cycles = 3;
 873         else
 874                 host->row_addr_cycles = 2;
 875
 876         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
 877         ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 878         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 879         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 880         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 881         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
 882
 883         ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 884         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 885
 886         info->reg_ndcr = ndcr;
 887
 888         pxa3xx_nand_set_timing(host, f->timing);
 889         return 0;
 890 }
 891
 892 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 893 {
 894         /*
 895          * We set 0 by hard coding here, for we don't support keep_config
 896          * when there is more than one chip attached to the controller
 897          */
 898         struct pxa3xx_nand_host *host = info->host[0];
 899         uint32_t ndcr = nand_readl(info, NDCR);
 900
 901         if (ndcr & NDCR_PAGE_SZ) {
 902                 host->page_size = 2048;
 903                 host->read_id_bytes = 4;
 904         } else {
 905                 host->page_size = 512;
 906                 host->read_id_bytes = 2;
 907         }
 908
 909         info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 910         info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 911         info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 912         return 0;
 913 }
 914
 915 /* the maximum possible buffer size for large page with OOB data
 916  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
 917  * data buffer and the DMA descriptor
 918  */
 919 #define MAX_BUFF_SIZE   PAGE_SIZE
 920
 921 #ifdef ARCH_HAS_DMA
 922 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 923 {
 924         struct platform_device *pdev = info->pdev;
 925         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
 926
 927         if (use_dma == 0) {
 928                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 929                 if (info->data_buff == NULL)
 930                         return -ENOMEM;
 931                 return 0;
 932         }
 933
 934         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
 935                                 &info->data_buff_phys, GFP_KERNEL);
 936         if (info->data_buff == NULL) {
 937                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 938                 return -ENOMEM;
 939         }
 940
 941         info->data_desc = (void *)info->data_buff + data_desc_offset;
 942         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 943
 944         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 945                                 pxa3xx_nand_data_dma_irq, info);
 946         if (info->data_dma_ch < 0) {
 947                 dev_err(&pdev->dev, "failed to request data dma\n");
 948                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 949                                 info->data_buff, info->data_buff_phys);
 950                 return info->data_dma_ch;
 951         }
 952
 953         return 0;
 954 }
 955
 956 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
 957 {
 958         struct platform_device *pdev = info->pdev;
 959         if (use_dma) {
 960                 pxa_free_dma(info->data_dma_ch);
 961                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 962                                   info->data_buff, info->data_buff_phys);
 963         } else {
 964                 kfree(info->data_buff);
 965         }
 966 }
 967 #else
 968 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 969 {
 970         info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 971         if (info->data_buff == NULL)
 972                 return -ENOMEM;
 973         return 0;
 974 }
 975
 976 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
 977 {
 978         kfree(info->data_buff);
 979 }
 980 #endif
 981
 982 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 983 {
 984         struct mtd_info *mtd;
 985         int ret;
 986         mtd = info->host[info->cs]->mtd;
 987         /* use the common timing to make a try */
 988         ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
 989         if (ret)
 990                 return ret;
 991
 992         pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 993         if (info->is_ready)
 994                 return 0;
 995
 996         return -ENODEV;
 997 }
 998
 999 static int pxa3xx_nand_scan(struct mtd_info *mtd)
1000 {
1001         struct pxa3xx_nand_host *host = mtd->priv;
1002         struct pxa3xx_nand_info *info = host->info_data;
1003         struct platform_device *pdev = info->pdev;
1004         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
1005         struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
1006         const struct pxa3xx_nand_flash *f = NULL;
1007         struct nand_chip *chip = mtd->priv;
1008         uint32_t id = -1;
1009         uint64_t chipsize;
1010         int i, ret, num;
1011
1012         if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
1013                 goto KEEP_CONFIG;
1014
1015         ret = pxa3xx_nand_sensing(info);
1016         if (ret) {
1017                 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
1018                          info->cs);
1019
1020                 return ret;
1021         }
1022
1023         chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
1024         id = *((uint16_t *)(info->data_buff));
1025         if (id != 0)
1026                 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
1027         else {
1028                 dev_warn(&info->pdev->dev,
1029                          "Read out ID 0, potential timing set wrong!!\n");
1030
1031                 return -EINVAL;
1032         }
1033
1034         num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1035         for (i = 0; i < num; i++) {
1036                 if (i < pdata->num_flash)
1037                         f = pdata->flash + i;
1038                 else
1039                         f = &builtin_flash_types[i - pdata->num_flash + 1];
1040
1041                 /* find the chip in default list */
1042                 if (f->chip_id == id)
1043                         break;
1044         }
1045
1046         if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
1047                 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
1048
1049                 return -EINVAL;
1050         }
1051
1052         ret = pxa3xx_nand_config_flash(info, f);
1053         if (ret) {
1054                 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1055                 return ret;
1056         }
1057
1058         pxa3xx_flash_ids[0].name = f->name;
1059         pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
1060         pxa3xx_flash_ids[0].pagesize = f->page_size;
1061         chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1062         pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1063         pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1064         if (f->flash_width == 16)
1065                 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
1066         pxa3xx_flash_ids[1].name = NULL;
1067         def = pxa3xx_flash_ids;
1068 KEEP_CONFIG:
1069         chip->ecc.mode = NAND_ECC_HW;
1070         chip->ecc.size = host->page_size;
1071         chip->ecc.strength = 1;
1072
1073         if (info->reg_ndcr & NDCR_DWIDTH_M)
1074                 chip->options |= NAND_BUSWIDTH_16;
1075
1076         if (nand_scan_ident(mtd, 1, def))
1077                 return -ENODEV;
1078         /* calculate addressing information */
1079         if (mtd->writesize >= 2048)
1080                 host->col_addr_cycles = 2;
1081         else
1082                 host->col_addr_cycles = 1;
1083
1084         info->oob_buff = info->data_buff + mtd->writesize;
1085         if ((mtd->size >> chip->page_shift) > 65536)
1086                 host->row_addr_cycles = 3;
1087         else
1088                 host->row_addr_cycles = 2;
1089         return nand_scan_tail(mtd);
1090 }
1091
1092 static int alloc_nand_resource(struct platform_device *pdev)
1093 {
1094         struct pxa3xx_nand_platform_data *pdata;
1095         struct pxa3xx_nand_info *info;
1096         struct pxa3xx_nand_host *host;
1097         struct nand_chip *chip = NULL;
1098         struct mtd_info *mtd;
1099         struct resource *r;
1100         int ret, irq, cs;
1101
1102         pdata = dev_get_platdata(&pdev->dev);
1103         info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1104                             sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1105         if (!info)
1106                 return -ENOMEM;
1107
1108         info->pdev = pdev;
1109         for (cs = 0; cs < pdata->num_cs; cs++) {
1110                 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1111                       (sizeof(*mtd) + sizeof(*host)) * cs);
1112                 chip = (struct nand_chip *)(&mtd[1]);
1113                 host = (struct pxa3xx_nand_host *)chip;
1114                 info->host[cs] = host;
1115                 host->mtd = mtd;
1116                 host->cs = cs;
1117                 host->info_data = info;
1118                 mtd->priv = host;
1119                 mtd->owner = THIS_MODULE;
1120
1121                 chip->ecc.read_page     = pxa3xx_nand_read_page_hwecc;
1122                 chip->ecc.write_page    = pxa3xx_nand_write_page_hwecc;
1123                 chip->controller        = &info->controller;
1124                 chip->waitfunc          = pxa3xx_nand_waitfunc;
1125                 chip->select_chip       = pxa3xx_nand_select_chip;
1126                 chip->cmdfunc           = pxa3xx_nand_cmdfunc;
1127                 chip->read_word         = pxa3xx_nand_read_word;
1128                 chip->read_byte         = pxa3xx_nand_read_byte;
1129                 chip->read_buf          = pxa3xx_nand_read_buf;
1130                 chip->write_buf         = pxa3xx_nand_write_buf;
1131         }
1132
1133         spin_lock_init(&chip->controller->lock);
1134         init_waitqueue_head(&chip->controller->wq);
1135         info->clk = devm_clk_get(&pdev->dev, NULL);
1136         if (IS_ERR(info->clk)) {
1137                 dev_err(&pdev->dev, "failed to get nand clock\n");
1138                 return PTR_ERR(info->clk);
1139         }
1140         ret = clk_prepare_enable(info->clk);
1141         if (ret < 0)
1142                 return ret;
1143
1144         if (use_dma) {
1145                 /*
1146                  * This is a dirty hack to make this driver work from
1147                  * devicetree bindings. It can be removed once we have
1148                  * a prober DMA controller framework for DT.
1149                  */
1150                 if (pdev->dev.of_node &&
1151                     of_machine_is_compatible("marvell,pxa3xx")) {
1152                         info->drcmr_dat = 97;
1153                         info->drcmr_cmd = 99;
1154                 } else {
1155                         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1156                         if (r == NULL) {
1157                                 dev_err(&pdev->dev,
1158                                         "no resource defined for data DMA\n");
1159                                 ret = -ENXIO;
1160                                 goto fail_disable_clk;
1161                         }
1162                         info->drcmr_dat = r->start;
1163
1164                         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1165                         if (r == NULL) {
1166                                 dev_err(&pdev->dev,
1167                                         "no resource defined for cmd DMA\n");
1168                                 ret = -ENXIO;
1169                                 goto fail_disable_clk;
1170                         }
1171                         info->drcmr_cmd = r->start;
1172                 }
1173         }
1174
1175         irq = platform_get_irq(pdev, 0);
1176         if (irq < 0) {
1177                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1178                 ret = -ENXIO;
1179                 goto fail_disable_clk;
1180         }
1181
1182         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183         info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1184         if (IS_ERR(info->mmio_base)) {
1185                 ret = PTR_ERR(info->mmio_base);
1186                 goto fail_disable_clk;
1187         }
1188         info->mmio_phys = r->start;
1189
1190         ret = pxa3xx_nand_init_buff(info);
1191         if (ret)
1192                 goto fail_disable_clk;
1193
1194         /* initialize all interrupts to be disabled */
1195         disable_int(info, NDSR_MASK);
1196
1197         ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1198                           pdev->name, info);
1199         if (ret < 0) {
1200                 dev_err(&pdev->dev, "failed to request IRQ\n");
1201                 goto fail_free_buf;
1202         }
1203
1204         platform_set_drvdata(pdev, info);
1205
1206         return 0;
1207
1208 fail_free_buf:
1209         free_irq(irq, info);
1210         pxa3xx_nand_free_buff(info);
1211 fail_disable_clk:
1212         clk_disable_unprepare(info->clk);
1213         return ret;
1214 }
1215
1216 static int pxa3xx_nand_remove(struct platform_device *pdev)
1217 {
1218         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1219         struct pxa3xx_nand_platform_data *pdata;
1220         int irq, cs;
1221
1222         if (!info)
1223                 return 0;
1224
1225         pdata = dev_get_platdata(&pdev->dev);
1226
1227         irq = platform_get_irq(pdev, 0);
1228         if (irq >= 0)
1229                 free_irq(irq, info);
1230         pxa3xx_nand_free_buff(info);
1231
1232         clk_disable_unprepare(info->clk);
1233
1234         for (cs = 0; cs < pdata->num_cs; cs++)
1235                 nand_release(info->host[cs]->mtd);
1236         return 0;
1237 }
1238
1239 static struct of_device_id pxa3xx_nand_dt_ids[] = {
1240         {
1241                 .compatible = "marvell,pxa3xx-nand",
1242                 .data       = (void *)PXA3XX_NAND_VARIANT_PXA,
1243         },
1244         {
1245                 .compatible = "marvell,armada370-nand",
1246                 .data       = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
1247         },
1248         {}
1249 };
1250 MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
1251
1252 static enum pxa3xx_nand_variant
1253 pxa3xx_nand_get_variant(struct platform_device *pdev)
1254 {
1255         const struct of_device_id *of_id =
1256                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1257         if (!of_id)
1258                 return PXA3XX_NAND_VARIANT_PXA;
1259         return (enum pxa3xx_nand_variant)of_id->data;
1260 }
1261
1262 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1263 {
1264         struct pxa3xx_nand_platform_data *pdata;
1265         struct device_node *np = pdev->dev.of_node;
1266         const struct of_device_id *of_id =
1267                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1268
1269         if (!of_id)
1270                 return 0;
1271
1272         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1273         if (!pdata)
1274                 return -ENOMEM;
1275
1276         if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1277                 pdata->enable_arbiter = 1;
1278         if (of_get_property(np, "marvell,nand-keep-config", NULL))
1279                 pdata->keep_config = 1;
1280         of_property_read_u32(np, "num-cs", &pdata->num_cs);
1281
1282         pdev->dev.platform_data = pdata;
1283
1284         return 0;
1285 }
1286
1287 static int pxa3xx_nand_probe(struct platform_device *pdev)
1288 {
1289         struct pxa3xx_nand_platform_data *pdata;
1290         struct mtd_part_parser_data ppdata = {};
1291         struct pxa3xx_nand_info *info;
1292         int ret, cs, probe_success;
1293
1294 #ifndef ARCH_HAS_DMA
1295         if (use_dma) {
1296                 use_dma = 0;
1297                 dev_warn(&pdev->dev,
1298                          "This platform can't do DMA on this device\n");
1299         }
1300 #endif
1301         ret = pxa3xx_nand_probe_dt(pdev);
1302         if (ret)
1303                 return ret;
1304
1305         pdata = dev_get_platdata(&pdev->dev);
1306         if (!pdata) {
1307                 dev_err(&pdev->dev, "no platform data defined\n");
1308                 return -ENODEV;
1309         }
1310
1311         ret = alloc_nand_resource(pdev);
1312         if (ret) {
1313                 dev_err(&pdev->dev, "alloc nand resource failed\n");
1314                 return ret;
1315         }
1316
1317         info = platform_get_drvdata(pdev);
1318         info->variant = pxa3xx_nand_get_variant(pdev);
1319         probe_success = 0;
1320         for (cs = 0; cs < pdata->num_cs; cs++) {
1321                 struct mtd_info *mtd = info->host[cs]->mtd;
1322
1323                 mtd->name = pdev->name;
1324                 info->cs = cs;
1325                 ret = pxa3xx_nand_scan(mtd);
1326                 if (ret) {
1327                         dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1328                                 cs);
1329                         continue;
1330                 }
1331
1332                 ppdata.of_node = pdev->dev.of_node;
1333                 ret = mtd_device_parse_register(mtd, NULL,
1334                                                 &ppdata, pdata->parts[cs],
1335                                                 pdata->nr_parts[cs]);
1336                 if (!ret)
1337                         probe_success = 1;
1338         }
1339
1340         if (!probe_success) {
1341                 pxa3xx_nand_remove(pdev);
1342                 return -ENODEV;
1343         }
1344
1345         return 0;
1346 }
1347
1348 #ifdef CONFIG_PM
1349 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1350 {
1351         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1352         struct pxa3xx_nand_platform_data *pdata;
1353         struct mtd_info *mtd;
1354         int cs;
1355
1356         pdata = dev_get_platdata(&pdev->dev);
1357         if (info->state) {
1358                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1359                 return -EAGAIN;
1360         }
1361
1362         for (cs = 0; cs < pdata->num_cs; cs++) {
1363                 mtd = info->host[cs]->mtd;
1364                 mtd_suspend(mtd);
1365         }
1366
1367         return 0;
1368 }
1369
1370 static int pxa3xx_nand_resume(struct platform_device *pdev)
1371 {
1372         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1373         struct pxa3xx_nand_platform_data *pdata;
1374         struct mtd_info *mtd;
1375         int cs;
1376
1377         pdata = dev_get_platdata(&pdev->dev);
1378         /* We don't want to handle interrupt without calling mtd routine */
1379         disable_int(info, NDCR_INT_MASK);
1380
1381         /*
1382          * Directly set the chip select to a invalid value,
1383          * then the driver would reset the timing according
1384          * to current chip select at the beginning of cmdfunc
1385          */
1386         info->cs = 0xff;
1387
1388         /*
1389          * As the spec says, the NDSR would be updated to 0x1800 when
1390          * doing the nand_clk disable/enable.
1391          * To prevent it damaging state machine of the driver, clear
1392          * all status before resume
1393          */
1394         nand_writel(info, NDSR, NDSR_MASK);
1395         for (cs = 0; cs < pdata->num_cs; cs++) {
1396                 mtd = info->host[cs]->mtd;
1397                 mtd_resume(mtd);
1398         }
1399
1400         return 0;
1401 }
1402 #else
1403 #define pxa3xx_nand_suspend     NULL
1404 #define pxa3xx_nand_resume      NULL
1405 #endif
1406
1407 static struct platform_driver pxa3xx_nand_driver = {
1408         .driver = {
1409                 .name   = "pxa3xx-nand",
1410                 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1411         },
1412         .probe          = pxa3xx_nand_probe,
1413         .remove         = pxa3xx_nand_remove,
1414         .suspend        = pxa3xx_nand_suspend,
1415         .resume         = pxa3xx_nand_resume,
1416 };
1417
1418 module_platform_driver(pxa3xx_nand_driver);
1419
1420 MODULE_LICENSE("GPL");
1421 MODULE_DESCRIPTION("PXA3xx NAND controller driver");