drivers/mtd/nand/pxa3xx_nand.c

   1 /*
   2  * drivers/mtd/nand/pxa3xx_nand.c
   3  *
   4  * Copyright © 2005 Intel Corporation
   5  * Copyright © 2006 Marvell International Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <mach/dma.h>
  29 #include <linux/platform_data/mtd-nand-pxa3xx.h>
  30
  31 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
  32 #define NAND_STOP_DELAY         (2 * HZ/50)
  33 #define PAGE_CHUNK_SIZE         (2048)
  34
  35 /* registers and bit definitions */
  36 #define NDCR            (0x00) /* Control register */
  37 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
  38 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
  39 #define NDSR            (0x14) /* Status Register */
  40 #define NDPCR           (0x18) /* Page Count Register */
  41 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
  42 #define NDBDR1          (0x20) /* Bad Block Register 1 */
  43 #define NDDB            (0x40) /* Data Buffer */
  44 #define NDCB0           (0x48) /* Command Buffer0 */
  45 #define NDCB1           (0x4C) /* Command Buffer1 */
  46 #define NDCB2           (0x50) /* Command Buffer2 */
  47
  48 #define NDCR_SPARE_EN           (0x1 << 31)
  49 #define NDCR_ECC_EN             (0x1 << 30)
  50 #define NDCR_DMA_EN             (0x1 << 29)
  51 #define NDCR_ND_RUN             (0x1 << 28)
  52 #define NDCR_DWIDTH_C           (0x1 << 27)
  53 #define NDCR_DWIDTH_M           (0x1 << 26)
  54 #define NDCR_PAGE_SZ            (0x1 << 24)
  55 #define NDCR_NCSX               (0x1 << 23)
  56 #define NDCR_ND_MODE            (0x3 << 21)
  57 #define NDCR_NAND_MODE          (0x0)
  58 #define NDCR_CLR_PG_CNT         (0x1 << 20)
  59 #define NDCR_STOP_ON_UNCOR      (0x1 << 19)
  60 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
  61 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  62
  63 #define NDCR_RA_START           (0x1 << 15)
  64 #define NDCR_PG_PER_BLK         (0x1 << 14)
  65 #define NDCR_ND_ARB_EN          (0x1 << 12)
  66 #define NDCR_INT_MASK           (0xFFF)
  67
  68 #define NDSR_MASK               (0xfff)
  69 #define NDSR_RDY                (0x1 << 12)
  70 #define NDSR_FLASH_RDY          (0x1 << 11)
  71 #define NDSR_CS0_PAGED          (0x1 << 10)
  72 #define NDSR_CS1_PAGED          (0x1 << 9)
  73 #define NDSR_CS0_CMDD           (0x1 << 8)
  74 #define NDSR_CS1_CMDD           (0x1 << 7)
  75 #define NDSR_CS0_BBD            (0x1 << 6)
  76 #define NDSR_CS1_BBD            (0x1 << 5)
  77 #define NDSR_DBERR              (0x1 << 4)
  78 #define NDSR_SBERR              (0x1 << 3)
  79 #define NDSR_WRDREQ             (0x1 << 2)
  80 #define NDSR_RDDREQ             (0x1 << 1)
  81 #define NDSR_WRCMDREQ           (0x1)
  82
  83 #define NDCB0_ST_ROW_EN         (0x1 << 26)
  84 #define NDCB0_AUTO_RS           (0x1 << 25)
  85 #define NDCB0_CSEL              (0x1 << 24)
  86 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
  87 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  88 #define NDCB0_NC                (0x1 << 20)
  89 #define NDCB0_DBC               (0x1 << 19)
  90 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
  91 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  92 #define NDCB0_CMD2_MASK         (0xff << 8)
  93 #define NDCB0_CMD1_MASK         (0xff)
  94 #define NDCB0_ADDR_CYC_SHIFT    (16)
  95
  96 /* macros for registers read/write */
  97 #define nand_writel(info, off, val)     \
  98         __raw_writel((val), (info)->mmio_base + (off))
  99
 100 #define nand_readl(info, off)           \
 101         __raw_readl((info)->mmio_base + (off))
 102
 103 /* error code and state */
 104 enum {
 105         ERR_NONE        = 0,
 106         ERR_DMABUSERR   = -1,
 107         ERR_SENDCMD     = -2,
 108         ERR_DBERR       = -3,
 109         ERR_BBERR       = -4,
 110         ERR_SBERR       = -5,
 111 };
 112
 113 enum {
 114         STATE_IDLE = 0,
 115         STATE_PREPARED,
 116         STATE_CMD_HANDLE,
 117         STATE_DMA_READING,
 118         STATE_DMA_WRITING,
 119         STATE_DMA_DONE,
 120         STATE_PIO_READING,
 121         STATE_PIO_WRITING,
 122         STATE_CMD_DONE,
 123         STATE_READY,
 124 };
 125
 126 struct pxa3xx_nand_host {
 127         struct nand_chip        chip;
 128         struct pxa3xx_nand_cmdset *cmdset;
 129         struct mtd_info         *mtd;
 130         void                    *info_data;
 131
 132         /* page size of attached chip */
 133         unsigned int            page_size;
 134         int                     use_ecc;
 135         int                     cs;
 136
 137         /* calculated from pxa3xx_nand_flash data */
 138         unsigned int            col_addr_cycles;
 139         unsigned int            row_addr_cycles;
 140         size_t                  read_id_bytes;
 141
 142         /* cached register value */
 143         uint32_t                reg_ndcr;
 144         uint32_t                ndtr0cs0;
 145         uint32_t                ndtr1cs0;
 146 };
 147
 148 struct pxa3xx_nand_info {
 149         struct nand_hw_control  controller;
 150         struct platform_device   *pdev;
 151
 152         struct clk              *clk;
 153         void __iomem            *mmio_base;
 154         unsigned long           mmio_phys;
 155         struct completion       cmd_complete;
 156
 157         unsigned int            buf_start;
 158         unsigned int            buf_count;
 159
 160         /* DMA information */
 161         int                     drcmr_dat;
 162         int                     drcmr_cmd;
 163
 164         unsigned char           *data_buff;
 165         unsigned char           *oob_buff;
 166         dma_addr_t              data_buff_phys;
 167         int                     data_dma_ch;
 168         struct pxa_dma_desc     *data_desc;
 169         dma_addr_t              data_desc_addr;
 170
 171         struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
 172         unsigned int            state;
 173
 174         int                     cs;
 175         int                     use_ecc;        /* use HW ECC ? */
 176         int                     use_dma;        /* use DMA ? */
 177         int                     is_ready;
 178
 179         unsigned int            page_size;      /* page size of attached chip */
 180         unsigned int            data_size;      /* data size in FIFO */
 181         unsigned int            oob_size;
 182         int                     retcode;
 183
 184         /* generated NDCBx register values */
 185         uint32_t                ndcb0;
 186         uint32_t                ndcb1;
 187         uint32_t                ndcb2;
 188 };
 189
 190 static bool use_dma = 1;
 191 module_param(use_dma, bool, 0444);
 192 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
 193
 194 /*
 195  * Default NAND flash controller configuration setup by the
 196  * bootloader. This configuration is used only when pdata->keep_config is set
 197  */
 198 static struct pxa3xx_nand_cmdset default_cmdset = {
 199         .read1          = 0x3000,
 200         .read2          = 0x0050,
 201         .program        = 0x1080,
 202         .read_status    = 0x0070,
 203         .read_id        = 0x0090,
 204         .erase          = 0xD060,
 205         .reset          = 0x00FF,
 206         .lock           = 0x002A,
 207         .unlock         = 0x2423,
 208         .lock_status    = 0x007A,
 209 };
 210
 211 static struct pxa3xx_nand_timing timing[] = {
 212         { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 213         { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 214         { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 215         { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 216 };
 217
 218 static struct pxa3xx_nand_flash builtin_flash_types[] = {
 219 { "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },
 220 { "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },
 221 { "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },
 222 { "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },
 223 { "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },
 224 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },
 225 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },
 226 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },
 227 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },
 228 };
 229
 230 /* Define a default flash type setting serve as flash detecting only */
 231 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 232
 233 const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
 234
 235 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 236 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 237 #define NDTR0_tWH(c)    (min((c), 7) << 11)
 238 #define NDTR0_tWP(c)    (min((c), 7) << 8)
 239 #define NDTR0_tRH(c)    (min((c), 7) << 3)
 240 #define NDTR0_tRP(c)    (min((c), 7) << 0)
 241
 242 #define NDTR1_tR(c)     (min((c), 65535) << 16)
 243 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 244 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 245
 246 /* convert nano-seconds to nand flash controller clock cycles */
 247 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 248
 249 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
 250                                    const struct pxa3xx_nand_timing *t)
 251 {
 252         struct pxa3xx_nand_info *info = host->info_data;
 253         unsigned long nand_clk = clk_get_rate(info->clk);
 254         uint32_t ndtr0, ndtr1;
 255
 256         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 257                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 258                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
 259                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
 260                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
 261                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
 262
 263         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
 264                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 265                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 266
 267         host->ndtr0cs0 = ndtr0;
 268         host->ndtr1cs0 = ndtr1;
 269         nand_writel(info, NDTR0CS0, ndtr0);
 270         nand_writel(info, NDTR1CS0, ndtr1);
 271 }
 272
 273 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 274 {
 275         struct pxa3xx_nand_host *host = info->host[info->cs];
 276         int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
 277
 278         info->data_size = host->page_size;
 279         if (!oob_enable) {
 280                 info->oob_size = 0;
 281                 return;
 282         }
 283
 284         switch (host->page_size) {
 285         case 2048:
 286                 info->oob_size = (info->use_ecc) ? 40 : 64;
 287                 break;
 288         case 512:
 289                 info->oob_size = (info->use_ecc) ? 8 : 16;
 290                 break;
 291         }
 292 }
 293
 294 /**
 295  * NOTE: it is a must to set ND_RUN firstly, then write
 296  * command buffer, otherwise, it does not work.
 297  * We enable all the interrupt at the same time, and
 298  * let pxa3xx_nand_irq to handle all logic.
 299  */
 300 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
 301 {
 302         struct pxa3xx_nand_host *host = info->host[info->cs];
 303         uint32_t ndcr;
 304
 305         ndcr = host->reg_ndcr;
 306         ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
 307         ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
 308         ndcr |= NDCR_ND_RUN;
 309
 310         /* clear status bits and run */
 311         nand_writel(info, NDCR, 0);
 312         nand_writel(info, NDSR, NDSR_MASK);
 313         nand_writel(info, NDCR, ndcr);
 314 }
 315
 316 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 317 {
 318         uint32_t ndcr;
 319         int timeout = NAND_STOP_DELAY;
 320
 321         /* wait RUN bit in NDCR become 0 */
 322         ndcr = nand_readl(info, NDCR);
 323         while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
 324                 ndcr = nand_readl(info, NDCR);
 325                 udelay(1);
 326         }
 327
 328         if (timeout <= 0) {
 329                 ndcr &= ~NDCR_ND_RUN;
 330                 nand_writel(info, NDCR, ndcr);
 331         }
 332         /* clear status bits */
 333         nand_writel(info, NDSR, NDSR_MASK);
 334 }
 335
 336 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 337 {
 338         uint32_t ndcr;
 339
 340         ndcr = nand_readl(info, NDCR);
 341         nand_writel(info, NDCR, ndcr & ~int_mask);
 342 }
 343
 344 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 345 {
 346         uint32_t ndcr;
 347
 348         ndcr = nand_readl(info, NDCR);
 349         nand_writel(info, NDCR, ndcr | int_mask);
 350 }
 351
 352 static void handle_data_pio(struct pxa3xx_nand_info *info)
 353 {
 354         switch (info->state) {
 355         case STATE_PIO_WRITING:
 356                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
 357                                 DIV_ROUND_UP(info->data_size, 4));
 358                 if (info->oob_size > 0)
 359                         __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 360                                         DIV_ROUND_UP(info->oob_size, 4));
 361                 break;
 362         case STATE_PIO_READING:
 363                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
 364                                 DIV_ROUND_UP(info->data_size, 4));
 365                 if (info->oob_size > 0)
 366                         __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 367                                         DIV_ROUND_UP(info->oob_size, 4));
 368                 break;
 369         default:
 370                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 371                                 info->state);
 372                 BUG();
 373         }
 374 }
 375
 376 static void start_data_dma(struct pxa3xx_nand_info *info)
 377 {
 378         struct pxa_dma_desc *desc = info->data_desc;
 379         int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 380
 381         desc->ddadr = DDADR_STOP;
 382         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
 383
 384         switch (info->state) {
 385         case STATE_DMA_WRITING:
 386                 desc->dsadr = info->data_buff_phys;
 387                 desc->dtadr = info->mmio_phys + NDDB;
 388                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 389                 break;
 390         case STATE_DMA_READING:
 391                 desc->dtadr = info->data_buff_phys;
 392                 desc->dsadr = info->mmio_phys + NDDB;
 393                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 394                 break;
 395         default:
 396                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 397                                 info->state);
 398                 BUG();
 399         }
 400
 401         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
 402         DDADR(info->data_dma_ch) = info->data_desc_addr;
 403         DCSR(info->data_dma_ch) |= DCSR_RUN;
 404 }
 405
 406 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 407 {
 408         struct pxa3xx_nand_info *info = data;
 409         uint32_t dcsr;
 410
 411         dcsr = DCSR(channel);
 412         DCSR(channel) = dcsr;
 413
 414         if (dcsr & DCSR_BUSERR) {
 415                 info->retcode = ERR_DMABUSERR;
 416         }
 417
 418         info->state = STATE_DMA_DONE;
 419         enable_int(info, NDCR_INT_MASK);
 420         nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 421 }
 422
 423 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 424 {
 425         struct pxa3xx_nand_info *info = devid;
 426         unsigned int status, is_completed = 0;
 427         unsigned int ready, cmd_done;
 428
 429         if (info->cs == 0) {
 430                 ready           = NDSR_FLASH_RDY;
 431                 cmd_done        = NDSR_CS0_CMDD;
 432         } else {
 433                 ready           = NDSR_RDY;
 434                 cmd_done        = NDSR_CS1_CMDD;
 435         }
 436
 437         status = nand_readl(info, NDSR);
 438
 439         if (status & NDSR_DBERR)
 440                 info->retcode = ERR_DBERR;
 441         if (status & NDSR_SBERR)
 442                 info->retcode = ERR_SBERR;
 443         if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 444                 /* whether use dma to transfer data */
 445                 if (info->use_dma) {
 446                         disable_int(info, NDCR_INT_MASK);
 447                         info->state = (status & NDSR_RDDREQ) ?
 448                                       STATE_DMA_READING : STATE_DMA_WRITING;
 449                         start_data_dma(info);
 450                         goto NORMAL_IRQ_EXIT;
 451                 } else {
 452                         info->state = (status & NDSR_RDDREQ) ?
 453                                       STATE_PIO_READING : STATE_PIO_WRITING;
 454                         handle_data_pio(info);
 455                 }
 456         }
 457         if (status & cmd_done) {
 458                 info->state = STATE_CMD_DONE;
 459                 is_completed = 1;
 460         }
 461         if (status & ready) {
 462                 info->is_ready = 1;
 463                 info->state = STATE_READY;
 464         }
 465
 466         if (status & NDSR_WRCMDREQ) {
 467                 nand_writel(info, NDSR, NDSR_WRCMDREQ);
 468                 status &= ~NDSR_WRCMDREQ;
 469                 info->state = STATE_CMD_HANDLE;
 470                 nand_writel(info, NDCB0, info->ndcb0);
 471                 nand_writel(info, NDCB0, info->ndcb1);
 472                 nand_writel(info, NDCB0, info->ndcb2);
 473         }
 474
 475         /* clear NDSR to let the controller exit the IRQ */
 476         nand_writel(info, NDSR, status);
 477         if (is_completed)
 478                 complete(&info->cmd_complete);
 479 NORMAL_IRQ_EXIT:
 480         return IRQ_HANDLED;
 481 }
 482
 483 static inline int is_buf_blank(uint8_t *buf, size_t len)
 484 {
 485         for (; len > 0; len--)
 486                 if (*buf++ != 0xff)
 487                         return 0;
 488         return 1;
 489 }
 490
 491 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
 492                 uint16_t column, int page_addr)
 493 {
 494         uint16_t cmd;
 495         int addr_cycle, exec_cmd;
 496         struct pxa3xx_nand_host *host;
 497         struct mtd_info *mtd;
 498
 499         host = info->host[info->cs];
 500         mtd = host->mtd;
 501         addr_cycle = 0;
 502         exec_cmd = 1;
 503
 504         /* reset data and oob column point to handle data */
 505         info->buf_start         = 0;
 506         info->buf_count         = 0;
 507         info->oob_size          = 0;
 508         info->use_ecc           = 0;
 509         info->is_ready          = 0;
 510         info->retcode           = ERR_NONE;
 511         if (info->cs != 0)
 512                 info->ndcb0 = NDCB0_CSEL;
 513         else
 514                 info->ndcb0 = 0;
 515
 516         switch (command) {
 517         case NAND_CMD_READ0:
 518         case NAND_CMD_PAGEPROG:
 519                 info->use_ecc = 1;
 520         case NAND_CMD_READOOB:
 521                 pxa3xx_set_datasize(info);
 522                 break;
 523         case NAND_CMD_SEQIN:
 524                 exec_cmd = 0;
 525                 break;
 526         default:
 527                 info->ndcb1 = 0;
 528                 info->ndcb2 = 0;
 529                 break;
 530         }
 531
 532         addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
 533                                     + host->col_addr_cycles);
 534
 535         switch (command) {
 536         case NAND_CMD_READOOB:
 537         case NAND_CMD_READ0:
 538                 cmd = host->cmdset->read1;
 539                 if (command == NAND_CMD_READOOB)
 540                         info->buf_start = mtd->writesize + column;
 541                 else
 542                         info->buf_start = column;
 543
 544                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
 545                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 546                                         | addr_cycle
 547                                         | (cmd & NDCB0_CMD1_MASK);
 548                 else
 549                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 550                                         | NDCB0_DBC
 551                                         | addr_cycle
 552                                         | cmd;
 553
 554         case NAND_CMD_SEQIN:
 555                 /* small page addr setting */
 556                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
 557                         info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 558                                         | (column & 0xFF);
 559
 560                         info->ndcb2 = 0;
 561                 } else {
 562                         info->ndcb1 = ((page_addr & 0xFFFF) << 16)
 563                                         | (column & 0xFFFF);
 564
 565                         if (page_addr & 0xFF0000)
 566                                 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
 567                         else
 568                                 info->ndcb2 = 0;
 569                 }
 570
 571                 info->buf_count = mtd->writesize + mtd->oobsize;
 572                 memset(info->data_buff, 0xFF, info->buf_count);
 573
 574                 break;
 575
 576         case NAND_CMD_PAGEPROG:
 577                 if (is_buf_blank(info->data_buff,
 578                                         (mtd->writesize + mtd->oobsize))) {
 579                         exec_cmd = 0;
 580                         break;
 581                 }
 582
 583                 cmd = host->cmdset->program;
 584                 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 585                                 | NDCB0_AUTO_RS
 586                                 | NDCB0_ST_ROW_EN
 587                                 | NDCB0_DBC
 588                                 | cmd
 589                                 | addr_cycle;
 590                 break;
 591
 592         case NAND_CMD_READID:
 593                 cmd = host->cmdset->read_id;
 594                 info->buf_count = host->read_id_bytes;
 595                 info->ndcb0 |= NDCB0_CMD_TYPE(3)
 596                                 | NDCB0_ADDR_CYC(1)
 597                                 | cmd;
 598
 599                 info->data_size = 8;
 600                 break;
 601         case NAND_CMD_STATUS:
 602                 cmd = host->cmdset->read_status;
 603                 info->buf_count = 1;
 604                 info->ndcb0 |= NDCB0_CMD_TYPE(4)
 605                                 | NDCB0_ADDR_CYC(1)
 606                                 | cmd;
 607
 608                 info->data_size = 8;
 609                 break;
 610
 611         case NAND_CMD_ERASE1:
 612                 cmd = host->cmdset->erase;
 613                 info->ndcb0 |= NDCB0_CMD_TYPE(2)
 614                                 | NDCB0_AUTO_RS
 615                                 | NDCB0_ADDR_CYC(3)
 616                                 | NDCB0_DBC
 617                                 | cmd;
 618                 info->ndcb1 = page_addr;
 619                 info->ndcb2 = 0;
 620
 621                 break;
 622         case NAND_CMD_RESET:
 623                 cmd = host->cmdset->reset;
 624                 info->ndcb0 |= NDCB0_CMD_TYPE(5)
 625                                 | cmd;
 626
 627                 break;
 628
 629         case NAND_CMD_ERASE2:
 630                 exec_cmd = 0;
 631                 break;
 632
 633         default:
 634                 exec_cmd = 0;
 635                 dev_err(&info->pdev->dev, "non-supported command %x\n",
 636                                 command);
 637                 break;
 638         }
 639
 640         return exec_cmd;
 641 }
 642
 643 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 644                                 int column, int page_addr)
 645 {
 646         struct pxa3xx_nand_host *host = mtd->priv;
 647         struct pxa3xx_nand_info *info = host->info_data;
 648         int ret, exec_cmd;
 649
 650         /*
 651          * if this is a x16 device ,then convert the input
 652          * "byte" address into a "word" address appropriate
 653          * for indexing a word-oriented device
 654          */
 655         if (host->reg_ndcr & NDCR_DWIDTH_M)
 656                 column /= 2;
 657
 658         /*
 659          * There may be different NAND chip hooked to
 660          * different chip select, so check whether
 661          * chip select has been changed, if yes, reset the timing
 662          */
 663         if (info->cs != host->cs) {
 664                 info->cs = host->cs;
 665                 nand_writel(info, NDTR0CS0, host->ndtr0cs0);
 666                 nand_writel(info, NDTR1CS0, host->ndtr1cs0);
 667         }
 668
 669         info->state = STATE_PREPARED;
 670         exec_cmd = prepare_command_pool(info, command, column, page_addr);
 671         if (exec_cmd) {
 672                 init_completion(&info->cmd_complete);
 673                 pxa3xx_nand_start(info);
 674
 675                 ret = wait_for_completion_timeout(&info->cmd_complete,
 676                                 CHIP_DELAY_TIMEOUT);
 677                 if (!ret) {
 678                         dev_err(&info->pdev->dev, "Wait time out!!!\n");
 679                         /* Stop State Machine for next command cycle */
 680                         pxa3xx_nand_stop(info);
 681                 }
 682         }
 683         info->state = STATE_IDLE;
 684 }
 685
 686 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 687                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 688 {
 689         chip->write_buf(mtd, buf, mtd->writesize);
 690         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 691
 692         return 0;
 693 }
 694
 695 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 696                 struct nand_chip *chip, uint8_t *buf, int oob_required,
 697                 int page)
 698 {
 699         struct pxa3xx_nand_host *host = mtd->priv;
 700         struct pxa3xx_nand_info *info = host->info_data;
 701
 702         chip->read_buf(mtd, buf, mtd->writesize);
 703         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 704
 705         if (info->retcode == ERR_SBERR) {
 706                 switch (info->use_ecc) {
 707                 case 1:
 708                         mtd->ecc_stats.corrected++;
 709                         break;
 710                 case 0:
 711                 default:
 712                         break;
 713                 }
 714         } else if (info->retcode == ERR_DBERR) {
 715                 /*
 716                  * for blank page (all 0xff), HW will calculate its ECC as
 717                  * 0, which is different from the ECC information within
 718                  * OOB, ignore such double bit errors
 719                  */
 720                 if (is_buf_blank(buf, mtd->writesize))
 721                         info->retcode = ERR_NONE;
 722                 else
 723                         mtd->ecc_stats.failed++;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 730 {
 731         struct pxa3xx_nand_host *host = mtd->priv;
 732         struct pxa3xx_nand_info *info = host->info_data;
 733         char retval = 0xFF;
 734
 735         if (info->buf_start < info->buf_count)
 736                 /* Has just send a new command? */
 737                 retval = info->data_buff[info->buf_start++];
 738
 739         return retval;
 740 }
 741
 742 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 743 {
 744         struct pxa3xx_nand_host *host = mtd->priv;
 745         struct pxa3xx_nand_info *info = host->info_data;
 746         u16 retval = 0xFFFF;
 747
 748         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
 749                 retval = *((u16 *)(info->data_buff+info->buf_start));
 750                 info->buf_start += 2;
 751         }
 752         return retval;
 753 }
 754
 755 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 756 {
 757         struct pxa3xx_nand_host *host = mtd->priv;
 758         struct pxa3xx_nand_info *info = host->info_data;
 759         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 760
 761         memcpy(buf, info->data_buff + info->buf_start, real_len);
 762         info->buf_start += real_len;
 763 }
 764
 765 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 766                 const uint8_t *buf, int len)
 767 {
 768         struct pxa3xx_nand_host *host = mtd->priv;
 769         struct pxa3xx_nand_info *info = host->info_data;
 770         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 771
 772         memcpy(info->data_buff + info->buf_start, buf, real_len);
 773         info->buf_start += real_len;
 774 }
 775
 776 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 777 {
 778         return;
 779 }
 780
 781 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 782 {
 783         struct pxa3xx_nand_host *host = mtd->priv;
 784         struct pxa3xx_nand_info *info = host->info_data;
 785
 786         /* pxa3xx_nand_send_command has waited for command complete */
 787         if (this->state == FL_WRITING || this->state == FL_ERASING) {
 788                 if (info->retcode == ERR_NONE)
 789                         return 0;
 790                 else {
 791                         /*
 792                          * any error make it return 0x01 which will tell
 793                          * the caller the erase and write fail
 794                          */
 795                         return 0x01;
 796                 }
 797         }
 798
 799         return 0;
 800 }
 801
 802 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 803                                     const struct pxa3xx_nand_flash *f)
 804 {
 805         struct platform_device *pdev = info->pdev;
 806         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 807         struct pxa3xx_nand_host *host = info->host[info->cs];
 808         uint32_t ndcr = 0x0; /* enable all interrupts */
 809
 810         if (f->page_size != 2048 && f->page_size != 512) {
 811                 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
 812                 return -EINVAL;
 813         }
 814
 815         if (f->flash_width != 16 && f->flash_width != 8) {
 816                 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
 817                 return -EINVAL;
 818         }
 819
 820         /* calculate flash information */
 821         host->cmdset = &default_cmdset;
 822         host->page_size = f->page_size;
 823         host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 824
 825         /* calculate addressing information */
 826         host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
 827
 828         if (f->num_blocks * f->page_per_block > 65536)
 829                 host->row_addr_cycles = 3;
 830         else
 831                 host->row_addr_cycles = 2;
 832
 833         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
 834         ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 835         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 836         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 837         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 838         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
 839
 840         ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 841         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 842
 843         host->reg_ndcr = ndcr;
 844
 845         pxa3xx_nand_set_timing(host, f->timing);
 846         return 0;
 847 }
 848
 849 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 850 {
 851         /*
 852          * We set 0 by hard coding here, for we don't support keep_config
 853          * when there is more than one chip attached to the controller
 854          */
 855         struct pxa3xx_nand_host *host = info->host[0];
 856         uint32_t ndcr = nand_readl(info, NDCR);
 857
 858         if (ndcr & NDCR_PAGE_SZ) {
 859                 host->page_size = 2048;
 860                 host->read_id_bytes = 4;
 861         } else {
 862                 host->page_size = 512;
 863                 host->read_id_bytes = 2;
 864         }
 865
 866         host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 867         host->cmdset = &default_cmdset;
 868
 869         host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 870         host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 871
 872         return 0;
 873 }
 874
 875 /* the maximum possible buffer size for large page with OOB data
 876  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
 877  * data buffer and the DMA descriptor
 878  */
 879 #define MAX_BUFF_SIZE   PAGE_SIZE
 880
 881 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 882 {
 883         struct platform_device *pdev = info->pdev;
 884         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
 885
 886         if (use_dma == 0) {
 887                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 888                 if (info->data_buff == NULL)
 889                         return -ENOMEM;
 890                 return 0;
 891         }
 892
 893         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
 894                                 &info->data_buff_phys, GFP_KERNEL);
 895         if (info->data_buff == NULL) {
 896                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 897                 return -ENOMEM;
 898         }
 899
 900         info->data_desc = (void *)info->data_buff + data_desc_offset;
 901         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 902
 903         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 904                                 pxa3xx_nand_data_dma_irq, info);
 905         if (info->data_dma_ch < 0) {
 906                 dev_err(&pdev->dev, "failed to request data dma\n");
 907                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 908                                 info->data_buff, info->data_buff_phys);
 909                 return info->data_dma_ch;
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 916 {
 917         struct mtd_info *mtd;
 918         int ret;
 919         mtd = info->host[info->cs]->mtd;
 920         /* use the common timing to make a try */
 921         ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
 922         if (ret)
 923                 return ret;
 924
 925         pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 926         if (info->is_ready)
 927                 return 0;
 928
 929         return -ENODEV;
 930 }
 931
 932 static int pxa3xx_nand_scan(struct mtd_info *mtd)
 933 {
 934         struct pxa3xx_nand_host *host = mtd->priv;
 935         struct pxa3xx_nand_info *info = host->info_data;
 936         struct platform_device *pdev = info->pdev;
 937         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 938         struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
 939         const struct pxa3xx_nand_flash *f = NULL;
 940         struct nand_chip *chip = mtd->priv;
 941         uint32_t id = -1;
 942         uint64_t chipsize;
 943         int i, ret, num;
 944
 945         if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
 946                 goto KEEP_CONFIG;
 947
 948         ret = pxa3xx_nand_sensing(info);
 949         if (ret) {
 950                 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
 951                          info->cs);
 952
 953                 return ret;
 954         }
 955
 956         chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
 957         id = *((uint16_t *)(info->data_buff));
 958         if (id != 0)
 959                 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
 960         else {
 961                 dev_warn(&info->pdev->dev,
 962                          "Read out ID 0, potential timing set wrong!!\n");
 963
 964                 return -EINVAL;
 965         }
 966
 967         num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
 968         for (i = 0; i < num; i++) {
 969                 if (i < pdata->num_flash)
 970                         f = pdata->flash + i;
 971                 else
 972                         f = &builtin_flash_types[i - pdata->num_flash + 1];
 973
 974                 /* find the chip in default list */
 975                 if (f->chip_id == id)
 976                         break;
 977         }
 978
 979         if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
 980                 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
 981
 982                 return -EINVAL;
 983         }
 984
 985         ret = pxa3xx_nand_config_flash(info, f);
 986         if (ret) {
 987                 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
 988                 return ret;
 989         }
 990
 991         pxa3xx_flash_ids[0].name = f->name;
 992         pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
 993         pxa3xx_flash_ids[0].pagesize = f->page_size;
 994         chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
 995         pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
 996         pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
 997         if (f->flash_width == 16)
 998                 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
 999         pxa3xx_flash_ids[1].name = NULL;
1000         def = pxa3xx_flash_ids;
1001 KEEP_CONFIG:
1002         chip->ecc.mode = NAND_ECC_HW;
1003         chip->ecc.size = host->page_size;
1004         chip->ecc.strength = 1;
1005
1006         if (host->reg_ndcr & NDCR_DWIDTH_M)
1007                 chip->options |= NAND_BUSWIDTH_16;
1008
1009         if (nand_scan_ident(mtd, 1, def))
1010                 return -ENODEV;
1011         /* calculate addressing information */
1012         if (mtd->writesize >= 2048)
1013                 host->col_addr_cycles = 2;
1014         else
1015                 host->col_addr_cycles = 1;
1016
1017         info->oob_buff = info->data_buff + mtd->writesize;
1018         if ((mtd->size >> chip->page_shift) > 65536)
1019                 host->row_addr_cycles = 3;
1020         else
1021                 host->row_addr_cycles = 2;
1022
1023         mtd->name = mtd_names[0];
1024         return nand_scan_tail(mtd);
1025 }
1026
1027 static int alloc_nand_resource(struct platform_device *pdev)
1028 {
1029         struct pxa3xx_nand_platform_data *pdata;
1030         struct pxa3xx_nand_info *info;
1031         struct pxa3xx_nand_host *host;
1032         struct nand_chip *chip = NULL;
1033         struct mtd_info *mtd;
1034         struct resource *r;
1035         int ret, irq, cs;
1036
1037         pdata = pdev->dev.platform_data;
1038         info = kzalloc(sizeof(*info) + (sizeof(*mtd) +
1039                        sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1040         if (!info) {
1041                 dev_err(&pdev->dev, "failed to allocate memory\n");
1042                 return -ENOMEM;
1043         }
1044
1045         info->pdev = pdev;
1046         for (cs = 0; cs < pdata->num_cs; cs++) {
1047                 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1048                       (sizeof(*mtd) + sizeof(*host)) * cs);
1049                 chip = (struct nand_chip *)(&mtd[1]);
1050                 host = (struct pxa3xx_nand_host *)chip;
1051                 info->host[cs] = host;
1052                 host->mtd = mtd;
1053                 host->cs = cs;
1054                 host->info_data = info;
1055                 mtd->priv = host;
1056                 mtd->owner = THIS_MODULE;
1057
1058                 chip->ecc.read_page     = pxa3xx_nand_read_page_hwecc;
1059                 chip->ecc.write_page    = pxa3xx_nand_write_page_hwecc;
1060                 chip->controller        = &info->controller;
1061                 chip->waitfunc          = pxa3xx_nand_waitfunc;
1062                 chip->select_chip       = pxa3xx_nand_select_chip;
1063                 chip->cmdfunc           = pxa3xx_nand_cmdfunc;
1064                 chip->read_word         = pxa3xx_nand_read_word;
1065                 chip->read_byte         = pxa3xx_nand_read_byte;
1066                 chip->read_buf          = pxa3xx_nand_read_buf;
1067                 chip->write_buf         = pxa3xx_nand_write_buf;
1068         }
1069
1070         spin_lock_init(&chip->controller->lock);
1071         init_waitqueue_head(&chip->controller->wq);
1072         info->clk = clk_get(&pdev->dev, NULL);
1073         if (IS_ERR(info->clk)) {
1074                 dev_err(&pdev->dev, "failed to get nand clock\n");
1075                 ret = PTR_ERR(info->clk);
1076                 goto fail_free_mtd;
1077         }
1078         clk_enable(info->clk);
1079
1080         /*
1081          * This is a dirty hack to make this driver work from devicetree
1082          * bindings. It can be removed once we have a prober DMA controller
1083          * framework for DT.
1084          */
1085         if (pdev->dev.of_node && cpu_is_pxa3xx()) {
1086                 info->drcmr_dat = 97;
1087                 info->drcmr_cmd = 99;
1088         } else {
1089                 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1090                 if (r == NULL) {
1091                         dev_err(&pdev->dev, "no resource defined for data DMA\n");
1092                         ret = -ENXIO;
1093                         goto fail_put_clk;
1094                 }
1095                 info->drcmr_dat = r->start;
1096
1097                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1098                 if (r == NULL) {
1099                         dev_err(&pdev->dev, "no resource defined for command DMA\n");
1100                         ret = -ENXIO;
1101                         goto fail_put_clk;
1102                 }
1103                 info->drcmr_cmd = r->start;
1104         }
1105
1106         irq = platform_get_irq(pdev, 0);
1107         if (irq < 0) {
1108                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1109                 ret = -ENXIO;
1110                 goto fail_put_clk;
1111         }
1112
1113         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1114         if (r == NULL) {
1115                 dev_err(&pdev->dev, "no IO memory resource defined\n");
1116                 ret = -ENODEV;
1117                 goto fail_put_clk;
1118         }
1119
1120         r = request_mem_region(r->start, resource_size(r), pdev->name);
1121         if (r == NULL) {
1122                 dev_err(&pdev->dev, "failed to request memory resource\n");
1123                 ret = -EBUSY;
1124                 goto fail_put_clk;
1125         }
1126
1127         info->mmio_base = ioremap(r->start, resource_size(r));
1128         if (info->mmio_base == NULL) {
1129                 dev_err(&pdev->dev, "ioremap() failed\n");
1130                 ret = -ENODEV;
1131                 goto fail_free_res;
1132         }
1133         info->mmio_phys = r->start;
1134
1135         ret = pxa3xx_nand_init_buff(info);
1136         if (ret)
1137                 goto fail_free_io;
1138
1139         /* initialize all interrupts to be disabled */
1140         disable_int(info, NDSR_MASK);
1141
1142         ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1143                           pdev->name, info);
1144         if (ret < 0) {
1145                 dev_err(&pdev->dev, "failed to request IRQ\n");
1146                 goto fail_free_buf;
1147         }
1148
1149         platform_set_drvdata(pdev, info);
1150
1151         return 0;
1152
1153 fail_free_buf:
1154         free_irq(irq, info);
1155         if (use_dma) {
1156                 pxa_free_dma(info->data_dma_ch);
1157                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
1158                         info->data_buff, info->data_buff_phys);
1159         } else
1160                 kfree(info->data_buff);
1161 fail_free_io:
1162         iounmap(info->mmio_base);
1163 fail_free_res:
1164         release_mem_region(r->start, resource_size(r));
1165 fail_put_clk:
1166         clk_disable(info->clk);
1167         clk_put(info->clk);
1168 fail_free_mtd:
1169         kfree(info);
1170         return ret;
1171 }
1172
1173 static int pxa3xx_nand_remove(struct platform_device *pdev)
1174 {
1175         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1176         struct pxa3xx_nand_platform_data *pdata;
1177         struct resource *r;
1178         int irq, cs;
1179
1180         if (!info)
1181                 return 0;
1182
1183         pdata = pdev->dev.platform_data;
1184         platform_set_drvdata(pdev, NULL);
1185
1186         irq = platform_get_irq(pdev, 0);
1187         if (irq >= 0)
1188                 free_irq(irq, info);
1189         if (use_dma) {
1190                 pxa_free_dma(info->data_dma_ch);
1191                 dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE,
1192                                 info->data_buff, info->data_buff_phys);
1193         } else
1194                 kfree(info->data_buff);
1195
1196         iounmap(info->mmio_base);
1197         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1198         release_mem_region(r->start, resource_size(r));
1199
1200         clk_disable(info->clk);
1201         clk_put(info->clk);
1202
1203         for (cs = 0; cs < pdata->num_cs; cs++)
1204                 nand_release(info->host[cs]->mtd);
1205         kfree(info);
1206         return 0;
1207 }
1208
1209 #ifdef CONFIG_OF
1210 static struct of_device_id pxa3xx_nand_dt_ids[] = {
1211         { .compatible = "marvell,pxa3xx-nand" },
1212         {}
1213 };
1214 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1215
1216 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1217 {
1218         struct pxa3xx_nand_platform_data *pdata;
1219         struct device_node *np = pdev->dev.of_node;
1220         const struct of_device_id *of_id =
1221                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1222
1223         if (!of_id)
1224                 return 0;
1225
1226         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1227         if (!pdata)
1228                 return -ENOMEM;
1229
1230         if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1231                 pdata->enable_arbiter = 1;
1232         if (of_get_property(np, "marvell,nand-keep-config", NULL))
1233                 pdata->keep_config = 1;
1234         of_property_read_u32(np, "num-cs", &pdata->num_cs);
1235
1236         pdev->dev.platform_data = pdata;
1237
1238         return 0;
1239 }
1240 #else
1241 static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1242 {
1243         return 0;
1244 }
1245 #endif
1246
1247 static int pxa3xx_nand_probe(struct platform_device *pdev)
1248 {
1249         struct pxa3xx_nand_platform_data *pdata;
1250         struct mtd_part_parser_data ppdata = {};
1251         struct pxa3xx_nand_info *info;
1252         int ret, cs, probe_success;
1253
1254         ret = pxa3xx_nand_probe_dt(pdev);
1255         if (ret)
1256                 return ret;
1257
1258         pdata = pdev->dev.platform_data;
1259         if (!pdata) {
1260                 dev_err(&pdev->dev, "no platform data defined\n");
1261                 return -ENODEV;
1262         }
1263
1264         ret = alloc_nand_resource(pdev);
1265         if (ret) {
1266                 dev_err(&pdev->dev, "alloc nand resource failed\n");
1267                 return ret;
1268         }
1269
1270         info = platform_get_drvdata(pdev);
1271         probe_success = 0;
1272         for (cs = 0; cs < pdata->num_cs; cs++) {
1273                 info->cs = cs;
1274                 ret = pxa3xx_nand_scan(info->host[cs]->mtd);
1275                 if (ret) {
1276                         dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1277                                 cs);
1278                         continue;
1279                 }
1280
1281                 ppdata.of_node = pdev->dev.of_node;
1282                 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1283                                                 &ppdata, pdata->parts[cs],
1284                                                 pdata->nr_parts[cs]);
1285                 if (!ret)
1286                         probe_success = 1;
1287         }
1288
1289         if (!probe_success) {
1290                 pxa3xx_nand_remove(pdev);
1291                 return -ENODEV;
1292         }
1293
1294         return 0;
1295 }
1296
1297 #ifdef CONFIG_PM
1298 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1299 {
1300         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1301         struct pxa3xx_nand_platform_data *pdata;
1302         struct mtd_info *mtd;
1303         int cs;
1304
1305         pdata = pdev->dev.platform_data;
1306         if (info->state) {
1307                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1308                 return -EAGAIN;
1309         }
1310
1311         for (cs = 0; cs < pdata->num_cs; cs++) {
1312                 mtd = info->host[cs]->mtd;
1313                 mtd_suspend(mtd);
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int pxa3xx_nand_resume(struct platform_device *pdev)
1320 {
1321         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1322         struct pxa3xx_nand_platform_data *pdata;
1323         struct mtd_info *mtd;
1324         int cs;
1325
1326         pdata = pdev->dev.platform_data;
1327         /* We don't want to handle interrupt without calling mtd routine */
1328         disable_int(info, NDCR_INT_MASK);
1329
1330         /*
1331          * Directly set the chip select to a invalid value,
1332          * then the driver would reset the timing according
1333          * to current chip select at the beginning of cmdfunc
1334          */
1335         info->cs = 0xff;
1336
1337         /*
1338          * As the spec says, the NDSR would be updated to 0x1800 when
1339          * doing the nand_clk disable/enable.
1340          * To prevent it damaging state machine of the driver, clear
1341          * all status before resume
1342          */
1343         nand_writel(info, NDSR, NDSR_MASK);
1344         for (cs = 0; cs < pdata->num_cs; cs++) {
1345                 mtd = info->host[cs]->mtd;
1346                 mtd_resume(mtd);
1347         }
1348
1349         return 0;
1350 }
1351 #else
1352 #define pxa3xx_nand_suspend     NULL
1353 #define pxa3xx_nand_resume      NULL
1354 #endif
1355
1356 static struct platform_driver pxa3xx_nand_driver = {
1357         .driver = {
1358                 .name   = "pxa3xx-nand",
1359                 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1360         },
1361         .probe          = pxa3xx_nand_probe,
1362         .remove         = pxa3xx_nand_remove,
1363         .suspend        = pxa3xx_nand_suspend,
1364         .resume         = pxa3xx_nand_resume,
1365 };
1366
1367 module_platform_driver(pxa3xx_nand_driver);
1368
1369 MODULE_LICENSE("GPL");
1370 MODULE_DESCRIPTION("PXA3xx NAND controller driver");