2 * Driver for Cadence QSPI Controller
4 * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/interrupt.h>
25 #include <linux/jiffies.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mtd/spi-nor.h>
31 #include <linux/of_device.h>
33 #include <linux/platform_device.h>
34 #include <linux/sched.h>
35 #include <linux/spi/spi.h>
36 #include <linux/timer.h>
38 #define CQSPI_NAME "cadence-qspi"
39 #define CQSPI_MAX_CHIPSELECT 16
43 struct cqspi_flash_pdata {
45 struct cqspi_st *cqspi;
60 struct platform_device *pdev;
66 void __iomem *ahb_base;
67 struct completion transfer_complete;
68 struct mutex bus_mutex;
71 int current_page_size;
72 int current_erase_size;
73 int current_addr_width;
74 unsigned long master_ref_clk_hz;
79 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
82 /* Operation timeout value */
83 #define CQSPI_TIMEOUT_MS 500
84 #define CQSPI_READ_TIMEOUT_MS 10
86 /* Instruction type */
87 #define CQSPI_INST_TYPE_SINGLE 0
88 #define CQSPI_INST_TYPE_DUAL 1
89 #define CQSPI_INST_TYPE_QUAD 2
91 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
92 #define CQSPI_DUMMY_BYTES_MAX 4
93 #define CQSPI_DUMMY_CLKS_MAX 31
95 #define CQSPI_STIG_DATA_LEN_MAX 8
98 #define CQSPI_REG_CONFIG 0x00
99 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
100 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
101 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
102 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
103 #define CQSPI_REG_CONFIG_BAUD_LSB 19
104 #define CQSPI_REG_CONFIG_IDLE_LSB 31
105 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
106 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
108 #define CQSPI_REG_RD_INSTR 0x04
109 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
110 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
111 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
112 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
113 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
114 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
115 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
116 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
117 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
118 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
120 #define CQSPI_REG_WR_INSTR 0x08
121 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
122 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
123 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
125 #define CQSPI_REG_DELAY 0x0C
126 #define CQSPI_REG_DELAY_TSLCH_LSB 0
127 #define CQSPI_REG_DELAY_TCHSH_LSB 8
128 #define CQSPI_REG_DELAY_TSD2D_LSB 16
129 #define CQSPI_REG_DELAY_TSHSL_LSB 24
130 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
131 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
132 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
133 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
135 #define CQSPI_REG_READCAPTURE 0x10
136 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
137 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
138 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
140 #define CQSPI_REG_SIZE 0x14
141 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
142 #define CQSPI_REG_SIZE_PAGE_LSB 4
143 #define CQSPI_REG_SIZE_BLOCK_LSB 16
144 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
145 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
146 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
148 #define CQSPI_REG_SRAMPARTITION 0x18
149 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
151 #define CQSPI_REG_DMA 0x20
152 #define CQSPI_REG_DMA_SINGLE_LSB 0
153 #define CQSPI_REG_DMA_BURST_LSB 8
154 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
155 #define CQSPI_REG_DMA_BURST_MASK 0xFF
157 #define CQSPI_REG_REMAP 0x24
158 #define CQSPI_REG_MODE_BIT 0x28
160 #define CQSPI_REG_SDRAMLEVEL 0x2C
161 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
162 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
163 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
164 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
166 #define CQSPI_REG_IRQSTATUS 0x40
167 #define CQSPI_REG_IRQMASK 0x44
169 #define CQSPI_REG_INDIRECTRD 0x60
170 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
171 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
172 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
174 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
175 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
176 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
178 #define CQSPI_REG_CMDCTRL 0x90
179 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
180 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
181 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
182 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
183 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
184 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
185 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
186 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
187 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
188 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
189 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
190 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
192 #define CQSPI_REG_INDIRECTWR 0x70
193 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
194 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
195 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
197 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
198 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
199 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
201 #define CQSPI_REG_CMDADDRESS 0x94
202 #define CQSPI_REG_CMDREADDATALOWER 0xA0
203 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
204 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
205 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
207 /* Interrupt status bits */
208 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
209 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
210 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
211 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
212 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
213 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
214 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
215 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
217 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
218 CQSPI_REG_IRQ_IND_SRAM_FULL | \
219 CQSPI_REG_IRQ_IND_COMP)
221 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
222 CQSPI_REG_IRQ_WATERMARK | \
223 CQSPI_REG_IRQ_UNDERFLOW)
225 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
227 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
229 unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
241 if (time_after(jiffies, end))
246 static bool cqspi_is_idle(struct cqspi_st *cqspi)
248 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
250 return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
253 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
255 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
257 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
258 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
261 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
263 struct cqspi_st *cqspi = dev;
264 unsigned int irq_status;
266 /* Read interrupt status */
267 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
269 /* Clear interrupt */
270 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
272 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
275 complete(&cqspi->transfer_complete);
280 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
282 struct cqspi_flash_pdata *f_pdata = nor->priv;
285 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
286 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
287 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
292 static int cqspi_wait_idle(struct cqspi_st *cqspi)
294 const unsigned int poll_idle_retry = 3;
295 unsigned int count = 0;
296 unsigned long timeout;
298 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
301 * Read few times in succession to ensure the controller
302 * is indeed idle, that is, the bit does not transition
305 if (cqspi_is_idle(cqspi))
310 if (count >= poll_idle_retry)
313 if (time_after(jiffies, timeout)) {
314 /* Timeout, in busy mode. */
315 dev_err(&cqspi->pdev->dev,
316 "QSPI is still busy after %dms timeout.\n",
325 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
327 void __iomem *reg_base = cqspi->iobase;
330 /* Write the CMDCTRL without start execution. */
331 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
333 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
334 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
336 /* Polling for completion. */
337 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
338 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
340 dev_err(&cqspi->pdev->dev,
341 "Flash command execution timed out.\n");
345 /* Polling QSPI idle status. */
346 return cqspi_wait_idle(cqspi);
349 static int cqspi_command_read(struct spi_nor *nor,
350 const u8 *txbuf, const unsigned n_tx,
351 u8 *rxbuf, const unsigned n_rx)
353 struct cqspi_flash_pdata *f_pdata = nor->priv;
354 struct cqspi_st *cqspi = f_pdata->cqspi;
355 void __iomem *reg_base = cqspi->iobase;
358 unsigned int read_len;
361 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
362 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
367 reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
369 rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
370 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
372 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
374 /* 0 means 1 byte. */
375 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
376 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
377 status = cqspi_exec_flash_cmd(cqspi, reg);
381 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
383 /* Put the read value into rx_buf */
384 read_len = (n_rx > 4) ? 4 : n_rx;
385 memcpy(rxbuf, ®, read_len);
389 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
391 read_len = n_rx - read_len;
392 memcpy(rxbuf, ®, read_len);
398 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
399 const u8 *txbuf, const unsigned n_tx)
401 struct cqspi_flash_pdata *f_pdata = nor->priv;
402 struct cqspi_st *cqspi = f_pdata->cqspi;
403 void __iomem *reg_base = cqspi->iobase;
408 if (n_tx > 4 || (n_tx && !txbuf)) {
410 "Invalid input argument, cmdlen %d txbuf 0x%p\n",
415 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
417 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
418 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
419 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
421 memcpy(&data, txbuf, n_tx);
422 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
425 ret = cqspi_exec_flash_cmd(cqspi, reg);
429 static int cqspi_command_write_addr(struct spi_nor *nor,
430 const u8 opcode, const unsigned int addr)
432 struct cqspi_flash_pdata *f_pdata = nor->priv;
433 struct cqspi_st *cqspi = f_pdata->cqspi;
434 void __iomem *reg_base = cqspi->iobase;
437 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
438 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
439 reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
440 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
442 writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
444 return cqspi_exec_flash_cmd(cqspi, reg);
447 static int cqspi_indirect_read_setup(struct spi_nor *nor,
448 const unsigned int from_addr)
450 struct cqspi_flash_pdata *f_pdata = nor->priv;
451 struct cqspi_st *cqspi = f_pdata->cqspi;
452 void __iomem *reg_base = cqspi->iobase;
453 unsigned int dummy_clk = 0;
456 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
458 reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
459 reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
461 /* Setup dummy clock cycles */
462 dummy_clk = nor->read_dummy;
463 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
464 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
467 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
468 /* Set mode bits high to ensure chip doesn't enter XIP */
469 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
471 /* Need to subtract the mode byte (8 clocks). */
472 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
476 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
477 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
480 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
482 /* Set address width */
483 reg = readl(reg_base + CQSPI_REG_SIZE);
484 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
485 reg |= (nor->addr_width - 1);
486 writel(reg, reg_base + CQSPI_REG_SIZE);
490 static int cqspi_indirect_read_execute(struct spi_nor *nor,
491 u8 *rxbuf, const unsigned n_rx)
493 struct cqspi_flash_pdata *f_pdata = nor->priv;
494 struct cqspi_st *cqspi = f_pdata->cqspi;
495 void __iomem *reg_base = cqspi->iobase;
496 void __iomem *ahb_base = cqspi->ahb_base;
497 unsigned int remaining = n_rx;
498 unsigned int bytes_to_read = 0;
501 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
503 /* Clear all interrupts. */
504 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
506 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
508 reinit_completion(&cqspi->transfer_complete);
509 writel(CQSPI_REG_INDIRECTRD_START_MASK,
510 reg_base + CQSPI_REG_INDIRECTRD);
512 while (remaining > 0) {
513 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
515 (CQSPI_READ_TIMEOUT_MS));
517 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
519 if (!ret && bytes_to_read == 0) {
520 dev_err(nor->dev, "Indirect read timeout, no bytes\n");
525 while (bytes_to_read != 0) {
526 bytes_to_read *= cqspi->fifo_width;
527 bytes_to_read = bytes_to_read > remaining ?
528 remaining : bytes_to_read;
529 ioread32_rep(ahb_base, rxbuf,
530 DIV_ROUND_UP(bytes_to_read, 4));
531 rxbuf += bytes_to_read;
532 remaining -= bytes_to_read;
533 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
537 reinit_completion(&cqspi->transfer_complete);
540 /* Check indirect done status */
541 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
542 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
545 "Indirect read completion error (%i)\n", ret);
549 /* Disable interrupt */
550 writel(0, reg_base + CQSPI_REG_IRQMASK);
552 /* Clear indirect completion status */
553 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
558 /* Disable interrupt */
559 writel(0, reg_base + CQSPI_REG_IRQMASK);
561 /* Cancel the indirect read */
562 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
563 reg_base + CQSPI_REG_INDIRECTRD);
567 static int cqspi_indirect_write_setup(struct spi_nor *nor,
568 const unsigned int to_addr)
571 struct cqspi_flash_pdata *f_pdata = nor->priv;
572 struct cqspi_st *cqspi = f_pdata->cqspi;
573 void __iomem *reg_base = cqspi->iobase;
576 reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
577 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
578 reg = cqspi_calc_rdreg(nor, nor->program_opcode);
579 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
581 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
583 reg = readl(reg_base + CQSPI_REG_SIZE);
584 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
585 reg |= (nor->addr_width - 1);
586 writel(reg, reg_base + CQSPI_REG_SIZE);
590 static int cqspi_indirect_write_execute(struct spi_nor *nor,
591 const u8 *txbuf, const unsigned n_tx)
593 const unsigned int page_size = nor->page_size;
594 struct cqspi_flash_pdata *f_pdata = nor->priv;
595 struct cqspi_st *cqspi = f_pdata->cqspi;
596 void __iomem *reg_base = cqspi->iobase;
597 unsigned int remaining = n_tx;
598 unsigned int write_bytes;
601 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
603 /* Clear all interrupts. */
604 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
606 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
608 reinit_completion(&cqspi->transfer_complete);
609 writel(CQSPI_REG_INDIRECTWR_START_MASK,
610 reg_base + CQSPI_REG_INDIRECTWR);
612 while (remaining > 0) {
613 write_bytes = remaining > page_size ? page_size : remaining;
614 iowrite32_rep(cqspi->ahb_base, txbuf,
615 DIV_ROUND_UP(write_bytes, 4));
617 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
621 dev_err(nor->dev, "Indirect write timeout\n");
626 txbuf += write_bytes;
627 remaining -= write_bytes;
630 reinit_completion(&cqspi->transfer_complete);
633 /* Check indirect done status */
634 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
635 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
638 "Indirect write completion error (%i)\n", ret);
642 /* Disable interrupt. */
643 writel(0, reg_base + CQSPI_REG_IRQMASK);
645 /* Clear indirect completion status */
646 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
648 cqspi_wait_idle(cqspi);
653 /* Disable interrupt. */
654 writel(0, reg_base + CQSPI_REG_IRQMASK);
656 /* Cancel the indirect write */
657 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
658 reg_base + CQSPI_REG_INDIRECTWR);
662 static void cqspi_chipselect(struct spi_nor *nor)
664 struct cqspi_flash_pdata *f_pdata = nor->priv;
665 struct cqspi_st *cqspi = f_pdata->cqspi;
666 void __iomem *reg_base = cqspi->iobase;
667 unsigned int chip_select = f_pdata->cs;
670 reg = readl(reg_base + CQSPI_REG_CONFIG);
671 if (cqspi->is_decoded_cs) {
672 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
674 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
676 /* Convert CS if without decoder.
682 chip_select = 0xF & ~(1 << chip_select);
685 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
686 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
687 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
688 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
689 writel(reg, reg_base + CQSPI_REG_CONFIG);
692 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
694 struct cqspi_flash_pdata *f_pdata = nor->priv;
695 struct cqspi_st *cqspi = f_pdata->cqspi;
696 void __iomem *iobase = cqspi->iobase;
699 /* configure page size and block size. */
700 reg = readl(iobase + CQSPI_REG_SIZE);
701 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
702 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
703 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
704 reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
705 reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
706 reg |= (nor->addr_width - 1);
707 writel(reg, iobase + CQSPI_REG_SIZE);
709 /* configure the chip select */
710 cqspi_chipselect(nor);
712 /* Store the new configuration of the controller */
713 cqspi->current_page_size = nor->page_size;
714 cqspi->current_erase_size = nor->mtd.erasesize;
715 cqspi->current_addr_width = nor->addr_width;
718 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
719 const unsigned int ns_val)
723 ticks = ref_clk_hz / 1000; /* kHz */
724 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
729 static void cqspi_delay(struct spi_nor *nor)
731 struct cqspi_flash_pdata *f_pdata = nor->priv;
732 struct cqspi_st *cqspi = f_pdata->cqspi;
733 void __iomem *iobase = cqspi->iobase;
734 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
735 unsigned int tshsl, tchsh, tslch, tsd2d;
739 /* calculate the number of ref ticks for one sclk tick */
740 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
742 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
743 /* this particular value must be at least one sclk */
747 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
748 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
749 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
751 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
752 << CQSPI_REG_DELAY_TSHSL_LSB;
753 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
754 << CQSPI_REG_DELAY_TCHSH_LSB;
755 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
756 << CQSPI_REG_DELAY_TSLCH_LSB;
757 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
758 << CQSPI_REG_DELAY_TSD2D_LSB;
759 writel(reg, iobase + CQSPI_REG_DELAY);
762 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
764 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
765 void __iomem *reg_base = cqspi->iobase;
768 /* Recalculate the baudrate divisor based on QSPI specification. */
769 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
771 reg = readl(reg_base + CQSPI_REG_CONFIG);
772 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
773 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
774 writel(reg, reg_base + CQSPI_REG_CONFIG);
777 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
778 const unsigned int bypass,
779 const unsigned int delay)
781 void __iomem *reg_base = cqspi->iobase;
784 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
787 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
789 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
791 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
792 << CQSPI_REG_READCAPTURE_DELAY_LSB);
794 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
795 << CQSPI_REG_READCAPTURE_DELAY_LSB;
797 writel(reg, reg_base + CQSPI_REG_READCAPTURE);
800 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
802 void __iomem *reg_base = cqspi->iobase;
805 reg = readl(reg_base + CQSPI_REG_CONFIG);
808 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
810 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
812 writel(reg, reg_base + CQSPI_REG_CONFIG);
815 static void cqspi_configure(struct spi_nor *nor)
817 struct cqspi_flash_pdata *f_pdata = nor->priv;
818 struct cqspi_st *cqspi = f_pdata->cqspi;
819 const unsigned int sclk = f_pdata->clk_rate;
820 int switch_cs = (cqspi->current_cs != f_pdata->cs);
821 int switch_ck = (cqspi->sclk != sclk);
823 if ((cqspi->current_page_size != nor->page_size) ||
824 (cqspi->current_erase_size != nor->mtd.erasesize) ||
825 (cqspi->current_addr_width != nor->addr_width))
828 if (switch_cs || switch_ck)
829 cqspi_controller_enable(cqspi, 0);
831 /* Switch chip select. */
833 cqspi->current_cs = f_pdata->cs;
834 cqspi_configure_cs_and_sizes(nor);
837 /* Setup baudrate divisor and delays */
840 cqspi_config_baudrate_div(cqspi);
842 cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
845 if (switch_cs || switch_ck)
846 cqspi_controller_enable(cqspi, 1);
849 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
851 struct cqspi_flash_pdata *f_pdata = nor->priv;
853 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
854 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
855 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
858 switch (nor->read_proto) {
859 case SNOR_PROTO_1_1_1:
860 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
862 case SNOR_PROTO_1_1_2:
863 f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
865 case SNOR_PROTO_1_1_4:
866 f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
873 cqspi_configure(nor);
878 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
879 size_t len, const u_char *buf)
883 ret = cqspi_set_protocol(nor, 0);
887 ret = cqspi_indirect_write_setup(nor, to);
891 ret = cqspi_indirect_write_execute(nor, buf, len);
898 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
899 size_t len, u_char *buf)
903 ret = cqspi_set_protocol(nor, 1);
907 ret = cqspi_indirect_read_setup(nor, from);
911 ret = cqspi_indirect_read_execute(nor, buf, len);
918 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
922 ret = cqspi_set_protocol(nor, 0);
926 /* Send write enable, then erase commands. */
927 ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
931 /* Set up command buffer. */
932 ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
939 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
941 struct cqspi_flash_pdata *f_pdata = nor->priv;
942 struct cqspi_st *cqspi = f_pdata->cqspi;
944 mutex_lock(&cqspi->bus_mutex);
949 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
951 struct cqspi_flash_pdata *f_pdata = nor->priv;
952 struct cqspi_st *cqspi = f_pdata->cqspi;
954 mutex_unlock(&cqspi->bus_mutex);
957 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
961 ret = cqspi_set_protocol(nor, 0);
963 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
968 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
972 ret = cqspi_set_protocol(nor, 0);
974 ret = cqspi_command_write(nor, opcode, buf, len);
979 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
980 struct cqspi_flash_pdata *f_pdata,
981 struct device_node *np)
983 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
984 dev_err(&pdev->dev, "couldn't determine read-delay\n");
988 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
989 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
993 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
994 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
998 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
999 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1003 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1004 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1008 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1009 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1016 static int cqspi_of_get_pdata(struct platform_device *pdev)
1018 struct device_node *np = pdev->dev.of_node;
1019 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1021 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1023 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1024 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1028 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1029 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1033 if (of_property_read_u32(np, "cdns,trigger-address",
1034 &cqspi->trigger_address)) {
1035 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1042 static void cqspi_controller_init(struct cqspi_st *cqspi)
1044 cqspi_controller_enable(cqspi, 0);
1046 /* Configure the remap address register, no remap */
1047 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1049 /* Disable all interrupts. */
1050 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1052 /* Configure the SRAM split to 1:1 . */
1053 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1055 /* Load indirect trigger address. */
1056 writel(cqspi->trigger_address,
1057 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1059 /* Program read watermark -- 1/2 of the FIFO. */
1060 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1061 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1062 /* Program write watermark -- 1/8 of the FIFO. */
1063 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1064 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1066 cqspi_controller_enable(cqspi, 1);
1069 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1071 const struct spi_nor_hwcaps hwcaps = {
1072 .mask = SNOR_HWCAPS_READ |
1073 SNOR_HWCAPS_READ_FAST |
1074 SNOR_HWCAPS_READ_1_1_2 |
1075 SNOR_HWCAPS_READ_1_1_4 |
1078 struct platform_device *pdev = cqspi->pdev;
1079 struct device *dev = &pdev->dev;
1080 struct cqspi_flash_pdata *f_pdata;
1081 struct spi_nor *nor;
1082 struct mtd_info *mtd;
1086 /* Get flash device data */
1087 for_each_available_child_of_node(dev->of_node, np) {
1088 ret = of_property_read_u32(np, "reg", &cs);
1090 dev_err(dev, "Couldn't determine chip select.\n");
1094 if (cs >= CQSPI_MAX_CHIPSELECT) {
1096 dev_err(dev, "Chip select %d out of range.\n", cs);
1100 f_pdata = &cqspi->f_pdata[cs];
1101 f_pdata->cqspi = cqspi;
1104 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1108 nor = &f_pdata->nor;
1114 spi_nor_set_flash_node(nor, np);
1115 nor->priv = f_pdata;
1117 nor->read_reg = cqspi_read_reg;
1118 nor->write_reg = cqspi_write_reg;
1119 nor->read = cqspi_read;
1120 nor->write = cqspi_write;
1121 nor->erase = cqspi_erase;
1122 nor->prepare = cqspi_prep;
1123 nor->unprepare = cqspi_unprep;
1125 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1132 ret = spi_nor_scan(nor, NULL, &hwcaps);
1136 ret = mtd_device_register(mtd, NULL, 0);
1140 f_pdata->registered = true;
1146 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1147 if (cqspi->f_pdata[i].registered)
1148 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1152 static int cqspi_probe(struct platform_device *pdev)
1154 struct device_node *np = pdev->dev.of_node;
1155 struct device *dev = &pdev->dev;
1156 struct cqspi_st *cqspi;
1157 struct resource *res;
1158 struct resource *res_ahb;
1162 cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1166 mutex_init(&cqspi->bus_mutex);
1168 platform_set_drvdata(pdev, cqspi);
1170 /* Obtain configuration from OF. */
1171 ret = cqspi_of_get_pdata(pdev);
1173 dev_err(dev, "Cannot get mandatory OF data.\n");
1177 /* Obtain QSPI clock. */
1178 cqspi->clk = devm_clk_get(dev, NULL);
1179 if (IS_ERR(cqspi->clk)) {
1180 dev_err(dev, "Cannot claim QSPI clock.\n");
1181 return PTR_ERR(cqspi->clk);
1184 /* Obtain and remap controller address. */
1185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186 cqspi->iobase = devm_ioremap_resource(dev, res);
1187 if (IS_ERR(cqspi->iobase)) {
1188 dev_err(dev, "Cannot remap controller address.\n");
1189 return PTR_ERR(cqspi->iobase);
1192 /* Obtain and remap AHB address. */
1193 res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1194 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1195 if (IS_ERR(cqspi->ahb_base)) {
1196 dev_err(dev, "Cannot remap AHB address.\n");
1197 return PTR_ERR(cqspi->ahb_base);
1200 init_completion(&cqspi->transfer_complete);
1202 /* Obtain IRQ line. */
1203 irq = platform_get_irq(pdev, 0);
1205 dev_err(dev, "Cannot obtain IRQ.\n");
1209 ret = clk_prepare_enable(cqspi->clk);
1211 dev_err(dev, "Cannot enable QSPI clock.\n");
1215 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1217 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1220 dev_err(dev, "Cannot request IRQ.\n");
1221 goto probe_irq_failed;
1224 cqspi_wait_idle(cqspi);
1225 cqspi_controller_init(cqspi);
1226 cqspi->current_cs = -1;
1229 ret = cqspi_setup_flash(cqspi, np);
1231 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1232 goto probe_setup_failed;
1237 cqspi_controller_enable(cqspi, 0);
1239 clk_disable_unprepare(cqspi->clk);
1243 static int cqspi_remove(struct platform_device *pdev)
1245 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1248 for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1249 if (cqspi->f_pdata[i].registered)
1250 mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1252 cqspi_controller_enable(cqspi, 0);
1254 clk_disable_unprepare(cqspi->clk);
1259 #ifdef CONFIG_PM_SLEEP
1260 static int cqspi_suspend(struct device *dev)
1262 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1264 cqspi_controller_enable(cqspi, 0);
1268 static int cqspi_resume(struct device *dev)
1270 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1272 cqspi_controller_enable(cqspi, 1);
1276 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1277 .suspend = cqspi_suspend,
1278 .resume = cqspi_resume,
1281 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops)
1283 #define CQSPI_DEV_PM_OPS NULL
1286 static struct of_device_id const cqspi_dt_ids[] = {
1287 {.compatible = "cdns,qspi-nor",},
1288 { /* end of table */ }
1291 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1293 static struct platform_driver cqspi_platform_driver = {
1294 .probe = cqspi_probe,
1295 .remove = cqspi_remove,
1298 .pm = CQSPI_DEV_PM_OPS,
1299 .of_match_table = cqspi_dt_ids,
1303 module_platform_driver(cqspi_platform_driver);
1305 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1306 MODULE_LICENSE("GPL v2");
1307 MODULE_ALIAS("platform:" CQSPI_NAME);
1308 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1309 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");