2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
29 * For everything but full-chip erase; probably could be much smaller, but kept
30 * around for safety for now
32 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
35 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
38 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
40 #define SPI_NOR_MAX_ID_LEN 6
41 #define SPI_NOR_MAX_ADDR_WIDTH 4
47 * This array stores the ID bytes.
48 * The first three bytes are the JEDIC ID.
49 * JEDEC ID zero means "no ID" (mostly older chips).
51 u8 id[SPI_NOR_MAX_ID_LEN];
54 /* The size listed here is what works with SPINOR_OP_SE, which isn't
55 * necessarily called a "sector" by the vendor.
64 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
65 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
66 #define SST_WRITE 0x04 /* use SST byte programming */
67 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
68 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
69 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
70 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
71 #define USE_FSR 0x80 /* use flag status register */
74 #define JEDEC_MFR(info) ((info)->id[0])
76 static const struct flash_info *spi_nor_match_id(const char *name);
79 * Read the status register, returning its value in the location
80 * Return the status register value.
81 * Returns negative if error occurred.
83 static int read_sr(struct spi_nor *nor)
88 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
90 pr_err("error %d reading SR\n", (int) ret);
98 * Read the flag status register, returning its value in the location
99 * Return the status register value.
100 * Returns negative if error occurred.
102 static int read_fsr(struct spi_nor *nor)
107 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
109 pr_err("error %d reading FSR\n", ret);
117 * Read configuration register, returning its value in the
118 * location. Return the configuration register value.
119 * Returns negative if error occured.
121 static int read_cr(struct spi_nor *nor)
126 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
128 dev_err(nor->dev, "error %d reading CR\n", ret);
136 * Dummy Cycle calculation for different type of read.
137 * It can be used to support more commands with
138 * different dummy cycle requirements.
140 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
142 switch (nor->flash_read) {
154 * Write status register 1 byte
155 * Returns negative if error occurred.
157 static inline int write_sr(struct spi_nor *nor, u8 val)
159 nor->cmd_buf[0] = val;
160 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
164 * Set write enable latch with Write Enable command.
165 * Returns negative if error occurred.
167 static inline int write_enable(struct spi_nor *nor)
169 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
173 * Send write disble instruction to the chip.
175 static inline int write_disable(struct spi_nor *nor)
177 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
180 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
185 /* Enable/disable 4-byte addressing mode. */
186 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
190 bool need_wren = false;
193 switch (JEDEC_MFR(info)) {
194 case SNOR_MFR_MICRON:
195 /* Some Micron need WREN command; all will accept it */
197 case SNOR_MFR_MACRONIX:
198 case SNOR_MFR_WINBOND:
202 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
203 status = nor->write_reg(nor, cmd, NULL, 0);
210 nor->cmd_buf[0] = enable << 7;
211 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
214 static inline int spi_nor_sr_ready(struct spi_nor *nor)
216 int sr = read_sr(nor);
220 return !(sr & SR_WIP);
223 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
225 int fsr = read_fsr(nor);
229 return fsr & FSR_READY;
232 static int spi_nor_ready(struct spi_nor *nor)
235 sr = spi_nor_sr_ready(nor);
238 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
245 * Service routine to read status register until ready, or timeout occurs.
246 * Returns non-zero if error.
248 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
249 unsigned long timeout_jiffies)
251 unsigned long deadline;
252 int timeout = 0, ret;
254 deadline = jiffies + timeout_jiffies;
257 if (time_after_eq(jiffies, deadline))
260 ret = spi_nor_ready(nor);
269 dev_err(nor->dev, "flash operation timed out\n");
274 static int spi_nor_wait_till_ready(struct spi_nor *nor)
276 return spi_nor_wait_till_ready_with_timeout(nor,
277 DEFAULT_READY_WAIT_JIFFIES);
281 * Erase the whole flash memory
283 * Returns 0 if successful, non-zero otherwise.
285 static int erase_chip(struct spi_nor *nor)
287 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
289 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
292 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
296 mutex_lock(&nor->lock);
299 ret = nor->prepare(nor, ops);
301 dev_err(nor->dev, "failed in the preparation.\n");
302 mutex_unlock(&nor->lock);
309 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
312 nor->unprepare(nor, ops);
313 mutex_unlock(&nor->lock);
317 * Initiate the erasure of a single sector
319 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
321 u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
325 return nor->erase(nor, addr);
328 * Default implementation, if driver doesn't have a specialized HW
331 for (i = nor->addr_width - 1; i >= 0; i--) {
332 buf[i] = addr & 0xff;
336 return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
340 * Erase an address range on the nor chip. The address range may extend
341 * one or more erase sectors. Return an error is there is a problem erasing.
343 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
345 struct spi_nor *nor = mtd_to_spi_nor(mtd);
350 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
351 (long long)instr->len);
353 div_u64_rem(instr->len, mtd->erasesize, &rem);
360 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
364 /* whole-chip erase? */
365 if (len == mtd->size) {
366 unsigned long timeout;
370 if (erase_chip(nor)) {
376 * Scale the timeout linearly with the size of the flash, with
377 * a minimum calibrated to an old 2MB flash. We could try to
378 * pull these from CFI/SFDP, but these values should be good
381 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
382 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
383 (unsigned long)(mtd->size / SZ_2M));
384 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
388 /* REVISIT in some cases we could speed up erasing large regions
389 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
390 * to use "small sector erase", but that's not always optimal.
393 /* "sector"-at-a-time erase */
398 ret = spi_nor_erase_sector(nor, addr);
402 addr += mtd->erasesize;
403 len -= mtd->erasesize;
405 ret = spi_nor_wait_till_ready(nor);
414 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
416 instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
417 mtd_erase_callback(instr);
422 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
425 struct mtd_info *mtd = &nor->mtd;
426 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
427 int shift = ffs(mask) - 1;
435 pow = ((sr & mask) ^ mask) >> shift;
436 *len = mtd->size >> pow;
437 *ofs = mtd->size - *len;
442 * Return 1 if the entire region is locked, 0 otherwise
444 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
450 stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
452 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
456 * Lock a region of the flash. Compatible with ST Micro and similar flash.
457 * Supports only the block protection bits BP{0,1,2} in the status register
458 * (SR). Does not support these features found in newer SR bitfields:
459 * - TB: top/bottom protect - only handle TB=0 (top protect)
460 * - SEC: sector/block protect - only handle SEC=0 (block protect)
461 * - CMP: complement protect - only support CMP=0 (range is not complemented)
463 * Sample table portion for 8MB flash (Winbond w25q64fw):
465 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
466 * --------------------------------------------------------------------------
467 * X | X | 0 | 0 | 0 | NONE | NONE
468 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
469 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
470 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
471 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
472 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
473 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
474 * X | X | 1 | 1 | 1 | 8 MB | ALL
476 * Returns negative on errors, 0 on success.
478 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
480 struct mtd_info *mtd = &nor->mtd;
481 int status_old, status_new;
482 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
483 u8 shift = ffs(mask) - 1, pow, val;
485 status_old = read_sr(nor);
489 /* SPI NOR always locks to the end */
490 if (ofs + len != mtd->size) {
491 /* Does combined region extend to end? */
492 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
495 len = mtd->size - ofs;
499 * Need smallest pow such that:
501 * 1 / (2^pow) <= (len / size)
503 * so (assuming power-of-2 size) we do:
505 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
507 pow = ilog2(mtd->size) - ilog2(len);
508 val = mask - (pow << shift);
511 /* Don't "lock" with no region! */
515 status_new = (status_old & ~mask) | val;
517 /* Only modify protection if it will not unlock other areas */
518 if ((status_new & mask) <= (status_old & mask))
522 return write_sr(nor, status_new);
526 * Unlock a region of the flash. See stm_lock() for more info
528 * Returns negative on errors, 0 on success.
530 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
532 struct mtd_info *mtd = &nor->mtd;
533 int status_old, status_new;
534 u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
535 u8 shift = ffs(mask) - 1, pow, val;
537 status_old = read_sr(nor);
541 /* Cannot unlock; would unlock larger region than requested */
542 if (stm_is_locked_sr(nor, status_old, ofs - mtd->erasesize,
547 * Need largest pow such that:
549 * 1 / (2^pow) >= (len / size)
551 * so (assuming power-of-2 size) we do:
553 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
555 pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
556 if (ofs + len == mtd->size) {
557 val = 0; /* fully unlocked */
559 val = mask - (pow << shift);
560 /* Some power-of-two sizes are not supported */
565 status_new = (status_old & ~mask) | val;
567 /* Only modify protection if it will not lock other areas */
568 if ((status_new & mask) >= (status_old & mask))
572 return write_sr(nor, status_new);
576 * Check if a region of the flash is (completely) locked. See stm_lock() for
579 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
580 * negative on errors.
582 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
586 status = read_sr(nor);
590 return stm_is_locked_sr(nor, ofs, len, status);
593 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
595 struct spi_nor *nor = mtd_to_spi_nor(mtd);
598 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
602 ret = nor->flash_lock(nor, ofs, len);
604 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
608 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
610 struct spi_nor *nor = mtd_to_spi_nor(mtd);
613 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
617 ret = nor->flash_unlock(nor, ofs, len);
619 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
623 static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
625 struct spi_nor *nor = mtd_to_spi_nor(mtd);
628 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
632 ret = nor->flash_is_locked(nor, ofs, len);
634 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
638 /* Used when the "_ext_id" is two bytes at most */
639 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
641 ((_jedec_id) >> 16) & 0xff, \
642 ((_jedec_id) >> 8) & 0xff, \
643 (_jedec_id) & 0xff, \
644 ((_ext_id) >> 8) & 0xff, \
647 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
648 .sector_size = (_sector_size), \
649 .n_sectors = (_n_sectors), \
653 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
655 ((_jedec_id) >> 16) & 0xff, \
656 ((_jedec_id) >> 8) & 0xff, \
657 (_jedec_id) & 0xff, \
658 ((_ext_id) >> 16) & 0xff, \
659 ((_ext_id) >> 8) & 0xff, \
663 .sector_size = (_sector_size), \
664 .n_sectors = (_n_sectors), \
668 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
669 .sector_size = (_sector_size), \
670 .n_sectors = (_n_sectors), \
671 .page_size = (_page_size), \
672 .addr_width = (_addr_width), \
675 /* NOTE: double check command sets and memory organization when you add
676 * more nor chips. This current list focusses on newer chips, which
677 * have been converging on command sets which including JEDEC ID.
679 * All newly added entries should describe *hardware* and should use SECT_4K
680 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
681 * scenarios excluding small sectors there is config option that can be
682 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
683 * For historical (and compatibility) reasons (before we got above config) some
684 * old entries may be missing 4K flag.
686 static const struct flash_info spi_nor_ids[] = {
687 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
688 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
689 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
691 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
692 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
693 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
695 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
696 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
697 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
698 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
700 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
703 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
704 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
705 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
706 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
707 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
708 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
709 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
710 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
713 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
716 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
717 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
720 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
723 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
724 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
725 { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
727 /* Intel/Numonyx -- xxxs33b */
728 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
729 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
730 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
733 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
736 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
737 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
738 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
739 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
740 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
741 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
742 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
743 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
744 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
745 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
746 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
747 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
748 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
749 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
750 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
753 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
754 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
755 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
756 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
757 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
758 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
759 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
760 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
761 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
762 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
765 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
766 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
767 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
769 /* Spansion -- single (large) sector size only, at least
770 * for the chips listed here (without boot sectors).
772 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
773 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
774 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
775 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
776 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
777 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
778 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
779 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
780 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
781 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
782 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
783 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
784 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
785 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
786 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
787 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
788 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
789 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
790 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
791 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
792 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
793 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
794 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
796 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
797 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
798 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
799 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
800 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
801 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
802 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
803 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
804 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
805 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
806 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
807 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
808 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
810 /* ST Microelectronics -- newer production may have feature updates */
811 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
812 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
813 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
814 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
815 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
816 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
817 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
818 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
819 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
821 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
822 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
823 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
824 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
825 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
826 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
827 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
828 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
829 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
831 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
832 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
833 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
835 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
836 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
837 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
839 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
840 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
841 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
842 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
843 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
844 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
846 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
847 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
848 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
849 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
850 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
851 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
852 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
853 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
854 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
855 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
856 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
857 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
858 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
859 { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
860 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
861 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
862 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
863 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
865 /* Catalyst / On Semiconductor -- non-JEDEC */
866 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
867 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
868 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
869 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
870 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
874 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
877 u8 id[SPI_NOR_MAX_ID_LEN];
878 const struct flash_info *info;
880 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
882 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
886 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
887 info = &spi_nor_ids[tmp];
889 if (!memcmp(info->id, id, info->id_len))
890 return &spi_nor_ids[tmp];
893 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
894 id[0], id[1], id[2]);
895 return ERR_PTR(-ENODEV);
898 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
899 size_t *retlen, u_char *buf)
901 struct spi_nor *nor = mtd_to_spi_nor(mtd);
904 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
906 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
910 ret = nor->read(nor, from, len, retlen, buf);
912 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
916 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
917 size_t *retlen, const u_char *buf)
919 struct spi_nor *nor = mtd_to_spi_nor(mtd);
923 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
925 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
931 nor->sst_write_second = false;
934 /* Start write from odd address. */
936 nor->program_opcode = SPINOR_OP_BP;
938 /* write one byte. */
939 nor->write(nor, to, 1, retlen, buf);
940 ret = spi_nor_wait_till_ready(nor);
946 /* Write out most of the data here. */
947 for (; actual < len - 1; actual += 2) {
948 nor->program_opcode = SPINOR_OP_AAI_WP;
950 /* write two bytes. */
951 nor->write(nor, to, 2, retlen, buf + actual);
952 ret = spi_nor_wait_till_ready(nor);
956 nor->sst_write_second = true;
958 nor->sst_write_second = false;
961 ret = spi_nor_wait_till_ready(nor);
965 /* Write out trailing byte if it exists. */
969 nor->program_opcode = SPINOR_OP_BP;
970 nor->write(nor, to, 1, retlen, buf + actual);
972 ret = spi_nor_wait_till_ready(nor);
978 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
983 * Write an address range to the nor chip. Data must be written in
984 * FLASH_PAGESIZE chunks. The address range may be any size provided
985 * it is within the physical boundaries.
987 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
988 size_t *retlen, const u_char *buf)
990 struct spi_nor *nor = mtd_to_spi_nor(mtd);
991 u32 page_offset, page_size, i;
994 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
996 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1002 page_offset = to & (nor->page_size - 1);
1004 /* do all the bytes fit onto one page? */
1005 if (page_offset + len <= nor->page_size) {
1006 nor->write(nor, to, len, retlen, buf);
1008 /* the size of data remaining on the first page */
1009 page_size = nor->page_size - page_offset;
1010 nor->write(nor, to, page_size, retlen, buf);
1012 /* write everything in nor->page_size chunks */
1013 for (i = page_size; i < len; i += page_size) {
1014 page_size = len - i;
1015 if (page_size > nor->page_size)
1016 page_size = nor->page_size;
1018 ret = spi_nor_wait_till_ready(nor);
1024 nor->write(nor, to + i, page_size, retlen, buf + i);
1028 ret = spi_nor_wait_till_ready(nor);
1030 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1034 static int macronix_quad_enable(struct spi_nor *nor)
1043 write_sr(nor, val | SR_QUAD_EN_MX);
1045 if (spi_nor_wait_till_ready(nor))
1049 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1050 dev_err(nor->dev, "Macronix Quad bit not set\n");
1058 * Write status Register and configuration register with 2 bytes
1059 * The first byte will be written to the status register, while the
1060 * second byte will be written to the configuration register.
1061 * Return negative if error occured.
1063 static int write_sr_cr(struct spi_nor *nor, u16 val)
1065 nor->cmd_buf[0] = val & 0xff;
1066 nor->cmd_buf[1] = (val >> 8);
1068 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
1071 static int spansion_quad_enable(struct spi_nor *nor)
1074 int quad_en = CR_QUAD_EN_SPAN << 8;
1078 ret = write_sr_cr(nor, quad_en);
1081 "error while writing configuration register\n");
1085 /* read back and check it */
1087 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1088 dev_err(nor->dev, "Spansion Quad bit not set\n");
1095 static int micron_quad_enable(struct spi_nor *nor)
1100 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
1102 dev_err(nor->dev, "error %d reading EVCR\n", ret);
1108 /* set EVCR, enable quad I/O */
1109 nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
1110 ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
1112 dev_err(nor->dev, "error while writing EVCR register\n");
1116 ret = spi_nor_wait_till_ready(nor);
1120 /* read EVCR and check it */
1121 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
1123 dev_err(nor->dev, "error %d reading EVCR\n", ret);
1126 if (val & EVCR_QUAD_EN_MICRON) {
1127 dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
1134 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
1138 switch (JEDEC_MFR(info)) {
1139 case SNOR_MFR_MACRONIX:
1140 status = macronix_quad_enable(nor);
1142 dev_err(nor->dev, "Macronix quad-read not enabled\n");
1146 case SNOR_MFR_MICRON:
1147 status = micron_quad_enable(nor);
1149 dev_err(nor->dev, "Micron quad-read not enabled\n");
1154 status = spansion_quad_enable(nor);
1156 dev_err(nor->dev, "Spansion quad-read not enabled\n");
1163 static int spi_nor_check(struct spi_nor *nor)
1165 if (!nor->dev || !nor->read || !nor->write ||
1166 !nor->read_reg || !nor->write_reg) {
1167 pr_err("spi-nor: please fill all the necessary fields!\n");
1174 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1176 const struct flash_info *info = NULL;
1177 struct device *dev = nor->dev;
1178 struct mtd_info *mtd = &nor->mtd;
1179 struct device_node *np = spi_nor_get_flash_node(nor);
1183 ret = spi_nor_check(nor);
1188 info = spi_nor_match_id(name);
1189 /* Try to auto-detect if chip name wasn't specified or not found */
1191 info = spi_nor_read_id(nor);
1192 if (IS_ERR_OR_NULL(info))
1196 * If caller has specified name of flash model that can normally be
1197 * detected using JEDEC, let's verify it.
1199 if (name && info->id_len) {
1200 const struct flash_info *jinfo;
1202 jinfo = spi_nor_read_id(nor);
1203 if (IS_ERR(jinfo)) {
1204 return PTR_ERR(jinfo);
1205 } else if (jinfo != info) {
1207 * JEDEC knows better, so overwrite platform ID. We
1208 * can't trust partitions any longer, but we'll let
1209 * mtd apply them anyway, since some partitions may be
1210 * marked read-only, and we don't want to lose that
1211 * information, even if it's not 100% accurate.
1213 dev_warn(dev, "found %s, expected %s\n",
1214 jinfo->name, info->name);
1219 mutex_init(&nor->lock);
1222 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
1223 * with the software protection bits set
1226 if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
1227 JEDEC_MFR(info) == SNOR_MFR_INTEL ||
1228 JEDEC_MFR(info) == SNOR_MFR_SST ||
1229 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
1235 mtd->name = dev_name(dev);
1237 mtd->type = MTD_NORFLASH;
1239 mtd->flags = MTD_CAP_NORFLASH;
1240 mtd->size = info->sector_size * info->n_sectors;
1241 mtd->_erase = spi_nor_erase;
1242 mtd->_read = spi_nor_read;
1244 /* NOR protection support for STmicro/Micron chips and similar */
1245 if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1246 JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
1247 nor->flash_lock = stm_lock;
1248 nor->flash_unlock = stm_unlock;
1249 nor->flash_is_locked = stm_is_locked;
1252 if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
1253 mtd->_lock = spi_nor_lock;
1254 mtd->_unlock = spi_nor_unlock;
1255 mtd->_is_locked = spi_nor_is_locked;
1258 /* sst nor chips use AAI word program */
1259 if (info->flags & SST_WRITE)
1260 mtd->_write = sst_write;
1262 mtd->_write = spi_nor_write;
1264 if (info->flags & USE_FSR)
1265 nor->flags |= SNOR_F_USE_FSR;
1267 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1268 /* prefer "small sector" erase if possible */
1269 if (info->flags & SECT_4K) {
1270 nor->erase_opcode = SPINOR_OP_BE_4K;
1271 mtd->erasesize = 4096;
1272 } else if (info->flags & SECT_4K_PMC) {
1273 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1274 mtd->erasesize = 4096;
1278 nor->erase_opcode = SPINOR_OP_SE;
1279 mtd->erasesize = info->sector_size;
1282 if (info->flags & SPI_NOR_NO_ERASE)
1283 mtd->flags |= MTD_NO_ERASE;
1285 mtd->dev.parent = dev;
1286 nor->page_size = info->page_size;
1287 mtd->writebufsize = nor->page_size;
1290 /* If we were instantiated by DT, use it */
1291 if (of_property_read_bool(np, "m25p,fast-read"))
1292 nor->flash_read = SPI_NOR_FAST;
1294 nor->flash_read = SPI_NOR_NORMAL;
1296 /* If we weren't instantiated by DT, default to fast-read */
1297 nor->flash_read = SPI_NOR_FAST;
1300 /* Some devices cannot do fast-read, no matter what DT tells us */
1301 if (info->flags & SPI_NOR_NO_FR)
1302 nor->flash_read = SPI_NOR_NORMAL;
1304 /* Quad/Dual-read mode takes precedence over fast/normal */
1305 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1306 ret = set_quad_mode(nor, info);
1308 dev_err(dev, "quad mode not supported\n");
1311 nor->flash_read = SPI_NOR_QUAD;
1312 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1313 nor->flash_read = SPI_NOR_DUAL;
1316 /* Default commands */
1317 switch (nor->flash_read) {
1319 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1322 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1325 nor->read_opcode = SPINOR_OP_READ_FAST;
1327 case SPI_NOR_NORMAL:
1328 nor->read_opcode = SPINOR_OP_READ;
1331 dev_err(dev, "No Read opcode defined\n");
1335 nor->program_opcode = SPINOR_OP_PP;
1337 if (info->addr_width)
1338 nor->addr_width = info->addr_width;
1339 else if (mtd->size > 0x1000000) {
1340 /* enable 4-byte addressing if the device exceeds 16MiB */
1341 nor->addr_width = 4;
1342 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
1343 /* Dedicated 4-byte command set */
1344 switch (nor->flash_read) {
1346 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1349 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1352 nor->read_opcode = SPINOR_OP_READ4_FAST;
1354 case SPI_NOR_NORMAL:
1355 nor->read_opcode = SPINOR_OP_READ4;
1358 nor->program_opcode = SPINOR_OP_PP_4B;
1359 /* No small sector erase for 4-byte command set */
1360 nor->erase_opcode = SPINOR_OP_SE_4B;
1361 mtd->erasesize = info->sector_size;
1363 set_4byte(nor, info, 1);
1365 nor->addr_width = 3;
1368 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
1369 dev_err(dev, "address width is too large: %u\n",
1374 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1376 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
1377 (long long)mtd->size >> 10);
1380 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1381 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1382 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1383 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1385 if (mtd->numeraseregions)
1386 for (i = 0; i < mtd->numeraseregions; i++)
1388 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1389 ".erasesize = 0x%.8x (%uKiB), "
1390 ".numblocks = %d }\n",
1391 i, (long long)mtd->eraseregions[i].offset,
1392 mtd->eraseregions[i].erasesize,
1393 mtd->eraseregions[i].erasesize / 1024,
1394 mtd->eraseregions[i].numblocks);
1397 EXPORT_SYMBOL_GPL(spi_nor_scan);
1399 static const struct flash_info *spi_nor_match_id(const char *name)
1401 const struct flash_info *id = spi_nor_ids;
1404 if (!strcmp(name, id->name))
1411 MODULE_LICENSE("GPL");
1412 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1413 MODULE_AUTHOR("Mike Lavender");
1414 MODULE_DESCRIPTION("framework for SPI NOR");