4 * Copyright (C) 2017, Ludovic Barre
6 * License terms: GNU General Public License (GPL), version 2
9 #include <linux/errno.h>
11 #include <linux/iopoll.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/spi-nor.h>
17 #include <linux/mutex.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
23 #define QUADSPI_CR 0x00
25 #define CR_ABORT BIT(1)
26 #define CR_DMAEN BIT(2)
27 #define CR_TCEN BIT(3)
28 #define CR_SSHIFT BIT(4)
30 #define CR_FSEL BIT(7)
31 #define CR_FTHRES_SHIFT 8
32 #define CR_FTHRES_MASK GENMASK(12, 8)
33 #define CR_FTHRES(n) (((n) << CR_FTHRES_SHIFT) & CR_FTHRES_MASK)
34 #define CR_TEIE BIT(16)
35 #define CR_TCIE BIT(17)
36 #define CR_FTIE BIT(18)
37 #define CR_SMIE BIT(19)
38 #define CR_TOIE BIT(20)
39 #define CR_PRESC_SHIFT 24
40 #define CR_PRESC_MASK GENMASK(31, 24)
41 #define CR_PRESC(n) (((n) << CR_PRESC_SHIFT) & CR_PRESC_MASK)
43 #define QUADSPI_DCR 0x04
44 #define DCR_CSHT_SHIFT 8
45 #define DCR_CSHT_MASK GENMASK(10, 8)
46 #define DCR_CSHT(n) (((n) << DCR_CSHT_SHIFT) & DCR_CSHT_MASK)
47 #define DCR_FSIZE_SHIFT 16
48 #define DCR_FSIZE_MASK GENMASK(20, 16)
49 #define DCR_FSIZE(n) (((n) << DCR_FSIZE_SHIFT) & DCR_FSIZE_MASK)
51 #define QUADSPI_SR 0x08
57 #define SR_BUSY BIT(5)
58 #define SR_FLEVEL_SHIFT 8
59 #define SR_FLEVEL_MASK GENMASK(13, 8)
61 #define QUADSPI_FCR 0x0c
62 #define FCR_CTCF BIT(1)
64 #define QUADSPI_DLR 0x10
66 #define QUADSPI_CCR 0x14
67 #define CCR_INST_SHIFT 0
68 #define CCR_INST_MASK GENMASK(7, 0)
69 #define CCR_INST(n) (((n) << CCR_INST_SHIFT) & CCR_INST_MASK)
70 #define CCR_IMODE_NONE (0U << 8)
71 #define CCR_IMODE_1 (1U << 8)
72 #define CCR_IMODE_2 (2U << 8)
73 #define CCR_IMODE_4 (3U << 8)
74 #define CCR_ADMODE_NONE (0U << 10)
75 #define CCR_ADMODE_1 (1U << 10)
76 #define CCR_ADMODE_2 (2U << 10)
77 #define CCR_ADMODE_4 (3U << 10)
78 #define CCR_ADSIZE_SHIFT 12
79 #define CCR_ADSIZE_MASK GENMASK(13, 12)
80 #define CCR_ADSIZE(n) (((n) << CCR_ADSIZE_SHIFT) & CCR_ADSIZE_MASK)
81 #define CCR_ABMODE_NONE (0U << 14)
82 #define CCR_ABMODE_1 (1U << 14)
83 #define CCR_ABMODE_2 (2U << 14)
84 #define CCR_ABMODE_4 (3U << 14)
85 #define CCR_ABSIZE_8 (0U << 16)
86 #define CCR_ABSIZE_16 (1U << 16)
87 #define CCR_ABSIZE_24 (2U << 16)
88 #define CCR_ABSIZE_32 (3U << 16)
89 #define CCR_DCYC_SHIFT 18
90 #define CCR_DCYC_MASK GENMASK(22, 18)
91 #define CCR_DCYC(n) (((n) << CCR_DCYC_SHIFT) & CCR_DCYC_MASK)
92 #define CCR_DMODE_NONE (0U << 24)
93 #define CCR_DMODE_1 (1U << 24)
94 #define CCR_DMODE_2 (2U << 24)
95 #define CCR_DMODE_4 (3U << 24)
96 #define CCR_FMODE_INDW (0U << 26)
97 #define CCR_FMODE_INDR (1U << 26)
98 #define CCR_FMODE_APM (2U << 26)
99 #define CCR_FMODE_MM (3U << 26)
101 #define QUADSPI_AR 0x18
102 #define QUADSPI_ABR 0x1c
103 #define QUADSPI_DR 0x20
104 #define QUADSPI_PSMKR 0x24
105 #define QUADSPI_PSMAR 0x28
106 #define QUADSPI_PIR 0x2c
107 #define QUADSPI_LPTR 0x30
108 #define LPTR_DFT_TIMEOUT 0x10
110 #define FSIZE_VAL(size) (__fls(size) - 1)
112 #define STM32_MAX_MMAP_SZ SZ_256M
113 #define STM32_MAX_NORCHIP 2
115 #define STM32_QSPI_FIFO_TIMEOUT_US 30000
116 #define STM32_QSPI_BUSY_TIMEOUT_US 100000
118 struct stm32_qspi_flash {
120 struct stm32_qspi *qspi;
130 void __iomem *io_base;
131 void __iomem *mm_base;
132 resource_size_t mm_size;
136 struct stm32_qspi_flash flash[STM32_MAX_NORCHIP];
137 struct completion cmd_completion;
140 * to protect device configuration, could be different between
141 * 2 flash access (bk1, bk2)
146 struct stm32_qspi_cmd {
158 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
163 if (readl_relaxed(qspi->io_base + QUADSPI_SR) & SR_TCF)
166 reinit_completion(&qspi->cmd_completion);
167 cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
168 writel_relaxed(cr | CR_TCIE, qspi->io_base + QUADSPI_CR);
170 if (!wait_for_completion_interruptible_timeout(&qspi->cmd_completion,
171 msecs_to_jiffies(1000)))
174 writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
178 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
182 return readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR, sr,
184 STM32_QSPI_BUSY_TIMEOUT_US);
187 static void stm32_qspi_set_framemode(struct spi_nor *nor,
188 struct stm32_qspi_cmd *cmd, bool read)
190 u32 dmode = CCR_DMODE_1;
192 cmd->framemode = CCR_IMODE_1;
195 switch (nor->flash_read) {
209 cmd->framemode |= cmd->tx_data ? dmode : 0;
210 cmd->framemode |= cmd->addr_width ? CCR_ADMODE_1 : 0;
213 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
215 *val = readb_relaxed(addr);
218 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
220 writeb_relaxed(*val, addr);
223 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
224 const struct stm32_qspi_cmd *cmd)
226 void (*tx_fifo)(u8 *, void __iomem *);
227 u32 len = cmd->len, sr;
231 if (cmd->qspimode == CCR_FMODE_INDW)
232 tx_fifo = stm32_qspi_write_fifo;
234 tx_fifo = stm32_qspi_read_fifo;
237 ret = readl_relaxed_poll_timeout(qspi->io_base + QUADSPI_SR,
238 sr, (sr & SR_FTF), 10,
239 STM32_QSPI_FIFO_TIMEOUT_US);
241 dev_err(qspi->dev, "fifo timeout (stat:%#x)\n", sr);
244 tx_fifo(buf++, qspi->io_base + QUADSPI_DR);
250 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
251 const struct stm32_qspi_cmd *cmd)
253 memcpy_fromio(cmd->buf, qspi->mm_base + cmd->addr, cmd->len);
257 static int stm32_qspi_tx(struct stm32_qspi *qspi,
258 const struct stm32_qspi_cmd *cmd)
263 if (cmd->qspimode == CCR_FMODE_MM)
264 return stm32_qspi_tx_mm(qspi, cmd);
266 return stm32_qspi_tx_poll(qspi, cmd);
269 static int stm32_qspi_send(struct stm32_qspi_flash *flash,
270 const struct stm32_qspi_cmd *cmd)
272 struct stm32_qspi *qspi = flash->qspi;
276 err = stm32_qspi_wait_nobusy(qspi);
280 dcr = readl_relaxed(qspi->io_base + QUADSPI_DCR) & ~DCR_FSIZE_MASK;
281 dcr |= DCR_FSIZE(flash->fsize);
282 writel_relaxed(dcr, qspi->io_base + QUADSPI_DCR);
284 cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
285 cr &= ~CR_PRESC_MASK & ~CR_FSEL;
286 cr |= CR_PRESC(flash->presc);
287 cr |= flash->cs ? CR_FSEL : 0;
288 writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
291 writel_relaxed(cmd->len - 1, qspi->io_base + QUADSPI_DLR);
293 ccr = cmd->framemode | cmd->qspimode;
296 ccr |= CCR_DCYC(cmd->dummy);
299 ccr |= CCR_ADSIZE(cmd->addr_width - 1);
301 ccr |= CCR_INST(cmd->opcode);
302 writel_relaxed(ccr, qspi->io_base + QUADSPI_CCR);
304 if (cmd->addr_width && cmd->qspimode != CCR_FMODE_MM)
305 writel_relaxed(cmd->addr, qspi->io_base + QUADSPI_AR);
307 err = stm32_qspi_tx(qspi, cmd);
311 if (cmd->qspimode != CCR_FMODE_MM) {
312 err = stm32_qspi_wait_cmd(qspi);
315 writel_relaxed(FCR_CTCF, qspi->io_base + QUADSPI_FCR);
321 cr = readl_relaxed(qspi->io_base + QUADSPI_CR) | CR_ABORT;
322 writel_relaxed(cr, qspi->io_base + QUADSPI_CR);
324 dev_err(qspi->dev, "%s abort err:%d\n", __func__, err);
328 static int stm32_qspi_read_reg(struct spi_nor *nor,
329 u8 opcode, u8 *buf, int len)
331 struct stm32_qspi_flash *flash = nor->priv;
332 struct device *dev = flash->qspi->dev;
333 struct stm32_qspi_cmd cmd;
335 dev_dbg(dev, "read_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
337 memset(&cmd, 0, sizeof(cmd));
342 cmd.qspimode = CCR_FMODE_INDR;
344 stm32_qspi_set_framemode(nor, &cmd, false);
346 return stm32_qspi_send(flash, &cmd);
349 static int stm32_qspi_write_reg(struct spi_nor *nor, u8 opcode,
352 struct stm32_qspi_flash *flash = nor->priv;
353 struct device *dev = flash->qspi->dev;
354 struct stm32_qspi_cmd cmd;
356 dev_dbg(dev, "write_reg: cmd:%#.2x buf:%p len:%#x\n", opcode, buf, len);
358 memset(&cmd, 0, sizeof(cmd));
360 cmd.tx_data = !!(buf && len > 0);
363 cmd.qspimode = CCR_FMODE_INDW;
365 stm32_qspi_set_framemode(nor, &cmd, false);
367 return stm32_qspi_send(flash, &cmd);
370 static ssize_t stm32_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
373 struct stm32_qspi_flash *flash = nor->priv;
374 struct stm32_qspi *qspi = flash->qspi;
375 struct stm32_qspi_cmd cmd;
378 dev_dbg(qspi->dev, "read(%#.2x): buf:%p from:%#.8x len:%#x\n",
379 nor->read_opcode, buf, (u32)from, len);
381 memset(&cmd, 0, sizeof(cmd));
382 cmd.opcode = nor->read_opcode;
383 cmd.addr_width = nor->addr_width;
384 cmd.addr = (u32)from;
386 cmd.dummy = nor->read_dummy;
389 cmd.qspimode = flash->read_mode;
391 stm32_qspi_set_framemode(nor, &cmd, true);
392 err = stm32_qspi_send(flash, &cmd);
394 return err ? err : len;
397 static ssize_t stm32_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
400 struct stm32_qspi_flash *flash = nor->priv;
401 struct device *dev = flash->qspi->dev;
402 struct stm32_qspi_cmd cmd;
405 dev_dbg(dev, "write(%#.2x): buf:%p to:%#.8x len:%#x\n",
406 nor->program_opcode, buf, (u32)to, len);
408 memset(&cmd, 0, sizeof(cmd));
409 cmd.opcode = nor->program_opcode;
410 cmd.addr_width = nor->addr_width;
414 cmd.buf = (void *)buf;
415 cmd.qspimode = CCR_FMODE_INDW;
417 stm32_qspi_set_framemode(nor, &cmd, false);
418 err = stm32_qspi_send(flash, &cmd);
420 return err ? err : len;
423 static int stm32_qspi_erase(struct spi_nor *nor, loff_t offs)
425 struct stm32_qspi_flash *flash = nor->priv;
426 struct device *dev = flash->qspi->dev;
427 struct stm32_qspi_cmd cmd;
429 dev_dbg(dev, "erase(%#.2x):offs:%#x\n", nor->erase_opcode, (u32)offs);
431 memset(&cmd, 0, sizeof(cmd));
432 cmd.opcode = nor->erase_opcode;
433 cmd.addr_width = nor->addr_width;
434 cmd.addr = (u32)offs;
435 cmd.qspimode = CCR_FMODE_INDW;
437 stm32_qspi_set_framemode(nor, &cmd, false);
439 return stm32_qspi_send(flash, &cmd);
442 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
444 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
447 cr = readl_relaxed(qspi->io_base + QUADSPI_CR);
448 sr = readl_relaxed(qspi->io_base + QUADSPI_SR);
450 if ((cr & CR_TCIE) && (sr & SR_TCF)) {
453 complete(&qspi->cmd_completion);
455 dev_info_ratelimited(qspi->dev, "spurious interrupt\n");
458 writel_relaxed(fcr, qspi->io_base + QUADSPI_FCR);
463 static int stm32_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
465 struct stm32_qspi_flash *flash = nor->priv;
466 struct stm32_qspi *qspi = flash->qspi;
468 mutex_lock(&qspi->lock);
472 static void stm32_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
474 struct stm32_qspi_flash *flash = nor->priv;
475 struct stm32_qspi *qspi = flash->qspi;
477 mutex_unlock(&qspi->lock);
480 static int stm32_qspi_flash_setup(struct stm32_qspi *qspi,
481 struct device_node *np)
483 u32 width, flash_read, presc, cs_num, max_rate = 0;
484 struct stm32_qspi_flash *flash;
485 struct mtd_info *mtd;
488 of_property_read_u32(np, "reg", &cs_num);
489 if (cs_num >= STM32_MAX_NORCHIP)
492 of_property_read_u32(np, "spi-max-frequency", &max_rate);
496 presc = DIV_ROUND_UP(qspi->clk_rate, max_rate) - 1;
498 if (of_property_read_u32(np, "spi-rx-bus-width", &width))
502 flash_read = SPI_NOR_QUAD;
504 flash_read = SPI_NOR_DUAL;
506 flash_read = SPI_NOR_NORMAL;
510 flash = &qspi->flash[cs_num];
513 flash->presc = presc;
515 flash->nor.dev = qspi->dev;
516 spi_nor_set_flash_node(&flash->nor, np);
517 flash->nor.priv = flash;
518 mtd = &flash->nor.mtd;
520 flash->nor.read = stm32_qspi_read;
521 flash->nor.write = stm32_qspi_write;
522 flash->nor.erase = stm32_qspi_erase;
523 flash->nor.read_reg = stm32_qspi_read_reg;
524 flash->nor.write_reg = stm32_qspi_write_reg;
525 flash->nor.prepare = stm32_qspi_prep;
526 flash->nor.unprepare = stm32_qspi_unprep;
528 writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QUADSPI_LPTR);
530 writel_relaxed(CR_PRESC(presc) | CR_FTHRES(3) | CR_TCEN | CR_SSHIFT
531 | CR_EN, qspi->io_base + QUADSPI_CR);
534 * in stm32 qspi controller, QUADSPI_DCR register has a fsize field
535 * which define the size of nor flash.
536 * if fsize is NULL, the controller can't sent spi-nor command.
537 * set a temporary value just to discover the nor flash with
538 * "spi_nor_scan". After, the right value (mtd->size) can be set.
540 flash->fsize = FSIZE_VAL(SZ_1K);
542 ret = spi_nor_scan(&flash->nor, NULL, flash_read);
544 dev_err(qspi->dev, "device scan failed\n");
548 flash->fsize = FSIZE_VAL(mtd->size);
550 flash->read_mode = CCR_FMODE_MM;
551 if (mtd->size > qspi->mm_size)
552 flash->read_mode = CCR_FMODE_INDR;
554 writel_relaxed(DCR_CSHT(1), qspi->io_base + QUADSPI_DCR);
556 ret = mtd_device_register(mtd, NULL, 0);
558 dev_err(qspi->dev, "mtd device parse failed\n");
562 flash->registered = true;
564 dev_dbg(qspi->dev, "read mm:%s cs:%d bus:%d\n",
565 flash->read_mode == CCR_FMODE_MM ? "yes" : "no", cs_num, width);
570 static void stm32_qspi_mtd_free(struct stm32_qspi *qspi)
574 for (i = 0; i < STM32_MAX_NORCHIP; i++)
575 if (qspi->flash[i].registered)
576 mtd_device_unregister(&qspi->flash[i].nor.mtd);
579 static int stm32_qspi_probe(struct platform_device *pdev)
581 struct device *dev = &pdev->dev;
582 struct device_node *flash_np;
583 struct reset_control *rstc;
584 struct stm32_qspi *qspi;
585 struct resource *res;
588 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
592 qspi->nor_num = of_get_child_count(dev->of_node);
593 if (!qspi->nor_num || qspi->nor_num > STM32_MAX_NORCHIP)
596 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
597 qspi->io_base = devm_ioremap_resource(dev, res);
598 if (IS_ERR(qspi->io_base))
599 return PTR_ERR(qspi->io_base);
601 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
602 qspi->mm_base = devm_ioremap_resource(dev, res);
603 if (IS_ERR(qspi->mm_base))
604 return PTR_ERR(qspi->mm_base);
606 qspi->mm_size = resource_size(res);
608 irq = platform_get_irq(pdev, 0);
609 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
610 dev_name(dev), qspi);
612 dev_err(dev, "failed to request irq\n");
616 init_completion(&qspi->cmd_completion);
618 qspi->clk = devm_clk_get(dev, NULL);
619 if (IS_ERR(qspi->clk))
620 return PTR_ERR(qspi->clk);
622 qspi->clk_rate = clk_get_rate(qspi->clk);
626 ret = clk_prepare_enable(qspi->clk);
628 dev_err(dev, "can not enable the clock\n");
632 rstc = devm_reset_control_get(dev, NULL);
634 reset_control_assert(rstc);
636 reset_control_deassert(rstc);
640 platform_set_drvdata(pdev, qspi);
641 mutex_init(&qspi->lock);
643 for_each_available_child_of_node(dev->of_node, flash_np) {
644 ret = stm32_qspi_flash_setup(qspi, flash_np);
646 dev_err(dev, "unable to setup flash chip\n");
654 mutex_destroy(&qspi->lock);
655 stm32_qspi_mtd_free(qspi);
657 clk_disable_unprepare(qspi->clk);
661 static int stm32_qspi_remove(struct platform_device *pdev)
663 struct stm32_qspi *qspi = platform_get_drvdata(pdev);
666 writel_relaxed(0, qspi->io_base + QUADSPI_CR);
668 stm32_qspi_mtd_free(qspi);
669 mutex_destroy(&qspi->lock);
671 clk_disable_unprepare(qspi->clk);
675 static const struct of_device_id stm32_qspi_match[] = {
676 {.compatible = "st,stm32f469-qspi"},
679 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
681 static struct platform_driver stm32_qspi_driver = {
682 .probe = stm32_qspi_probe,
683 .remove = stm32_qspi_remove,
685 .name = "stm32-quadspi",
686 .of_match_table = stm32_qspi_match,
689 module_platform_driver(stm32_qspi_driver);
691 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
692 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
693 MODULE_LICENSE("GPL v2");