drivers/mxc/ipu3/ipu_common.c

   1 /*
   2  * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /*!
  15  * @file ipu_common.c
  16  *
  17  * @brief This file contains the IPU driver common API functions.
  18  *
  19  * @ingroup IPU
  20  */
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/err.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/irqdesc.h>
  31 #include <linux/clk.h>
  32 #include <mach/clock.h>
  33 #include <mach/hardware.h>
  34 #include <mach/ipu-v3.h>
  35 #include <mach/devices-common.h>
  36 #include <asm/cacheflush.h>
  37 #include <linux/delay.h>
  38
  39 #include "ipu_prv.h"
  40 #include "ipu_regs.h"
  41 #include "ipu_param_mem.h"
  42
  43 static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM];
  44 int g_ipu_hw_rev;
  45
  46 /* Static functions */
  47 static irqreturn_t ipu_irq_handler(int irq, void *desc);
  48
  49 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
  50 {
  51         return ((uint32_t) ch >> (6 * type)) & 0x3F;
  52 };
  53
  54 static inline int _ipu_is_ic_chan(uint32_t dma_chan)
  55 {
  56         return ((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) && (dma_chan != 18));
  57 }
  58
  59 static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
  60 {
  61         return (dma_chan == 14 || dma_chan == 15);
  62 }
  63
  64 /* Either DP BG or DP FG can be graphic window */
  65 static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
  66 {
  67         return (dma_chan == 23 || dma_chan == 27);
  68 }
  69
  70 static inline int _ipu_is_irt_chan(uint32_t dma_chan)
  71 {
  72         return ((dma_chan >= 45) && (dma_chan <= 50));
  73 }
  74
  75 static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
  76 {
  77         return ((dma_chan >= 23) && (dma_chan <= 29));
  78 }
  79
  80 static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
  81 {
  82         return ((dma_chan >= 0) && (dma_chan <= 3));
  83 }
  84
  85 static inline int _ipu_is_trb_chan(uint32_t dma_chan)
  86 {
  87         return (((dma_chan == 8) || (dma_chan == 9) ||
  88                  (dma_chan == 10) || (dma_chan == 13) ||
  89                  (dma_chan == 21) || (dma_chan == 23) ||
  90                  (dma_chan == 27) || (dma_chan == 28)) &&
  91                 (g_ipu_hw_rev >= 2));
  92 }
  93
  94 #define idma_is_valid(ch)       (ch != NO_DMA)
  95 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
  96 #define idma_is_set(ipu, reg, dma)      (ipu_idmac_read(ipu, reg(dma)) & idma_mask(dma))
  97 #define tri_cur_buf_mask(ch)    (idma_mask(ch*2) * 3)
  98 #define tri_cur_buf_shift(ch)   (ffs(idma_mask(ch*2)) - 1)
  99
 100 static int ipu_reset(struct ipu_soc *ipu)
 101 {
 102         int timeout = 1000;
 103
 104         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 105
 106         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 107                 if (!timeout--)
 108                         return -ETIME;
 109                 msleep(1);
 110         }
 111
 112         return 0;
 113 }
 114
 115 static int __devinit ipu_clk_setup_enable(struct ipu_soc *ipu,
 116                 struct platform_device *pdev)
 117 {
 118         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
 119         char ipu_clk[] = "ipu1_clk";
 120         char di0_clk[] = "ipu1_di0_clk";
 121         char di1_clk[] = "ipu1_di1_clk";
 122
 123         ipu_clk[3] += pdev->id;
 124         di0_clk[3] += pdev->id;
 125         di1_clk[3] += pdev->id;
 126
 127         ipu->ipu_clk = clk_get(ipu->dev, ipu_clk);
 128         if (IS_ERR(ipu->ipu_clk)) {
 129                 dev_err(ipu->dev, "clk_get failed");
 130                 return PTR_ERR(ipu->ipu_clk);
 131         }
 132         dev_dbg(ipu->dev, "ipu_clk = %lu\n", clk_get_rate(ipu->ipu_clk));
 133
 134         ipu->pixel_clk[0] = ipu_pixel_clk[0];
 135         ipu->pixel_clk[1] = ipu_pixel_clk[1];
 136
 137         ipu_lookups[0].clk = &ipu->pixel_clk[0];
 138         ipu_lookups[1].clk = &ipu->pixel_clk[1];
 139         clkdev_add(&ipu_lookups[0]);
 140         clkdev_add(&ipu_lookups[1]);
 141
 142         clk_debug_register(&ipu->pixel_clk[0]);
 143         clk_debug_register(&ipu->pixel_clk[1]);
 144
 145         clk_enable(ipu->ipu_clk);
 146
 147         clk_set_parent(&ipu->pixel_clk[0], ipu->ipu_clk);
 148         clk_set_parent(&ipu->pixel_clk[1], ipu->ipu_clk);
 149
 150         ipu->di_clk[0] = clk_get(ipu->dev, di0_clk);
 151         ipu->di_clk[1] = clk_get(ipu->dev, di1_clk);
 152
 153         ipu->csi_clk[0] = clk_get(ipu->dev, plat_data->csi_clk[0]);
 154         ipu->csi_clk[1] = clk_get(ipu->dev, plat_data->csi_clk[1]);
 155
 156         return 0;
 157 }
 158
 159 #if 0
 160 static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
 161 {
 162         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 163         const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
 164         u32 status;
 165         int i, line;
 166
 167         for (i = 0;; i++) {
 168                 if (int_reg[i] == 0)
 169                         break;
 170
 171                 status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
 172                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
 173
 174                 while ((line = ffs(status))) {
 175                         line--;
 176                         status &= ~(1UL << line);
 177                         line += ipu->irq_start + (int_reg[i] - 1) * 32;
 178                         generic_handle_irq(line);
 179                 }
 180
 181         }
 182 }
 183
 184 static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 185 {
 186         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 187         const int int_reg[] = { 5, 6, 9, 10, 0 };
 188         u32 status;
 189         int i, line;
 190
 191         for (i = 0;; i++) {
 192                 if (int_reg[i] == 0)
 193                         break;
 194
 195                 status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
 196                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
 197
 198                 while ((line = ffs(status))) {
 199                         line--;
 200                         status &= ~(1UL << line);
 201                         line += ipu->irq_start + (int_reg[i] - 1) * 32;
 202                         generic_handle_irq(line);
 203                 }
 204
 205         }
 206 }
 207
 208 static void ipu_ack_irq(struct irq_data *d)
 209 {
 210         struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
 211         unsigned int irq = d->irq - ipu->irq_start;
 212         unsigned long flags;
 213
 214         spin_lock_irqsave(&ipu->ipu_lock, flags);
 215         ipu_cm_write(ipu, 1 << (irq % 32), IPU_INT_STAT(irq / 32 + 1));
 216         spin_unlock_irqrestore(&ipu->ipu_lock, flags);
 217 }
 218
 219 static void ipu_unmask_irq(struct irq_data *d)
 220 {
 221         struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
 222         unsigned int irq = d->irq - ipu->irq_start;
 223         unsigned long flags;
 224         u32 reg;
 225
 226         spin_lock_irqsave(&ipu->ipu_lock, flags);
 227         reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
 228         reg |= 1 << (irq % 32);
 229         ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
 230         spin_unlock_irqrestore(&ipu->ipu_lock, flags);
 231 }
 232
 233 static void ipu_mask_irq(struct irq_data *d)
 234 {
 235         struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
 236         unsigned int irq = d->irq - ipu->irq_start;
 237         unsigned long flags;
 238         u32 reg;
 239
 240         spin_lock_irqsave(&ipu->ipu_lock, flags);
 241         reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
 242         reg &= ~(1 << (irq % 32));
 243         ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
 244         spin_unlock_irqrestore(&ipu->ipu_lock, flags);
 245 }
 246
 247 static struct irq_chip ipu_irq_chip = {
 248         .name = "IPU",
 249         .irq_ack = ipu_ack_irq,
 250         .irq_mask = ipu_mask_irq,
 251         .irq_unmask = ipu_unmask_irq,
 252 };
 253
 254 static void __devinit ipu_irq_setup(struct ipu_soc *ipu)
 255 {
 256         int i;
 257
 258         for (i = ipu->irq_start; i < ipu->irq_start + MX5_IPU_IRQS; i++) {
 259                 irq_set_chip_and_handler(i, &ipu_irq_chip, handle_level_irq);
 260                 set_irq_flags(i, IRQF_VALID);
 261                 irq_set_chip_data(i, ipu);
 262         }
 263
 264         irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
 265         irq_set_handler_data(ipu->irq_sync, ipu);
 266         irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
 267         irq_set_handler_data(ipu->irq_err, ipu);
 268 }
 269
 270 int ipu_request_irq(struct ipu_soc *ipu, unsigned int irq,
 271                 irq_handler_t handler, unsigned long flags,
 272                 const char *name, void *dev)
 273 {
 274         return request_irq(ipu->irq_start + irq, handler, flags, name, dev);
 275 }
 276 EXPORT_SYMBOL_GPL(ipu_request_irq);
 277
 278 void ipu_enable_irq(struct ipu_soc *ipu, unsigned int irq)
 279 {
 280         return enable_irq(ipu->irq_start + irq);
 281 }
 282 EXPORT_SYMBOL_GPL(ipu_disable_irq);
 283
 284 void ipu_disable_irq(struct ipu_soc *ipu, unsigned int irq)
 285 {
 286         return disable_irq(ipu->irq_start + irq);
 287 }
 288 EXPORT_SYMBOL_GPL(ipu_disable_irq);
 289
 290 void ipu_free_irq(struct ipu_soc *ipu, unsigned int irq, void *dev_id)
 291 {
 292         free_irq(ipu->irq_start + irq, dev_id);
 293 }
 294 EXPORT_SYMBOL_GPL(ipu_free_irq);
 295
 296 static irqreturn_t ipu_completion_handler(int irq, void *dev)
 297 {
 298         struct completion *completion = dev;
 299
 300         complete(completion);
 301         return IRQ_HANDLED;
 302 }
 303
 304 int ipu_wait_for_interrupt(struct ipu_soc *ipu, int interrupt, int timeout_ms)
 305 {
 306         DECLARE_COMPLETION_ONSTACK(completion);
 307         int ret;
 308
 309         ret = ipu_request_irq(ipu, interrupt, ipu_completion_handler,
 310                         0, NULL, &completion);
 311         if (ret) {
 312                 dev_err(ipu->dev,
 313                         "ipu request irq %d fail\n", interrupt);
 314                 return ret;
 315         }
 316
 317         ret = wait_for_completion_timeout(&completion,
 318                         msecs_to_jiffies(timeout_ms));
 319
 320         ipu_free_irq(ipu, interrupt, &completion);
 321
 322         return ret > 0 ? 0 : -ETIMEDOUT;
 323 }
 324 EXPORT_SYMBOL_GPL(ipu_wait_for_interrupt);
 325 #endif
 326
 327 struct ipu_soc *ipu_get_soc(int id)
 328 {
 329         if (id >= MXC_IPU_MAX_NUM)
 330                 return ERR_PTR(-ENODEV);
 331         else if (!ipu_array[id].online)
 332                 return ERR_PTR(-ENODEV);
 333         else
 334                 return &(ipu_array[id]);
 335 }
 336 EXPORT_SYMBOL_GPL(ipu_get_soc);
 337
 338 void _ipu_lock(struct ipu_soc *ipu)
 339 {
 340         /*TODO:remove in_irq() condition after v4l2 driver rewrite*/
 341         if (!in_irq() && !in_softirq())
 342                 mutex_lock(&ipu->mutex_lock);
 343 }
 344
 345 void _ipu_unlock(struct ipu_soc *ipu)
 346 {
 347         /*TODO:remove in_irq() condition after v4l2 driver rewrite*/
 348         if (!in_irq() && !in_softirq())
 349                 mutex_unlock(&ipu->mutex_lock);
 350 }
 351
 352 void _ipu_get(struct ipu_soc *ipu)
 353 {
 354         if (atomic_inc_return(&ipu->ipu_use_count) == 1)
 355                 clk_enable(ipu->ipu_clk);
 356 }
 357
 358 void _ipu_put(struct ipu_soc *ipu)
 359 {
 360         if (atomic_dec_return(&ipu->ipu_use_count) == 0)
 361                 clk_disable(ipu->ipu_clk);
 362 }
 363
 364 /*!
 365  * This function is called by the driver framework to initialize the IPU
 366  * hardware.
 367  *
 368  * @param       dev     The device structure for the IPU passed in by the
 369  *                      driver framework.
 370  *
 371  * @return      Returns 0 on success or negative error code on error
 372  */
 373 static int __devinit ipu_probe(struct platform_device *pdev)
 374 {
 375         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
 376         struct ipu_soc *ipu;
 377         struct resource *res;
 378         unsigned long ipu_base;
 379         int ret = 0;
 380
 381         if (pdev->id >= MXC_IPU_MAX_NUM)
 382                 return -ENODEV;
 383
 384         ipu = &ipu_array[pdev->id];
 385         memset(ipu, 0, sizeof(struct ipu_soc));
 386
 387         spin_lock_init(&ipu->spin_lock);
 388         mutex_init(&ipu->mutex_lock);
 389         atomic_set(&ipu->ipu_use_count, 0);
 390
 391         g_ipu_hw_rev = plat_data->rev;
 392
 393         ipu->dev = &pdev->dev;
 394
 395         if (plat_data->init)
 396                 plat_data->init(pdev->id);
 397
 398         ipu->irq_sync = platform_get_irq(pdev, 0);
 399         ipu->irq_err = platform_get_irq(pdev, 1);
 400         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 401
 402         if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
 403                 ret = -ENODEV;
 404                 goto failed_get_res;
 405         }
 406
 407         if (request_irq(ipu->irq_sync, ipu_irq_handler, 0, pdev->name, ipu) != 0) {
 408                 dev_err(ipu->dev, "request SYNC interrupt failed\n");
 409                 ret = -EBUSY;
 410                 goto failed_req_irq_sync;
 411         }
 412         /* Some platforms have 2 IPU interrupts */
 413         if (ipu->irq_err >= 0) {
 414                 if (request_irq
 415                     (ipu->irq_err, ipu_irq_handler, 0, pdev->name, ipu) != 0) {
 416                         dev_err(ipu->dev, "request ERR interrupt failed\n");
 417                         ret = -EBUSY;
 418                         goto failed_req_irq_err;
 419                 }
 420         }
 421
 422         ipu_base = res->start;
 423         /* base fixup */
 424         if (g_ipu_hw_rev == 4)  /* IPUv3H */
 425                 ipu_base += IPUV3H_REG_BASE;
 426         else if (g_ipu_hw_rev == 3)     /* IPUv3M */
 427                 ipu_base += IPUV3M_REG_BASE;
 428         else                    /* IPUv3D, v3E, v3EX */
 429                 ipu_base += IPUV3DEX_REG_BASE;
 430
 431         ipu->cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
 432         ipu->ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
 433         ipu->idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
 434         /* DP Registers are accessed thru the SRM */
 435         ipu->dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
 436         ipu->dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
 437         ipu->dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
 438         ipu->di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
 439         ipu->di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
 440         ipu->smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
 441         ipu->csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
 442         ipu->csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
 443         ipu->cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
 444         ipu->tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K);
 445         ipu->dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
 446         ipu->vdi_reg = ioremap(ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
 447         ipu->disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K);
 448
 449         if (!ipu->cm_reg || !ipu->ic_reg || !ipu->idmac_reg ||
 450                 !ipu->dp_reg || !ipu->dc_reg || !ipu->dmfc_reg ||
 451                 !ipu->di_reg[0] || !ipu->di_reg[1] || !ipu->smfc_reg ||
 452                 !ipu->csi_reg[0] || !ipu->csi_reg[1] || !ipu->cpmem_base ||
 453                 !ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->disp_base[1]
 454                 || !ipu->vdi_reg) {
 455                 ret = -ENOMEM;
 456                 goto failed_ioremap;
 457         }
 458
 459         dev_dbg(ipu->dev, "IPU CM Regs = %p\n", ipu->cm_reg);
 460         dev_dbg(ipu->dev, "IPU IC Regs = %p\n", ipu->ic_reg);
 461         dev_dbg(ipu->dev, "IPU IDMAC Regs = %p\n", ipu->idmac_reg);
 462         dev_dbg(ipu->dev, "IPU DP Regs = %p\n", ipu->dp_reg);
 463         dev_dbg(ipu->dev, "IPU DC Regs = %p\n", ipu->dc_reg);
 464         dev_dbg(ipu->dev, "IPU DMFC Regs = %p\n", ipu->dmfc_reg);
 465         dev_dbg(ipu->dev, "IPU DI0 Regs = %p\n", ipu->di_reg[0]);
 466         dev_dbg(ipu->dev, "IPU DI1 Regs = %p\n", ipu->di_reg[1]);
 467         dev_dbg(ipu->dev, "IPU SMFC Regs = %p\n", ipu->smfc_reg);
 468         dev_dbg(ipu->dev, "IPU CSI0 Regs = %p\n", ipu->csi_reg[0]);
 469         dev_dbg(ipu->dev, "IPU CSI1 Regs = %p\n", ipu->csi_reg[1]);
 470         dev_dbg(ipu->dev, "IPU CPMem = %p\n", ipu->cpmem_base);
 471         dev_dbg(ipu->dev, "IPU TPMem = %p\n", ipu->tpmem_base);
 472         dev_dbg(ipu->dev, "IPU DC Template Mem = %p\n", ipu->dc_tmpl_reg);
 473         dev_dbg(ipu->dev, "IPU Display Region 1 Mem = %p\n", ipu->disp_base[1]);
 474         dev_dbg(ipu->dev, "IPU VDI Regs = %p\n", ipu->vdi_reg);
 475
 476         ret = ipu_clk_setup_enable(ipu, pdev);
 477         if (ret < 0) {
 478                 dev_err(ipu->dev, "ipu clk setup failed\n");
 479                 goto failed_clk_setup;
 480         }
 481
 482         platform_set_drvdata(pdev, ipu);
 483
 484         ipu_reset(ipu);
 485
 486         ipu_disp_init(ipu);
 487
 488         /* Set sync refresh channels and CSI->mem channel as high priority */
 489         ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
 490
 491         /* Set MCU_T to divide MCU access window into 2 */
 492         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 493
 494         clk_disable(ipu->ipu_clk);
 495
 496         register_ipu_device(ipu, pdev->id);
 497
 498         ipu->online = true;
 499
 500         return ret;
 501
 502 failed_clk_setup:
 503         iounmap(ipu->cm_reg);
 504         iounmap(ipu->ic_reg);
 505         iounmap(ipu->idmac_reg);
 506         iounmap(ipu->dc_reg);
 507         iounmap(ipu->dp_reg);
 508         iounmap(ipu->dmfc_reg);
 509         iounmap(ipu->di_reg[0]);
 510         iounmap(ipu->di_reg[1]);
 511         iounmap(ipu->smfc_reg);
 512         iounmap(ipu->csi_reg[0]);
 513         iounmap(ipu->csi_reg[1]);
 514         iounmap(ipu->cpmem_base);
 515         iounmap(ipu->tpmem_base);
 516         iounmap(ipu->dc_tmpl_reg);
 517         iounmap(ipu->disp_base[1]);
 518         iounmap(ipu->vdi_reg);
 519 failed_ioremap:
 520         if (ipu->irq_sync)
 521                 free_irq(ipu->irq_err, ipu);
 522 failed_req_irq_err:
 523         free_irq(ipu->irq_sync, ipu);
 524 failed_req_irq_sync:
 525 failed_get_res:
 526         return ret;
 527 }
 528
 529 int __devexit ipu_remove(struct platform_device *pdev)
 530 {
 531         struct ipu_soc *ipu = platform_get_drvdata(pdev);
 532
 533         unregister_ipu_device(ipu, pdev->id);
 534
 535         if (ipu->irq_sync)
 536                 free_irq(ipu->irq_sync, ipu);
 537         if (ipu->irq_err)
 538                 free_irq(ipu->irq_err, ipu);
 539
 540         clk_put(ipu->ipu_clk);
 541
 542         iounmap(ipu->cm_reg);
 543         iounmap(ipu->ic_reg);
 544         iounmap(ipu->idmac_reg);
 545         iounmap(ipu->dc_reg);
 546         iounmap(ipu->dp_reg);
 547         iounmap(ipu->dmfc_reg);
 548         iounmap(ipu->di_reg[0]);
 549         iounmap(ipu->di_reg[1]);
 550         iounmap(ipu->smfc_reg);
 551         iounmap(ipu->csi_reg[0]);
 552         iounmap(ipu->csi_reg[1]);
 553         iounmap(ipu->cpmem_base);
 554         iounmap(ipu->tpmem_base);
 555         iounmap(ipu->dc_tmpl_reg);
 556         iounmap(ipu->disp_base[1]);
 557         iounmap(ipu->vdi_reg);
 558
 559         return 0;
 560 }
 561
 562 void ipu_dump_registers(struct ipu_soc *ipu)
 563 {
 564         dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", ipu_cm_read(ipu, IPU_CONF));
 565         dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", ipu_idmac_read(ipu, IDMAC_CONF));
 566         dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
 567                ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
 568         dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
 569                ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
 570         dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
 571                ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
 572         dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
 573                ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
 574         dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
 575                ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
 576         dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
 577                ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
 578         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
 579                ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
 580         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
 581                ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
 582         if (g_ipu_hw_rev >= 2) {
 583                 dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
 584                        ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0)));
 585                 dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
 586                        ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32)));
 587         }
 588         dev_dbg(ipu->dev, "DMFC_WR_CHAN = \t0x%08X\n",
 589                ipu_dmfc_read(ipu, DMFC_WR_CHAN));
 590         dev_dbg(ipu->dev, "DMFC_WR_CHAN_DEF = \t0x%08X\n",
 591                ipu_dmfc_read(ipu, DMFC_WR_CHAN_DEF));
 592         dev_dbg(ipu->dev, "DMFC_DP_CHAN = \t0x%08X\n",
 593                ipu_dmfc_read(ipu, DMFC_DP_CHAN));
 594         dev_dbg(ipu->dev, "DMFC_DP_CHAN_DEF = \t0x%08X\n",
 595                ipu_dmfc_read(ipu, DMFC_DP_CHAN_DEF));
 596         dev_dbg(ipu->dev, "DMFC_IC_CTRL = \t0x%08X\n",
 597                ipu_dmfc_read(ipu, DMFC_IC_CTRL));
 598         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
 599                ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
 600         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
 601                ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
 602         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
 603                ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
 604         dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
 605                ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
 606 }
 607
 608 /*!
 609  * This function is called to initialize a logical IPU channel.
 610  *
 611  * @param       ipu     ipu handler
 612  * @param       channel Input parameter for the logical channel ID to init.
 613  *
 614  * @param       params  Input parameter containing union of channel
 615  *                      initialization parameters.
 616  *
 617  * @return      Returns 0 on success or negative error code on fail
 618  */
 619 int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
 620 {
 621         int ret = 0;
 622         uint32_t ipu_conf;
 623         uint32_t reg;
 624
 625         dev_dbg(ipu->dev, "init channel = %d\n", IPU_CHAN_ID(channel));
 626
 627         _ipu_get(ipu);
 628
 629         _ipu_lock(ipu);
 630
 631         if (ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 632                 dev_warn(ipu->dev, "Warning: channel already initialized %d\n",
 633                         IPU_CHAN_ID(channel));
 634         }
 635
 636         ipu_conf = ipu_cm_read(ipu, IPU_CONF);
 637
 638         switch (channel) {
 639         case CSI_MEM0:
 640         case CSI_MEM1:
 641         case CSI_MEM2:
 642         case CSI_MEM3:
 643                 if (params->csi_mem.csi > 1) {
 644                         ret = -EINVAL;
 645                         goto err;
 646                 }
 647
 648                 if (params->csi_mem.interlaced)
 649                         ipu->chan_is_interlaced[channel_2_dma(channel,
 650                                 IPU_OUTPUT_BUFFER)] = true;
 651                 else
 652                         ipu->chan_is_interlaced[channel_2_dma(channel,
 653                                 IPU_OUTPUT_BUFFER)] = false;
 654
 655                 ipu->smfc_use_count++;
 656                 ipu->csi_channel[params->csi_mem.csi] = channel;
 657
 658                 /*SMFC setting*/
 659                 if (params->csi_mem.mipi_en) {
 660                         ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 661                                 params->csi_mem.csi));
 662                         _ipu_smfc_init(ipu, channel, params->csi_mem.mipi_id,
 663                                 params->csi_mem.csi);
 664                 } else {
 665                         ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 666                                 params->csi_mem.csi));
 667                         _ipu_smfc_init(ipu, channel, 0, params->csi_mem.csi);
 668                 }
 669
 670                 /*CSI data (include compander) dest*/
 671                 _ipu_csi_init(ipu, channel, params->csi_mem.csi);
 672                 break;
 673         case CSI_PRP_ENC_MEM:
 674                 if (params->csi_prp_enc_mem.csi > 1) {
 675                         ret = -EINVAL;
 676                         goto err;
 677                 }
 678                 if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
 679                         ret = -EINVAL;
 680                         goto err;
 681                 }
 682                 ipu->using_ic_dirct_ch = CSI_PRP_ENC_MEM;
 683
 684                 ipu->ic_use_count++;
 685                 ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel;
 686
 687                 /*Without SMFC, CSI only support parallel data source*/
 688                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 689                         params->csi_prp_enc_mem.csi));
 690
 691                 /*CSI0/1 feed into IC*/
 692                 ipu_conf &= ~IPU_CONF_IC_INPUT;
 693                 if (params->csi_prp_enc_mem.csi)
 694                         ipu_conf |= IPU_CONF_CSI_SEL;
 695                 else
 696                         ipu_conf &= ~IPU_CONF_CSI_SEL;
 697
 698                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
 699                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 700                 ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
 701
 702                 /*CSI data (include compander) dest*/
 703                 _ipu_csi_init(ipu, channel, params->csi_prp_enc_mem.csi);
 704                 _ipu_ic_init_prpenc(ipu, params, true);
 705                 break;
 706         case CSI_PRP_VF_MEM:
 707                 if (params->csi_prp_vf_mem.csi > 1) {
 708                         ret = -EINVAL;
 709                         goto err;
 710                 }
 711                 if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
 712                         ret = -EINVAL;
 713                         goto err;
 714                 }
 715                 ipu->using_ic_dirct_ch = CSI_PRP_VF_MEM;
 716
 717                 ipu->ic_use_count++;
 718                 ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel;
 719
 720                 /*Without SMFC, CSI only support parallel data source*/
 721                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 722                         params->csi_prp_vf_mem.csi));
 723
 724                 /*CSI0/1 feed into IC*/
 725                 ipu_conf &= ~IPU_CONF_IC_INPUT;
 726                 if (params->csi_prp_vf_mem.csi)
 727                         ipu_conf |= IPU_CONF_CSI_SEL;
 728                 else
 729                         ipu_conf &= ~IPU_CONF_CSI_SEL;
 730
 731                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
 732                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 733                 ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 734
 735                 /*CSI data (include compander) dest*/
 736                 _ipu_csi_init(ipu, channel, params->csi_prp_vf_mem.csi);
 737                 _ipu_ic_init_prpvf(ipu, params, true);
 738                 break;
 739         case MEM_PRP_VF_MEM:
 740                 ipu->ic_use_count++;
 741                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 742                 ipu_cm_write(ipu, reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 743
 744                 if (params->mem_prp_vf_mem.graphics_combine_en)
 745                         ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
 746                 if (params->mem_prp_vf_mem.alpha_chan_en)
 747                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 748
 749                 _ipu_ic_init_prpvf(ipu, params, false);
 750                 break;
 751         case MEM_VDI_PRP_VF_MEM:
 752                 if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
 753                      (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
 754                         ret = -EINVAL;
 755                         goto err;
 756                 }
 757                 ipu->using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
 758                 ipu->ic_use_count++;
 759                 ipu->vdi_use_count++;
 760                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 761                 reg &= ~FS_VDI_SRC_SEL_MASK;
 762                 ipu_cm_write(ipu, reg , IPU_FS_PROC_FLOW1);
 763
 764                 if (params->mem_prp_vf_mem.graphics_combine_en)
 765                         ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
 766                 _ipu_ic_init_prpvf(ipu, params, false);
 767                 _ipu_vdi_init(ipu, channel, params);
 768                 break;
 769         case MEM_VDI_PRP_VF_MEM_P:
 770                 _ipu_vdi_init(ipu, channel, params);
 771                 break;
 772         case MEM_VDI_PRP_VF_MEM_N:
 773                 _ipu_vdi_init(ipu, channel, params);
 774                 break;
 775         case MEM_ROT_VF_MEM:
 776                 ipu->ic_use_count++;
 777                 ipu->rot_use_count++;
 778                 _ipu_ic_init_rotate_vf(ipu, params);
 779                 break;
 780         case MEM_PRP_ENC_MEM:
 781                 ipu->ic_use_count++;
 782                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 783                 ipu_cm_write(ipu, reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
 784                 _ipu_ic_init_prpenc(ipu, params, false);
 785                 break;
 786         case MEM_ROT_ENC_MEM:
 787                 ipu->ic_use_count++;
 788                 ipu->rot_use_count++;
 789                 _ipu_ic_init_rotate_enc(ipu, params);
 790                 break;
 791         case MEM_PP_MEM:
 792                 if (params->mem_pp_mem.graphics_combine_en)
 793                         ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
 794                 if (params->mem_pp_mem.alpha_chan_en)
 795                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 796                 _ipu_ic_init_pp(ipu, params);
 797                 ipu->ic_use_count++;
 798                 break;
 799         case MEM_ROT_PP_MEM:
 800                 _ipu_ic_init_rotate_pp(ipu, params);
 801                 ipu->ic_use_count++;
 802                 ipu->rot_use_count++;
 803                 break;
 804         case MEM_DC_SYNC:
 805                 if (params->mem_dc_sync.di > 1) {
 806                         ret = -EINVAL;
 807                         goto err;
 808                 }
 809
 810                 ipu->dc_di_assignment[1] = params->mem_dc_sync.di;
 811                 _ipu_dc_init(ipu, 1, params->mem_dc_sync.di,
 812                              params->mem_dc_sync.interlaced,
 813                              params->mem_dc_sync.out_pixel_fmt);
 814                 ipu->di_use_count[params->mem_dc_sync.di]++;
 815                 ipu->dc_use_count++;
 816                 ipu->dmfc_use_count++;
 817                 break;
 818         case MEM_BG_SYNC:
 819                 if (params->mem_dp_bg_sync.di > 1) {
 820                         ret = -EINVAL;
 821                         goto err;
 822                 }
 823
 824                 if (params->mem_dp_bg_sync.alpha_chan_en)
 825                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 826
 827                 ipu->dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 828                 _ipu_dp_init(ipu, channel, params->mem_dp_bg_sync.in_pixel_fmt,
 829                              params->mem_dp_bg_sync.out_pixel_fmt);
 830                 _ipu_dc_init(ipu, 5, params->mem_dp_bg_sync.di,
 831                              params->mem_dp_bg_sync.interlaced,
 832                              params->mem_dp_bg_sync.out_pixel_fmt);
 833                 ipu->di_use_count[params->mem_dp_bg_sync.di]++;
 834                 ipu->dc_use_count++;
 835                 ipu->dp_use_count++;
 836                 ipu->dmfc_use_count++;
 837                 break;
 838         case MEM_FG_SYNC:
 839                 _ipu_dp_init(ipu, channel, params->mem_dp_fg_sync.in_pixel_fmt,
 840                              params->mem_dp_fg_sync.out_pixel_fmt);
 841
 842                 if (params->mem_dp_fg_sync.alpha_chan_en)
 843                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 844
 845                 ipu->dc_use_count++;
 846                 ipu->dp_use_count++;
 847                 ipu->dmfc_use_count++;
 848                 break;
 849         case DIRECT_ASYNC0:
 850                 if (params->direct_async.di > 1) {
 851                         ret = -EINVAL;
 852                         goto err;
 853                 }
 854
 855                 ipu->dc_di_assignment[8] = params->direct_async.di;
 856                 _ipu_dc_init(ipu, 8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 857                 ipu->di_use_count[params->direct_async.di]++;
 858                 ipu->dc_use_count++;
 859                 break;
 860         case DIRECT_ASYNC1:
 861                 if (params->direct_async.di > 1) {
 862                         ret = -EINVAL;
 863                         goto err;
 864                 }
 865
 866                 ipu->dc_di_assignment[9] = params->direct_async.di;
 867                 _ipu_dc_init(ipu, 9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 868                 ipu->di_use_count[params->direct_async.di]++;
 869                 ipu->dc_use_count++;
 870                 break;
 871         default:
 872                 dev_err(ipu->dev, "Missing channel initialization\n");
 873                 break;
 874         }
 875
 876         ipu->channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 877
 878         ipu_cm_write(ipu, ipu_conf, IPU_CONF);
 879
 880 err:
 881         _ipu_unlock(ipu);
 882         return ret;
 883 }
 884 EXPORT_SYMBOL(ipu_init_channel);
 885
 886 /*!
 887  * This function is called to uninitialize a logical IPU channel.
 888  *
 889  * @param       ipu     ipu handler
 890  * @param       channel Input parameter for the logical channel ID to uninit.
 891  */
 892 void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel)
 893 {
 894         uint32_t reg;
 895         uint32_t in_dma, out_dma = 0;
 896         uint32_t ipu_conf;
 897
 898         _ipu_lock(ipu);
 899
 900         if ((ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 901                 dev_err(ipu->dev, "Channel already uninitialized %d\n",
 902                         IPU_CHAN_ID(channel));
 903                 _ipu_unlock(ipu);
 904                 return;
 905         }
 906
 907         /* Make sure channel is disabled */
 908         /* Get input and output dma channels */
 909         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 910         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 911
 912         if (idma_is_set(ipu, IDMAC_CHA_EN, in_dma) ||
 913             idma_is_set(ipu, IDMAC_CHA_EN, out_dma)) {
 914                 dev_err(ipu->dev,
 915                         "Channel %d is not disabled, disable first\n",
 916                         IPU_CHAN_ID(channel));
 917                 _ipu_unlock(ipu);
 918                 return;
 919         }
 920
 921         ipu_conf = ipu_cm_read(ipu, IPU_CONF);
 922
 923         /* Reset the double buffer */
 924         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(in_dma));
 925         ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 926         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(out_dma));
 927         ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 928
 929         /* Reset the triple buffer */
 930         reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(in_dma));
 931         ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
 932         reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(out_dma));
 933         ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
 934
 935         if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
 936                 ipu->sec_chan_en[IPU_CHAN_ID(channel)] = false;
 937                 ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = false;
 938         }
 939
 940         switch (channel) {
 941         case CSI_MEM0:
 942         case CSI_MEM1:
 943         case CSI_MEM2:
 944         case CSI_MEM3:
 945                 ipu->smfc_use_count--;
 946                 if (ipu->csi_channel[0] == channel) {
 947                         ipu->csi_channel[0] = CHAN_NONE;
 948                 } else if (ipu->csi_channel[1] == channel) {
 949                         ipu->csi_channel[1] = CHAN_NONE;
 950                 }
 951                 break;
 952         case CSI_PRP_ENC_MEM:
 953                 ipu->ic_use_count--;
 954                 if (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)
 955                         ipu->using_ic_dirct_ch = 0;
 956                 _ipu_ic_uninit_prpenc(ipu);
 957                 if (ipu->csi_channel[0] == channel) {
 958                         ipu->csi_channel[0] = CHAN_NONE;
 959                 } else if (ipu->csi_channel[1] == channel) {
 960                         ipu->csi_channel[1] = CHAN_NONE;
 961                 }
 962                 break;
 963         case CSI_PRP_VF_MEM:
 964                 ipu->ic_use_count--;
 965                 if (ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM)
 966                         ipu->using_ic_dirct_ch = 0;
 967                 _ipu_ic_uninit_prpvf(ipu);
 968                 if (ipu->csi_channel[0] == channel) {
 969                         ipu->csi_channel[0] = CHAN_NONE;
 970                 } else if (ipu->csi_channel[1] == channel) {
 971                         ipu->csi_channel[1] = CHAN_NONE;
 972                 }
 973                 break;
 974         case MEM_PRP_VF_MEM:
 975                 ipu->ic_use_count--;
 976                 _ipu_ic_uninit_prpvf(ipu);
 977                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 978                 ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 979                 break;
 980         case MEM_VDI_PRP_VF_MEM:
 981                 ipu->ic_use_count--;
 982                 ipu->vdi_use_count--;
 983                 if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
 984                         ipu->using_ic_dirct_ch = 0;
 985                 _ipu_ic_uninit_prpvf(ipu);
 986                 _ipu_vdi_uninit(ipu);
 987                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 988                 ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 989                 break;
 990         case MEM_VDI_PRP_VF_MEM_P:
 991         case MEM_VDI_PRP_VF_MEM_N:
 992                 break;
 993         case MEM_ROT_VF_MEM:
 994                 ipu->rot_use_count--;
 995                 ipu->ic_use_count--;
 996                 _ipu_ic_uninit_rotate_vf(ipu);
 997                 break;
 998         case MEM_PRP_ENC_MEM:
 999                 ipu->ic_use_count--;
1000                 _ipu_ic_uninit_prpenc(ipu);
1001                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1002                 ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
1003                 break;
1004         case MEM_ROT_ENC_MEM:
1005                 ipu->rot_use_count--;
1006                 ipu->ic_use_count--;
1007                 _ipu_ic_uninit_rotate_enc(ipu);
1008                 break;
1009         case MEM_PP_MEM:
1010                 ipu->ic_use_count--;
1011                 _ipu_ic_uninit_pp(ipu);
1012                 break;
1013         case MEM_ROT_PP_MEM:
1014                 ipu->rot_use_count--;
1015                 ipu->ic_use_count--;
1016                 _ipu_ic_uninit_rotate_pp(ipu);
1017                 break;
1018         case MEM_DC_SYNC:
1019                 _ipu_dc_uninit(ipu, 1);
1020                 ipu->di_use_count[ipu->dc_di_assignment[1]]--;
1021                 ipu->dc_use_count--;
1022                 ipu->dmfc_use_count--;
1023                 break;
1024         case MEM_BG_SYNC:
1025                 _ipu_dp_uninit(ipu, channel);
1026                 _ipu_dc_uninit(ipu, 5);
1027                 ipu->di_use_count[ipu->dc_di_assignment[5]]--;
1028                 ipu->dc_use_count--;
1029                 ipu->dp_use_count--;
1030                 ipu->dmfc_use_count--;
1031                 break;
1032         case MEM_FG_SYNC:
1033                 _ipu_dp_uninit(ipu, channel);
1034                 ipu->dc_use_count--;
1035                 ipu->dp_use_count--;
1036                 ipu->dmfc_use_count--;
1037                 break;
1038         case DIRECT_ASYNC0:
1039                 _ipu_dc_uninit(ipu, 8);
1040                 ipu->di_use_count[ipu->dc_di_assignment[8]]--;
1041                 ipu->dc_use_count--;
1042                 break;
1043         case DIRECT_ASYNC1:
1044                 _ipu_dc_uninit(ipu, 9);
1045                 ipu->di_use_count[ipu->dc_di_assignment[9]]--;
1046                 ipu->dc_use_count--;
1047                 break;
1048         default:
1049                 break;
1050         }
1051
1052         if (ipu->ic_use_count == 0)
1053                 ipu_conf &= ~IPU_CONF_IC_EN;
1054         if (ipu->vdi_use_count == 0) {
1055                 ipu_conf &= ~IPU_CONF_ISP_EN;
1056                 ipu_conf &= ~IPU_CONF_VDI_EN;
1057                 ipu_conf &= ~IPU_CONF_IC_INPUT;
1058         }
1059         if (ipu->rot_use_count == 0)
1060                 ipu_conf &= ~IPU_CONF_ROT_EN;
1061         if (ipu->dc_use_count == 0)
1062                 ipu_conf &= ~IPU_CONF_DC_EN;
1063         if (ipu->dp_use_count == 0)
1064                 ipu_conf &= ~IPU_CONF_DP_EN;
1065         if (ipu->dmfc_use_count == 0)
1066                 ipu_conf &= ~IPU_CONF_DMFC_EN;
1067         if (ipu->di_use_count[0] == 0) {
1068                 ipu_conf &= ~IPU_CONF_DI0_EN;
1069         }
1070         if (ipu->di_use_count[1] == 0) {
1071                 ipu_conf &= ~IPU_CONF_DI1_EN;
1072         }
1073         if (ipu->smfc_use_count == 0)
1074                 ipu_conf &= ~IPU_CONF_SMFC_EN;
1075
1076         ipu_cm_write(ipu, ipu_conf, IPU_CONF);
1077
1078         ipu->channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
1079
1080         _ipu_unlock(ipu);
1081
1082         _ipu_put(ipu);
1083
1084         WARN_ON(ipu->ic_use_count < 0);
1085         WARN_ON(ipu->vdi_use_count < 0);
1086         WARN_ON(ipu->rot_use_count < 0);
1087         WARN_ON(ipu->dc_use_count < 0);
1088         WARN_ON(ipu->dp_use_count < 0);
1089         WARN_ON(ipu->dmfc_use_count < 0);
1090         WARN_ON(ipu->smfc_use_count < 0);
1091 }
1092 EXPORT_SYMBOL(ipu_uninit_channel);
1093
1094 /*!
1095  * This function is called to initialize buffer(s) for logical IPU channel.
1096  *
1097  * @param       ipu             ipu handler
1098  *
1099  * @param       channel         Input parameter for the logical channel ID.
1100  *
1101  * @param       type            Input parameter which buffer to initialize.
1102  *
1103  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1104  *                              Pixel format is a FOURCC ASCII code.
1105  *
1106  * @param       width           Input parameter for width of buffer in pixels.
1107  *
1108  * @param       height          Input parameter for height of buffer in pixels.
1109  *
1110  * @param       stride          Input parameter for stride length of buffer
1111  *                              in pixels.
1112  *
1113  * @param       rot_mode        Input parameter for rotation setting of buffer.
1114  *                              A rotation setting other than
1115  *                              IPU_ROTATE_VERT_FLIP
1116  *                              should only be used for input buffers of
1117  *                              rotation channels.
1118  *
1119  * @param       phyaddr_0       Input parameter buffer 0 physical address.
1120  *
1121  * @param       phyaddr_1       Input parameter buffer 1 physical address.
1122  *                              Setting this to a value other than NULL enables
1123  *                              double buffering mode.
1124  *
1125  * @param       phyaddr_2       Input parameter buffer 2 physical address.
1126  *                              Setting this to a value other than NULL enables
1127  *                              triple buffering mode, phyaddr_1 should not be
1128  *                              NULL then.
1129  *
1130  * @param       u               private u offset for additional cropping,
1131  *                              zero if not used.
1132  *
1133  * @param       v               private v offset for additional cropping,
1134  *                              zero if not used.
1135  *
1136  * @return      Returns 0 on success or negative error code on fail
1137  */
1138 int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
1139                                 ipu_buffer_t type,
1140                                 uint32_t pixel_fmt,
1141                                 uint16_t width, uint16_t height,
1142                                 uint32_t stride,
1143                                 ipu_rotate_mode_t rot_mode,
1144                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
1145                                 dma_addr_t phyaddr_2,
1146                                 uint32_t u, uint32_t v)
1147 {
1148         uint32_t reg;
1149         uint32_t dma_chan;
1150         uint32_t burst_size;
1151
1152         dma_chan = channel_2_dma(channel, type);
1153         if (!idma_is_valid(dma_chan))
1154                 return -EINVAL;
1155
1156         if (stride < width * bytes_per_pixel(pixel_fmt))
1157                 stride = width * bytes_per_pixel(pixel_fmt);
1158
1159         if (stride % 4) {
1160                 dev_err(ipu->dev,
1161                         "Stride not 32-bit aligned, stride = %d\n", stride);
1162                 return -EINVAL;
1163         }
1164         /* IC & IRT channels' width must be multiple of 8 pixels */
1165         if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
1166                 && (width % 8)) {
1167                 dev_err(ipu->dev, "Width must be 8 pixel multiple\n");
1168                 return -EINVAL;
1169         }
1170
1171         /* IPUv3EX and IPUv3M support triple buffer */
1172         if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
1173                 dev_err(ipu->dev, "Chan%d doesn't support triple buffer "
1174                                    "mode\n", dma_chan);
1175                 return -EINVAL;
1176         }
1177         if (!phyaddr_1 && phyaddr_2) {
1178                 dev_err(ipu->dev, "Chan%d's buf1 physical addr is NULL for "
1179                                    "triple buffer mode\n", dma_chan);
1180                 return -EINVAL;
1181         }
1182
1183         _ipu_lock(ipu);
1184
1185         /* Build parameter memory data for DMA channel */
1186         _ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, u, v, 0,
1187                            phyaddr_0, phyaddr_1, phyaddr_2);
1188
1189         /* Set correlative channel parameter of local alpha channel */
1190         if ((_ipu_is_ic_graphic_chan(dma_chan) ||
1191              _ipu_is_dp_graphic_chan(dma_chan)) &&
1192             (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
1193                 _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, true);
1194                 _ipu_ch_param_set_alpha_buffer_memory(ipu, dma_chan);
1195                 _ipu_ch_param_set_alpha_condition_read(ipu, dma_chan);
1196                 /* fix alpha width as 8 and burst size as 16*/
1197                 _ipu_ch_params_set_alpha_width(ipu, dma_chan, 8);
1198                 _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
1199         } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
1200                    ipu_pixel_format_has_alpha(pixel_fmt))
1201                 _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, false);
1202
1203         if (rot_mode)
1204                 _ipu_ch_param_set_rotation(ipu, dma_chan, rot_mode);
1205
1206         /* IC and ROT channels have restriction of 8 or 16 pix burst length */
1207         if (_ipu_is_ic_chan(dma_chan)) {
1208                 if ((width % 16) == 0)
1209                         _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
1210                 else
1211                         _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
1212         } else if (_ipu_is_irt_chan(dma_chan)) {
1213                 _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
1214                 _ipu_ch_param_set_block_mode(ipu, dma_chan);
1215         } else if (_ipu_is_dmfc_chan(dma_chan)) {
1216                 burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
1217                 _ipu_dmfc_set_wait4eot(ipu, dma_chan, width);
1218                 _ipu_dmfc_set_burst_size(ipu, dma_chan, burst_size);
1219         }
1220
1221         if (_ipu_disp_chan_is_interlaced(ipu, channel) ||
1222                 ipu->chan_is_interlaced[dma_chan])
1223                 _ipu_ch_param_set_interlaced_scan(ipu, dma_chan);
1224
1225         if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) {
1226                 burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
1227                 _ipu_ic_idma_init(ipu, dma_chan, width, height, burst_size,
1228                         rot_mode);
1229         } else if (_ipu_is_smfc_chan(dma_chan)) {
1230                 burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
1231                 if ((pixel_fmt == IPU_PIX_FMT_GENERIC) &&
1232                         ((_ipu_ch_param_get_bpp(ipu, dma_chan) == 5) ||
1233                         (_ipu_ch_param_get_bpp(ipu, dma_chan) == 3)))
1234                         burst_size = burst_size >> 4;
1235                 else
1236                         burst_size = burst_size >> 2;
1237                 _ipu_smfc_set_burst_size(ipu, channel, burst_size-1);
1238         }
1239
1240         /* AXI-id */
1241         if (idma_is_set(ipu, IDMAC_CHA_PRI, dma_chan)) {
1242                 unsigned reg = IDMAC_CH_LOCK_EN_1;
1243                 uint32_t value = 0;
1244                 if (cpu_is_mx53() || cpu_is_mx6q()) {
1245                         _ipu_ch_param_set_axi_id(ipu, dma_chan, 0);
1246                         switch (dma_chan) {
1247                         case 5:
1248                                 value = 0x3;
1249                                 break;
1250                         case 11:
1251                                 value = 0x3 << 2;
1252                                 break;
1253                         case 12:
1254                                 value = 0x3 << 4;
1255                                 break;
1256                         case 14:
1257                                 value = 0x3 << 6;
1258                                 break;
1259                         case 15:
1260                                 value = 0x3 << 8;
1261                                 break;
1262                         case 20:
1263                                 value = 0x3 << 10;
1264                                 break;
1265                         case 21:
1266                                 value = 0x3 << 12;
1267                                 break;
1268                         case 22:
1269                                 value = 0x3 << 14;
1270                                 break;
1271                         case 23:
1272                                 value = 0x3 << 16;
1273                                 break;
1274                         case 27:
1275                                 value = 0x3 << 18;
1276                                 break;
1277                         case 28:
1278                                 value = 0x3 << 20;
1279                                 break;
1280                         case 45:
1281                                 reg = IDMAC_CH_LOCK_EN_2;
1282                                 value = 0x3 << 0;
1283                                 break;
1284                         case 46:
1285                                 reg = IDMAC_CH_LOCK_EN_2;
1286                                 value = 0x3 << 2;
1287                                 break;
1288                         case 47:
1289                                 reg = IDMAC_CH_LOCK_EN_2;
1290                                 value = 0x3 << 4;
1291                                 break;
1292                         case 48:
1293                                 reg = IDMAC_CH_LOCK_EN_2;
1294                                 value = 0x3 << 6;
1295                                 break;
1296                         case 49:
1297                                 reg = IDMAC_CH_LOCK_EN_2;
1298                                 value = 0x3 << 8;
1299                                 break;
1300                         case 50:
1301                                 reg = IDMAC_CH_LOCK_EN_2;
1302                                 value = 0x3 << 10;
1303                                 break;
1304                         default:
1305                                 break;
1306                         }
1307                         value |= ipu_idmac_read(ipu, reg);
1308                         ipu_idmac_write(ipu, value, reg);
1309                 } else
1310                         _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
1311         } else {
1312                 if (cpu_is_mx6q())
1313                         _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
1314         }
1315
1316         _ipu_ch_param_dump(ipu, dma_chan);
1317
1318         if (phyaddr_2 && g_ipu_hw_rev >= 2) {
1319                 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
1320                 reg &= ~idma_mask(dma_chan);
1321                 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1322
1323                 reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
1324                 reg |= idma_mask(dma_chan);
1325                 ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1326
1327                 /* Set IDMAC third buffer's cpmem number */
1328                 /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
1329                 ipu_idmac_write(ipu, 0x00444047L, IDMAC_SUB_ADDR_4);
1330                 ipu_idmac_write(ipu, 0x46004241L, IDMAC_SUB_ADDR_3);
1331                 ipu_idmac_write(ipu, 0x00000045L, IDMAC_SUB_ADDR_1);
1332
1333                 /* Reset to buffer 0 */
1334                 ipu_cm_write(ipu, tri_cur_buf_mask(dma_chan),
1335                                 IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
1336         } else {
1337                 reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
1338                 reg &= ~idma_mask(dma_chan);
1339                 ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1340
1341                 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
1342                 if (phyaddr_1)
1343                         reg |= idma_mask(dma_chan);
1344                 else
1345                         reg &= ~idma_mask(dma_chan);
1346                 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1347
1348                 /* Reset to buffer 0 */
1349                 ipu_cm_write(ipu, idma_mask(dma_chan),
1350                                 IPU_CHA_CUR_BUF(dma_chan));
1351
1352         }
1353
1354         _ipu_unlock(ipu);
1355
1356         return 0;
1357 }
1358 EXPORT_SYMBOL(ipu_init_channel_buffer);
1359
1360 /*!
1361  * This function is called to update the physical address of a buffer for
1362  * a logical IPU channel.
1363  *
1364  * @param       ipu             ipu handler
1365  * @param       channel         Input parameter for the logical channel ID.
1366  *
1367  * @param       type            Input parameter which buffer to initialize.
1368  *
1369  * @param       bufNum          Input parameter for buffer number to update.
1370  *                              0 or 1 are the only valid values.
1371  *
1372  * @param       phyaddr         Input parameter buffer physical address.
1373  *
1374  * @return      This function returns 0 on success or negative error code on
1375  *              fail. This function will fail if the buffer is set to ready.
1376  */
1377 int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
1378                                 ipu_buffer_t type, uint32_t bufNum, dma_addr_t phyaddr)
1379 {
1380         uint32_t reg;
1381         int ret = 0;
1382         uint32_t dma_chan = channel_2_dma(channel, type);
1383
1384         if (dma_chan == IDMA_CHAN_INVALID)
1385                 return -EINVAL;
1386
1387         _ipu_lock(ipu);
1388
1389         if (bufNum == 0)
1390                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
1391         else if (bufNum == 1)
1392                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
1393         else
1394                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
1395
1396         if ((reg & idma_mask(dma_chan)) == 0)
1397                 _ipu_ch_param_set_buffer(ipu, dma_chan, bufNum, phyaddr);
1398         else
1399                 ret = -EACCES;
1400
1401         _ipu_unlock(ipu);
1402
1403         return ret;
1404 }
1405 EXPORT_SYMBOL(ipu_update_channel_buffer);
1406
1407
1408 /*!
1409  * This function is called to initialize a buffer for logical IPU channel.
1410  *
1411  * @param       ipu             ipu handler
1412  * @param       channel         Input parameter for the logical channel ID.
1413  *
1414  * @param       type            Input parameter which buffer to initialize.
1415  *
1416  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1417  *                              Pixel format is a FOURCC ASCII code.
1418  *
1419  * @param       width           Input parameter for width of buffer in pixels.
1420  *
1421  * @param       height          Input parameter for height of buffer in pixels.
1422  *
1423  * @param       stride          Input parameter for stride length of buffer
1424  *                              in pixels.
1425  *
1426  * @param       u               predefined private u offset for additional cropping,
1427  *                                                              zero if not used.
1428  *
1429  * @param       v               predefined private v offset for additional cropping,
1430  *                                                              zero if not used.
1431  *
1432  * @param                       vertical_offset vertical offset for Y coordinate
1433  *                                                              in the existed frame
1434  *
1435  *
1436  * @param                       horizontal_offset horizontal offset for X coordinate
1437  *                                                              in the existed frame
1438  *
1439  *
1440  * @return      Returns 0 on success or negative error code on fail
1441  *              This function will fail if any buffer is set to ready.
1442  */
1443
1444 int32_t ipu_update_channel_offset(struct ipu_soc *ipu,
1445                                 ipu_channel_t channel, ipu_buffer_t type,
1446                                 uint32_t pixel_fmt,
1447                                 uint16_t width, uint16_t height,
1448                                 uint32_t stride,
1449                                 uint32_t u, uint32_t v,
1450                                 uint32_t vertical_offset, uint32_t horizontal_offset)
1451 {
1452         int ret = 0;
1453         uint32_t dma_chan = channel_2_dma(channel, type);
1454
1455         if (dma_chan == IDMA_CHAN_INVALID)
1456                 return -EINVAL;
1457
1458         _ipu_lock(ipu);
1459
1460         if ((ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1461             (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1462             ((ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
1463              (ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
1464              _ipu_is_trb_chan(dma_chan)))
1465                 ret = -EACCES;
1466         else
1467                 _ipu_ch_offset_update(ipu, dma_chan, pixel_fmt, width, height, stride,
1468                                       u, v, 0, vertical_offset, horizontal_offset);
1469
1470         _ipu_unlock(ipu);
1471         return ret;
1472 }
1473 EXPORT_SYMBOL(ipu_update_channel_offset);
1474
1475
1476 /*!
1477  * This function is called to set a channel's buffer as ready.
1478  *
1479  * @param       ipu             ipu handler
1480  * @param       channel         Input parameter for the logical channel ID.
1481  *
1482  * @param       type            Input parameter which buffer to initialize.
1483  *
1484  * @param       bufNum          Input parameter for which buffer number set to
1485  *                              ready state.
1486  *
1487  * @return      Returns 0 on success or negative error code on fail
1488  */
1489 int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
1490                         ipu_buffer_t type, uint32_t bufNum)
1491 {
1492         uint32_t dma_chan = channel_2_dma(channel, type);
1493
1494         if (dma_chan == IDMA_CHAN_INVALID)
1495                 return -EINVAL;
1496
1497         /* Mark buffer to be ready. */
1498         _ipu_lock(ipu);
1499         if (bufNum == 0)
1500                 ipu_cm_write(ipu, idma_mask(dma_chan),
1501                              IPU_CHA_BUF0_RDY(dma_chan));
1502         else if (bufNum == 1)
1503                 ipu_cm_write(ipu, idma_mask(dma_chan),
1504                              IPU_CHA_BUF1_RDY(dma_chan));
1505         else
1506                 ipu_cm_write(ipu, idma_mask(dma_chan),
1507                              IPU_CHA_BUF2_RDY(dma_chan));
1508         _ipu_unlock(ipu);
1509         return 0;
1510 }
1511 EXPORT_SYMBOL(ipu_select_buffer);
1512
1513 /*!
1514  * This function is called to set a channel's buffer as ready.
1515  *
1516  * @param       ipu             ipu handler
1517  * @param       bufNum          Input parameter for which buffer number set to
1518  *                              ready state.
1519  *
1520  * @return      Returns 0 on success or negative error code on fail
1521  */
1522 int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum)
1523 {
1524
1525         uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
1526         uint32_t mask_bit =
1527                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
1528                 idma_mask(dma_chan)|
1529                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
1530
1531         /* Mark buffers to be ready. */
1532         _ipu_lock(ipu);
1533         if (bufNum == 0)
1534                 ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
1535         else
1536                 ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
1537         _ipu_unlock(ipu);
1538         return 0;
1539 }
1540 EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
1541
1542 #define NA      -1
1543 static int proc_dest_sel[] = {
1544         0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
1545         0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
1546 static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
1547   NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, 8, NA };
1548 static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
1549   NA, NA, NA, NA, NA,  1, NA,  2, NA,  3,  4,  4,  4,  4 };
1550
1551
1552 /*!
1553  * This function links 2 channels together for automatic frame
1554  * synchronization. The output of the source channel is linked to the input of
1555  * the destination channel.
1556  *
1557  * @param       ipu             ipu handler
1558  * @param       src_ch          Input parameter for the logical channel ID of
1559  *                              the source channel.
1560  *
1561  * @param       dest_ch         Input parameter for the logical channel ID of
1562  *                              the destination channel.
1563  *
1564  * @return      This function returns 0 on success or negative error code on
1565  *              fail.
1566  */
1567 int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
1568 {
1569         int retval = 0;
1570         uint32_t fs_proc_flow1;
1571         uint32_t fs_proc_flow2;
1572         uint32_t fs_proc_flow3;
1573         uint32_t fs_disp_flow1;
1574
1575         _ipu_lock(ipu);
1576
1577         fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1578         fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
1579         fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
1580         fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
1581
1582         switch (src_ch) {
1583         case CSI_MEM0:
1584                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1585                 fs_proc_flow3 |=
1586                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1587                         FS_SMFC0_DEST_SEL_OFFSET;
1588                 break;
1589         case CSI_MEM1:
1590                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1591                 fs_proc_flow3 |=
1592                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1593                         FS_SMFC1_DEST_SEL_OFFSET;
1594                 break;
1595         case CSI_MEM2:
1596                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1597                 fs_proc_flow3 |=
1598                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1599                         FS_SMFC2_DEST_SEL_OFFSET;
1600                 break;
1601         case CSI_MEM3:
1602                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1603                 fs_proc_flow3 |=
1604                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1605                         FS_SMFC3_DEST_SEL_OFFSET;
1606                 break;
1607         case CSI_PRP_ENC_MEM:
1608                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1609                 fs_proc_flow2 |=
1610                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1611                         FS_PRPENC_DEST_SEL_OFFSET;
1612                 break;
1613         case CSI_PRP_VF_MEM:
1614                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1615                 fs_proc_flow2 |=
1616                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1617                         FS_PRPVF_DEST_SEL_OFFSET;
1618                 break;
1619         case MEM_PP_MEM:
1620                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1621                 fs_proc_flow2 |=
1622                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1623                     FS_PP_DEST_SEL_OFFSET;
1624                 break;
1625         case MEM_ROT_PP_MEM:
1626                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1627                 fs_proc_flow2 |=
1628                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1629                     FS_PP_ROT_DEST_SEL_OFFSET;
1630                 break;
1631         case MEM_PRP_ENC_MEM:
1632                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1633                 fs_proc_flow2 |=
1634                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1635                     FS_PRPENC_DEST_SEL_OFFSET;
1636                 break;
1637         case MEM_ROT_ENC_MEM:
1638                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1639                 fs_proc_flow2 |=
1640                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1641                     FS_PRPENC_ROT_DEST_SEL_OFFSET;
1642                 break;
1643         case MEM_PRP_VF_MEM:
1644                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1645                 fs_proc_flow2 |=
1646                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1647                     FS_PRPVF_DEST_SEL_OFFSET;
1648                 break;
1649         case MEM_VDI_PRP_VF_MEM:
1650                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1651                 fs_proc_flow2 |=
1652                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1653                     FS_PRPVF_DEST_SEL_OFFSET;
1654                 break;
1655         case MEM_ROT_VF_MEM:
1656                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1657                 fs_proc_flow2 |=
1658                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1659                     FS_PRPVF_ROT_DEST_SEL_OFFSET;
1660                 break;
1661         default:
1662                 retval = -EINVAL;
1663                 goto err;
1664         }
1665
1666         switch (dest_ch) {
1667         case MEM_PP_MEM:
1668                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1669                 fs_proc_flow1 |=
1670                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET;
1671                 break;
1672         case MEM_ROT_PP_MEM:
1673                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1674                 fs_proc_flow1 |=
1675                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1676                     FS_PP_ROT_SRC_SEL_OFFSET;
1677                 break;
1678         case MEM_PRP_ENC_MEM:
1679                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1680                 fs_proc_flow1 |=
1681                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1682                 break;
1683         case MEM_ROT_ENC_MEM:
1684                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1685                 fs_proc_flow1 |=
1686                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1687                     FS_PRPENC_ROT_SRC_SEL_OFFSET;
1688                 break;
1689         case MEM_PRP_VF_MEM:
1690                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1691                 fs_proc_flow1 |=
1692                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1693                 break;
1694         case MEM_VDI_PRP_VF_MEM:
1695                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1696                 fs_proc_flow1 |=
1697                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1698                 break;
1699         case MEM_ROT_VF_MEM:
1700                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1701                 fs_proc_flow1 |=
1702                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1703                     FS_PRPVF_ROT_SRC_SEL_OFFSET;
1704                 break;
1705         case MEM_DC_SYNC:
1706                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1707                 fs_disp_flow1 |=
1708                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
1709                 break;
1710         case MEM_BG_SYNC:
1711                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1712                 fs_disp_flow1 |=
1713                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1714                     FS_DP_SYNC0_SRC_SEL_OFFSET;
1715                 break;
1716         case MEM_FG_SYNC:
1717                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1718                 fs_disp_flow1 |=
1719                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1720                     FS_DP_SYNC1_SRC_SEL_OFFSET;
1721                 break;
1722         case MEM_DC_ASYNC:
1723                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1724                 fs_disp_flow1 |=
1725                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
1726                 break;
1727         case MEM_BG_ASYNC0:
1728                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1729                 fs_disp_flow1 |=
1730                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1731                     FS_DP_ASYNC0_SRC_SEL_OFFSET;
1732                 break;
1733         case MEM_FG_ASYNC0:
1734                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1735                 fs_disp_flow1 |=
1736                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1737                     FS_DP_ASYNC1_SRC_SEL_OFFSET;
1738                 break;
1739         default:
1740                 retval = -EINVAL;
1741                 goto err;
1742         }
1743
1744         ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
1745         ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
1746         ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
1747         ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
1748
1749 err:
1750         _ipu_unlock(ipu);
1751         return retval;
1752 }
1753 EXPORT_SYMBOL(ipu_link_channels);
1754
1755 /*!
1756  * This function unlinks 2 channels and disables automatic frame
1757  * synchronization.
1758  *
1759  * @param       ipu             ipu handler
1760  * @param       src_ch          Input parameter for the logical channel ID of
1761  *                              the source channel.
1762  *
1763  * @param       dest_ch         Input parameter for the logical channel ID of
1764  *                              the destination channel.
1765  *
1766  * @return      This function returns 0 on success or negative error code on
1767  *              fail.
1768  */
1769 int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
1770 {
1771         int retval = 0;
1772         uint32_t fs_proc_flow1;
1773         uint32_t fs_proc_flow2;
1774         uint32_t fs_proc_flow3;
1775         uint32_t fs_disp_flow1;
1776
1777         _ipu_lock(ipu);
1778
1779         fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1780         fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
1781         fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
1782         fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
1783
1784         switch (src_ch) {
1785         case CSI_MEM0:
1786                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1787                 break;
1788         case CSI_MEM1:
1789                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1790                 break;
1791         case CSI_MEM2:
1792                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1793                 break;
1794         case CSI_MEM3:
1795                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1796                 break;
1797         case CSI_PRP_ENC_MEM:
1798                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1799                 break;
1800         case CSI_PRP_VF_MEM:
1801                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1802                 break;
1803         case MEM_PP_MEM:
1804                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1805                 break;
1806         case MEM_ROT_PP_MEM:
1807                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1808                 break;
1809         case MEM_PRP_ENC_MEM:
1810                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1811                 break;
1812         case MEM_ROT_ENC_MEM:
1813                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1814                 break;
1815         case MEM_PRP_VF_MEM:
1816                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1817                 break;
1818         case MEM_VDI_PRP_VF_MEM:
1819                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1820                 break;
1821         case MEM_ROT_VF_MEM:
1822                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1823                 break;
1824         default:
1825                 retval = -EINVAL;
1826                 goto err;
1827         }
1828
1829         switch (dest_ch) {
1830         case MEM_PP_MEM:
1831                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1832                 break;
1833         case MEM_ROT_PP_MEM:
1834                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1835                 break;
1836         case MEM_PRP_ENC_MEM:
1837                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1838                 break;
1839         case MEM_ROT_ENC_MEM:
1840                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1841                 break;
1842         case MEM_PRP_VF_MEM:
1843                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1844                 break;
1845         case MEM_VDI_PRP_VF_MEM:
1846                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1847                 break;
1848         case MEM_ROT_VF_MEM:
1849                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1850                 break;
1851         case MEM_DC_SYNC:
1852                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1853                 break;
1854         case MEM_BG_SYNC:
1855                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1856                 break;
1857         case MEM_FG_SYNC:
1858                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1859                 break;
1860         case MEM_DC_ASYNC:
1861                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1862                 break;
1863         case MEM_BG_ASYNC0:
1864                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1865                 break;
1866         case MEM_FG_ASYNC0:
1867                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1868                 break;
1869         default:
1870                 retval = -EINVAL;
1871                 goto err;
1872         }
1873
1874         ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
1875         ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
1876         ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
1877         ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
1878
1879 err:
1880         _ipu_unlock(ipu);
1881         return retval;
1882 }
1883 EXPORT_SYMBOL(ipu_unlink_channels);
1884
1885 /*!
1886  * This function check whether a logical channel was enabled.
1887  *
1888  * @param       ipu             ipu handler
1889  * @param       channel         Input parameter for the logical channel ID.
1890  *
1891  * @return      This function returns 1 while request channel is enabled or
1892  *              0 for not enabled.
1893  */
1894 int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel)
1895 {
1896         uint32_t reg;
1897         uint32_t in_dma;
1898         uint32_t out_dma;
1899
1900         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1901         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1902
1903         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
1904         if (reg & idma_mask(in_dma))
1905                 return 1;
1906         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
1907         if (reg & idma_mask(out_dma))
1908                 return 1;
1909         return 0;
1910 }
1911 EXPORT_SYMBOL(ipu_is_channel_busy);
1912
1913 /*!
1914  * This function enables a logical channel.
1915  *
1916  * @param       ipu             ipu handler
1917  * @param       channel         Input parameter for the logical channel ID.
1918  *
1919  * @return      This function returns 0 on success or negative error code on
1920  *              fail.
1921  */
1922 int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel)
1923 {
1924         uint32_t reg;
1925         uint32_t ipu_conf;
1926         uint32_t in_dma;
1927         uint32_t out_dma;
1928         uint32_t sec_dma;
1929         uint32_t thrd_dma;
1930
1931         _ipu_lock(ipu);
1932
1933         if (ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1934                 dev_err(ipu->dev, "Warning: channel already enabled %d\n",
1935                         IPU_CHAN_ID(channel));
1936                 _ipu_unlock(ipu);
1937                 return -EACCES;
1938         }
1939
1940         /* Get input and output dma channels */
1941         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1942         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1943
1944         ipu_conf = ipu_cm_read(ipu, IPU_CONF);
1945         if (ipu->di_use_count[0] > 0) {
1946                 ipu_conf |= IPU_CONF_DI0_EN;
1947         }
1948         if (ipu->di_use_count[1] > 0) {
1949                 ipu_conf |= IPU_CONF_DI1_EN;
1950         }
1951         if (ipu->dp_use_count > 0)
1952                 ipu_conf |= IPU_CONF_DP_EN;
1953         if (ipu->dc_use_count > 0)
1954                 ipu_conf |= IPU_CONF_DC_EN;
1955         if (ipu->dmfc_use_count > 0)
1956                 ipu_conf |= IPU_CONF_DMFC_EN;
1957         if (ipu->ic_use_count > 0)
1958                 ipu_conf |= IPU_CONF_IC_EN;
1959         if (ipu->vdi_use_count > 0) {
1960                 ipu_conf |= IPU_CONF_ISP_EN;
1961                 ipu_conf |= IPU_CONF_VDI_EN;
1962                 ipu_conf |= IPU_CONF_IC_INPUT;
1963         }
1964         if (ipu->rot_use_count > 0)
1965                 ipu_conf |= IPU_CONF_ROT_EN;
1966         if (ipu->smfc_use_count > 0)
1967                 ipu_conf |= IPU_CONF_SMFC_EN;
1968         ipu_cm_write(ipu, ipu_conf, IPU_CONF);
1969
1970         if (idma_is_valid(in_dma)) {
1971                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
1972                 ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1973         }
1974         if (idma_is_valid(out_dma)) {
1975                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
1976                 ipu_idmac_write(ipu, reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1977         }
1978
1979         if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
1980                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
1981                  (channel == MEM_VDI_PRP_VF_MEM))) {
1982                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1983                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
1984                 ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
1985         }
1986         if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
1987                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
1988                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
1989                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
1990                 ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
1991
1992                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1993                 reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
1994                 ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
1995         } else if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
1996                    ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
1997                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
1998                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
1999                 ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
2000                 reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
2001                 ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
2002         }
2003
2004         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
2005             (channel == MEM_FG_SYNC)) {
2006                 reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
2007                 ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
2008
2009                 _ipu_dp_dc_enable(ipu, channel);
2010         }
2011
2012         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
2013                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
2014                 _ipu_ic_enable_task(ipu, channel);
2015
2016         ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
2017
2018         _ipu_unlock(ipu);
2019
2020         return 0;
2021 }
2022 EXPORT_SYMBOL(ipu_enable_channel);
2023
2024 /*!
2025  * This function check buffer ready for a logical channel.
2026  *
2027  * @param       ipu             ipu handler
2028  * @param       channel         Input parameter for the logical channel ID.
2029  *
2030  * @param       type            Input parameter which buffer to clear.
2031  *
2032  * @param       bufNum          Input parameter for which buffer number clear
2033  *                              ready state.
2034  *
2035  */
2036 int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
2037                 uint32_t bufNum)
2038 {
2039         uint32_t dma_chan = channel_2_dma(channel, type);
2040         uint32_t reg;
2041
2042         if (dma_chan == IDMA_CHAN_INVALID)
2043                 return -EINVAL;
2044
2045         if (bufNum == 0)
2046                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
2047         else if (bufNum == 1)
2048                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
2049         else
2050                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
2051
2052         if (reg & idma_mask(dma_chan))
2053                 return 1;
2054         else
2055                 return 0;
2056 }
2057 EXPORT_SYMBOL(ipu_check_buffer_ready);
2058
2059 /*!
2060  * This function clear buffer ready for a logical channel.
2061  *
2062  * @param       ipu             ipu handler
2063  * @param       channel         Input parameter for the logical channel ID.
2064  *
2065  * @param       type            Input parameter which buffer to clear.
2066  *
2067  * @param       bufNum          Input parameter for which buffer number clear
2068  *                              ready state.
2069  *
2070  */
2071 void _ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
2072                 uint32_t bufNum)
2073 {
2074         uint32_t dma_ch = channel_2_dma(channel, type);
2075
2076         if (!idma_is_valid(dma_ch))
2077                 return;
2078
2079         ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
2080         if (bufNum == 0)
2081                 ipu_cm_write(ipu, idma_mask(dma_ch),
2082                                 IPU_CHA_BUF0_RDY(dma_ch));
2083         else if (bufNum == 1)
2084                 ipu_cm_write(ipu, idma_mask(dma_ch),
2085                                 IPU_CHA_BUF1_RDY(dma_ch));
2086         else
2087                 ipu_cm_write(ipu, idma_mask(dma_ch),
2088                                 IPU_CHA_BUF2_RDY(dma_ch));
2089         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
2090 }
2091
2092 void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
2093                 uint32_t bufNum)
2094 {
2095         _ipu_lock(ipu);
2096         _ipu_clear_buffer_ready(ipu, channel, type, bufNum);
2097         _ipu_unlock(ipu);
2098 }
2099 EXPORT_SYMBOL(ipu_clear_buffer_ready);
2100
2101 /*!
2102  * This function disables a logical channel.
2103  *
2104  * @param       ipu             ipu handler
2105  * @param       channel         Input parameter for the logical channel ID.
2106  *
2107  * @param       wait_for_stop   Flag to set whether to wait for channel end
2108  *                              of frame or return immediately.
2109  *
2110  * @return      This function returns 0 on success or negative error code on
2111  *              fail.
2112  */
2113 int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop)
2114 {
2115         uint32_t reg;
2116         uint32_t in_dma;
2117         uint32_t out_dma;
2118         uint32_t sec_dma = NO_DMA;
2119         uint32_t thrd_dma = NO_DMA;
2120         uint16_t fg_pos_x, fg_pos_y;
2121
2122         _ipu_lock(ipu);
2123
2124         if ((ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
2125                 dev_err(ipu->dev, "Channel already disabled %d\n",
2126                         IPU_CHAN_ID(channel));
2127                 _ipu_unlock(ipu);
2128                 return -EACCES;
2129         }
2130
2131         /* Get input and output dma channels */
2132         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
2133         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
2134
2135         if ((idma_is_valid(in_dma) &&
2136                 !idma_is_set(ipu, IDMAC_CHA_EN, in_dma))
2137                 && (idma_is_valid(out_dma) &&
2138                 !idma_is_set(ipu, IDMAC_CHA_EN, out_dma))) {
2139                 _ipu_unlock(ipu);
2140                 return -EINVAL;
2141         }
2142
2143         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)])
2144                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2145         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) {
2146                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2147                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
2148         }
2149
2150         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
2151             (channel == MEM_DC_SYNC)) {
2152                 if (channel == MEM_FG_SYNC) {
2153                         _ipu_disp_get_window_pos(ipu, channel, &fg_pos_x, &fg_pos_y);
2154                         _ipu_disp_set_window_pos(ipu, channel, 0, 0);
2155                 }
2156
2157                 _ipu_dp_dc_disable(ipu, channel, false);
2158
2159                 /*
2160                  * wait for BG channel EOF then disable FG-IDMAC,
2161                  * it avoid FG NFB4EOF error.
2162                  */
2163                 if ((channel == MEM_FG_SYNC) && (ipu_is_channel_busy(ipu, MEM_BG_SYNC))) {
2164                         int timeout = 50;
2165
2166                         ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
2167                                         IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
2168                         while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
2169                                                 IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
2170                                 msleep(10);
2171                                 timeout -= 10;
2172                                 if (timeout <= 0) {
2173                                         dev_err(ipu->dev, "warning: wait for bg sync eof timeout\n");
2174                                         break;
2175                                 }
2176                         }
2177                 }
2178         } else if (wait_for_stop) {
2179                 while (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma) ||
2180                        idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma) ||
2181                         (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
2182                         idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma)) ||
2183                         (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
2184                         idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))) {
2185                         uint32_t irq = 0xffffffff;
2186                         int timeout = 50;
2187
2188                         if (idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma))
2189                                 irq = out_dma;
2190                         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
2191                                 idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma))
2192                                 irq = sec_dma;
2193                         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
2194                                 idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))
2195                                 irq = thrd_dma;
2196                         if (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma))
2197                                 irq = in_dma;
2198
2199                         if (irq == 0xffffffff) {
2200                                 dev_dbg(ipu->dev, "warning: no channel busy, break\n");
2201                                 break;
2202                         }
2203
2204                         ipu_cm_write(ipu, IPUIRQ_2_MASK(irq),
2205                                         IPUIRQ_2_STATREG(irq));
2206
2207                         dev_dbg(ipu->dev, "warning: channel %d busy, need wait\n", irq);
2208
2209                         while (((ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq))
2210                                 & IPUIRQ_2_MASK(irq)) == 0) &&
2211                                 (idma_is_set(ipu, IDMAC_CHA_BUSY, irq))) {
2212                                 msleep(10);
2213                                 timeout -= 10;
2214                                 if (timeout <= 0) {
2215                                         ipu_dump_registers(ipu);
2216                                         dev_err(ipu->dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
2217                                         break;
2218                                 }
2219                         }
2220
2221                 }
2222         }
2223
2224         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
2225             (channel == MEM_DC_SYNC)) {
2226                 reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
2227                 ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
2228         }
2229
2230         /* Disable IC task */
2231         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
2232                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
2233                 _ipu_ic_disable_task(ipu, channel);
2234
2235         /* Disable DMA channel(s) */
2236         if (idma_is_valid(in_dma)) {
2237                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
2238                 ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
2239                 ipu_cm_write(ipu, idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
2240                 ipu_cm_write(ipu, tri_cur_buf_mask(in_dma),
2241                                         IPU_CHA_TRIPLE_CUR_BUF(in_dma));
2242         }
2243         if (idma_is_valid(out_dma)) {
2244                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
2245                 ipu_idmac_write(ipu, reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
2246                 ipu_cm_write(ipu, idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
2247                 ipu_cm_write(ipu, tri_cur_buf_mask(out_dma),
2248                                         IPU_CHA_TRIPLE_CUR_BUF(out_dma));
2249         }
2250         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2251                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
2252                 ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
2253                 ipu_cm_write(ipu, idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
2254         }
2255         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2256                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
2257                 ipu_idmac_write(ipu, reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
2258                 if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
2259                         reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
2260                         ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
2261                 } else {
2262                         reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
2263                         ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
2264                 }
2265                 ipu_cm_write(ipu, idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
2266         }
2267
2268         if (channel == MEM_FG_SYNC)
2269                 _ipu_disp_set_window_pos(ipu, channel, fg_pos_x, fg_pos_y);
2270
2271         /* Set channel buffers NOT to be ready */
2272         if (idma_is_valid(in_dma)) {
2273                 _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 0);
2274                 _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 1);
2275                 _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 2);
2276         }
2277         if (idma_is_valid(out_dma)) {
2278                 _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 0);
2279                 _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 1);
2280         }
2281         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2282                 _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 0);
2283                 _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 1);
2284         }
2285         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2286                 _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 0);
2287                 _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 1);
2288         }
2289
2290         ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
2291
2292         _ipu_unlock(ipu);
2293
2294         return 0;
2295 }
2296 EXPORT_SYMBOL(ipu_disable_channel);
2297
2298 /*!
2299  * This function enables CSI.
2300  *
2301  * @param       ipu             ipu handler
2302  * @param       csi     csi num 0 or 1
2303  *
2304  * @return      This function returns 0 on success or negative error code on
2305  *              fail.
2306  */
2307 int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
2308 {
2309         uint32_t reg;
2310
2311         if (csi > 1) {
2312                 dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
2313                 return -EINVAL;
2314         }
2315
2316         _ipu_lock(ipu);
2317         ipu->csi_use_count[csi]++;
2318
2319         if (ipu->csi_use_count[csi] == 1) {
2320                 reg = ipu_cm_read(ipu, IPU_CONF);
2321                 if (csi == 0)
2322                         ipu_cm_write(ipu, reg | IPU_CONF_CSI0_EN, IPU_CONF);
2323                 else
2324                         ipu_cm_write(ipu, reg | IPU_CONF_CSI1_EN, IPU_CONF);
2325         }
2326         _ipu_unlock(ipu);
2327         return 0;
2328 }
2329 EXPORT_SYMBOL(ipu_enable_csi);
2330
2331 /*!
2332  * This function disables CSI.
2333  *
2334  * @param       ipu             ipu handler
2335  * @param       csi     csi num 0 or 1
2336  *
2337  * @return      This function returns 0 on success or negative error code on
2338  *              fail.
2339  */
2340 int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
2341 {
2342         uint32_t reg;
2343
2344         if (csi > 1) {
2345                 dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
2346                 return -EINVAL;
2347         }
2348
2349         _ipu_lock(ipu);
2350         ipu->csi_use_count[csi]--;
2351         if (ipu->csi_use_count[csi] == 0) {
2352                 reg = ipu_cm_read(ipu, IPU_CONF);
2353                 if (csi == 0)
2354                         ipu_cm_write(ipu, reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
2355                 else
2356                         ipu_cm_write(ipu, reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
2357         }
2358         _ipu_unlock(ipu);
2359         return 0;
2360 }
2361 EXPORT_SYMBOL(ipu_disable_csi);
2362
2363 static irqreturn_t ipu_irq_handler(int irq, void *desc)
2364 {
2365         struct ipu_soc *ipu = desc;
2366         int i;
2367         uint32_t line;
2368         irqreturn_t result = IRQ_NONE;
2369         uint32_t int_stat;
2370         const int err_reg[] = { 5, 6, 9, 10, 0 };
2371         const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
2372         unsigned long lock_flags;
2373
2374         for (i = 0;; i++) {
2375                 if (err_reg[i] == 0)
2376                         break;
2377
2378                 spin_lock_irqsave(&ipu->spin_lock, lock_flags);
2379
2380                 int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
2381                 int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
2382                 if (int_stat) {
2383                         ipu_cm_write(ipu, int_stat, IPU_INT_STAT(err_reg[i]));
2384                         dev_err(ipu->dev,
2385                                 "IPU Error - IPU_INT_STAT_%d = 0x%08X\n",
2386                                 err_reg[i], int_stat);
2387                         /* Disable interrupts so we only get error once */
2388                         int_stat =
2389                             ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) & ~int_stat;
2390                         ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
2391                 }
2392
2393                 spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2394         }
2395
2396         for (i = 0;; i++) {
2397                 if (int_reg[i] == 0)
2398                         break;
2399                 spin_lock_irqsave(&ipu->spin_lock, lock_flags);
2400                 int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
2401                 int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
2402                 ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
2403                 spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2404                 while ((line = ffs(int_stat)) != 0) {
2405                         line--;
2406                         int_stat &= ~(1UL << line);
2407                         line += (int_reg[i] - 1) * 32;
2408                         result |=
2409                             ipu->irq_list[line].handler(line,
2410                                                        ipu->irq_list[line].
2411                                                        dev_id);
2412                 }
2413         }
2414
2415         return result;
2416 }
2417
2418 /*!
2419  * This function enables the interrupt for the specified interrupt line.
2420  * The interrupt lines are defined in \b ipu_irq_line enum.
2421  *
2422  * @param       ipu             ipu handler
2423  * @param       irq             Interrupt line to enable interrupt for.
2424  *
2425  */
2426 void ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq)
2427 {
2428         uint32_t reg;
2429         unsigned long lock_flags;
2430
2431         _ipu_get(ipu);
2432
2433         spin_lock_irqsave(&ipu->spin_lock, lock_flags);
2434
2435         reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
2436         reg |= IPUIRQ_2_MASK(irq);
2437         ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
2438
2439         spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2440
2441         _ipu_put(ipu);
2442 }
2443 EXPORT_SYMBOL(ipu_enable_irq);
2444
2445 /*!
2446  * This function disables the interrupt for the specified interrupt line.
2447  * The interrupt lines are defined in \b ipu_irq_line enum.
2448  *
2449  * @param       ipu             ipu handler
2450  * @param       irq             Interrupt line to disable interrupt for.
2451  *
2452  */
2453 void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq)
2454 {
2455         uint32_t reg;
2456         unsigned long lock_flags;
2457
2458         _ipu_get(ipu);
2459
2460         spin_lock_irqsave(&ipu->spin_lock, lock_flags);
2461
2462         reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
2463         reg &= ~IPUIRQ_2_MASK(irq);
2464         ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
2465
2466         spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2467
2468         _ipu_put(ipu);
2469 }
2470 EXPORT_SYMBOL(ipu_disable_irq);
2471
2472 /*!
2473  * This function clears the interrupt for the specified interrupt line.
2474  * The interrupt lines are defined in \b ipu_irq_line enum.
2475  *
2476  * @param       ipu             ipu handler
2477  * @param       irq             Interrupt line to clear interrupt for.
2478  *
2479  */
2480 void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq)
2481 {
2482         unsigned long lock_flags;
2483
2484         _ipu_get(ipu);
2485
2486         spin_lock_irqsave(&ipu->spin_lock, lock_flags);
2487
2488         ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
2489
2490         spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2491
2492         _ipu_put(ipu);
2493 }
2494 EXPORT_SYMBOL(ipu_clear_irq);
2495
2496 /*!
2497  * This function returns the current interrupt status for the specified
2498  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2499  *
2500  * @param       ipu             ipu handler
2501  * @param       irq             Interrupt line to get status for.
2502  *
2503  * @return      Returns true if the interrupt is pending/asserted or false if
2504  *              the interrupt is not pending.
2505  */
2506 bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq)
2507 {
2508         uint32_t reg;
2509
2510         _ipu_get(ipu);
2511
2512         reg = ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq));
2513
2514         _ipu_put(ipu);
2515
2516         if (reg & IPUIRQ_2_MASK(irq))
2517                 return true;
2518         else
2519                 return false;
2520 }
2521 EXPORT_SYMBOL(ipu_get_irq_status);
2522
2523 /*!
2524  * This function registers an interrupt handler function for the specified
2525  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2526  *
2527  * @param       ipu             ipu handler
2528  * @param       irq             Interrupt line to get status for.
2529  *
2530  * @param       handler         Input parameter for address of the handler
2531  *                              function.
2532  *
2533  * @param       irq_flags       Flags for interrupt mode. Currently not used.
2534  *
2535  * @param       devname         Input parameter for string name of driver
2536  *                              registering the handler.
2537  *
2538  * @param       dev_id          Input parameter for pointer of data to be
2539  *                              passed to the handler.
2540  *
2541  * @return      This function returns 0 on success or negative error code on
2542  *              fail.
2543  */
2544 int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
2545                     irqreturn_t(*handler) (int, void *),
2546                     uint32_t irq_flags, const char *devname, void *dev_id)
2547 {
2548         unsigned long lock_flags;
2549
2550         BUG_ON(irq >= IPU_IRQ_COUNT);
2551
2552         _ipu_get(ipu);
2553
2554         spin_lock_irqsave(&ipu->spin_lock, lock_flags);
2555
2556         if (ipu->irq_list[irq].handler != NULL) {
2557                 dev_err(ipu->dev,
2558                         "handler already installed on irq %d\n", irq);
2559                 spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2560                 return -EINVAL;
2561         }
2562
2563         ipu->irq_list[irq].handler = handler;
2564         ipu->irq_list[irq].flags = irq_flags;
2565         ipu->irq_list[irq].dev_id = dev_id;
2566         ipu->irq_list[irq].name = devname;
2567
2568         /* clear irq stat for previous use */
2569         ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
2570
2571         spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2572
2573         _ipu_put(ipu);
2574
2575         ipu_enable_irq(ipu, irq);       /* enable the interrupt */
2576
2577         return 0;
2578 }
2579 EXPORT_SYMBOL(ipu_request_irq);
2580
2581 /*!
2582  * This function unregisters an interrupt handler for the specified interrupt
2583  * line. The interrupt lines are defined in \b ipu_irq_line enum.
2584  *
2585  * @param       ipu             ipu handler
2586  * @param       irq             Interrupt line to get status for.
2587  *
2588  * @param       dev_id          Input parameter for pointer of data to be passed
2589  *                              to the handler. This must match value passed to
2590  *                              ipu_request_irq().
2591  *
2592  */
2593 void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id)
2594 {
2595         unsigned long lock_flags;
2596
2597         ipu_disable_irq(ipu, irq);      /* disable the interrupt */
2598
2599         spin_lock_irqsave(&ipu->spin_lock, lock_flags);
2600         if (ipu->irq_list[irq].dev_id == dev_id)
2601                 ipu->irq_list[irq].handler = NULL;
2602         spin_unlock_irqrestore(&ipu->spin_lock, lock_flags);
2603 }
2604 EXPORT_SYMBOL(ipu_free_irq);
2605
2606 uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type)
2607 {
2608         uint32_t reg, dma_chan;
2609
2610         dma_chan = channel_2_dma(channel, type);
2611         if (!idma_is_valid(dma_chan))
2612                 return -EINVAL;
2613
2614         reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
2615         if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
2616                 reg = ipu_cm_read(ipu, IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
2617                 return (reg & tri_cur_buf_mask(dma_chan)) >>
2618                                 tri_cur_buf_shift(dma_chan);
2619         } else {
2620                 reg = ipu_cm_read(ipu, IPU_CHA_CUR_BUF(dma_chan));
2621                 if (reg & idma_mask(dma_chan))
2622                         return 1;
2623                 else
2624                         return 0;
2625         }
2626 }
2627 EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
2628
2629 uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
2630 {
2631         uint32_t stat = 0;
2632         uint32_t task_stat_reg = ipu_cm_read(ipu, IPU_PROC_TASK_STAT);
2633
2634         switch (channel) {
2635         case MEM_PRP_VF_MEM:
2636                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2637                 break;
2638         case MEM_VDI_PRP_VF_MEM:
2639                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2640                 break;
2641         case MEM_ROT_VF_MEM:
2642                 stat =
2643                     (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
2644                 break;
2645         case MEM_PRP_ENC_MEM:
2646                 stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
2647                 break;
2648         case MEM_ROT_ENC_MEM:
2649                 stat =
2650                     (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
2651                     TSTAT_ENC_ROT_OFFSET;
2652                 break;
2653         case MEM_PP_MEM:
2654                 stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
2655                 break;
2656         case MEM_ROT_PP_MEM:
2657                 stat =
2658                     (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
2659                 break;
2660
2661         default:
2662                 stat = TASK_STAT_IDLE;
2663                 break;
2664         }
2665         return stat;
2666 }
2667
2668 int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch)
2669 {
2670         uint32_t reg;
2671
2672         int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
2673         int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
2674
2675         _ipu_lock(ipu);
2676
2677         /* enable target channel */
2678         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(to_dma));
2679         ipu_idmac_write(ipu, reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
2680
2681         ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
2682
2683         /* switch dp dc */
2684         _ipu_dp_dc_disable(ipu, from_ch, true);
2685
2686         /* disable source channel */
2687         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(from_dma));
2688         ipu_idmac_write(ipu, reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
2689         ipu_cm_write(ipu, idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
2690         ipu_cm_write(ipu, tri_cur_buf_mask(from_dma),
2691                                 IPU_CHA_TRIPLE_CUR_BUF(from_dma));
2692
2693         ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
2694
2695         _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 0);
2696         _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 1);
2697         _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 2);
2698
2699         _ipu_unlock(ipu);
2700
2701         return 0;
2702 }
2703 EXPORT_SYMBOL(ipu_swap_channel);
2704
2705 uint32_t bytes_per_pixel(uint32_t fmt)
2706 {
2707         switch (fmt) {
2708         case IPU_PIX_FMT_GENERIC:       /*generic data */
2709         case IPU_PIX_FMT_RGB332:
2710         case IPU_PIX_FMT_YUV420P:
2711         case IPU_PIX_FMT_YVU420P:
2712         case IPU_PIX_FMT_YUV422P:
2713                 return 1;
2714                 break;
2715         case IPU_PIX_FMT_RGB565:
2716         case IPU_PIX_FMT_YUYV:
2717         case IPU_PIX_FMT_UYVY:
2718                 return 2;
2719                 break;
2720         case IPU_PIX_FMT_BGR24:
2721         case IPU_PIX_FMT_RGB24:
2722                 return 3;
2723                 break;
2724         case IPU_PIX_FMT_GENERIC_32:    /*generic data */
2725         case IPU_PIX_FMT_BGR32:
2726         case IPU_PIX_FMT_BGRA32:
2727         case IPU_PIX_FMT_RGB32:
2728         case IPU_PIX_FMT_RGBA32:
2729         case IPU_PIX_FMT_ABGR32:
2730                 return 4;
2731                 break;
2732         default:
2733                 return 1;
2734                 break;
2735         }
2736         return 0;
2737 }
2738 EXPORT_SYMBOL(bytes_per_pixel);
2739
2740 ipu_color_space_t format_to_colorspace(uint32_t fmt)
2741 {
2742         switch (fmt) {
2743         case IPU_PIX_FMT_RGB666:
2744         case IPU_PIX_FMT_RGB565:
2745         case IPU_PIX_FMT_BGR24:
2746         case IPU_PIX_FMT_RGB24:
2747         case IPU_PIX_FMT_GBR24:
2748         case IPU_PIX_FMT_BGR32:
2749         case IPU_PIX_FMT_BGRA32:
2750         case IPU_PIX_FMT_RGB32:
2751         case IPU_PIX_FMT_RGBA32:
2752         case IPU_PIX_FMT_ABGR32:
2753         case IPU_PIX_FMT_LVDS666:
2754         case IPU_PIX_FMT_LVDS888:
2755                 return RGB;
2756                 break;
2757
2758         default:
2759                 return YCbCr;
2760                 break;
2761         }
2762         return RGB;
2763 }
2764
2765 bool ipu_pixel_format_has_alpha(uint32_t fmt)
2766 {
2767         switch (fmt) {
2768         case IPU_PIX_FMT_RGBA32:
2769         case IPU_PIX_FMT_BGRA32:
2770         case IPU_PIX_FMT_ABGR32:
2771                 return true;
2772                 break;
2773         default:
2774                 return false;
2775                 break;
2776         }
2777         return false;
2778 }
2779
2780 static int ipu_suspend(struct platform_device *pdev, pm_message_t state)
2781 {
2782         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
2783         struct ipu_soc *ipu = platform_get_drvdata(pdev);
2784
2785         if (atomic_read(&ipu->ipu_use_count)) {
2786                 /* save and disable enabled channels*/
2787                 ipu->idma_enable_reg[0] = ipu_idmac_read(ipu, IDMAC_CHA_EN(0));
2788                 ipu->idma_enable_reg[1] = ipu_idmac_read(ipu, IDMAC_CHA_EN(32));
2789                 while ((ipu_idmac_read(ipu, IDMAC_CHA_BUSY(0))
2790                         & ipu->idma_enable_reg[0])
2791                         || (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(32))
2792                         & ipu->idma_enable_reg[1])) {
2793                         /* disable channel not busy already */
2794                         uint32_t chan_should_disable, timeout = 1000, time = 0;
2795
2796                         chan_should_disable =
2797                                 ipu_idmac_read(ipu, IDMAC_CHA_BUSY(0))
2798                                         ^ ipu->idma_enable_reg[0];
2799                         ipu_idmac_write(ipu, (~chan_should_disable) &
2800                                         ipu->idma_enable_reg[0], IDMAC_CHA_EN(0));
2801                         chan_should_disable =
2802                                 ipu_idmac_read(ipu, IDMAC_CHA_BUSY(1))
2803                                         ^ ipu->idma_enable_reg[1];
2804                         ipu_idmac_write(ipu, (~chan_should_disable) &
2805                                         ipu->idma_enable_reg[1], IDMAC_CHA_EN(32));
2806                         msleep(2);
2807                         time += 2;
2808                         if (time >= timeout)
2809                                 return -1;
2810                 }
2811                 ipu_idmac_write(ipu, 0, IDMAC_CHA_EN(0));
2812                 ipu_idmac_write(ipu, 0, IDMAC_CHA_EN(32));
2813
2814                 /* save double buffer select regs */
2815                 ipu->cha_db_mode_reg[0] = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0));
2816                 ipu->cha_db_mode_reg[1] = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32));
2817                 ipu->cha_db_mode_reg[2] =
2818                         ipu_cm_read(ipu, IPU_ALT_CHA_DB_MODE_SEL(0));
2819                 ipu->cha_db_mode_reg[3] =
2820                         ipu_cm_read(ipu, IPU_ALT_CHA_DB_MODE_SEL(32));
2821
2822                 /* save triple buffer select regs */
2823                 ipu->cha_trb_mode_reg[0] = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0));
2824                 ipu->cha_trb_mode_reg[1] = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32));
2825
2826                 /* save idamc sub addr regs */
2827                 ipu->idma_sub_addr_reg[0] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_0);
2828                 ipu->idma_sub_addr_reg[1] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_1);
2829                 ipu->idma_sub_addr_reg[2] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_2);
2830                 ipu->idma_sub_addr_reg[3] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_3);
2831                 ipu->idma_sub_addr_reg[4] = ipu_idmac_read(ipu, IDMAC_SUB_ADDR_4);
2832
2833                 /* save sub-modules status and disable all */
2834                 ipu->ic_conf_reg = ipu_ic_read(ipu, IC_CONF);
2835                 ipu_ic_write(ipu, 0, IC_CONF);
2836                 ipu->ipu_conf_reg = ipu_cm_read(ipu, IPU_CONF);
2837                 ipu_cm_write(ipu, 0, IPU_CONF);
2838
2839                 /* save buf ready regs */
2840                 ipu->buf_ready_reg[0] = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(0));
2841                 ipu->buf_ready_reg[1] = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(32));
2842                 ipu->buf_ready_reg[2] = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(0));
2843                 ipu->buf_ready_reg[3] = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(32));
2844                 ipu->buf_ready_reg[4] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF0_RDY(0));
2845                 ipu->buf_ready_reg[5] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF0_RDY(32));
2846                 ipu->buf_ready_reg[6] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF1_RDY(0));
2847                 ipu->buf_ready_reg[7] = ipu_cm_read(ipu, IPU_ALT_CHA_BUF1_RDY(32));
2848                 ipu->buf_ready_reg[8] = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(0));
2849                 ipu->buf_ready_reg[9] = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(32));
2850         }
2851
2852         if (plat_data->pg)
2853                 plat_data->pg(1);
2854
2855         return 0;
2856 }
2857
2858 static int ipu_resume(struct platform_device *pdev)
2859 {
2860         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
2861         struct ipu_soc *ipu = platform_get_drvdata(pdev);
2862
2863         if (plat_data->pg)
2864                 plat_data->pg(0);
2865
2866         if (atomic_read(&ipu->ipu_use_count)) {
2867                 /* restore buf ready regs */
2868                 ipu_cm_write(ipu, ipu->buf_ready_reg[0], IPU_CHA_BUF0_RDY(0));
2869                 ipu_cm_write(ipu, ipu->buf_ready_reg[1], IPU_CHA_BUF0_RDY(32));
2870                 ipu_cm_write(ipu, ipu->buf_ready_reg[2], IPU_CHA_BUF1_RDY(0));
2871                 ipu_cm_write(ipu, ipu->buf_ready_reg[3], IPU_CHA_BUF1_RDY(32));
2872                 ipu_cm_write(ipu, ipu->buf_ready_reg[4], IPU_ALT_CHA_BUF0_RDY(0));
2873                 ipu_cm_write(ipu, ipu->buf_ready_reg[5], IPU_ALT_CHA_BUF0_RDY(32));
2874                 ipu_cm_write(ipu, ipu->buf_ready_reg[6], IPU_ALT_CHA_BUF1_RDY(0));
2875                 ipu_cm_write(ipu, ipu->buf_ready_reg[7], IPU_ALT_CHA_BUF1_RDY(32));
2876                 ipu_cm_write(ipu, ipu->buf_ready_reg[8], IPU_CHA_BUF2_RDY(0));
2877                 ipu_cm_write(ipu, ipu->buf_ready_reg[9], IPU_CHA_BUF2_RDY(32));
2878
2879                 /* re-enable sub-modules*/
2880                 ipu_cm_write(ipu, ipu->ipu_conf_reg, IPU_CONF);
2881                 ipu_ic_write(ipu, ipu->ic_conf_reg, IC_CONF);
2882
2883                 /* restore double buffer select regs */
2884                 ipu_cm_write(ipu, ipu->cha_db_mode_reg[0], IPU_CHA_DB_MODE_SEL(0));
2885                 ipu_cm_write(ipu, ipu->cha_db_mode_reg[1], IPU_CHA_DB_MODE_SEL(32));
2886                 ipu_cm_write(ipu, ipu->cha_db_mode_reg[2],
2887                                 IPU_ALT_CHA_DB_MODE_SEL(0));
2888                 ipu_cm_write(ipu, ipu->cha_db_mode_reg[3],
2889                                 IPU_ALT_CHA_DB_MODE_SEL(32));
2890
2891                 /* restore triple buffer select regs */
2892                 ipu_cm_write(ipu, ipu->cha_trb_mode_reg[0], IPU_CHA_TRB_MODE_SEL(0));
2893                 ipu_cm_write(ipu, ipu->cha_trb_mode_reg[1], IPU_CHA_TRB_MODE_SEL(32));
2894
2895                 /* restore idamc sub addr regs */
2896                 ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[0], IDMAC_SUB_ADDR_0);
2897                 ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[1], IDMAC_SUB_ADDR_1);
2898                 ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[2], IDMAC_SUB_ADDR_2);
2899                 ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[3], IDMAC_SUB_ADDR_3);
2900                 ipu_idmac_write(ipu, ipu->idma_sub_addr_reg[4], IDMAC_SUB_ADDR_4);
2901
2902                 /* restart idma channel*/
2903                 ipu_idmac_write(ipu, ipu->idma_enable_reg[0], IDMAC_CHA_EN(0));
2904                 ipu_idmac_write(ipu, ipu->idma_enable_reg[1], IDMAC_CHA_EN(32));
2905         } else {
2906                 _ipu_get(ipu);
2907                 _ipu_dmfc_init(ipu, dmfc_type_setup, 1);
2908                 _ipu_init_dc_mappings(ipu);
2909                 /* Set sync refresh channels as high priority */
2910                 ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
2911                 _ipu_put(ipu);
2912         }
2913
2914         return 0;
2915 }
2916
2917 /*!
2918  * This structure contains pointers to the power management callback functions.
2919  */
2920 static struct platform_driver mxcipu_driver = {
2921         .driver = {
2922                    .name = "imx-ipuv3",
2923                    },
2924         .probe = ipu_probe,
2925         .remove = ipu_remove,
2926         .suspend = ipu_suspend,
2927         .resume = ipu_resume,
2928 };
2929
2930 int32_t __init ipu_gen_init(void)
2931 {
2932         int32_t ret;
2933
2934         ret = platform_driver_register(&mxcipu_driver);
2935         return 0;
2936 }
2937
2938 subsys_initcall(ipu_gen_init);
2939
2940 static void __exit ipu_gen_uninit(void)
2941 {
2942         platform_driver_unregister(&mxcipu_driver);
2943 }
2944
2945 module_exit(ipu_gen_uninit);