drivers/mxc/ipu3/ipu_common.c

   1 /*
   2  * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /*!
  15  * @file ipu_common.c
  16  *
  17  * @brief This file contains the IPU driver common API functions.
  18  *
  19  * @ingroup IPU
  20  */
  21 #include <linux/types.h>
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/err.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/irqdesc.h>
  31 #include <linux/ipu.h>
  32 #include <linux/clk.h>
  33 #include <linux/clkdev.h>
  34 #include <mach/clock.h>
  35 #include <mach/hardware.h>
  36 #include <mach/ipu-v3.h>
  37 #include <mach/devices-common.h>
  38
  39 #include "ipu_prv.h"
  40 #include "ipu_regs.h"
  41 #include "ipu_param_mem.h"
  42
  43 static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM];
  44 int g_ipu_hw_rev;
  45
  46 /* for power gating */
  47 static uint32_t ipu_conf_reg;
  48 static uint32_t ic_conf_reg;
  49 static uint32_t ipu_cha_db_mode_reg[4];
  50 static uint32_t ipu_cha_trb_mode_reg[2];
  51 static uint32_t ipu_cha_cur_buf_reg[4];
  52 static uint32_t ipu_cha_triple_cur_buf_reg[4];
  53 static uint32_t idma_sub_addr_reg[5];
  54 static uint32_t idma_enable_reg[2];
  55 static uint32_t buf_ready_reg[10];
  56
  57 /* Static functions */
  58 static irqreturn_t ipu_irq_handler(int irq, void *desc);
  59
  60 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
  61 {
  62         return ((uint32_t) ch >> (6 * type)) & 0x3F;
  63 };
  64
  65 static inline int _ipu_is_ic_chan(uint32_t dma_chan)
  66 {
  67         return ((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) && (dma_chan != 18));
  68 }
  69
  70 static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
  71 {
  72         return (dma_chan == 14 || dma_chan == 15);
  73 }
  74
  75 /* Either DP BG or DP FG can be graphic window */
  76 static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
  77 {
  78         return (dma_chan == 23 || dma_chan == 27);
  79 }
  80
  81 static inline int _ipu_is_irt_chan(uint32_t dma_chan)
  82 {
  83         return ((dma_chan >= 45) && (dma_chan <= 50));
  84 }
  85
  86 static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
  87 {
  88         return ((dma_chan >= 23) && (dma_chan <= 29));
  89 }
  90
  91 static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
  92 {
  93         return ((dma_chan >= 0) && (dma_chan <= 3));
  94 }
  95
  96 static inline int _ipu_is_trb_chan(uint32_t dma_chan)
  97 {
  98         return (((dma_chan == 8) || (dma_chan == 9) ||
  99                  (dma_chan == 10) || (dma_chan == 13) ||
 100                  (dma_chan == 21) || (dma_chan == 23) ||
 101                  (dma_chan == 27) || (dma_chan == 28)) &&
 102                 (g_ipu_hw_rev >= 2));
 103 }
 104
 105 #define idma_is_valid(ch)       (ch != NO_DMA)
 106 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 107 #define idma_is_set(ipu, reg, dma)      (ipu_idmac_read(ipu, reg(dma)) & idma_mask(dma))
 108 #define tri_cur_buf_mask(ch)    (idma_mask(ch*2) * 3)
 109 #define tri_cur_buf_shift(ch)   (ffs(idma_mask(ch*2)) - 1)
 110
 111 static int ipu_reset(struct ipu_soc *ipu)
 112 {
 113         int timeout = 1000;
 114
 115         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 116
 117         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 118                 if (!timeout--)
 119                         return -ETIME;
 120                 msleep(1);
 121         }
 122
 123         return 0;
 124 }
 125
 126 static inline struct ipu_soc *pixelclk2ipu(struct clk *clk)
 127 {
 128         struct ipu_soc *ipu;
 129         struct clk *base = clk - clk->id;
 130
 131         ipu = container_of(base, struct ipu_soc, pixel_clk[0]);
 132
 133         return ipu;
 134 }
 135
 136 static unsigned long _ipu_pixel_clk_get_rate(struct clk *clk)
 137 {
 138         struct ipu_soc *ipu = pixelclk2ipu(clk);
 139         u32 div = ipu_di_read(ipu, clk->id, DI_BS_CLKGEN0);
 140         if (div == 0)
 141                 return 0;
 142         return  (clk_get_rate(clk->parent) * 16) / div;
 143 }
 144
 145 static unsigned long _ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate)
 146 {
 147         u32 div;
 148         u32 parent_rate = clk_get_rate(clk->parent) * 16;
 149         /*
 150          * Calculate divider
 151          * Fractional part is 4 bits,
 152          * so simply multiply by 2^4 to get fractional part.
 153          */
 154         div = parent_rate / rate;
 155
 156         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 157                 div = 0x10;
 158         if (div & ~0xFEF)
 159                 div &= 0xFF8;
 160         else {
 161                 /* Round up divider if it gets us closer to desired pix clk */
 162                 if ((div & 0xC) == 0xC) {
 163                         div += 0x10;
 164                         div &= ~0xF;
 165                 }
 166         }
 167         return parent_rate / div;
 168 }
 169
 170 static int _ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 171 {
 172         struct ipu_soc *ipu = pixelclk2ipu(clk);
 173         u32 div = (clk_get_rate(clk->parent) * 16) / rate;
 174         unsigned long lock_flags;
 175
 176         /* Round up divider if it gets us closer to desired pix clk */
 177         if ((div & 0xC) == 0xC) {
 178                 div += 0x10;
 179                 div &= ~0xF;
 180         }
 181
 182         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
 183         ipu_di_write(ipu, clk->id, div, DI_BS_CLKGEN0);
 184
 185         /* Setup pixel clock timing */
 186         /* FIXME: needs to be more flexible */
 187         /* Down time is half of period */
 188         ipu_di_write(ipu, clk->id, (div / 16) << 16, DI_BS_CLKGEN1);
 189         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
 190
 191         return 0;
 192 }
 193
 194 static int _ipu_pixel_clk_enable(struct clk *clk)
 195 {
 196         struct ipu_soc *ipu = pixelclk2ipu(clk);
 197         u32 disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
 198         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 199         ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
 200
 201         return 0;
 202 }
 203
 204 static void _ipu_pixel_clk_disable(struct clk *clk)
 205 {
 206         struct ipu_soc *ipu = pixelclk2ipu(clk);
 207
 208         u32 disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
 209         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 210         ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
 211 }
 212
 213 static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 214 {
 215         struct ipu_soc *ipu = pixelclk2ipu(clk);
 216         unsigned long lock_flags;
 217         u32 di_gen;
 218
 219         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
 220         di_gen = ipu_di_read(ipu, clk->id, DI_GENERAL);
 221         if (parent == ipu->ipu_clk)
 222                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 223         else if (!IS_ERR(ipu->di_clk[clk->id]) && parent == ipu->di_clk[clk->id])
 224                 di_gen |= DI_GEN_DI_CLK_EXT;
 225         else {
 226                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
 227                 return -EINVAL;
 228         }
 229
 230         ipu_di_write(ipu, clk->id, di_gen, DI_GENERAL);
 231         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
 232         return 0;
 233 }
 234
 235 #ifdef CONFIG_CLK_DEBUG
 236 #define __INIT_CLK_DEBUG(n)     .name = #n,
 237 #else
 238 #define __INIT_CLK_DEBUG(n)
 239 #endif
 240 static int __devinit ipu_clk_setup_enable(struct ipu_soc *ipu,
 241                 struct platform_device *pdev)
 242 {
 243         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
 244         static struct clk ipu_pixel_clk[] = {
 245                 {
 246                         __INIT_CLK_DEBUG(pixel_clk_0)
 247                                 .id = 0,
 248                         .get_rate = _ipu_pixel_clk_get_rate,
 249                         .set_rate = _ipu_pixel_clk_set_rate,
 250                         .round_rate = _ipu_pixel_clk_round_rate,
 251                         .set_parent = _ipu_pixel_clk_set_parent,
 252                         .enable = _ipu_pixel_clk_enable,
 253                         .disable = _ipu_pixel_clk_disable,
 254                 },
 255                 {
 256                         __INIT_CLK_DEBUG(pixel_clk_1)
 257                                 .id = 1,
 258                         .get_rate = _ipu_pixel_clk_get_rate,
 259                         .set_rate = _ipu_pixel_clk_set_rate,
 260                         .round_rate = _ipu_pixel_clk_round_rate,
 261                         .set_parent = _ipu_pixel_clk_set_parent,
 262                         .enable = _ipu_pixel_clk_enable,
 263                         .disable = _ipu_pixel_clk_disable,
 264                 },
 265         };
 266         static struct clk_lookup ipu_lookups[] = {
 267                 {
 268                         .dev_id = NULL,
 269                         .con_id = "pixel_clk_0",
 270                 },
 271                 {
 272                         .dev_id = NULL,
 273                         .con_id = "pixel_clk_1",
 274                 },
 275         };
 276         char ipu_clk[] = "ipu1_clk";
 277         char di0_clk[] = "ipu1_di0_clk";
 278         char di1_clk[] = "ipu1_di1_clk";
 279
 280         ipu_clk[3] += pdev->id;
 281         di0_clk[3] += pdev->id;
 282         di1_clk[3] += pdev->id;
 283
 284         ipu->ipu_clk = clk_get(ipu->dev, ipu_clk);
 285         if (IS_ERR(ipu->ipu_clk)) {
 286                 dev_err(ipu->dev, "clk_get failed");
 287                 return PTR_ERR(ipu->ipu_clk);
 288         }
 289         dev_dbg(ipu->dev, "ipu_clk = %lu\n", clk_get_rate(ipu->ipu_clk));
 290
 291         ipu->pixel_clk[0] = ipu_pixel_clk[0];
 292         ipu->pixel_clk[1] = ipu_pixel_clk[1];
 293
 294         ipu_lookups[0].clk = &ipu->pixel_clk[0];
 295         ipu_lookups[1].clk = &ipu->pixel_clk[1];
 296         clkdev_add(&ipu_lookups[0]);
 297         clkdev_add(&ipu_lookups[1]);
 298
 299         clk_debug_register(&ipu->pixel_clk[0]);
 300         clk_debug_register(&ipu->pixel_clk[1]);
 301
 302         clk_enable(ipu->ipu_clk);
 303
 304         clk_set_parent(&ipu->pixel_clk[0], ipu->ipu_clk);
 305         clk_set_parent(&ipu->pixel_clk[1], ipu->ipu_clk);
 306
 307         ipu->di_clk[0] = clk_get(ipu->dev, di0_clk);
 308         ipu->di_clk[1] = clk_get(ipu->dev, di1_clk);
 309
 310         ipu->csi_clk[0] = clk_get(ipu->dev, plat_data->csi_clk[0]);
 311         ipu->csi_clk[1] = clk_get(ipu->dev, plat_data->csi_clk[1]);
 312
 313         return 0;
 314 }
 315
 316 #if 0
 317 static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
 318 {
 319         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 320         const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
 321         u32 status;
 322         int i, line;
 323
 324         for (i = 0;; i++) {
 325                 if (int_reg[i] == 0)
 326                         break;
 327
 328                 status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
 329                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
 330
 331                 while ((line = ffs(status))) {
 332                         line--;
 333                         status &= ~(1UL << line);
 334                         line += ipu->irq_start + (int_reg[i] - 1) * 32;
 335                         generic_handle_irq(line);
 336                 }
 337
 338         }
 339 }
 340
 341 static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 342 {
 343         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 344         const int int_reg[] = { 5, 6, 9, 10, 0 };
 345         u32 status;
 346         int i, line;
 347
 348         for (i = 0;; i++) {
 349                 if (int_reg[i] == 0)
 350                         break;
 351
 352                 status = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
 353                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
 354
 355                 while ((line = ffs(status))) {
 356                         line--;
 357                         status &= ~(1UL << line);
 358                         line += ipu->irq_start + (int_reg[i] - 1) * 32;
 359                         generic_handle_irq(line);
 360                 }
 361
 362         }
 363 }
 364
 365 static void ipu_ack_irq(struct irq_data *d)
 366 {
 367         struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
 368         unsigned int irq = d->irq - ipu->irq_start;
 369         unsigned long flags;
 370
 371         spin_lock_irqsave(&ipu->ipu_lock, flags);
 372         ipu_cm_write(ipu, 1 << (irq % 32), IPU_INT_STAT(irq / 32 + 1));
 373         spin_unlock_irqrestore(&ipu->ipu_lock, flags);
 374 }
 375
 376 static void ipu_unmask_irq(struct irq_data *d)
 377 {
 378         struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
 379         unsigned int irq = d->irq - ipu->irq_start;
 380         unsigned long flags;
 381         u32 reg;
 382
 383         spin_lock_irqsave(&ipu->ipu_lock, flags);
 384         reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
 385         reg |= 1 << (irq % 32);
 386         ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
 387         spin_unlock_irqrestore(&ipu->ipu_lock, flags);
 388 }
 389
 390 static void ipu_mask_irq(struct irq_data *d)
 391 {
 392         struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
 393         unsigned int irq = d->irq - ipu->irq_start;
 394         unsigned long flags;
 395         u32 reg;
 396
 397         spin_lock_irqsave(&ipu->ipu_lock, flags);
 398         reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32 + 1));
 399         reg &= ~(1 << (irq % 32));
 400         ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32 + 1));
 401         spin_unlock_irqrestore(&ipu->ipu_lock, flags);
 402 }
 403
 404 static struct irq_chip ipu_irq_chip = {
 405         .name = "IPU",
 406         .irq_ack = ipu_ack_irq,
 407         .irq_mask = ipu_mask_irq,
 408         .irq_unmask = ipu_unmask_irq,
 409 };
 410
 411 static void __devinit ipu_irq_setup(struct ipu_soc *ipu)
 412 {
 413         int i;
 414
 415         for (i = ipu->irq_start; i < ipu->irq_start + MX5_IPU_IRQS; i++) {
 416                 irq_set_chip_and_handler(i, &ipu_irq_chip, handle_level_irq);
 417                 set_irq_flags(i, IRQF_VALID);
 418                 irq_set_chip_data(i, ipu);
 419         }
 420
 421         irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
 422         irq_set_handler_data(ipu->irq_sync, ipu);
 423         irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
 424         irq_set_handler_data(ipu->irq_err, ipu);
 425 }
 426
 427 int ipu_request_irq(struct ipu_soc *ipu, unsigned int irq,
 428                 irq_handler_t handler, unsigned long flags,
 429                 const char *name, void *dev)
 430 {
 431         return request_irq(ipu->irq_start + irq, handler, flags, name, dev);
 432 }
 433 EXPORT_SYMBOL_GPL(ipu_request_irq);
 434
 435 void ipu_enable_irq(struct ipu_soc *ipu, unsigned int irq)
 436 {
 437         return enable_irq(ipu->irq_start + irq);
 438 }
 439 EXPORT_SYMBOL_GPL(ipu_disable_irq);
 440
 441 void ipu_disable_irq(struct ipu_soc *ipu, unsigned int irq)
 442 {
 443         return disable_irq(ipu->irq_start + irq);
 444 }
 445 EXPORT_SYMBOL_GPL(ipu_disable_irq);
 446
 447 void ipu_free_irq(struct ipu_soc *ipu, unsigned int irq, void *dev_id)
 448 {
 449         free_irq(ipu->irq_start + irq, dev_id);
 450 }
 451 EXPORT_SYMBOL_GPL(ipu_free_irq);
 452
 453 static irqreturn_t ipu_completion_handler(int irq, void *dev)
 454 {
 455         struct completion *completion = dev;
 456
 457         complete(completion);
 458         return IRQ_HANDLED;
 459 }
 460
 461 int ipu_wait_for_interrupt(struct ipu_soc *ipu, int interrupt, int timeout_ms)
 462 {
 463         DECLARE_COMPLETION_ONSTACK(completion);
 464         int ret;
 465
 466         ret = ipu_request_irq(ipu, interrupt, ipu_completion_handler,
 467                         0, NULL, &completion);
 468         if (ret) {
 469                 dev_err(ipu->dev,
 470                         "ipu request irq %d fail\n", interrupt);
 471                 return ret;
 472         }
 473
 474         ret = wait_for_completion_timeout(&completion,
 475                         msecs_to_jiffies(timeout_ms));
 476
 477         ipu_free_irq(ipu, interrupt, &completion);
 478
 479         return ret > 0 ? 0 : -ETIMEDOUT;
 480 }
 481 EXPORT_SYMBOL_GPL(ipu_wait_for_interrupt);
 482 #endif
 483
 484 struct ipu_soc *ipu_get_soc(int id)
 485 {
 486         if (id >= MXC_IPU_MAX_NUM)
 487                 return ERR_PTR(-ENODEV);
 488         else
 489                 return &(ipu_array[id]);
 490 }
 491
 492 /*!
 493  * This function is called by the driver framework to initialize the IPU
 494  * hardware.
 495  *
 496  * @param       dev     The device structure for the IPU passed in by the
 497  *                      driver framework.
 498  *
 499  * @return      Returns 0 on success or negative error code on error
 500  */
 501 static int __devinit ipu_probe(struct platform_device *pdev)
 502 {
 503         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
 504         struct ipu_soc *ipu;
 505         struct resource *res;
 506         unsigned long ipu_base;
 507         int ret = 0;
 508
 509         if (pdev->id >= MXC_IPU_MAX_NUM)
 510                 return -ENODEV;
 511
 512         ipu = &ipu_array[pdev->id];
 513         memset(ipu, 0, sizeof(struct ipu_soc));
 514
 515         spin_lock_init(&ipu->ipu_lock);
 516
 517         g_ipu_hw_rev = plat_data->rev;
 518
 519         ipu->dev = &pdev->dev;
 520
 521         if (plat_data->init)
 522                 plat_data->init(pdev->id);
 523
 524         ipu->irq_sync = platform_get_irq(pdev, 0);
 525         ipu->irq_err = platform_get_irq(pdev, 1);
 526         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 527
 528         if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
 529                 ret = -ENODEV;
 530                 goto failed_get_res;
 531         }
 532
 533         if (request_irq(ipu->irq_sync, ipu_irq_handler, 0, pdev->name, ipu) != 0) {
 534                 dev_err(ipu->dev, "request SYNC interrupt failed\n");
 535                 ret = -EBUSY;
 536                 goto failed_req_irq_sync;
 537         }
 538         /* Some platforms have 2 IPU interrupts */
 539         if (ipu->irq_err >= 0) {
 540                 if (request_irq
 541                     (ipu->irq_err, ipu_irq_handler, 0, pdev->name, ipu) != 0) {
 542                         dev_err(ipu->dev, "request ERR interrupt failed\n");
 543                         ret = -EBUSY;
 544                         goto failed_req_irq_err;
 545                 }
 546         }
 547
 548         ipu_base = res->start;
 549         /* base fixup */
 550         if (g_ipu_hw_rev == 4)  /* IPUv3H */
 551                 ipu_base += IPUV3H_REG_BASE;
 552         else if (g_ipu_hw_rev == 3)     /* IPUv3M */
 553                 ipu_base += IPUV3M_REG_BASE;
 554         else                    /* IPUv3D, v3E, v3EX */
 555                 ipu_base += IPUV3DEX_REG_BASE;
 556
 557         ipu->cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
 558         ipu->ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
 559         ipu->idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
 560         /* DP Registers are accessed thru the SRM */
 561         ipu->dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
 562         ipu->dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
 563         ipu->dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
 564         ipu->di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
 565         ipu->di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
 566         ipu->smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
 567         ipu->csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
 568         ipu->csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
 569         ipu->cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
 570         ipu->tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K);
 571         ipu->dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
 572         ipu->vdi_reg = ioremap(ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
 573         ipu->disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K);
 574
 575         if (!ipu->cm_reg || !ipu->ic_reg || !ipu->idmac_reg ||
 576                 !ipu->dp_reg || !ipu->dc_reg || !ipu->dmfc_reg ||
 577                 !ipu->di_reg[0] || !ipu->di_reg[1] || !ipu->smfc_reg ||
 578                 !ipu->csi_reg[0] || !ipu->csi_reg[1] || !ipu->cpmem_base ||
 579                 !ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->disp_base[1]
 580                 || !ipu->vdi_reg) {
 581                 ret = -ENOMEM;
 582                 goto failed_ioremap;
 583         }
 584
 585         dev_dbg(ipu->dev, "IPU CM Regs = %p\n", ipu->cm_reg);
 586         dev_dbg(ipu->dev, "IPU IC Regs = %p\n", ipu->ic_reg);
 587         dev_dbg(ipu->dev, "IPU IDMAC Regs = %p\n", ipu->idmac_reg);
 588         dev_dbg(ipu->dev, "IPU DP Regs = %p\n", ipu->dp_reg);
 589         dev_dbg(ipu->dev, "IPU DC Regs = %p\n", ipu->dc_reg);
 590         dev_dbg(ipu->dev, "IPU DMFC Regs = %p\n", ipu->dmfc_reg);
 591         dev_dbg(ipu->dev, "IPU DI0 Regs = %p\n", ipu->di_reg[0]);
 592         dev_dbg(ipu->dev, "IPU DI1 Regs = %p\n", ipu->di_reg[1]);
 593         dev_dbg(ipu->dev, "IPU SMFC Regs = %p\n", ipu->smfc_reg);
 594         dev_dbg(ipu->dev, "IPU CSI0 Regs = %p\n", ipu->csi_reg[0]);
 595         dev_dbg(ipu->dev, "IPU CSI1 Regs = %p\n", ipu->csi_reg[1]);
 596         dev_dbg(ipu->dev, "IPU CPMem = %p\n", ipu->cpmem_base);
 597         dev_dbg(ipu->dev, "IPU TPMem = %p\n", ipu->tpmem_base);
 598         dev_dbg(ipu->dev, "IPU DC Template Mem = %p\n", ipu->dc_tmpl_reg);
 599         dev_dbg(ipu->dev, "IPU Display Region 1 Mem = %p\n", ipu->disp_base[1]);
 600         dev_dbg(ipu->dev, "IPU VDI Regs = %p\n", ipu->vdi_reg);
 601
 602         ret = ipu_clk_setup_enable(ipu, pdev);
 603         if (ret < 0) {
 604                 dev_err(ipu->dev, "ipu clk setup failed\n");
 605                 goto failed_clk_setup;
 606         }
 607
 608         platform_set_drvdata(pdev, ipu);
 609
 610         ipu_reset(ipu);
 611
 612         ipu_disp_init(ipu);
 613
 614         /* Set sync refresh channels and CSI->mem channel as high priority */
 615         ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
 616
 617         /* Set MCU_T to divide MCU access window into 2 */
 618         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 619
 620         clk_disable(ipu->ipu_clk);
 621
 622         register_ipu_device(ipu, pdev->id);
 623
 624         return ret;
 625
 626 failed_clk_setup:
 627         iounmap(ipu->cm_reg);
 628         iounmap(ipu->ic_reg);
 629         iounmap(ipu->idmac_reg);
 630         iounmap(ipu->dc_reg);
 631         iounmap(ipu->dp_reg);
 632         iounmap(ipu->dmfc_reg);
 633         iounmap(ipu->di_reg[0]);
 634         iounmap(ipu->di_reg[1]);
 635         iounmap(ipu->smfc_reg);
 636         iounmap(ipu->csi_reg[0]);
 637         iounmap(ipu->csi_reg[1]);
 638         iounmap(ipu->cpmem_base);
 639         iounmap(ipu->tpmem_base);
 640         iounmap(ipu->dc_tmpl_reg);
 641         iounmap(ipu->disp_base[1]);
 642         iounmap(ipu->vdi_reg);
 643 failed_ioremap:
 644         if (ipu->irq_sync)
 645                 free_irq(ipu->irq_err, ipu);
 646 failed_req_irq_err:
 647         free_irq(ipu->irq_sync, ipu);
 648 failed_req_irq_sync:
 649 failed_get_res:
 650         return ret;
 651 }
 652
 653 int __devexit ipu_remove(struct platform_device *pdev)
 654 {
 655         struct ipu_soc *ipu = platform_get_drvdata(pdev);
 656
 657         unregister_ipu_device(ipu, pdev->id);
 658
 659         if (ipu->irq_sync)
 660                 free_irq(ipu->irq_sync, ipu);
 661         if (ipu->irq_err)
 662                 free_irq(ipu->irq_err, ipu);
 663
 664         clk_put(ipu->ipu_clk);
 665
 666         iounmap(ipu->cm_reg);
 667         iounmap(ipu->ic_reg);
 668         iounmap(ipu->idmac_reg);
 669         iounmap(ipu->dc_reg);
 670         iounmap(ipu->dp_reg);
 671         iounmap(ipu->dmfc_reg);
 672         iounmap(ipu->di_reg[0]);
 673         iounmap(ipu->di_reg[1]);
 674         iounmap(ipu->smfc_reg);
 675         iounmap(ipu->csi_reg[0]);
 676         iounmap(ipu->csi_reg[1]);
 677         iounmap(ipu->cpmem_base);
 678         iounmap(ipu->tpmem_base);
 679         iounmap(ipu->dc_tmpl_reg);
 680         iounmap(ipu->disp_base[1]);
 681         iounmap(ipu->vdi_reg);
 682
 683         return 0;
 684 }
 685
 686 void ipu_dump_registers(struct ipu_soc *ipu)
 687 {
 688         dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", ipu_cm_read(ipu, IPU_CONF));
 689         dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", ipu_idmac_read(ipu, IDMAC_CONF));
 690         dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
 691                ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
 692         dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
 693                ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
 694         dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
 695                ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
 696         dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
 697                ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
 698         dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
 699                ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
 700         dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
 701                ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
 702         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
 703                ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
 704         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
 705                ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
 706         if (g_ipu_hw_rev >= 2) {
 707                 dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
 708                        ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0)));
 709                 dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
 710                        ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32)));
 711         }
 712         dev_dbg(ipu->dev, "DMFC_WR_CHAN = \t0x%08X\n",
 713                ipu_dmfc_read(ipu, DMFC_WR_CHAN));
 714         dev_dbg(ipu->dev, "DMFC_WR_CHAN_DEF = \t0x%08X\n",
 715                ipu_dmfc_read(ipu, DMFC_WR_CHAN_DEF));
 716         dev_dbg(ipu->dev, "DMFC_DP_CHAN = \t0x%08X\n",
 717                ipu_dmfc_read(ipu, DMFC_DP_CHAN));
 718         dev_dbg(ipu->dev, "DMFC_DP_CHAN_DEF = \t0x%08X\n",
 719                ipu_dmfc_read(ipu, DMFC_DP_CHAN_DEF));
 720         dev_dbg(ipu->dev, "DMFC_IC_CTRL = \t0x%08X\n",
 721                ipu_dmfc_read(ipu, DMFC_IC_CTRL));
 722         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
 723                ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
 724         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
 725                ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
 726         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
 727                ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
 728         dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
 729                ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
 730 }
 731
 732 /*!
 733  * This function is called to initialize a logical IPU channel.
 734  *
 735  * @param       ipu     ipu handler
 736  * @param       channel Input parameter for the logical channel ID to init.
 737  *
 738  * @param       params  Input parameter containing union of channel
 739  *                      initialization parameters.
 740  *
 741  * @return      Returns 0 on success or negative error code on fail
 742  */
 743 int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
 744 {
 745         int ret = 0;
 746         uint32_t ipu_conf;
 747         uint32_t reg;
 748         unsigned long lock_flags;
 749
 750         dev_dbg(ipu->dev, "init channel = %d\n", IPU_CHAN_ID(channel));
 751
 752         if (ipu->clk_enabled == false) {
 753                 ipu->clk_enabled = true;
 754                 clk_enable(ipu->ipu_clk);
 755         }
 756
 757         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
 758
 759         if (ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 760                 dev_err(ipu->dev, "Warning: channel already initialized %d\n",
 761                         IPU_CHAN_ID(channel));
 762         }
 763
 764         ipu_conf = ipu_cm_read(ipu, IPU_CONF);
 765
 766         switch (channel) {
 767         case CSI_MEM0:
 768         case CSI_MEM1:
 769         case CSI_MEM2:
 770         case CSI_MEM3:
 771                 if (params->csi_mem.csi > 1) {
 772                         ret = -EINVAL;
 773                         goto err;
 774                 }
 775
 776                 if (params->csi_mem.interlaced)
 777                         ipu->chan_is_interlaced[channel_2_dma(channel,
 778                                 IPU_OUTPUT_BUFFER)] = true;
 779                 else
 780                         ipu->chan_is_interlaced[channel_2_dma(channel,
 781                                 IPU_OUTPUT_BUFFER)] = false;
 782
 783                 ipu->smfc_use_count++;
 784                 ipu->csi_channel[params->csi_mem.csi] = channel;
 785
 786                 /*SMFC setting*/
 787                 if (params->csi_mem.mipi_en) {
 788                         ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 789                                 params->csi_mem.csi));
 790                         _ipu_smfc_init(ipu, channel, params->csi_mem.mipi_id,
 791                                 params->csi_mem.csi);
 792                 } else {
 793                         ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 794                                 params->csi_mem.csi));
 795                         _ipu_smfc_init(ipu, channel, 0, params->csi_mem.csi);
 796                 }
 797
 798                 /*CSI data (include compander) dest*/
 799                 _ipu_csi_init(ipu, channel, params->csi_mem.csi);
 800                 break;
 801         case CSI_PRP_ENC_MEM:
 802                 if (params->csi_prp_enc_mem.csi > 1) {
 803                         ret = -EINVAL;
 804                         goto err;
 805                 }
 806                 if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
 807                         ret = -EINVAL;
 808                         goto err;
 809                 }
 810                 ipu->using_ic_dirct_ch = CSI_PRP_ENC_MEM;
 811
 812                 ipu->ic_use_count++;
 813                 ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel;
 814
 815                 /*Without SMFC, CSI only support parallel data source*/
 816                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 817                         params->csi_prp_enc_mem.csi));
 818
 819                 /*CSI0/1 feed into IC*/
 820                 ipu_conf &= ~IPU_CONF_IC_INPUT;
 821                 if (params->csi_prp_enc_mem.csi)
 822                         ipu_conf |= IPU_CONF_CSI_SEL;
 823                 else
 824                         ipu_conf &= ~IPU_CONF_CSI_SEL;
 825
 826                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
 827                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 828                 ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
 829
 830                 /*CSI data (include compander) dest*/
 831                 _ipu_csi_init(ipu, channel, params->csi_prp_enc_mem.csi);
 832                 _ipu_ic_init_prpenc(ipu, params, true);
 833                 break;
 834         case CSI_PRP_VF_MEM:
 835                 if (params->csi_prp_vf_mem.csi > 1) {
 836                         ret = -EINVAL;
 837                         goto err;
 838                 }
 839                 if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
 840                         ret = -EINVAL;
 841                         goto err;
 842                 }
 843                 ipu->using_ic_dirct_ch = CSI_PRP_VF_MEM;
 844
 845                 ipu->ic_use_count++;
 846                 ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel;
 847
 848                 /*Without SMFC, CSI only support parallel data source*/
 849                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
 850                         params->csi_prp_vf_mem.csi));
 851
 852                 /*CSI0/1 feed into IC*/
 853                 ipu_conf &= ~IPU_CONF_IC_INPUT;
 854                 if (params->csi_prp_vf_mem.csi)
 855                         ipu_conf |= IPU_CONF_CSI_SEL;
 856                 else
 857                         ipu_conf &= ~IPU_CONF_CSI_SEL;
 858
 859                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
 860                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 861                 ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 862
 863                 /*CSI data (include compander) dest*/
 864                 _ipu_csi_init(ipu, channel, params->csi_prp_vf_mem.csi);
 865                 _ipu_ic_init_prpvf(ipu, params, true);
 866                 break;
 867         case MEM_PRP_VF_MEM:
 868                 ipu->ic_use_count++;
 869                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 870                 ipu_cm_write(ipu, reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
 871
 872                 if (params->mem_prp_vf_mem.graphics_combine_en)
 873                         ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
 874                 if (params->mem_prp_vf_mem.alpha_chan_en)
 875                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 876
 877                 _ipu_ic_init_prpvf(ipu, params, false);
 878                 break;
 879         case MEM_VDI_PRP_VF_MEM:
 880                 if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
 881                      (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
 882                         ret = -EINVAL;
 883                         goto err;
 884                 }
 885                 ipu->using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
 886                 ipu->ic_use_count++;
 887                 ipu->vdi_use_count++;
 888                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 889                 reg &= ~FS_VDI_SRC_SEL_MASK;
 890                 ipu_cm_write(ipu, reg , IPU_FS_PROC_FLOW1);
 891
 892                 if (params->mem_prp_vf_mem.graphics_combine_en)
 893                         ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
 894                 _ipu_ic_init_prpvf(ipu, params, false);
 895                 _ipu_vdi_init(ipu, channel, params);
 896                 break;
 897         case MEM_VDI_PRP_VF_MEM_P:
 898                 _ipu_vdi_init(ipu, channel, params);
 899                 break;
 900         case MEM_VDI_PRP_VF_MEM_N:
 901                 _ipu_vdi_init(ipu, channel, params);
 902                 break;
 903         case MEM_ROT_VF_MEM:
 904                 ipu->ic_use_count++;
 905                 ipu->rot_use_count++;
 906                 _ipu_ic_init_rotate_vf(ipu, params);
 907                 break;
 908         case MEM_PRP_ENC_MEM:
 909                 ipu->ic_use_count++;
 910                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
 911                 ipu_cm_write(ipu, reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
 912                 _ipu_ic_init_prpenc(ipu, params, false);
 913                 break;
 914         case MEM_ROT_ENC_MEM:
 915                 ipu->ic_use_count++;
 916                 ipu->rot_use_count++;
 917                 _ipu_ic_init_rotate_enc(ipu, params);
 918                 break;
 919         case MEM_PP_MEM:
 920                 if (params->mem_pp_mem.graphics_combine_en)
 921                         ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
 922                 if (params->mem_pp_mem.alpha_chan_en)
 923                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 924                 _ipu_ic_init_pp(ipu, params);
 925                 ipu->ic_use_count++;
 926                 break;
 927         case MEM_ROT_PP_MEM:
 928                 _ipu_ic_init_rotate_pp(ipu, params);
 929                 ipu->ic_use_count++;
 930                 ipu->rot_use_count++;
 931                 break;
 932         case MEM_DC_SYNC:
 933                 if (params->mem_dc_sync.di > 1) {
 934                         ret = -EINVAL;
 935                         goto err;
 936                 }
 937
 938                 ipu->dc_di_assignment[1] = params->mem_dc_sync.di;
 939                 _ipu_dc_init(ipu, 1, params->mem_dc_sync.di,
 940                              params->mem_dc_sync.interlaced,
 941                              params->mem_dc_sync.out_pixel_fmt);
 942                 ipu->di_use_count[params->mem_dc_sync.di]++;
 943                 ipu->dc_use_count++;
 944                 ipu->dmfc_use_count++;
 945                 break;
 946         case MEM_BG_SYNC:
 947                 if (params->mem_dp_bg_sync.di > 1) {
 948                         ret = -EINVAL;
 949                         goto err;
 950                 }
 951
 952                 if (params->mem_dp_bg_sync.alpha_chan_en)
 953                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 954
 955                 ipu->dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 956                 _ipu_dp_init(ipu, channel, params->mem_dp_bg_sync.in_pixel_fmt,
 957                              params->mem_dp_bg_sync.out_pixel_fmt);
 958                 _ipu_dc_init(ipu, 5, params->mem_dp_bg_sync.di,
 959                              params->mem_dp_bg_sync.interlaced,
 960                              params->mem_dp_bg_sync.out_pixel_fmt);
 961                 ipu->di_use_count[params->mem_dp_bg_sync.di]++;
 962                 ipu->dc_use_count++;
 963                 ipu->dp_use_count++;
 964                 ipu->dmfc_use_count++;
 965                 break;
 966         case MEM_FG_SYNC:
 967                 _ipu_dp_init(ipu, channel, params->mem_dp_fg_sync.in_pixel_fmt,
 968                              params->mem_dp_fg_sync.out_pixel_fmt);
 969
 970                 if (params->mem_dp_fg_sync.alpha_chan_en)
 971                         ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
 972
 973                 ipu->dc_use_count++;
 974                 ipu->dp_use_count++;
 975                 ipu->dmfc_use_count++;
 976                 break;
 977         case DIRECT_ASYNC0:
 978                 if (params->direct_async.di > 1) {
 979                         ret = -EINVAL;
 980                         goto err;
 981                 }
 982
 983                 ipu->dc_di_assignment[8] = params->direct_async.di;
 984                 _ipu_dc_init(ipu, 8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 985                 ipu->di_use_count[params->direct_async.di]++;
 986                 ipu->dc_use_count++;
 987                 break;
 988         case DIRECT_ASYNC1:
 989                 if (params->direct_async.di > 1) {
 990                         ret = -EINVAL;
 991                         goto err;
 992                 }
 993
 994                 ipu->dc_di_assignment[9] = params->direct_async.di;
 995                 _ipu_dc_init(ipu, 9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
 996                 ipu->di_use_count[params->direct_async.di]++;
 997                 ipu->dc_use_count++;
 998                 break;
 999         default:
1000                 dev_err(ipu->dev, "Missing channel initialization\n");
1001                 break;
1002         }
1003
1004         /* Enable IPU sub module */
1005         ipu->channel_init_mask |= 1L << IPU_CHAN_ID(channel);
1006
1007         ipu_cm_write(ipu, ipu_conf, IPU_CONF);
1008
1009 err:
1010         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1011         return ret;
1012 }
1013 EXPORT_SYMBOL(ipu_init_channel);
1014
1015 /*!
1016  * This function is called to uninitialize a logical IPU channel.
1017  *
1018  * @param       ipu     ipu handler
1019  * @param       channel Input parameter for the logical channel ID to uninit.
1020  */
1021 void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel)
1022 {
1023         unsigned long lock_flags;
1024         uint32_t reg;
1025         uint32_t in_dma, out_dma = 0;
1026         uint32_t ipu_conf;
1027
1028         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1029
1030         if ((ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1031                 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1032                         IPU_CHAN_ID(channel));
1033                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1034                 return;
1035         }
1036
1037         /* Make sure channel is disabled */
1038         /* Get input and output dma channels */
1039         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1040         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1041
1042         if (idma_is_set(ipu, IDMAC_CHA_EN, in_dma) ||
1043             idma_is_set(ipu, IDMAC_CHA_EN, out_dma)) {
1044                 dev_err(ipu->dev,
1045                         "Channel %d is not disabled, disable first\n",
1046                         IPU_CHAN_ID(channel));
1047                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1048                 return;
1049         }
1050
1051         ipu_conf = ipu_cm_read(ipu, IPU_CONF);
1052
1053         /* Reset the double buffer */
1054         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(in_dma));
1055         ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
1056         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(out_dma));
1057         ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
1058
1059         /* Reset the triple buffer */
1060         reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(in_dma));
1061         ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
1062         reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(out_dma));
1063         ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
1064
1065         if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
1066                 ipu->sec_chan_en[IPU_CHAN_ID(channel)] = false;
1067                 ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = false;
1068         }
1069
1070         switch (channel) {
1071         case CSI_MEM0:
1072         case CSI_MEM1:
1073         case CSI_MEM2:
1074         case CSI_MEM3:
1075                 ipu->smfc_use_count--;
1076                 if (ipu->csi_channel[0] == channel) {
1077                         ipu->csi_channel[0] = CHAN_NONE;
1078                 } else if (ipu->csi_channel[1] == channel) {
1079                         ipu->csi_channel[1] = CHAN_NONE;
1080                 }
1081                 break;
1082         case CSI_PRP_ENC_MEM:
1083                 ipu->ic_use_count--;
1084                 if (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)
1085                         ipu->using_ic_dirct_ch = 0;
1086                 _ipu_ic_uninit_prpenc(ipu);
1087                 if (ipu->csi_channel[0] == channel) {
1088                         ipu->csi_channel[0] = CHAN_NONE;
1089                 } else if (ipu->csi_channel[1] == channel) {
1090                         ipu->csi_channel[1] = CHAN_NONE;
1091                 }
1092                 break;
1093         case CSI_PRP_VF_MEM:
1094                 ipu->ic_use_count--;
1095                 if (ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM)
1096                         ipu->using_ic_dirct_ch = 0;
1097                 _ipu_ic_uninit_prpvf(ipu);
1098                 if (ipu->csi_channel[0] == channel) {
1099                         ipu->csi_channel[0] = CHAN_NONE;
1100                 } else if (ipu->csi_channel[1] == channel) {
1101                         ipu->csi_channel[1] = CHAN_NONE;
1102                 }
1103                 break;
1104         case MEM_PRP_VF_MEM:
1105                 ipu->ic_use_count--;
1106                 _ipu_ic_uninit_prpvf(ipu);
1107                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1108                 ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
1109                 break;
1110         case MEM_VDI_PRP_VF_MEM:
1111                 ipu->ic_use_count--;
1112                 ipu->vdi_use_count--;
1113                 if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
1114                         ipu->using_ic_dirct_ch = 0;
1115                 _ipu_ic_uninit_prpvf(ipu);
1116                 _ipu_vdi_uninit(ipu);
1117                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1118                 ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
1119                 break;
1120         case MEM_VDI_PRP_VF_MEM_P:
1121         case MEM_VDI_PRP_VF_MEM_N:
1122                 break;
1123         case MEM_ROT_VF_MEM:
1124                 ipu->rot_use_count--;
1125                 ipu->ic_use_count--;
1126                 _ipu_ic_uninit_rotate_vf(ipu);
1127                 break;
1128         case MEM_PRP_ENC_MEM:
1129                 ipu->ic_use_count--;
1130                 _ipu_ic_uninit_prpenc(ipu);
1131                 reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1132                 ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
1133                 break;
1134         case MEM_ROT_ENC_MEM:
1135                 ipu->rot_use_count--;
1136                 ipu->ic_use_count--;
1137                 _ipu_ic_uninit_rotate_enc(ipu);
1138                 break;
1139         case MEM_PP_MEM:
1140                 ipu->ic_use_count--;
1141                 _ipu_ic_uninit_pp(ipu);
1142                 break;
1143         case MEM_ROT_PP_MEM:
1144                 ipu->rot_use_count--;
1145                 ipu->ic_use_count--;
1146                 _ipu_ic_uninit_rotate_pp(ipu);
1147                 break;
1148         case MEM_DC_SYNC:
1149                 _ipu_dc_uninit(ipu, 1);
1150                 ipu->di_use_count[ipu->dc_di_assignment[1]]--;
1151                 ipu->dc_use_count--;
1152                 ipu->dmfc_use_count--;
1153                 break;
1154         case MEM_BG_SYNC:
1155                 _ipu_dp_uninit(ipu, channel);
1156                 _ipu_dc_uninit(ipu, 5);
1157                 ipu->di_use_count[ipu->dc_di_assignment[5]]--;
1158                 ipu->dc_use_count--;
1159                 ipu->dp_use_count--;
1160                 ipu->dmfc_use_count--;
1161                 break;
1162         case MEM_FG_SYNC:
1163                 _ipu_dp_uninit(ipu, channel);
1164                 ipu->dc_use_count--;
1165                 ipu->dp_use_count--;
1166                 ipu->dmfc_use_count--;
1167                 break;
1168         case DIRECT_ASYNC0:
1169                 _ipu_dc_uninit(ipu, 8);
1170                 ipu->di_use_count[ipu->dc_di_assignment[8]]--;
1171                 ipu->dc_use_count--;
1172                 break;
1173         case DIRECT_ASYNC1:
1174                 _ipu_dc_uninit(ipu, 9);
1175                 ipu->di_use_count[ipu->dc_di_assignment[9]]--;
1176                 ipu->dc_use_count--;
1177                 break;
1178         default:
1179                 break;
1180         }
1181
1182         ipu->channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
1183
1184         if (ipu->ic_use_count == 0)
1185                 ipu_conf &= ~IPU_CONF_IC_EN;
1186         if (ipu->vdi_use_count == 0) {
1187                 ipu_conf &= ~IPU_CONF_ISP_EN;
1188                 ipu_conf &= ~IPU_CONF_VDI_EN;
1189                 ipu_conf &= ~IPU_CONF_IC_INPUT;
1190         }
1191         if (ipu->rot_use_count == 0)
1192                 ipu_conf &= ~IPU_CONF_ROT_EN;
1193         if (ipu->dc_use_count == 0)
1194                 ipu_conf &= ~IPU_CONF_DC_EN;
1195         if (ipu->dp_use_count == 0)
1196                 ipu_conf &= ~IPU_CONF_DP_EN;
1197         if (ipu->dmfc_use_count == 0)
1198                 ipu_conf &= ~IPU_CONF_DMFC_EN;
1199         if (ipu->di_use_count[0] == 0) {
1200                 ipu_conf &= ~IPU_CONF_DI0_EN;
1201         }
1202         if (ipu->di_use_count[1] == 0) {
1203                 ipu_conf &= ~IPU_CONF_DI1_EN;
1204         }
1205         if (ipu->smfc_use_count == 0)
1206                 ipu_conf &= ~IPU_CONF_SMFC_EN;
1207
1208         ipu_cm_write(ipu, ipu_conf, IPU_CONF);
1209
1210         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1211
1212         if (ipu_conf == 0) {
1213                 clk_disable(ipu->ipu_clk);
1214                 ipu->clk_enabled = false;
1215         }
1216
1217         WARN_ON(ipu->ic_use_count < 0);
1218         WARN_ON(ipu->vdi_use_count < 0);
1219         WARN_ON(ipu->rot_use_count < 0);
1220         WARN_ON(ipu->dc_use_count < 0);
1221         WARN_ON(ipu->dp_use_count < 0);
1222         WARN_ON(ipu->dmfc_use_count < 0);
1223         WARN_ON(ipu->smfc_use_count < 0);
1224 }
1225 EXPORT_SYMBOL(ipu_uninit_channel);
1226
1227 /*!
1228  * This function is called to initialize buffer(s) for logical IPU channel.
1229  *
1230  * @param       ipu             ipu handler
1231  *
1232  * @param       channel         Input parameter for the logical channel ID.
1233  *
1234  * @param       type            Input parameter which buffer to initialize.
1235  *
1236  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1237  *                              Pixel format is a FOURCC ASCII code.
1238  *
1239  * @param       width           Input parameter for width of buffer in pixels.
1240  *
1241  * @param       height          Input parameter for height of buffer in pixels.
1242  *
1243  * @param       stride          Input parameter for stride length of buffer
1244  *                              in pixels.
1245  *
1246  * @param       rot_mode        Input parameter for rotation setting of buffer.
1247  *                              A rotation setting other than
1248  *                              IPU_ROTATE_VERT_FLIP
1249  *                              should only be used for input buffers of
1250  *                              rotation channels.
1251  *
1252  * @param       phyaddr_0       Input parameter buffer 0 physical address.
1253  *
1254  * @param       phyaddr_1       Input parameter buffer 1 physical address.
1255  *                              Setting this to a value other than NULL enables
1256  *                              double buffering mode.
1257  *
1258  * @param       phyaddr_2       Input parameter buffer 2 physical address.
1259  *                              Setting this to a value other than NULL enables
1260  *                              triple buffering mode, phyaddr_1 should not be
1261  *                              NULL then.
1262  *
1263  * @param       u               private u offset for additional cropping,
1264  *                              zero if not used.
1265  *
1266  * @param       v               private v offset for additional cropping,
1267  *                              zero if not used.
1268  *
1269  * @return      Returns 0 on success or negative error code on fail
1270  */
1271 int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
1272                                 ipu_buffer_t type,
1273                                 uint32_t pixel_fmt,
1274                                 uint16_t width, uint16_t height,
1275                                 uint32_t stride,
1276                                 ipu_rotate_mode_t rot_mode,
1277                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
1278                                 dma_addr_t phyaddr_2,
1279                                 uint32_t u, uint32_t v)
1280 {
1281         unsigned long lock_flags;
1282         uint32_t reg;
1283         uint32_t dma_chan;
1284         uint32_t burst_size;
1285
1286         dma_chan = channel_2_dma(channel, type);
1287         if (!idma_is_valid(dma_chan))
1288                 return -EINVAL;
1289
1290         if (stride < width * bytes_per_pixel(pixel_fmt))
1291                 stride = width * bytes_per_pixel(pixel_fmt);
1292
1293         if (stride % 4) {
1294                 dev_err(ipu->dev,
1295                         "Stride not 32-bit aligned, stride = %d\n", stride);
1296                 return -EINVAL;
1297         }
1298         /* IC & IRT channels' width must be multiple of 8 pixels */
1299         if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
1300                 && (width % 8)) {
1301                 dev_err(ipu->dev, "Width must be 8 pixel multiple\n");
1302                 return -EINVAL;
1303         }
1304
1305         /* IPUv3EX and IPUv3M support triple buffer */
1306         if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
1307                 dev_err(ipu->dev, "Chan%d doesn't support triple buffer "
1308                                    "mode\n", dma_chan);
1309                 return -EINVAL;
1310         }
1311         if (!phyaddr_1 && phyaddr_2) {
1312                 dev_err(ipu->dev, "Chan%d's buf1 physical addr is NULL for "
1313                                    "triple buffer mode\n", dma_chan);
1314                 return -EINVAL;
1315         }
1316
1317         /* Build parameter memory data for DMA channel */
1318         _ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, u, v, 0,
1319                            phyaddr_0, phyaddr_1, phyaddr_2);
1320
1321         /* Set correlative channel parameter of local alpha channel */
1322         if ((_ipu_is_ic_graphic_chan(dma_chan) ||
1323              _ipu_is_dp_graphic_chan(dma_chan)) &&
1324             (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
1325                 _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, true);
1326                 _ipu_ch_param_set_alpha_buffer_memory(ipu, dma_chan);
1327                 _ipu_ch_param_set_alpha_condition_read(ipu, dma_chan);
1328                 /* fix alpha width as 8 and burst size as 16*/
1329                 _ipu_ch_params_set_alpha_width(ipu, dma_chan, 8);
1330                 _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
1331         } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
1332                    ipu_pixel_format_has_alpha(pixel_fmt))
1333                 _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, false);
1334
1335         if (rot_mode)
1336                 _ipu_ch_param_set_rotation(ipu, dma_chan, rot_mode);
1337
1338         /* IC and ROT channels have restriction of 8 or 16 pix burst length */
1339         if (_ipu_is_ic_chan(dma_chan)) {
1340                 if ((width % 16) == 0)
1341                         _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
1342                 else
1343                         _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
1344         } else if (_ipu_is_irt_chan(dma_chan)) {
1345                 _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
1346                 _ipu_ch_param_set_block_mode(ipu, dma_chan);
1347         } else if (_ipu_is_dmfc_chan(dma_chan)) {
1348                 burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
1349                 spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1350                 _ipu_dmfc_set_wait4eot(ipu, dma_chan, width);
1351                 _ipu_dmfc_set_burst_size(ipu, dma_chan, burst_size);
1352                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1353         }
1354
1355         if (_ipu_disp_chan_is_interlaced(ipu, channel) ||
1356                 ipu->chan_is_interlaced[dma_chan])
1357                 _ipu_ch_param_set_interlaced_scan(ipu, dma_chan);
1358
1359         if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) {
1360                 burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
1361                 _ipu_ic_idma_init(ipu, dma_chan, width, height, burst_size,
1362                         rot_mode);
1363         } else if (_ipu_is_smfc_chan(dma_chan)) {
1364                 burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
1365                 if ((pixel_fmt == IPU_PIX_FMT_GENERIC) &&
1366                         ((_ipu_ch_param_get_bpp(ipu, dma_chan) == 5) ||
1367                         (_ipu_ch_param_get_bpp(ipu, dma_chan) == 3)))
1368                         burst_size = burst_size >> 4;
1369                 else
1370                         burst_size = burst_size >> 2;
1371                 _ipu_smfc_set_burst_size(ipu, channel, burst_size-1);
1372         }
1373
1374         if (idma_is_set(ipu, IDMAC_CHA_PRI, dma_chan) && !cpu_is_mx53()
1375                 && !cpu_is_mx6q())
1376                 _ipu_ch_param_set_high_priority(ipu, dma_chan);
1377
1378         _ipu_ch_param_dump(ipu, dma_chan);
1379
1380         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1381         if (phyaddr_2 && g_ipu_hw_rev >= 2) {
1382                 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
1383                 reg &= ~idma_mask(dma_chan);
1384                 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1385
1386                 reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
1387                 reg |= idma_mask(dma_chan);
1388                 ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1389
1390                 /* Set IDMAC third buffer's cpmem number */
1391                 /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
1392                 ipu_idmac_write(ipu, 0x00444047L, IDMAC_SUB_ADDR_4);
1393                 ipu_idmac_write(ipu, 0x46004241L, IDMAC_SUB_ADDR_3);
1394                 ipu_idmac_write(ipu, 0x00000045L, IDMAC_SUB_ADDR_1);
1395
1396                 /* Reset to buffer 0 */
1397                 ipu_cm_write(ipu, tri_cur_buf_mask(dma_chan),
1398                                 IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
1399         } else {
1400                 reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
1401                 reg &= ~idma_mask(dma_chan);
1402                 ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1403
1404                 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
1405                 if (phyaddr_1)
1406                         reg |= idma_mask(dma_chan);
1407                 else
1408                         reg &= ~idma_mask(dma_chan);
1409                 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1410
1411                 /* Reset to buffer 0 */
1412                 ipu_cm_write(ipu, idma_mask(dma_chan),
1413                                 IPU_CHA_CUR_BUF(dma_chan));
1414
1415         }
1416         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1417
1418         return 0;
1419 }
1420 EXPORT_SYMBOL(ipu_init_channel_buffer);
1421
1422 /*!
1423  * This function is called to update the physical address of a buffer for
1424  * a logical IPU channel.
1425  *
1426  * @param       ipu             ipu handler
1427  * @param       channel         Input parameter for the logical channel ID.
1428  *
1429  * @param       type            Input parameter which buffer to initialize.
1430  *
1431  * @param       bufNum          Input parameter for buffer number to update.
1432  *                              0 or 1 are the only valid values.
1433  *
1434  * @param       phyaddr         Input parameter buffer physical address.
1435  *
1436  * @return      This function returns 0 on success or negative error code on
1437  *              fail. This function will fail if the buffer is set to ready.
1438  */
1439 int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
1440                                 ipu_buffer_t type, uint32_t bufNum, dma_addr_t phyaddr)
1441 {
1442         uint32_t reg;
1443         int ret = 0;
1444         unsigned long lock_flags;
1445         uint32_t dma_chan = channel_2_dma(channel, type);
1446         if (dma_chan == IDMA_CHAN_INVALID)
1447                 return -EINVAL;
1448
1449         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1450
1451         if (bufNum == 0)
1452                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
1453         else if (bufNum == 1)
1454                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
1455         else
1456                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
1457
1458         if ((reg & idma_mask(dma_chan)) == 0)
1459                 _ipu_ch_param_set_buffer(ipu, dma_chan, bufNum, phyaddr);
1460         else
1461                 ret = -EACCES;
1462
1463         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1464         return ret;
1465 }
1466 EXPORT_SYMBOL(ipu_update_channel_buffer);
1467
1468
1469 /*!
1470  * This function is called to initialize a buffer for logical IPU channel.
1471  *
1472  * @param       ipu             ipu handler
1473  * @param       channel         Input parameter for the logical channel ID.
1474  *
1475  * @param       type            Input parameter which buffer to initialize.
1476  *
1477  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1478  *                              Pixel format is a FOURCC ASCII code.
1479  *
1480  * @param       width           Input parameter for width of buffer in pixels.
1481  *
1482  * @param       height          Input parameter for height of buffer in pixels.
1483  *
1484  * @param       stride          Input parameter for stride length of buffer
1485  *                              in pixels.
1486  *
1487  * @param       u               predefined private u offset for additional cropping,
1488  *                                                              zero if not used.
1489  *
1490  * @param       v               predefined private v offset for additional cropping,
1491  *                                                              zero if not used.
1492  *
1493  * @param                       vertical_offset vertical offset for Y coordinate
1494  *                                                              in the existed frame
1495  *
1496  *
1497  * @param                       horizontal_offset horizontal offset for X coordinate
1498  *                                                              in the existed frame
1499  *
1500  *
1501  * @return      Returns 0 on success or negative error code on fail
1502  *              This function will fail if any buffer is set to ready.
1503  */
1504
1505 int32_t ipu_update_channel_offset(struct ipu_soc *ipu,
1506                                 ipu_channel_t channel, ipu_buffer_t type,
1507                                 uint32_t pixel_fmt,
1508                                 uint16_t width, uint16_t height,
1509                                 uint32_t stride,
1510                                 uint32_t u, uint32_t v,
1511                                 uint32_t vertical_offset, uint32_t horizontal_offset)
1512 {
1513         int ret = 0;
1514         unsigned long lock_flags;
1515         uint32_t dma_chan = channel_2_dma(channel, type);
1516
1517         if (dma_chan == IDMA_CHAN_INVALID)
1518                 return -EINVAL;
1519
1520         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1521
1522         if ((ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1523             (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1524             ((ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
1525              (ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
1526              _ipu_is_trb_chan(dma_chan)))
1527                 ret = -EACCES;
1528         else
1529                 _ipu_ch_offset_update(ipu, dma_chan, pixel_fmt, width, height, stride,
1530                                       u, v, 0, vertical_offset, horizontal_offset);
1531
1532         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1533         return ret;
1534 }
1535 EXPORT_SYMBOL(ipu_update_channel_offset);
1536
1537
1538 /*!
1539  * This function is called to set a channel's buffer as ready.
1540  *
1541  * @param       ipu             ipu handler
1542  * @param       channel         Input parameter for the logical channel ID.
1543  *
1544  * @param       type            Input parameter which buffer to initialize.
1545  *
1546  * @param       bufNum          Input parameter for which buffer number set to
1547  *                              ready state.
1548  *
1549  * @return      Returns 0 on success or negative error code on fail
1550  */
1551 int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
1552                         ipu_buffer_t type, uint32_t bufNum)
1553 {
1554         uint32_t dma_chan = channel_2_dma(channel, type);
1555         unsigned long lock_flags;
1556
1557         if (dma_chan == IDMA_CHAN_INVALID)
1558                 return -EINVAL;
1559
1560         /* Mark buffer to be ready. */
1561         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1562         if (bufNum == 0)
1563                 ipu_cm_write(ipu, idma_mask(dma_chan),
1564                              IPU_CHA_BUF0_RDY(dma_chan));
1565         else if (bufNum == 1)
1566                 ipu_cm_write(ipu, idma_mask(dma_chan),
1567                              IPU_CHA_BUF1_RDY(dma_chan));
1568         else
1569                 ipu_cm_write(ipu, idma_mask(dma_chan),
1570                              IPU_CHA_BUF2_RDY(dma_chan));
1571         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1572         return 0;
1573 }
1574 EXPORT_SYMBOL(ipu_select_buffer);
1575
1576 /*!
1577  * This function is called to set a channel's buffer as ready.
1578  *
1579  * @param       ipu             ipu handler
1580  * @param       bufNum          Input parameter for which buffer number set to
1581  *                              ready state.
1582  *
1583  * @return      Returns 0 on success or negative error code on fail
1584  */
1585 int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum)
1586 {
1587
1588         uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
1589         uint32_t mask_bit =
1590                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
1591                 idma_mask(dma_chan)|
1592                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
1593         unsigned long lock_flags;
1594
1595         /* Mark buffers to be ready. */
1596         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1597         if (bufNum == 0)
1598                 ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
1599         else
1600                 ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
1601         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1602         return 0;
1603 }
1604 EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
1605
1606 #define NA      -1
1607 static int proc_dest_sel[] = {
1608         0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
1609         0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
1610 static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
1611   NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, 8, NA };
1612 static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
1613   NA, NA, NA, NA, NA,  1, NA,  2, NA,  3,  4,  4,  4,  4 };
1614
1615
1616 /*!
1617  * This function links 2 channels together for automatic frame
1618  * synchronization. The output of the source channel is linked to the input of
1619  * the destination channel.
1620  *
1621  * @param       ipu             ipu handler
1622  * @param       src_ch          Input parameter for the logical channel ID of
1623  *                              the source channel.
1624  *
1625  * @param       dest_ch         Input parameter for the logical channel ID of
1626  *                              the destination channel.
1627  *
1628  * @return      This function returns 0 on success or negative error code on
1629  *              fail.
1630  */
1631 int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
1632 {
1633         int retval = 0;
1634         unsigned long lock_flags;
1635         uint32_t fs_proc_flow1;
1636         uint32_t fs_proc_flow2;
1637         uint32_t fs_proc_flow3;
1638         uint32_t fs_disp_flow1;
1639
1640         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1641
1642         fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1643         fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
1644         fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
1645         fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
1646
1647         switch (src_ch) {
1648         case CSI_MEM0:
1649                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1650                 fs_proc_flow3 |=
1651                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1652                         FS_SMFC0_DEST_SEL_OFFSET;
1653                 break;
1654         case CSI_MEM1:
1655                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1656                 fs_proc_flow3 |=
1657                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1658                         FS_SMFC1_DEST_SEL_OFFSET;
1659                 break;
1660         case CSI_MEM2:
1661                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1662                 fs_proc_flow3 |=
1663                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1664                         FS_SMFC2_DEST_SEL_OFFSET;
1665                 break;
1666         case CSI_MEM3:
1667                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1668                 fs_proc_flow3 |=
1669                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1670                         FS_SMFC3_DEST_SEL_OFFSET;
1671                 break;
1672         case CSI_PRP_ENC_MEM:
1673                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1674                 fs_proc_flow2 |=
1675                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1676                         FS_PRPENC_DEST_SEL_OFFSET;
1677                 break;
1678         case CSI_PRP_VF_MEM:
1679                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1680                 fs_proc_flow2 |=
1681                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1682                         FS_PRPVF_DEST_SEL_OFFSET;
1683                 break;
1684         case MEM_PP_MEM:
1685                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1686                 fs_proc_flow2 |=
1687                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1688                     FS_PP_DEST_SEL_OFFSET;
1689                 break;
1690         case MEM_ROT_PP_MEM:
1691                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1692                 fs_proc_flow2 |=
1693                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1694                     FS_PP_ROT_DEST_SEL_OFFSET;
1695                 break;
1696         case MEM_PRP_ENC_MEM:
1697                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1698                 fs_proc_flow2 |=
1699                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1700                     FS_PRPENC_DEST_SEL_OFFSET;
1701                 break;
1702         case MEM_ROT_ENC_MEM:
1703                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1704                 fs_proc_flow2 |=
1705                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1706                     FS_PRPENC_ROT_DEST_SEL_OFFSET;
1707                 break;
1708         case MEM_PRP_VF_MEM:
1709                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1710                 fs_proc_flow2 |=
1711                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1712                     FS_PRPVF_DEST_SEL_OFFSET;
1713                 break;
1714         case MEM_VDI_PRP_VF_MEM:
1715                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1716                 fs_proc_flow2 |=
1717                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1718                     FS_PRPVF_DEST_SEL_OFFSET;
1719                 break;
1720         case MEM_ROT_VF_MEM:
1721                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1722                 fs_proc_flow2 |=
1723                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1724                     FS_PRPVF_ROT_DEST_SEL_OFFSET;
1725                 break;
1726         default:
1727                 retval = -EINVAL;
1728                 goto err;
1729         }
1730
1731         switch (dest_ch) {
1732         case MEM_PP_MEM:
1733                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1734                 fs_proc_flow1 |=
1735                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET;
1736                 break;
1737         case MEM_ROT_PP_MEM:
1738                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1739                 fs_proc_flow1 |=
1740                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1741                     FS_PP_ROT_SRC_SEL_OFFSET;
1742                 break;
1743         case MEM_PRP_ENC_MEM:
1744                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1745                 fs_proc_flow1 |=
1746                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1747                 break;
1748         case MEM_ROT_ENC_MEM:
1749                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1750                 fs_proc_flow1 |=
1751                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1752                     FS_PRPENC_ROT_SRC_SEL_OFFSET;
1753                 break;
1754         case MEM_PRP_VF_MEM:
1755                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1756                 fs_proc_flow1 |=
1757                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1758                 break;
1759         case MEM_VDI_PRP_VF_MEM:
1760                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1761                 fs_proc_flow1 |=
1762                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1763                 break;
1764         case MEM_ROT_VF_MEM:
1765                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1766                 fs_proc_flow1 |=
1767                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1768                     FS_PRPVF_ROT_SRC_SEL_OFFSET;
1769                 break;
1770         case MEM_DC_SYNC:
1771                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1772                 fs_disp_flow1 |=
1773                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
1774                 break;
1775         case MEM_BG_SYNC:
1776                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1777                 fs_disp_flow1 |=
1778                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1779                     FS_DP_SYNC0_SRC_SEL_OFFSET;
1780                 break;
1781         case MEM_FG_SYNC:
1782                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1783                 fs_disp_flow1 |=
1784                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1785                     FS_DP_SYNC1_SRC_SEL_OFFSET;
1786                 break;
1787         case MEM_DC_ASYNC:
1788                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1789                 fs_disp_flow1 |=
1790                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
1791                 break;
1792         case MEM_BG_ASYNC0:
1793                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1794                 fs_disp_flow1 |=
1795                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1796                     FS_DP_ASYNC0_SRC_SEL_OFFSET;
1797                 break;
1798         case MEM_FG_ASYNC0:
1799                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1800                 fs_disp_flow1 |=
1801                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1802                     FS_DP_ASYNC1_SRC_SEL_OFFSET;
1803                 break;
1804         default:
1805                 retval = -EINVAL;
1806                 goto err;
1807         }
1808
1809         ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
1810         ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
1811         ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
1812         ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
1813
1814 err:
1815         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1816         return retval;
1817 }
1818 EXPORT_SYMBOL(ipu_link_channels);
1819
1820 /*!
1821  * This function unlinks 2 channels and disables automatic frame
1822  * synchronization.
1823  *
1824  * @param       ipu             ipu handler
1825  * @param       src_ch          Input parameter for the logical channel ID of
1826  *                              the source channel.
1827  *
1828  * @param       dest_ch         Input parameter for the logical channel ID of
1829  *                              the destination channel.
1830  *
1831  * @return      This function returns 0 on success or negative error code on
1832  *              fail.
1833  */
1834 int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
1835 {
1836         int retval = 0;
1837         unsigned long lock_flags;
1838         uint32_t fs_proc_flow1;
1839         uint32_t fs_proc_flow2;
1840         uint32_t fs_proc_flow3;
1841         uint32_t fs_disp_flow1;
1842
1843         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1844
1845         fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
1846         fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
1847         fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
1848         fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
1849
1850         switch (src_ch) {
1851         case CSI_MEM0:
1852                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1853                 break;
1854         case CSI_MEM1:
1855                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1856                 break;
1857         case CSI_MEM2:
1858                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1859                 break;
1860         case CSI_MEM3:
1861                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1862                 break;
1863         case CSI_PRP_ENC_MEM:
1864                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1865                 break;
1866         case CSI_PRP_VF_MEM:
1867                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1868                 break;
1869         case MEM_PP_MEM:
1870                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1871                 break;
1872         case MEM_ROT_PP_MEM:
1873                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1874                 break;
1875         case MEM_PRP_ENC_MEM:
1876                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1877                 break;
1878         case MEM_ROT_ENC_MEM:
1879                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1880                 break;
1881         case MEM_PRP_VF_MEM:
1882                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1883                 break;
1884         case MEM_VDI_PRP_VF_MEM:
1885                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1886                 break;
1887         case MEM_ROT_VF_MEM:
1888                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1889                 break;
1890         default:
1891                 retval = -EINVAL;
1892                 goto err;
1893         }
1894
1895         switch (dest_ch) {
1896         case MEM_PP_MEM:
1897                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1898                 break;
1899         case MEM_ROT_PP_MEM:
1900                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1901                 break;
1902         case MEM_PRP_ENC_MEM:
1903                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1904                 break;
1905         case MEM_ROT_ENC_MEM:
1906                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1907                 break;
1908         case MEM_PRP_VF_MEM:
1909                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1910                 break;
1911         case MEM_VDI_PRP_VF_MEM:
1912                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1913                 break;
1914         case MEM_ROT_VF_MEM:
1915                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1916                 break;
1917         case MEM_DC_SYNC:
1918                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1919                 break;
1920         case MEM_BG_SYNC:
1921                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1922                 break;
1923         case MEM_FG_SYNC:
1924                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1925                 break;
1926         case MEM_DC_ASYNC:
1927                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1928                 break;
1929         case MEM_BG_ASYNC0:
1930                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1931                 break;
1932         case MEM_FG_ASYNC0:
1933                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1934                 break;
1935         default:
1936                 retval = -EINVAL;
1937                 goto err;
1938         }
1939
1940         ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
1941         ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
1942         ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
1943         ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
1944
1945 err:
1946         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1947         return retval;
1948 }
1949 EXPORT_SYMBOL(ipu_unlink_channels);
1950
1951 /*!
1952  * This function check whether a logical channel was enabled.
1953  *
1954  * @param       ipu             ipu handler
1955  * @param       channel         Input parameter for the logical channel ID.
1956  *
1957  * @return      This function returns 1 while request channel is enabled or
1958  *              0 for not enabled.
1959  */
1960 int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel)
1961 {
1962         uint32_t reg;
1963         uint32_t in_dma;
1964         uint32_t out_dma;
1965
1966         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1967         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1968
1969         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
1970         if (reg & idma_mask(in_dma))
1971                 return 1;
1972         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
1973         if (reg & idma_mask(out_dma))
1974                 return 1;
1975         return 0;
1976 }
1977 EXPORT_SYMBOL(ipu_is_channel_busy);
1978
1979 /*!
1980  * This function enables a logical channel.
1981  *
1982  * @param       ipu             ipu handler
1983  * @param       channel         Input parameter for the logical channel ID.
1984  *
1985  * @return      This function returns 0 on success or negative error code on
1986  *              fail.
1987  */
1988 int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel)
1989 {
1990         uint32_t reg;
1991         unsigned long lock_flags;
1992         uint32_t ipu_conf;
1993         uint32_t in_dma;
1994         uint32_t out_dma;
1995         uint32_t sec_dma;
1996         uint32_t thrd_dma;
1997
1998         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1999
2000         if (ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
2001                 dev_err(ipu->dev, "Warning: channel already enabled %d\n",
2002                         IPU_CHAN_ID(channel));
2003                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2004                 return -EACCES;
2005         }
2006
2007         /* Get input and output dma channels */
2008         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
2009         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
2010
2011         ipu_conf = ipu_cm_read(ipu, IPU_CONF);
2012         if (ipu->di_use_count[0] > 0) {
2013                 ipu_conf |= IPU_CONF_DI0_EN;
2014         }
2015         if (ipu->di_use_count[1] > 0) {
2016                 ipu_conf |= IPU_CONF_DI1_EN;
2017         }
2018         if (ipu->dp_use_count > 0)
2019                 ipu_conf |= IPU_CONF_DP_EN;
2020         if (ipu->dc_use_count > 0)
2021                 ipu_conf |= IPU_CONF_DC_EN;
2022         if (ipu->dmfc_use_count > 0)
2023                 ipu_conf |= IPU_CONF_DMFC_EN;
2024         if (ipu->ic_use_count > 0)
2025                 ipu_conf |= IPU_CONF_IC_EN;
2026         if (ipu->vdi_use_count > 0) {
2027                 ipu_conf |= IPU_CONF_ISP_EN;
2028                 ipu_conf |= IPU_CONF_VDI_EN;
2029                 ipu_conf |= IPU_CONF_IC_INPUT;
2030         }
2031         if (ipu->rot_use_count > 0)
2032                 ipu_conf |= IPU_CONF_ROT_EN;
2033         if (ipu->smfc_use_count > 0)
2034                 ipu_conf |= IPU_CONF_SMFC_EN;
2035         ipu_cm_write(ipu, ipu_conf, IPU_CONF);
2036
2037         if (idma_is_valid(in_dma)) {
2038                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
2039                 ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
2040         }
2041         if (idma_is_valid(out_dma)) {
2042                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
2043                 ipu_idmac_write(ipu, reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
2044         }
2045
2046         if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
2047                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
2048                  (channel == MEM_VDI_PRP_VF_MEM))) {
2049                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2050                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
2051                 ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
2052         }
2053         if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
2054                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
2055                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
2056                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
2057                 ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
2058
2059                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2060                 reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
2061                 ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
2062         } else if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
2063                    ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
2064                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
2065                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
2066                 ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
2067                 reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
2068                 ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
2069         }
2070
2071         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
2072             (channel == MEM_FG_SYNC)) {
2073                 reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
2074                 ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
2075
2076                 _ipu_dp_dc_enable(ipu, channel);
2077         }
2078
2079         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
2080                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
2081                 _ipu_ic_enable_task(ipu, channel);
2082
2083         ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
2084
2085         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2086
2087         return 0;
2088 }
2089 EXPORT_SYMBOL(ipu_enable_channel);
2090
2091 /*!
2092  * This function check buffer ready for a logical channel.
2093  *
2094  * @param       ipu             ipu handler
2095  * @param       channel         Input parameter for the logical channel ID.
2096  *
2097  * @param       type            Input parameter which buffer to clear.
2098  *
2099  * @param       bufNum          Input parameter for which buffer number clear
2100  *                              ready state.
2101  *
2102  */
2103 int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
2104                 uint32_t bufNum)
2105 {
2106         uint32_t dma_chan = channel_2_dma(channel, type);
2107         uint32_t reg;
2108
2109         if (dma_chan == IDMA_CHAN_INVALID)
2110                 return -EINVAL;
2111
2112         if (bufNum == 0)
2113                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
2114         else if (bufNum == 1)
2115                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
2116         else
2117                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
2118
2119         if (reg & idma_mask(dma_chan))
2120                 return 1;
2121         else
2122                 return 0;
2123 }
2124 EXPORT_SYMBOL(ipu_check_buffer_ready);
2125
2126 /*!
2127  * This function clear buffer ready for a logical channel.
2128  *
2129  * @param       ipu             ipu handler
2130  * @param       channel         Input parameter for the logical channel ID.
2131  *
2132  * @param       type            Input parameter which buffer to clear.
2133  *
2134  * @param       bufNum          Input parameter for which buffer number clear
2135  *                              ready state.
2136  *
2137  */
2138 void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
2139                 uint32_t bufNum)
2140 {
2141         unsigned long lock_flags;
2142         uint32_t dma_ch = channel_2_dma(channel, type);
2143
2144         if (!idma_is_valid(dma_ch))
2145                 return;
2146
2147         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2148         ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
2149         if (bufNum == 0)
2150                 ipu_cm_write(ipu, idma_mask(dma_ch),
2151                                 IPU_CHA_BUF0_RDY(dma_ch));
2152         else if (bufNum == 1)
2153                 ipu_cm_write(ipu, idma_mask(dma_ch),
2154                                 IPU_CHA_BUF1_RDY(dma_ch));
2155         else
2156                 ipu_cm_write(ipu, idma_mask(dma_ch),
2157                                 IPU_CHA_BUF2_RDY(dma_ch));
2158         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
2159         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2160 }
2161 EXPORT_SYMBOL(ipu_clear_buffer_ready);
2162
2163 static irqreturn_t disable_chan_irq_handler(int irq, void *dev_id)
2164 {
2165         struct completion *comp = dev_id;
2166
2167         complete(comp);
2168         return IRQ_HANDLED;
2169 }
2170
2171 /*!
2172  * This function disables a logical channel.
2173  *
2174  * @param       ipu             ipu handler
2175  * @param       channel         Input parameter for the logical channel ID.
2176  *
2177  * @param       wait_for_stop   Flag to set whether to wait for channel end
2178  *                              of frame or return immediately.
2179  *
2180  * @return      This function returns 0 on success or negative error code on
2181  *              fail.
2182  */
2183 int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop)
2184 {
2185         uint32_t reg;
2186         unsigned long lock_flags;
2187         uint32_t in_dma;
2188         uint32_t out_dma;
2189         uint32_t sec_dma = NO_DMA;
2190         uint32_t thrd_dma = NO_DMA;
2191         uint16_t fg_pos_x, fg_pos_y;
2192
2193         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2194
2195         if ((ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
2196                 dev_err(ipu->dev, "Channel already disabled %d\n",
2197                         IPU_CHAN_ID(channel));
2198                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2199                 return -EACCES;
2200         }
2201
2202         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2203
2204         /* Get input and output dma channels */
2205         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
2206         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
2207
2208         if ((idma_is_valid(in_dma) &&
2209                 !idma_is_set(ipu, IDMAC_CHA_EN, in_dma))
2210                 && (idma_is_valid(out_dma) &&
2211                 !idma_is_set(ipu, IDMAC_CHA_EN, out_dma)))
2212                 return -EINVAL;
2213
2214         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)])
2215                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2216         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) {
2217                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
2218                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
2219         }
2220
2221         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
2222             (channel == MEM_DC_SYNC)) {
2223                 if (channel == MEM_FG_SYNC) {
2224                         ipu_disp_get_window_pos(ipu, channel, &fg_pos_x, &fg_pos_y);
2225                         ipu_disp_set_window_pos(ipu, channel, 0, 0);
2226                 }
2227
2228                 _ipu_dp_dc_disable(ipu, channel, false);
2229
2230                 /*
2231                  * wait for BG channel EOF then disable FG-IDMAC,
2232                  * it avoid FG NFB4EOF error.
2233                  */
2234                 if (channel == MEM_FG_SYNC) {
2235                         int timeout = 50;
2236
2237                         ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
2238                                         IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
2239                         while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
2240                                                 IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
2241                                 msleep(10);
2242                                 timeout -= 10;
2243                                 if (timeout <= 0) {
2244                                         dev_err(ipu->dev, "warning: wait for bg sync eof timeout\n");
2245                                         break;
2246                                 }
2247                         }
2248                 }
2249         } else if (wait_for_stop) {
2250                 while (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma) ||
2251                        idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma) ||
2252                         (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
2253                         idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma)) ||
2254                         (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
2255                         idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))) {
2256                         uint32_t ret, irq = 0xffffffff;
2257                         DECLARE_COMPLETION_ONSTACK(disable_comp);
2258
2259                         if (idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma))
2260                                 irq = out_dma;
2261                         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
2262                                 idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma))
2263                                 irq = sec_dma;
2264                         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
2265                                 idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))
2266                                 irq = thrd_dma;
2267                         if (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma))
2268                                 irq = in_dma;
2269
2270                         if (irq == 0xffffffff) {
2271                                 dev_err(ipu->dev, "warning: no channel busy, break\n");
2272                                 break;
2273                         }
2274
2275                         dev_err(ipu->dev, "warning: channel %d busy, need wait\n", irq);
2276
2277                         ret = ipu_request_irq(ipu, irq, disable_chan_irq_handler, 0, NULL, &disable_comp);
2278                         if (ret < 0) {
2279                                 dev_err(ipu->dev, "irq %d in use\n", irq);
2280                                 break;
2281                         } else {
2282                                 ret = wait_for_completion_timeout(&disable_comp, msecs_to_jiffies(200));
2283                                 ipu_free_irq(ipu, irq, &disable_comp);
2284                                 if (ret == 0) {
2285                                         ipu_dump_registers(ipu);
2286                                         dev_err(ipu->dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
2287                                         break;
2288                                 }
2289                         }
2290                 }
2291         }
2292
2293         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2294
2295         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
2296             (channel == MEM_DC_SYNC)) {
2297                 reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
2298                 ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
2299         }
2300
2301         /* Disable IC task */
2302         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
2303                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
2304                 _ipu_ic_disable_task(ipu, channel);
2305
2306         /* Disable DMA channel(s) */
2307         if (idma_is_valid(in_dma)) {
2308                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
2309                 ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
2310                 ipu_cm_write(ipu, idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
2311                 ipu_cm_write(ipu, tri_cur_buf_mask(in_dma),
2312                                         IPU_CHA_TRIPLE_CUR_BUF(in_dma));
2313         }
2314         if (idma_is_valid(out_dma)) {
2315                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
2316                 ipu_idmac_write(ipu, reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
2317                 ipu_cm_write(ipu, idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
2318                 ipu_cm_write(ipu, tri_cur_buf_mask(out_dma),
2319                                         IPU_CHA_TRIPLE_CUR_BUF(out_dma));
2320         }
2321         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2322                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
2323                 ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
2324                 ipu_cm_write(ipu, idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
2325         }
2326         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2327                 reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
2328                 ipu_idmac_write(ipu, reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
2329                 if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
2330                         reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
2331                         ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
2332                 } else {
2333                         reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
2334                         ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
2335                 }
2336                 ipu_cm_write(ipu, idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
2337         }
2338
2339         ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
2340
2341         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2342
2343         /* Set channel buffers NOT to be ready */
2344         if (idma_is_valid(in_dma)) {
2345                 ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 0);
2346                 ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 1);
2347                 ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 2);
2348         }
2349         if (idma_is_valid(out_dma)) {
2350                 ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 0);
2351                 ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 1);
2352         }
2353         if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2354                 ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 0);
2355                 ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 1);
2356         }
2357         if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2358                 ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 0);
2359                 ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 1);
2360         }
2361
2362         if (channel == MEM_FG_SYNC)
2363                 ipu_disp_set_window_pos(ipu, channel, fg_pos_x, fg_pos_y);
2364
2365         return 0;
2366 }
2367 EXPORT_SYMBOL(ipu_disable_channel);
2368
2369 /*!
2370  * This function enables CSI.
2371  *
2372  * @param       ipu             ipu handler
2373  * @param       csi     csi num 0 or 1
2374  *
2375  * @return      This function returns 0 on success or negative error code on
2376  *              fail.
2377  */
2378 int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
2379 {
2380         uint32_t reg;
2381         unsigned long lock_flags;
2382
2383         if (csi > 1) {
2384                 dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
2385                 return -EINVAL;
2386         }
2387
2388         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2389         ipu->csi_use_count[csi]++;
2390
2391         if (ipu->csi_use_count[csi] == 1) {
2392                 reg = ipu_cm_read(ipu, IPU_CONF);
2393                 if (csi == 0)
2394                         ipu_cm_write(ipu, reg | IPU_CONF_CSI0_EN, IPU_CONF);
2395                 else
2396                         ipu_cm_write(ipu, reg | IPU_CONF_CSI1_EN, IPU_CONF);
2397         }
2398         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2399         return 0;
2400 }
2401 EXPORT_SYMBOL(ipu_enable_csi);
2402
2403 /*!
2404  * This function disables CSI.
2405  *
2406  * @param       ipu             ipu handler
2407  * @param       csi     csi num 0 or 1
2408  *
2409  * @return      This function returns 0 on success or negative error code on
2410  *              fail.
2411  */
2412 int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
2413 {
2414         uint32_t reg;
2415         unsigned long lock_flags;
2416
2417         if (csi > 1) {
2418                 dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
2419                 return -EINVAL;
2420         }
2421
2422         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2423         ipu->csi_use_count[csi]--;
2424
2425         if (ipu->csi_use_count[csi] == 0) {
2426                 reg = ipu_cm_read(ipu, IPU_CONF);
2427                 if (csi == 0)
2428                         ipu_cm_write(ipu, reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
2429                 else
2430                         ipu_cm_write(ipu, reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
2431         }
2432         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2433         return 0;
2434 }
2435 EXPORT_SYMBOL(ipu_disable_csi);
2436
2437 static irqreturn_t ipu_irq_handler(int irq, void *desc)
2438 {
2439         struct ipu_soc *ipu = desc;
2440         int i;
2441         uint32_t line;
2442         irqreturn_t result = IRQ_NONE;
2443         uint32_t int_stat;
2444         const int err_reg[] = { 5, 6, 9, 10, 0 };
2445         const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
2446
2447         for (i = 0;; i++) {
2448                 if (err_reg[i] == 0)
2449                         break;
2450                 int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
2451                 int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
2452                 if (int_stat) {
2453                         ipu_cm_write(ipu, int_stat, IPU_INT_STAT(err_reg[i]));
2454                         dev_err(ipu->dev,
2455                                 "IPU Error - IPU_INT_STAT_%d = 0x%08X\n",
2456                                 err_reg[i], int_stat);
2457                         /* Disable interrupts so we only get error once */
2458                         int_stat =
2459                             ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) & ~int_stat;
2460                         ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
2461                 }
2462         }
2463
2464         for (i = 0;; i++) {
2465                 if (int_reg[i] == 0)
2466                         break;
2467                 int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
2468                 int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
2469                 ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
2470                 while ((line = ffs(int_stat)) != 0) {
2471                         line--;
2472                         int_stat &= ~(1UL << line);
2473                         line += (int_reg[i] - 1) * 32;
2474                         result |=
2475                             ipu->irq_list[line].handler(line,
2476                                                        ipu->irq_list[line].
2477                                                        dev_id);
2478                 }
2479         }
2480
2481         return result;
2482 }
2483
2484 /*!
2485  * This function enables the interrupt for the specified interrupt line.
2486  * The interrupt lines are defined in \b ipu_irq_line enum.
2487  *
2488  * @param       ipu             ipu handler
2489  * @param       irq             Interrupt line to enable interrupt for.
2490  *
2491  */
2492 void ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq)
2493 {
2494         uint32_t reg;
2495         unsigned long lock_flags;
2496
2497         if (!ipu->clk_enabled)
2498                 clk_enable(ipu->ipu_clk);
2499
2500         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2501
2502         reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
2503         reg |= IPUIRQ_2_MASK(irq);
2504         ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
2505
2506         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2507         if (!ipu->clk_enabled)
2508                 clk_disable(ipu->ipu_clk);
2509 }
2510 EXPORT_SYMBOL(ipu_enable_irq);
2511
2512 /*!
2513  * This function disables the interrupt for the specified interrupt line.
2514  * The interrupt lines are defined in \b ipu_irq_line enum.
2515  *
2516  * @param       ipu             ipu handler
2517  * @param       irq             Interrupt line to disable interrupt for.
2518  *
2519  */
2520 void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq)
2521 {
2522         uint32_t reg;
2523         unsigned long lock_flags;
2524
2525         if (!ipu->clk_enabled)
2526                 clk_enable(ipu->ipu_clk);
2527
2528         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2529
2530         reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
2531         reg &= ~IPUIRQ_2_MASK(irq);
2532         ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
2533
2534         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2535         if (!ipu->clk_enabled)
2536                 clk_disable(ipu->ipu_clk);
2537 }
2538 EXPORT_SYMBOL(ipu_disable_irq);
2539
2540 /*!
2541  * This function clears the interrupt for the specified interrupt line.
2542  * The interrupt lines are defined in \b ipu_irq_line enum.
2543  *
2544  * @param       ipu             ipu handler
2545  * @param       irq             Interrupt line to clear interrupt for.
2546  *
2547  */
2548 void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq)
2549 {
2550         if (!ipu->clk_enabled)
2551                 clk_enable(ipu->ipu_clk);
2552
2553         ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
2554
2555         if (!ipu->clk_enabled)
2556                 clk_disable(ipu->ipu_clk);
2557 }
2558 EXPORT_SYMBOL(ipu_clear_irq);
2559
2560 /*!
2561  * This function returns the current interrupt status for the specified
2562  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2563  *
2564  * @param       ipu             ipu handler
2565  * @param       irq             Interrupt line to get status for.
2566  *
2567  * @return      Returns true if the interrupt is pending/asserted or false if
2568  *              the interrupt is not pending.
2569  */
2570 bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq)
2571 {
2572         uint32_t reg;
2573
2574         if (!ipu->clk_enabled)
2575                 clk_enable(ipu->ipu_clk);
2576
2577         reg = ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq));
2578
2579         if (!ipu->clk_enabled)
2580                 clk_disable(ipu->ipu_clk);
2581
2582         if (reg & IPUIRQ_2_MASK(irq))
2583                 return true;
2584         else
2585                 return false;
2586 }
2587 EXPORT_SYMBOL(ipu_get_irq_status);
2588
2589 /*!
2590  * This function registers an interrupt handler function for the specified
2591  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2592  *
2593  * @param       ipu             ipu handler
2594  * @param       irq             Interrupt line to get status for.
2595  *
2596  * @param       handler         Input parameter for address of the handler
2597  *                              function.
2598  *
2599  * @param       irq_flags       Flags for interrupt mode. Currently not used.
2600  *
2601  * @param       devname         Input parameter for string name of driver
2602  *                              registering the handler.
2603  *
2604  * @param       dev_id          Input parameter for pointer of data to be
2605  *                              passed to the handler.
2606  *
2607  * @return      This function returns 0 on success or negative error code on
2608  *              fail.
2609  */
2610 int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
2611                     irqreturn_t(*handler) (int, void *),
2612                     uint32_t irq_flags, const char *devname, void *dev_id)
2613 {
2614         unsigned long lock_flags;
2615
2616         BUG_ON(irq >= IPU_IRQ_COUNT);
2617
2618         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2619
2620         if (ipu->irq_list[irq].handler != NULL) {
2621                 dev_err(ipu->dev,
2622                         "handler already installed on irq %d\n", irq);
2623                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2624                 return -EINVAL;
2625         }
2626
2627         ipu->irq_list[irq].handler = handler;
2628         ipu->irq_list[irq].flags = irq_flags;
2629         ipu->irq_list[irq].dev_id = dev_id;
2630         ipu->irq_list[irq].name = devname;
2631
2632         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2633
2634         ipu_enable_irq(ipu, irq);       /* enable the interrupt */
2635
2636         return 0;
2637 }
2638 EXPORT_SYMBOL(ipu_request_irq);
2639
2640 /*!
2641  * This function unregisters an interrupt handler for the specified interrupt
2642  * line. The interrupt lines are defined in \b ipu_irq_line enum.
2643  *
2644  * @param       ipu             ipu handler
2645  * @param       irq             Interrupt line to get status for.
2646  *
2647  * @param       dev_id          Input parameter for pointer of data to be passed
2648  *                              to the handler. This must match value passed to
2649  *                              ipu_request_irq().
2650  *
2651  */
2652 void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id)
2653 {
2654         ipu_disable_irq(ipu, irq);      /* disable the interrupt */
2655
2656         if (ipu->irq_list[irq].dev_id == dev_id)
2657                 ipu->irq_list[irq].handler = NULL;
2658 }
2659 EXPORT_SYMBOL(ipu_free_irq);
2660
2661 uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type)
2662 {
2663         uint32_t reg, dma_chan;
2664
2665         dma_chan = channel_2_dma(channel, type);
2666         if (!idma_is_valid(dma_chan))
2667                 return -EINVAL;
2668
2669         reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
2670         if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
2671                 reg = ipu_cm_read(ipu, IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
2672                 return (reg & tri_cur_buf_mask(dma_chan)) >>
2673                                 tri_cur_buf_shift(dma_chan);
2674         } else {
2675                 reg = ipu_cm_read(ipu, IPU_CHA_CUR_BUF(dma_chan));
2676                 if (reg & idma_mask(dma_chan))
2677                         return 1;
2678                 else
2679                         return 0;
2680         }
2681 }
2682 EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
2683
2684 uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
2685 {
2686         uint32_t stat = 0;
2687         uint32_t task_stat_reg = ipu_cm_read(ipu, IPU_PROC_TASK_STAT);
2688
2689         switch (channel) {
2690         case MEM_PRP_VF_MEM:
2691                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2692                 break;
2693         case MEM_VDI_PRP_VF_MEM:
2694                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2695                 break;
2696         case MEM_ROT_VF_MEM:
2697                 stat =
2698                     (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
2699                 break;
2700         case MEM_PRP_ENC_MEM:
2701                 stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
2702                 break;
2703         case MEM_ROT_ENC_MEM:
2704                 stat =
2705                     (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
2706                     TSTAT_ENC_ROT_OFFSET;
2707                 break;
2708         case MEM_PP_MEM:
2709                 stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
2710                 break;
2711         case MEM_ROT_PP_MEM:
2712                 stat =
2713                     (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
2714                 break;
2715
2716         default:
2717                 stat = TASK_STAT_IDLE;
2718                 break;
2719         }
2720         return stat;
2721 }
2722
2723 int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch)
2724 {
2725         uint32_t reg;
2726         unsigned long lock_flags;
2727
2728         int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
2729         int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
2730
2731         /* enable target channel */
2732         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2733
2734         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(to_dma));
2735         ipu_idmac_write(ipu, reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
2736
2737         ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
2738
2739         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2740
2741         /* switch dp dc */
2742         _ipu_dp_dc_disable(ipu, from_ch, true);
2743
2744         /* disable source channel */
2745         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
2746
2747         reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(from_dma));
2748         ipu_idmac_write(ipu, reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
2749         ipu_cm_write(ipu, idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
2750         ipu_cm_write(ipu, tri_cur_buf_mask(from_dma),
2751                                 IPU_CHA_TRIPLE_CUR_BUF(from_dma));
2752
2753         ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
2754
2755         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
2756
2757         ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 0);
2758         ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 1);
2759         ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 2);
2760
2761         return 0;
2762 }
2763 EXPORT_SYMBOL(ipu_swap_channel);
2764
2765 uint32_t bytes_per_pixel(uint32_t fmt)
2766 {
2767         switch (fmt) {
2768         case IPU_PIX_FMT_GENERIC:       /*generic data */
2769         case IPU_PIX_FMT_RGB332:
2770         case IPU_PIX_FMT_YUV420P:
2771         case IPU_PIX_FMT_YVU420P:
2772         case IPU_PIX_FMT_YUV422P:
2773                 return 1;
2774                 break;
2775         case IPU_PIX_FMT_RGB565:
2776         case IPU_PIX_FMT_YUYV:
2777         case IPU_PIX_FMT_UYVY:
2778                 return 2;
2779                 break;
2780         case IPU_PIX_FMT_BGR24:
2781         case IPU_PIX_FMT_RGB24:
2782                 return 3;
2783                 break;
2784         case IPU_PIX_FMT_GENERIC_32:    /*generic data */
2785         case IPU_PIX_FMT_BGR32:
2786         case IPU_PIX_FMT_BGRA32:
2787         case IPU_PIX_FMT_RGB32:
2788         case IPU_PIX_FMT_RGBA32:
2789         case IPU_PIX_FMT_ABGR32:
2790                 return 4;
2791                 break;
2792         default:
2793                 return 1;
2794                 break;
2795         }
2796         return 0;
2797 }
2798 EXPORT_SYMBOL(bytes_per_pixel);
2799
2800 ipu_color_space_t format_to_colorspace(uint32_t fmt)
2801 {
2802         switch (fmt) {
2803         case IPU_PIX_FMT_RGB666:
2804         case IPU_PIX_FMT_RGB565:
2805         case IPU_PIX_FMT_BGR24:
2806         case IPU_PIX_FMT_RGB24:
2807         case IPU_PIX_FMT_GBR24:
2808         case IPU_PIX_FMT_BGR32:
2809         case IPU_PIX_FMT_BGRA32:
2810         case IPU_PIX_FMT_RGB32:
2811         case IPU_PIX_FMT_RGBA32:
2812         case IPU_PIX_FMT_ABGR32:
2813         case IPU_PIX_FMT_LVDS666:
2814         case IPU_PIX_FMT_LVDS888:
2815                 return RGB;
2816                 break;
2817
2818         default:
2819                 return YCbCr;
2820                 break;
2821         }
2822         return RGB;
2823 }
2824
2825 bool ipu_pixel_format_has_alpha(uint32_t fmt)
2826 {
2827         switch (fmt) {
2828         case IPU_PIX_FMT_RGBA32:
2829         case IPU_PIX_FMT_BGRA32:
2830         case IPU_PIX_FMT_ABGR32:
2831                 return true;
2832                 break;
2833         default:
2834                 return false;
2835                 break;
2836         }
2837         return false;
2838 }
2839
2840 void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
2841 {
2842         _ipu_dp_set_csc_coefficients(ipu, channel, param);
2843 }
2844 EXPORT_SYMBOL(ipu_set_csc_coefficients);
2845
2846 static int ipu_suspend(struct platform_device *pdev, pm_message_t state)
2847 {
2848         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
2849
2850 #if 0
2851         if (g_ipu_clk_enabled) {
2852                 /* save and disable enabled channels*/
2853                 idma_enable_reg[0] = __raw_readl(IDMAC_CHA_EN(0));
2854                 idma_enable_reg[1] = __raw_readl(IDMAC_CHA_EN(32));
2855                 while ((__raw_readl(IDMAC_CHA_BUSY(0)) & idma_enable_reg[0])
2856                         || (__raw_readl(IDMAC_CHA_BUSY(32)) &
2857                                 idma_enable_reg[1])) {
2858                         /* disable channel not busy already */
2859                         uint32_t chan_should_disable, timeout = 1000, time = 0;
2860
2861                         chan_should_disable =
2862                                 __raw_readl(IDMAC_CHA_BUSY(0))
2863                                         ^ idma_enable_reg[0];
2864                         __raw_writel((~chan_should_disable) &
2865                                         idma_enable_reg[0], IDMAC_CHA_EN(0));
2866                         chan_should_disable =
2867                                 __raw_readl(IDMAC_CHA_BUSY(1))
2868                                         ^ idma_enable_reg[1];
2869                         __raw_writel((~chan_should_disable) &
2870                                         idma_enable_reg[1], IDMAC_CHA_EN(32));
2871                         msleep(2);
2872                         time += 2;
2873                         if (time >= timeout)
2874                                 return -1;
2875                 }
2876                 __raw_writel(0, IDMAC_CHA_EN(0));
2877                 __raw_writel(0, IDMAC_CHA_EN(32));
2878
2879                 /* save double buffer select regs */
2880                 ipu_cha_db_mode_reg[0] = __raw_readl(IPU_CHA_DB_MODE_SEL(0));
2881                 ipu_cha_db_mode_reg[1] = __raw_readl(IPU_CHA_DB_MODE_SEL(32));
2882                 ipu_cha_db_mode_reg[2] =
2883                         __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(0));
2884                 ipu_cha_db_mode_reg[3] =
2885                         __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(32));
2886
2887                 /* save triple buffer select regs */
2888                 ipu_cha_trb_mode_reg[0] = __raw_readl(IPU_CHA_TRB_MODE_SEL(0));
2889                 ipu_cha_trb_mode_reg[1] = __raw_readl(IPU_CHA_TRB_MODE_SEL(32));
2890
2891                 /* save current buffer regs */
2892                 ipu_cha_cur_buf_reg[0] = __raw_readl(IPU_CHA_CUR_BUF(0));
2893                 ipu_cha_cur_buf_reg[1] = __raw_readl(IPU_CHA_CUR_BUF(32));
2894                 ipu_cha_cur_buf_reg[2] = __raw_readl(IPU_ALT_CUR_BUF0);
2895                 ipu_cha_cur_buf_reg[3] = __raw_readl(IPU_ALT_CUR_BUF1);
2896
2897                 /* save current triple buffer regs */
2898                 ipu_cha_triple_cur_buf_reg[0] =
2899                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(0));
2900                 ipu_cha_triple_cur_buf_reg[1] =
2901                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(32));
2902                 ipu_cha_triple_cur_buf_reg[2] =
2903                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(64));
2904                 ipu_cha_triple_cur_buf_reg[3] =
2905                                         __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(96));
2906
2907                 /* save idamc sub addr regs */
2908                 idma_sub_addr_reg[0] = __raw_readl(IDMAC_SUB_ADDR_0);
2909                 idma_sub_addr_reg[1] = __raw_readl(IDMAC_SUB_ADDR_1);
2910                 idma_sub_addr_reg[2] = __raw_readl(IDMAC_SUB_ADDR_2);
2911                 idma_sub_addr_reg[3] = __raw_readl(IDMAC_SUB_ADDR_3);
2912                 idma_sub_addr_reg[4] = __raw_readl(IDMAC_SUB_ADDR_4);
2913
2914                 /* save sub-modules status and disable all */
2915                 ic_conf_reg = __raw_readl(IC_CONF);
2916                 __raw_writel(0, IC_CONF);
2917                 ipu_conf_reg = __raw_readl(IPU_CONF);
2918                 __raw_writel(0, IPU_CONF);
2919
2920                 /* save buf ready regs */
2921                 buf_ready_reg[0] = __raw_readl(IPU_CHA_BUF0_RDY(0));
2922                 buf_ready_reg[1] = __raw_readl(IPU_CHA_BUF0_RDY(32));
2923                 buf_ready_reg[2] = __raw_readl(IPU_CHA_BUF1_RDY(0));
2924                 buf_ready_reg[3] = __raw_readl(IPU_CHA_BUF1_RDY(32));
2925                 buf_ready_reg[4] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(0));
2926                 buf_ready_reg[5] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(32));
2927                 buf_ready_reg[6] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(0));
2928                 buf_ready_reg[7] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(32));
2929                 buf_ready_reg[8] = __raw_readl(IPU_CHA_BUF2_RDY(0));
2930                 buf_ready_reg[9] = __raw_readl(IPU_CHA_BUF2_RDY(32));
2931         }
2932 #endif
2933
2934         if (plat_data->pg)
2935                 plat_data->pg(1);
2936
2937         return 0;
2938 }
2939
2940 static int ipu_resume(struct platform_device *pdev)
2941 {
2942         struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
2943
2944         if (plat_data->pg)
2945                 plat_data->pg(0);
2946
2947 #if 0
2948         if (g_ipu_clk_enabled) {
2949
2950                 /* restore buf ready regs */
2951                 __raw_writel(buf_ready_reg[0], IPU_CHA_BUF0_RDY(0));
2952                 __raw_writel(buf_ready_reg[1], IPU_CHA_BUF0_RDY(32));
2953                 __raw_writel(buf_ready_reg[2], IPU_CHA_BUF1_RDY(0));
2954                 __raw_writel(buf_ready_reg[3], IPU_CHA_BUF1_RDY(32));
2955                 __raw_writel(buf_ready_reg[4], IPU_ALT_CHA_BUF0_RDY(0));
2956                 __raw_writel(buf_ready_reg[5], IPU_ALT_CHA_BUF0_RDY(32));
2957                 __raw_writel(buf_ready_reg[6], IPU_ALT_CHA_BUF1_RDY(0));
2958                 __raw_writel(buf_ready_reg[7], IPU_ALT_CHA_BUF1_RDY(32));
2959                 __raw_writel(buf_ready_reg[8], IPU_CHA_BUF2_RDY(0));
2960                 __raw_writel(buf_ready_reg[9], IPU_CHA_BUF2_RDY(32));
2961
2962                 /* re-enable sub-modules*/
2963                 __raw_writel(ipu_conf_reg, IPU_CONF);
2964                 __raw_writel(ic_conf_reg, IC_CONF);
2965
2966                 /* restore double buffer select regs */
2967                 __raw_writel(ipu_cha_db_mode_reg[0], IPU_CHA_DB_MODE_SEL(0));
2968                 __raw_writel(ipu_cha_db_mode_reg[1], IPU_CHA_DB_MODE_SEL(32));
2969                 __raw_writel(ipu_cha_db_mode_reg[2],
2970                                 IPU_ALT_CHA_DB_MODE_SEL(0));
2971                 __raw_writel(ipu_cha_db_mode_reg[3],
2972                                 IPU_ALT_CHA_DB_MODE_SEL(32));
2973
2974                 /* restore triple buffer select regs */
2975                 __raw_writel(ipu_cha_trb_mode_reg[0], IPU_CHA_TRB_MODE_SEL(0));
2976                 __raw_writel(ipu_cha_trb_mode_reg[1], IPU_CHA_TRB_MODE_SEL(32));
2977
2978                 /* restore current buffer select regs */
2979                 __raw_writel(~(ipu_cha_cur_buf_reg[0]), IPU_CHA_CUR_BUF(0));
2980                 __raw_writel(~(ipu_cha_cur_buf_reg[1]), IPU_CHA_CUR_BUF(32));
2981                 __raw_writel(~(ipu_cha_cur_buf_reg[2]), IPU_ALT_CUR_BUF0);
2982                 __raw_writel(~(ipu_cha_cur_buf_reg[3]), IPU_ALT_CUR_BUF1);
2983
2984                 /* restore triple current buffer select regs */
2985                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[0]),
2986                                                 IPU_CHA_TRIPLE_CUR_BUF(0));
2987                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[1]),
2988                                                 IPU_CHA_TRIPLE_CUR_BUF(32));
2989                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[2]),
2990                                                 IPU_CHA_TRIPLE_CUR_BUF(64));
2991                 __raw_writel(~(ipu_cha_triple_cur_buf_reg[3]),
2992                                                 IPU_CHA_TRIPLE_CUR_BUF(96));
2993
2994                 /* restore idamc sub addr regs */
2995                 __raw_writel(idma_sub_addr_reg[0], IDMAC_SUB_ADDR_0);
2996                 __raw_writel(idma_sub_addr_reg[1], IDMAC_SUB_ADDR_1);
2997                 __raw_writel(idma_sub_addr_reg[2], IDMAC_SUB_ADDR_2);
2998                 __raw_writel(idma_sub_addr_reg[3], IDMAC_SUB_ADDR_3);
2999                 __raw_writel(idma_sub_addr_reg[4], IDMAC_SUB_ADDR_4);
3000
3001                 /* restart idma channel*/
3002                 __raw_writel(idma_enable_reg[0], IDMAC_CHA_EN(0));
3003                 __raw_writel(idma_enable_reg[1], IDMAC_CHA_EN(32));
3004         } else {
3005                 clk_enable(g_ipu_clk);
3006                 _ipu_dmfc_init(dmfc_type_setup, 1);
3007                 _ipu_init_dc_mappings();
3008
3009                 /* Set sync refresh channels as high priority */
3010                 __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
3011                 clk_disable(g_ipu_clk);
3012         }
3013 #endif
3014
3015         return 0;
3016 }
3017
3018 /*!
3019  * This structure contains pointers to the power management callback functions.
3020  */
3021 static struct platform_driver mxcipu_driver = {
3022         .driver = {
3023                    .name = "imx-ipuv3",
3024                    },
3025         .probe = ipu_probe,
3026         .remove = ipu_remove,
3027         .suspend = ipu_suspend,
3028         .resume = ipu_resume,
3029 };
3030
3031 int32_t __init ipu_gen_init(void)
3032 {
3033         int32_t ret;
3034
3035         ret = platform_driver_register(&mxcipu_driver);
3036         return 0;
3037 }
3038
3039 subsys_initcall(ipu_gen_init);
3040
3041 static void __exit ipu_gen_uninit(void)
3042 {
3043         platform_driver_unregister(&mxcipu_driver);
3044 }
3045
3046 module_exit(ipu_gen_uninit);