drivers/mxc/ipu3/ipu_disp.c

   1 /*
   2  * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /*!
  15  * @file ipu_disp.c
  16  *
  17  * @brief IPU display submodule API functions
  18  *
  19  * @ingroup IPU
  20  */
  21
  22 #include <linux/types.h>
  23 #include <linux/errno.h>
  24 #include <linux/delay.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/io.h>
  27 #include <linux/ipu.h>
  28 #include <linux/clk.h>
  29 #include <asm/atomic.h>
  30 #include <mach/clock.h>
  31 #include "ipu_prv.h"
  32 #include "ipu_regs.h"
  33 #include "ipu_param_mem.h"
  34
  35 struct dp_csc_param_t {
  36         int mode;
  37         void *coeff;
  38 };
  39
  40 #define SYNC_WAVE 0
  41 #define ASYNC_SER_WAVE 6
  42
  43 /* DC display ID assignments */
  44 #define DC_DISP_ID_SYNC(di)     (di)
  45 #define DC_DISP_ID_SERIAL       2
  46 #define DC_DISP_ID_ASYNC        3
  47
  48 int dmfc_type_setup;
  49
  50 void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first)
  51 {
  52         u32 dmfc_wr_chan, dmfc_dp_chan;
  53
  54         if (first) {
  55                 if (dmfc_type_setup > dmfc_type)
  56                         dmfc_type = dmfc_type_setup;
  57                 else
  58                         dmfc_type_setup = dmfc_type;
  59
  60                 /* disable DMFC-IC channel*/
  61                 ipu_dmfc_write(ipu, 0x2, DMFC_IC_CTRL);
  62         } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
  63                 dev_dbg(ipu->dev, "DMFC high resolution has set, will not change\n");
  64                 return;
  65         } else
  66                 dmfc_type_setup = dmfc_type;
  67
  68         if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
  69                 /* 1 - segment 0~3;
  70                  * 5B - segement 4, 5;
  71                  * 5F - segement 6, 7;
  72                  * 1C, 2C and 6B, 6F unused;
  73                  */
  74                 dev_info(ipu->dev, "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
  75                 dmfc_wr_chan = 0x00000088;
  76                 dmfc_dp_chan = 0x00009694;
  77                 ipu->dmfc_size_28 = 256*4;
  78                 ipu->dmfc_size_29 = 0;
  79                 ipu->dmfc_size_24 = 0;
  80                 ipu->dmfc_size_27 = 128*4;
  81                 ipu->dmfc_size_23 = 128*4;
  82         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
  83                 /* 1 - segment 0, 1;
  84                  * 5B - segement 2~5;
  85                  * 5F - segement 6,7;
  86                  * 1C, 2C and 6B, 6F unused;
  87                  */
  88                 dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
  89                 dmfc_wr_chan = 0x00000090;
  90                 dmfc_dp_chan = 0x0000968a;
  91                 ipu->dmfc_size_28 = 128*4;
  92                 ipu->dmfc_size_29 = 0;
  93                 ipu->dmfc_size_24 = 0;
  94                 ipu->dmfc_size_27 = 128*4;
  95                 ipu->dmfc_size_23 = 256*4;
  96         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
  97                 /* 5B - segement 0~3;
  98                  * 5F - segement 4~7;
  99                  * 1, 1C, 2C and 6B, 6F unused;
 100                  */
 101                 dev_info(ipu->dev, "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
 102                 dmfc_wr_chan = 0x00000000;
 103                 dmfc_dp_chan = 0x00008c88;
 104                 ipu->dmfc_size_28 = 0;
 105                 ipu->dmfc_size_29 = 0;
 106                 ipu->dmfc_size_24 = 0;
 107                 ipu->dmfc_size_27 = 256*4;
 108                 ipu->dmfc_size_23 = 256*4;
 109         } else {
 110                 /* 1 - segment 0, 1;
 111                  * 5B - segement 4, 5;
 112                  * 5F - segement 6, 7;
 113                  * 1C, 2C and 6B, 6F unused;
 114                  */
 115                 dev_info(ipu->dev, "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
 116                 dmfc_wr_chan = 0x00000090;
 117                 dmfc_dp_chan = 0x00009694;
 118                 ipu->dmfc_size_28 = 128*4;
 119                 ipu->dmfc_size_29 = 0;
 120                 ipu->dmfc_size_24 = 0;
 121                 ipu->dmfc_size_27 = 128*4;
 122                 ipu->dmfc_size_23 = 128*4;
 123         }
 124         ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
 125         ipu_dmfc_write(ipu, 0x202020F6, DMFC_WR_CHAN_DEF);
 126         ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
 127         /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
 128         ipu_dmfc_write(ipu, 0x2020F6F6, DMFC_DP_CHAN_DEF);
 129 }
 130
 131 static int __init dmfc_setup(char *options)
 132 {
 133         get_option(&options, &dmfc_type_setup);
 134         if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
 135                 dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
 136         return 1;
 137 }
 138 __setup("dmfc=", dmfc_setup);
 139
 140 void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width)
 141 {
 142         u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
 143
 144         if (width >= HIGH_RESOLUTION_WIDTH) {
 145                 if (dma_chan == 23)
 146                         _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
 147                 else if (dma_chan == 28)
 148                         _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DC, 0);
 149         }
 150
 151         if (dma_chan == 23) { /*5B*/
 152                 if (ipu->dmfc_size_23/width > 3)
 153                         dmfc_gen1 |= 1UL << 20;
 154                 else
 155                         dmfc_gen1 &= ~(1UL << 20);
 156         } else if (dma_chan == 24) { /*6B*/
 157                 if (ipu->dmfc_size_24/width > 1)
 158                         dmfc_gen1 |= 1UL << 22;
 159                 else
 160                         dmfc_gen1 &= ~(1UL << 22);
 161         } else if (dma_chan == 27) { /*5F*/
 162                 if (ipu->dmfc_size_27/width > 2)
 163                         dmfc_gen1 |= 1UL << 21;
 164                 else
 165                         dmfc_gen1 &= ~(1UL << 21);
 166         } else if (dma_chan == 28) { /*1*/
 167                 if (ipu->dmfc_size_28/width > 2)
 168                         dmfc_gen1 |= 1UL << 16;
 169                 else
 170                         dmfc_gen1 &= ~(1UL << 16);
 171         } else if (dma_chan == 29) { /*6F*/
 172                 if (ipu->dmfc_size_29/width > 1)
 173                         dmfc_gen1 |= 1UL << 23;
 174                 else
 175                         dmfc_gen1 &= ~(1UL << 23);
 176         }
 177
 178         ipu_dmfc_write(ipu, dmfc_gen1, DMFC_GENERAL1);
 179 }
 180
 181 void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size)
 182 {
 183         u32 dmfc_wr_chan = ipu_dmfc_read(ipu, DMFC_WR_CHAN);
 184         u32 dmfc_dp_chan = ipu_dmfc_read(ipu, DMFC_DP_CHAN);
 185         int dmfc_bs = 0;
 186
 187         switch (burst_size) {
 188         case 64:
 189                 dmfc_bs = 0x40;
 190                 break;
 191         case 32:
 192         case 20:
 193                 dmfc_bs = 0x80;
 194                 break;
 195         case 16:
 196                 dmfc_bs = 0xc0;
 197                 break;
 198         default:
 199                 dev_err(ipu->dev, "Unsupported burst size %d\n",
 200                         burst_size);
 201                 return;
 202         }
 203
 204         if (dma_chan == 23) { /*5B*/
 205                 dmfc_dp_chan &= ~(0xc0);
 206                 dmfc_dp_chan |= dmfc_bs;
 207         } else if (dma_chan == 27) { /*5F*/
 208                 dmfc_dp_chan &= ~(0xc000);
 209                 dmfc_dp_chan |= (dmfc_bs << 8);
 210         } else if (dma_chan == 28) { /*1*/
 211                 dmfc_wr_chan &= ~(0xc0);
 212                 dmfc_wr_chan |= dmfc_bs;
 213         }
 214
 215         ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
 216         ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
 217 }
 218
 219 static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
 220                                 int di, int wave_gen,
 221                                 int access_size, int component_size)
 222 {
 223         u32 reg;
 224         reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
 225             (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
 226         ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
 227 }
 228
 229 static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
 230                         int di, int wave_gen, int di_pin, int set,
 231                         int up, int down)
 232 {
 233         u32 reg;
 234
 235         reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
 236         reg &= ~(0x3 << (di_pin * 2));
 237         reg |= set << (di_pin * 2);
 238         ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
 239
 240         ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
 241 }
 242
 243 static void _ipu_di_sync_config(struct ipu_soc *ipu,
 244                                 int di, int wave_gen,
 245                                 int run_count, int run_src,
 246                                 int offset_count, int offset_src,
 247                                 int repeat_count, int cnt_clr_src,
 248                                 int cnt_polarity_gen_en,
 249                                 int cnt_polarity_clr_src,
 250                                 int cnt_polarity_trigger_src,
 251                                 int cnt_up, int cnt_down)
 252 {
 253         u32 reg;
 254
 255         if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
 256                 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
 257                 dev_err(ipu->dev, "DI%d counters out of range.\n", di);
 258                 return;
 259         }
 260
 261         reg = (run_count << 19) | (++run_src << 16) |
 262             (offset_count << 3) | ++offset_src;
 263         ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
 264         reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
 265             (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
 266         reg |= (cnt_down << 16) | cnt_up;
 267         if (repeat_count == 0) {
 268                 /* Enable auto reload */
 269                 reg |= 0x10000000;
 270         }
 271         ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
 272         reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
 273         reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
 274         reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
 275         ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
 276 }
 277
 278 static void _ipu_dc_map_link(struct ipu_soc *ipu,
 279                 int current_map,
 280                 int base_map_0, int buf_num_0,
 281                 int base_map_1, int buf_num_1,
 282                 int base_map_2, int buf_num_2)
 283 {
 284         int ptr_0 = base_map_0 * 3 + buf_num_0;
 285         int ptr_1 = base_map_1 * 3 + buf_num_1;
 286         int ptr_2 = base_map_2 * 3 + buf_num_2;
 287         int ptr;
 288         u32 reg;
 289         ptr = (ptr_2 << 10) +  (ptr_1 << 5) + ptr_0;
 290
 291         reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(current_map));
 292         reg &= ~(0x1F << ((16 * (current_map & 0x1))));
 293         reg |= ptr << ((16 * (current_map & 0x1)));
 294         ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(current_map));
 295 }
 296
 297 static void _ipu_dc_map_config(struct ipu_soc *ipu,
 298                 int map, int byte_num, int offset, int mask)
 299 {
 300         int ptr = map * 3 + byte_num;
 301         u32 reg;
 302
 303         reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
 304         reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
 305         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 306         ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
 307
 308         reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
 309         reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
 310         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 311         ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
 312 }
 313
 314 static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
 315 {
 316         u32 reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
 317         ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
 318                      DC_MAP_CONF_PTR(map));
 319 }
 320
 321 static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
 322                         int word, u32 opcode, u32 operand, int map,
 323                         int wave, int glue, int sync, int stop)
 324 {
 325         u32 reg;
 326
 327         if (opcode == WRG) {
 328                 reg = sync;
 329                 reg |= (glue << 4);
 330                 reg |= (++wave << 11);
 331                 reg |= ((operand & 0x1FFFF) << 15);
 332                 ipu_dc_tmpl_write(ipu, reg, word * 2);
 333
 334                 reg = (operand >> 17);
 335                 reg |= opcode << 7;
 336                 reg |= (stop << 9);
 337                 ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
 338         } else {
 339                 reg = sync;
 340                 reg |= (glue << 4);
 341                 reg |= (++wave << 11);
 342                 reg |= (++map << 15);
 343                 reg |= (operand << 20) & 0xFFF00000;
 344                 ipu_dc_tmpl_write(ipu, reg, word * 2);
 345
 346                 reg = (operand >> 12);
 347                 reg |= opcode << 4;
 348                 reg |= (stop << 9);
 349                 ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
 350         }
 351 }
 352
 353 static void _ipu_dc_link_event(struct ipu_soc *ipu,
 354                 int chan, int event, int addr, int priority)
 355 {
 356         u32 reg;
 357         u32 address_shift;
 358         if (event < DC_EVEN_UGDE0) {
 359                 reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
 360                 reg &= ~(0xFFFF << (16 * (event & 0x1)));
 361                 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 362                 ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
 363         } else {
 364                 reg = ipu_dc_read(ipu, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
 365                 if ((event - DC_EVEN_UGDE0) & 0x1) {
 366                         reg &= ~(0x2FF << 16);
 367                         reg |= (addr << 16);
 368                         reg |= priority ? (2 << 24) : 0x0;
 369                 } else {
 370                         reg &= ~0xFC00FFFF;
 371                         if (priority)
 372                                 chan = (chan >> 1) +
 373                                         ((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
 374                         else
 375                                 chan = 0x7;
 376                         address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
 377                         reg |= (addr << address_shift) | (priority << 3) | chan;
 378                 }
 379                 ipu_dc_write(ipu, reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
 380         }
 381 }
 382
 383 /*     Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
 384        U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
 385        V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;*/
 386 static const int rgb2ycbcr_coeff[5][3] = {
 387         {0x4D, 0x96, 0x1D},
 388         {-0x2B, -0x55, 0x80},
 389         {0x80, -0x6B, -0x15},
 390         {0x0000, 0x0200, 0x0200},       /* B0, B1, B2 */
 391         {0x2, 0x2, 0x2},        /* S0, S1, S2 */
 392 };
 393
 394 /*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
 395        G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
 396        B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
 397 static const int ycbcr2rgb_coeff[5][3] = {
 398         {0x095, 0x000, 0x0CC},
 399         {0x095, 0x3CE, 0x398},
 400         {0x095, 0x0FF, 0x000},
 401         {0x3E42, 0x010A, 0x3DD6},       /*B0,B1,B2 */
 402         {0x1, 0x1, 0x1},        /*S0,S1,S2 */
 403 };
 404
 405 #define mask_a(a) ((u32)(a) & 0x3FF)
 406 #define mask_b(b) ((u32)(b) & 0x3FFF)
 407
 408 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
 409 static int _rgb_to_yuv(int n, int red, int green, int blue)
 410 {
 411         int c;
 412         c = red * rgb2ycbcr_coeff[n][0];
 413         c += green * rgb2ycbcr_coeff[n][1];
 414         c += blue * rgb2ycbcr_coeff[n][2];
 415         c /= 16;
 416         c += rgb2ycbcr_coeff[3][n] * 4;
 417         c += 8;
 418         c /= 16;
 419         if (c < 0)
 420                 c = 0;
 421         if (c > 255)
 422                 c = 255;
 423         return c;
 424 }
 425
 426 /*
 427  * Row is for BG:       RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 428  * Column is for FG:    RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 429  */
 430 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
 431 {{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} },
 432 {{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} },
 433 {{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} },
 434 {{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
 435 {{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }
 436 };
 437
 438 void __ipu_dp_csc_setup(struct ipu_soc *ipu,
 439                 int dp, struct dp_csc_param_t dp_csc_param,
 440                 bool srm_mode_update)
 441 {
 442         u32 reg;
 443         const int (*coeff)[5][3];
 444
 445         if (dp_csc_param.mode >= 0) {
 446                 reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
 447                 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 448                 reg |= dp_csc_param.mode;
 449                 ipu_dp_write(ipu, reg, DP_COM_CONF(dp));
 450         }
 451
 452         coeff = dp_csc_param.coeff;
 453
 454         if (coeff) {
 455                 ipu_dp_write(ipu, mask_a((*coeff)[0][0]) |
 456                                 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
 457                 ipu_dp_write(ipu, mask_a((*coeff)[0][2]) |
 458                                 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
 459                 ipu_dp_write(ipu, mask_a((*coeff)[1][1]) |
 460                                 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
 461                 ipu_dp_write(ipu, mask_a((*coeff)[2][0]) |
 462                                 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
 463                 ipu_dp_write(ipu, mask_a((*coeff)[2][2]) |
 464                                 (mask_b((*coeff)[3][0]) << 16) |
 465                                 ((*coeff)[4][0] << 30), DP_CSC_0(dp));
 466                 ipu_dp_write(ipu, mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
 467                                 (mask_b((*coeff)[3][2]) << 16) |
 468                                 ((*coeff)[4][2] << 30), DP_CSC_1(dp));
 469         }
 470
 471         if (srm_mode_update) {
 472                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
 473                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
 474         }
 475 }
 476
 477 int _ipu_dp_init(struct ipu_soc *ipu,
 478                 ipu_channel_t channel, uint32_t in_pixel_fmt,
 479                 uint32_t out_pixel_fmt)
 480 {
 481         int in_fmt, out_fmt;
 482         int dp;
 483         int partial = false;
 484         uint32_t reg;
 485
 486         if (channel == MEM_FG_SYNC) {
 487                 dp = DP_SYNC;
 488                 partial = true;
 489         } else if (channel == MEM_BG_SYNC) {
 490                 dp = DP_SYNC;
 491                 partial = false;
 492         } else if (channel == MEM_BG_ASYNC0) {
 493                 dp = DP_ASYNC0;
 494                 partial = false;
 495         } else {
 496                 return -EINVAL;
 497         }
 498
 499         in_fmt = format_to_colorspace(in_pixel_fmt);
 500         out_fmt = format_to_colorspace(out_pixel_fmt);
 501
 502         if (partial) {
 503                 if (in_fmt == RGB) {
 504                         if (out_fmt == RGB)
 505                                 ipu->fg_csc_type = RGB2RGB;
 506                         else
 507                                 ipu->fg_csc_type = RGB2YUV;
 508                 } else {
 509                         if (out_fmt == RGB)
 510                                 ipu->fg_csc_type = YUV2RGB;
 511                         else
 512                                 ipu->fg_csc_type = YUV2YUV;
 513                 }
 514         } else {
 515                 if (in_fmt == RGB) {
 516                         if (out_fmt == RGB)
 517                                 ipu->bg_csc_type = RGB2RGB;
 518                         else
 519                                 ipu->bg_csc_type = RGB2YUV;
 520                 } else {
 521                         if (out_fmt == RGB)
 522                                 ipu->bg_csc_type = YUV2RGB;
 523                         else
 524                                 ipu->bg_csc_type = YUV2YUV;
 525                 }
 526         }
 527
 528         /* Transform color key from rgb to yuv if CSC is enabled */
 529         reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
 530         if (ipu->color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
 531                         (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
 532                          ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
 533                          ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
 534                          ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB)))) {
 535                 int red, green, blue;
 536                 int y, u, v;
 537                 uint32_t color_key = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
 538
 539                 dev_dbg(ipu->dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
 540
 541                 red = (color_key >> 16) & 0xFF;
 542                 green = (color_key >> 8) & 0xFF;
 543                 blue = color_key & 0xFF;
 544
 545                 y = _rgb_to_yuv(0, red, green, blue);
 546                 u = _rgb_to_yuv(1, red, green, blue);
 547                 v = _rgb_to_yuv(2, red, green, blue);
 548                 color_key = (y << 16) | (u << 8) | v;
 549
 550                 reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
 551                 ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(dp));
 552                 ipu->color_key_4rgb = false;
 553
 554                 dev_dbg(ipu->dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
 555         }
 556
 557         __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], true);
 558
 559         return 0;
 560 }
 561
 562 void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel)
 563 {
 564         int dp;
 565         int partial = false;
 566
 567         if (channel == MEM_FG_SYNC) {
 568                 dp = DP_SYNC;
 569                 partial = true;
 570         } else if (channel == MEM_BG_SYNC) {
 571                 dp = DP_SYNC;
 572                 partial = false;
 573         } else if (channel == MEM_BG_ASYNC0) {
 574                 dp = DP_ASYNC0;
 575                 partial = false;
 576         } else {
 577                 return;
 578         }
 579
 580         if (partial)
 581                 ipu->fg_csc_type = CSC_NONE;
 582         else
 583                 ipu->bg_csc_type = CSC_NONE;
 584
 585         __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], false);
 586 }
 587
 588 void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
 589 {
 590         u32 reg = 0;
 591
 592         if ((dc_chan == 1) || (dc_chan == 5)) {
 593                 if (interlaced) {
 594                         _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 3);
 595                         _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 2);
 596                         _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 1);
 597                 } else {
 598                         if (di) {
 599                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);
 600                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);
 601                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 4, 1);
 602                                 if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
 603                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
 604                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
 605                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
 606                                         _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
 607                                         _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
 608                                 }
 609                         } else {
 610                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
 611                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
 612                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 7, 1);
 613                                 if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
 614                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
 615                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
 616                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
 617                                         _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
 618                                         _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
 619                                 }
 620                         }
 621                 }
 622                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
 623                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
 624                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
 625                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
 626                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 627                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 628
 629                 reg = 0x2;
 630                 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 631                 reg |= di << 2;
 632                 if (interlaced)
 633                         reg |= DC_WR_CH_CONF_FIELD_MODE;
 634         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 635                 /* async channels */
 636                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
 637                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
 638
 639                 reg = 0x3;
 640                 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 641         }
 642         ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 643
 644         ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
 645
 646         ipu_dc_write(ipu, 0x00000084, DC_GEN);
 647 }
 648
 649 void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
 650 {
 651         if ((dc_chan == 1) || (dc_chan == 5)) {
 652                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
 653                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
 654                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
 655                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
 656                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
 657                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
 658                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
 659                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 660                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 661                 _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 0, 0);
 662                 _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 0, 0);
 663                 _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 0, 0);
 664                 _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 0, 0);
 665         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 666                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
 667                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
 668                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
 669                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
 670                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
 671                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
 672                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
 673                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
 674                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
 675                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
 676                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
 677                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
 678         }
 679 }
 680
 681 int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel)
 682 {
 683         if (channel == MEM_DC_SYNC)
 684                 return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_1) &
 685                           DC_WR_CH_CONF_FIELD_MODE);
 686         else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
 687                 return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_5) &
 688                           DC_WR_CH_CONF_FIELD_MODE);
 689         return 0;
 690 }
 691
 692 void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
 693 {
 694         int di;
 695         uint32_t reg;
 696         uint32_t dc_chan;
 697         int irq = 0;
 698
 699         if (channel == MEM_FG_SYNC)
 700                 irq = IPU_IRQ_DP_SF_END;
 701         else if (channel == MEM_DC_SYNC)
 702                 dc_chan = 1;
 703         else if (channel == MEM_BG_SYNC)
 704                 dc_chan = 5;
 705         else
 706                 return;
 707
 708         if (channel == MEM_FG_SYNC) {
 709                 /* Enable FG channel */
 710                 reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
 711                 ipu_dp_write(ipu, reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
 712
 713                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
 714                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
 715                 return;
 716         }
 717
 718         di = ipu->dc_di_assignment[dc_chan];
 719
 720         /* Make sure other DC sync channel is not assigned same DI */
 721         reg = ipu_dc_read(ipu, DC_WR_CH_CONF(6 - dc_chan));
 722         if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
 723                 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
 724                 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
 725                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
 726         }
 727
 728         reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
 729         reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
 730         ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 731
 732         clk_enable(&ipu->pixel_clk[di]);
 733 }
 734
 735 static irqreturn_t dc_irq_handler(int irq, void *dev_id)
 736 {
 737         struct ipu_soc *ipu = dev_id;
 738         struct completion *comp = &ipu->dc_comp;
 739         uint32_t reg;
 740         uint32_t dc_chan;
 741
 742         if (irq == IPU_IRQ_DC_FC_1)
 743                 dc_chan = 1;
 744         else
 745                 dc_chan = 5;
 746
 747         if (!ipu->dc_swap) {
 748                 reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
 749                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 750                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 751
 752                 reg = ipu_cm_read(ipu, IPU_DISP_GEN);
 753                 if (ipu->dc_di_assignment[dc_chan])
 754                         reg &= ~DI1_COUNTER_RELEASE;
 755                 else
 756                         reg &= ~DI0_COUNTER_RELEASE;
 757                 ipu_cm_write(ipu, reg, IPU_DISP_GEN);
 758         }
 759
 760         complete(comp);
 761         return IRQ_HANDLED;
 762 }
 763
 764 void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap)
 765 {
 766         int ret;
 767         unsigned long lock_flags;
 768         uint32_t reg;
 769         uint32_t csc;
 770         uint32_t dc_chan;
 771         int irq = 0;
 772         int timeout = 50;
 773
 774         ipu->dc_swap = swap;
 775
 776         if (channel == MEM_DC_SYNC) {
 777                 dc_chan = 1;
 778                 irq = IPU_IRQ_DC_FC_1;
 779         } else if (channel == MEM_BG_SYNC) {
 780                 dc_chan = 5;
 781                 irq = IPU_IRQ_DP_SF_END;
 782         } else if (channel == MEM_FG_SYNC) {
 783                 /* Disable FG channel */
 784                 dc_chan = 5;
 785
 786                 spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
 787
 788                 reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
 789                 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
 790                 if (csc == DP_COM_CONF_CSC_DEF_FG)
 791                         reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 792
 793                 reg &= ~DP_COM_CONF_FG_EN;
 794                 ipu_dp_write(ipu, reg, DP_COM_CONF(DP_SYNC));
 795
 796                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
 797                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
 798
 799                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
 800
 801                 ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
 802                              IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
 803                 while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
 804                         IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
 805                         msleep(2);
 806                         timeout -= 2;
 807                         if (timeout <= 0)
 808                                 break;
 809                 }
 810                 return;
 811         } else {
 812                 return;
 813         }
 814
 815         init_completion(&ipu->dc_comp);
 816         ipu_clear_irq(ipu, irq);
 817         ret = ipu_request_irq(ipu, irq, dc_irq_handler, 0, NULL, ipu);
 818         if (ret < 0) {
 819                 dev_err(ipu->dev, "DC irq %d in use\n", irq);
 820                 return;
 821         }
 822         ret = wait_for_completion_timeout(&ipu->dc_comp, msecs_to_jiffies(50));
 823         ipu_free_irq(ipu, irq, ipu);
 824         dev_dbg(ipu->dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
 825
 826         if (ipu->dc_swap) {
 827                 spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
 828                 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
 829                 reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
 830                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
 831                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 832                 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
 833                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 834                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
 835         } else
 836                 /* Clock is already off because it must be done quickly, but
 837                    we need to fix the ref count */
 838                 clk_disable(&ipu->pixel_clk[ipu->dc_di_assignment[dc_chan]]);
 839 }
 840
 841 void _ipu_init_dc_mappings(struct ipu_soc *ipu)
 842 {
 843         /* IPU_PIX_FMT_RGB24 */
 844         _ipu_dc_map_clear(ipu, 0);
 845         _ipu_dc_map_config(ipu, 0, 0, 7, 0xFF);
 846         _ipu_dc_map_config(ipu, 0, 1, 15, 0xFF);
 847         _ipu_dc_map_config(ipu, 0, 2, 23, 0xFF);
 848
 849         /* IPU_PIX_FMT_RGB666 */
 850         _ipu_dc_map_clear(ipu, 1);
 851         _ipu_dc_map_config(ipu, 1, 0, 5, 0xFC);
 852         _ipu_dc_map_config(ipu, 1, 1, 11, 0xFC);
 853         _ipu_dc_map_config(ipu, 1, 2, 17, 0xFC);
 854
 855         /* IPU_PIX_FMT_YUV444 */
 856         _ipu_dc_map_clear(ipu, 2);
 857         _ipu_dc_map_config(ipu, 2, 0, 15, 0xFF);
 858         _ipu_dc_map_config(ipu, 2, 1, 23, 0xFF);
 859         _ipu_dc_map_config(ipu, 2, 2, 7, 0xFF);
 860
 861         /* IPU_PIX_FMT_RGB565 */
 862         _ipu_dc_map_clear(ipu, 3);
 863         _ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
 864         _ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
 865         _ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);
 866
 867         /* IPU_PIX_FMT_LVDS666 */
 868         _ipu_dc_map_clear(ipu, 4);
 869         _ipu_dc_map_config(ipu, 4, 0, 5, 0xFC);
 870         _ipu_dc_map_config(ipu, 4, 1, 13, 0xFC);
 871         _ipu_dc_map_config(ipu, 4, 2, 21, 0xFC);
 872
 873         /* IPU_PIX_FMT_VYUY 16bit width */
 874         _ipu_dc_map_clear(ipu, 5);
 875         _ipu_dc_map_config(ipu, 5, 0, 7, 0xFF);
 876         _ipu_dc_map_config(ipu, 5, 1, 0, 0x0);
 877         _ipu_dc_map_config(ipu, 5, 2, 15, 0xFF);
 878         _ipu_dc_map_clear(ipu, 6);
 879         _ipu_dc_map_config(ipu, 6, 0, 0, 0x0);
 880         _ipu_dc_map_config(ipu, 6, 1, 7, 0xFF);
 881         _ipu_dc_map_config(ipu, 6, 2, 15, 0xFF);
 882
 883         /* IPU_PIX_FMT_UYUV 16bit width */
 884         _ipu_dc_map_clear(ipu, 7);
 885         _ipu_dc_map_link(ipu, 7, 6, 0, 6, 1, 6, 2);
 886         _ipu_dc_map_clear(ipu, 8);
 887         _ipu_dc_map_link(ipu, 8, 5, 0, 5, 1, 5, 2);
 888
 889         /* IPU_PIX_FMT_YUYV 16bit width */
 890         _ipu_dc_map_clear(ipu, 9);
 891         _ipu_dc_map_link(ipu, 9, 5, 2, 5, 1, 5, 0);
 892         _ipu_dc_map_clear(ipu, 10);
 893         _ipu_dc_map_link(ipu, 10, 5, 1, 5, 2, 5, 0);
 894
 895         /* IPU_PIX_FMT_YVYU 16bit width */
 896         _ipu_dc_map_clear(ipu, 11);
 897         _ipu_dc_map_link(ipu, 11, 5, 1, 5, 2, 5, 0);
 898         _ipu_dc_map_clear(ipu, 12);
 899         _ipu_dc_map_link(ipu, 12, 5, 2, 5, 1, 5, 0);
 900
 901         /* IPU_PIX_FMT_GBR24 */
 902         /* IPU_PIX_FMT_VYU444 */
 903         _ipu_dc_map_clear(ipu, 13);
 904         _ipu_dc_map_link(ipu, 13, 0, 2, 0, 0, 0, 1);
 905
 906         /* IPU_PIX_FMT_BGR24 */
 907         _ipu_dc_map_clear(ipu, 14);
 908         _ipu_dc_map_link(ipu, 14, 0, 2, 0, 1, 0, 0);
 909 }
 910
 911 int _ipu_pixfmt_to_map(uint32_t fmt)
 912 {
 913         switch (fmt) {
 914         case IPU_PIX_FMT_GENERIC:
 915         case IPU_PIX_FMT_RGB24:
 916                 return 0;
 917         case IPU_PIX_FMT_RGB666:
 918                 return 1;
 919         case IPU_PIX_FMT_YUV444:
 920                 return 2;
 921         case IPU_PIX_FMT_RGB565:
 922                 return 3;
 923         case IPU_PIX_FMT_LVDS666:
 924                 return 4;
 925         case IPU_PIX_FMT_VYUY:
 926                 return 6;
 927         case IPU_PIX_FMT_UYVY:
 928                 return 8;
 929         case IPU_PIX_FMT_YUYV:
 930                 return 10;
 931         case IPU_PIX_FMT_YVYU:
 932                 return 12;
 933         case IPU_PIX_FMT_GBR24:
 934         case IPU_PIX_FMT_VYU444:
 935                 return 13;
 936         case IPU_PIX_FMT_BGR24:
 937                 return 14;
 938         }
 939
 940         return -1;
 941 }
 942
 943 /*!
 944  * This function sets the colorspace for of dp.
 945  * modes.
 946  *
 947  * @param       ipu             ipu handler
 948  * @param       channel         Input parameter for the logical channel ID.
 949  *
 950  * @param       param           If it's not NULL, update the csc table
 951  *                              with this parameter.
 952  *
 953  * @return      N/A
 954  */
 955 void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
 956 {
 957         int dp;
 958         struct dp_csc_param_t dp_csc_param;
 959
 960         if (channel == MEM_FG_SYNC)
 961                 dp = DP_SYNC;
 962         else if (channel == MEM_BG_SYNC)
 963                 dp = DP_SYNC;
 964         else if (channel == MEM_BG_ASYNC0)
 965                 dp = DP_ASYNC0;
 966         else
 967                 return;
 968
 969         dp_csc_param.mode = -1;
 970         dp_csc_param.coeff = param;
 971         __ipu_dp_csc_setup(ipu, dp, dp_csc_param, true);
 972 }
 973
 974 /*!
 975  * This function is called to adapt synchronous LCD panel to IPU restriction.
 976  *
 977  */
 978 void adapt_panel_to_ipu_restricitions(struct ipu_soc *ipu, uint16_t *v_start_width,
 979                                         uint16_t *v_sync_width,
 980                                         uint16_t *v_end_width)
 981 {
 982         if (*v_end_width < 2) {
 983                 uint16_t diff = 2 - *v_end_width;
 984                 if (*v_start_width >= diff) {
 985                         *v_end_width = 2;
 986                         *v_start_width = *v_start_width - diff;
 987                 } else if (*v_sync_width > diff) {
 988                         *v_end_width = 2;
 989                         *v_sync_width = *v_sync_width - diff;
 990                 } else
 991                         dev_err(ipu->dev, "WARNING: try to adapt timming, but failed\n");
 992                 dev_err(ipu->dev, "WARNING: adapt panel end blank lines\n");
 993         }
 994 }
 995
 996 /*!
 997  * This function is called to initialize a synchronous LCD panel.
 998  *
 999  * @param       ipu             ipu handler
1000  * @param       disp            The DI the panel is attached to.
1001  *
1002  * @param       pixel_clk       Desired pixel clock frequency in Hz.
1003  *
1004  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1005  *                              Pixel format is a FOURCC ASCII code.
1006  *
1007  * @param       width           The width of panel in pixels.
1008  *
1009  * @param       height          The height of panel in pixels.
1010  *
1011  * @param       hStartWidth     The number of pixel clocks between the HSYNC
1012  *                              signal pulse and the start of valid data.
1013  *
1014  * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
1015  *                              clocks.
1016  *
1017  * @param       hEndWidth       The number of pixel clocks between the end of
1018  *                              valid data and the HSYNC signal for next line.
1019  *
1020  * @param       vStartWidth     The number of lines between the VSYNC
1021  *                              signal pulse and the start of valid data.
1022  *
1023  * @param       vSyncWidth      The width of the VSYNC signal in units of lines
1024  *
1025  * @param       vEndWidth       The number of lines between the end of valid
1026  *                              data and the VSYNC signal for next frame.
1027  *
1028  * @param       sig             Bitfield of signal polarities for LCD interface.
1029  *
1030  * @return      This function returns 0 on success or negative error code on
1031  *              fail.
1032  */
1033 int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
1034                             uint16_t width, uint16_t height,
1035                             uint32_t pixel_fmt,
1036                             uint16_t h_start_width, uint16_t h_sync_width,
1037                             uint16_t h_end_width, uint16_t v_start_width,
1038                             uint16_t v_sync_width, uint16_t v_end_width,
1039                             uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
1040 {
1041         unsigned long lock_flags;
1042         uint32_t field0_offset = 0;
1043         uint32_t field1_offset;
1044         uint32_t reg;
1045         uint32_t di_gen, vsync_cnt;
1046         uint32_t div, rounded_pixel_clk, rounded_parent_clk;
1047         uint32_t h_total, v_total;
1048         int map;
1049         struct clk *di_parent;
1050
1051         dev_dbg(ipu->dev, "panel size = %d x %d\n", width, height);
1052
1053         if ((v_sync_width == 0) || (h_sync_width == 0))
1054                 return EINVAL;
1055
1056         adapt_panel_to_ipu_restricitions(ipu, &v_start_width, &v_sync_width, &v_end_width);
1057         h_total = width + h_sync_width + h_start_width + h_end_width;
1058         v_total = height + v_sync_width + v_start_width + v_end_width;
1059
1060         /* Init clocking */
1061         dev_dbg(ipu->dev, "pixel clk = %d\n", pixel_clk);
1062
1063         di_parent = clk_get_parent(ipu->di_clk[disp]);
1064         if (clk_get(NULL, "tve_clk") == di_parent ||
1065                 clk_get(NULL, "ldb_di0_clk") == di_parent ||
1066                 clk_get(NULL, "ldb_di1_clk") == di_parent) {
1067                 /* if di clk parent is tve/ldb, then keep it;*/
1068                 dev_dbg(ipu->dev, "use special clk parent\n");
1069                 clk_set_parent(&ipu->pixel_clk[disp], ipu->di_clk[disp]);
1070         } else {
1071                 /* try ipu clk first*/
1072                 dev_dbg(ipu->dev, "try ipu internal clk\n");
1073                 clk_set_parent(&ipu->pixel_clk[disp], ipu->ipu_clk);
1074                 rounded_pixel_clk = clk_round_rate(&ipu->pixel_clk[disp], pixel_clk);
1075                 /*
1076                  * we will only use 1/2 fraction for ipu clk,
1077                  * so if the clk rate is not fit, try ext clk.
1078                  */
1079                 if (!sig.int_clk &&
1080                         ((rounded_pixel_clk >= pixel_clk + pixel_clk/200) ||
1081                         (rounded_pixel_clk <= pixel_clk - pixel_clk/200))) {
1082                         dev_dbg(ipu->dev, "try ipu ext di clk\n");
1083                         if (clk_get_usecount(di_parent))
1084                                 dev_warn(ipu->dev,
1085                                         "ext di clk already in use, go back to internal clk\n");
1086                         else {
1087                                 rounded_pixel_clk = pixel_clk * 2;
1088                                 rounded_parent_clk = clk_round_rate(di_parent,
1089                                                         rounded_pixel_clk);
1090                                 while (rounded_pixel_clk < rounded_parent_clk) {
1091                                         /* the max divider from parent to di is 8 */
1092                                         if (rounded_parent_clk / pixel_clk < 8)
1093                                                 rounded_pixel_clk += pixel_clk * 2;
1094                                         else
1095                                                 rounded_pixel_clk *= 2;
1096                                 }
1097                                 clk_set_rate(di_parent, rounded_pixel_clk);
1098                                 rounded_pixel_clk =
1099                                         clk_round_rate(ipu->di_clk[disp], pixel_clk);
1100                                 clk_set_rate(ipu->di_clk[disp], rounded_pixel_clk);
1101                                 clk_set_parent(&ipu->pixel_clk[disp], ipu->di_clk[disp]);
1102                         }
1103                 }
1104         }
1105         rounded_pixel_clk = clk_round_rate(&ipu->pixel_clk[disp], pixel_clk);
1106         clk_set_rate(&ipu->pixel_clk[disp], rounded_pixel_clk);
1107         msleep(5);
1108         /* Get integer portion of divider */
1109         div = clk_get_rate(clk_get_parent(&ipu->pixel_clk[disp])) / rounded_pixel_clk;
1110
1111         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1112
1113         _ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);
1114         _ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
1115
1116         map = _ipu_pixfmt_to_map(pixel_fmt);
1117         if (map < 0) {
1118                 dev_dbg(ipu->dev, "IPU_DISP: No MAP\n");
1119                 spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1120                 return -EINVAL;
1121         }
1122
1123         /*clear DI*/
1124         di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
1125         ipu_di_write(ipu, disp,
1126                 di_gen & (0x3 << 20), DI_GENERAL);
1127
1128         if (sig.interlaced) {
1129                 if (g_ipu_hw_rev >= 2) {
1130                         /* Setup internal HSYNC waveform */
1131                         _ipu_di_sync_config(ipu,
1132                                         disp,           /* display */
1133                                         1,              /* counter */
1134                                         h_total/2 - 1,  /* run count */
1135                                         DI_SYNC_CLK,    /* run_resolution */
1136                                         0,              /* offset */
1137                                         DI_SYNC_NONE,   /* offset resolution */
1138                                         0,              /* repeat count */
1139                                         DI_SYNC_NONE,   /* CNT_CLR_SEL */
1140                                         0,              /* CNT_POLARITY_GEN_EN */
1141                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1142                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1143                                         0,              /* COUNT UP */
1144                                         0               /* COUNT DOWN */
1145                                         );
1146
1147                         /* Field 1 VSYNC waveform */
1148                         _ipu_di_sync_config(ipu,
1149                                         disp,           /* display */
1150                                         2,              /* counter */
1151                                         h_total - 1,    /* run count */
1152                                         DI_SYNC_CLK,    /* run_resolution */
1153                                         0,              /* offset */
1154                                         DI_SYNC_NONE,   /* offset resolution */
1155                                         0,              /* repeat count */
1156                                         DI_SYNC_NONE,   /* CNT_CLR_SEL */
1157                                         0,              /* CNT_POLARITY_GEN_EN */
1158                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1159                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1160                                         0,              /* COUNT UP */
1161                                         2*div           /* COUNT DOWN */
1162                                         );
1163
1164                         /* Setup internal HSYNC waveform */
1165                         _ipu_di_sync_config(ipu,
1166                                         disp,           /* display */
1167                                         3,              /* counter */
1168                                         v_total*2 - 1,  /* run count */
1169                                         DI_SYNC_INT_HSYNC,      /* run_resolution */
1170                                         1,                      /* offset */
1171                                         DI_SYNC_INT_HSYNC,      /* offset resolution */
1172                                         0,              /* repeat count */
1173                                         DI_SYNC_NONE,   /* CNT_CLR_SEL */
1174                                         0,              /* CNT_POLARITY_GEN_EN */
1175                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1176                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1177                                         0,              /* COUNT UP */
1178                                         2*div           /* COUNT DOWN */
1179                                         );
1180
1181                         /* Active Field ? */
1182                         _ipu_di_sync_config(ipu,
1183                                         disp,           /* display */
1184                                         4,              /* counter */
1185                                         v_total/2 - 1,  /* run count */
1186                                         DI_SYNC_HSYNC,  /* run_resolution */
1187                                         v_start_width,  /*  offset */
1188                                         DI_SYNC_HSYNC,  /* offset resolution */
1189                                         2,              /* repeat count */
1190                                         DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1191                                         0,              /* CNT_POLARITY_GEN_EN */
1192                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1193                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1194                                         0,              /* COUNT UP */
1195                                         0               /* COUNT DOWN */
1196                                         );
1197
1198                         /* Active Line */
1199                         _ipu_di_sync_config(ipu,
1200                                         disp,           /* display */
1201                                         5,              /* counter */
1202                                         0,              /* run count */
1203                                         DI_SYNC_HSYNC,  /* run_resolution */
1204                                         0,              /*  offset */
1205                                         DI_SYNC_NONE,   /* offset resolution */
1206                                         height/2,       /* repeat count */
1207                                         4,              /* CNT_CLR_SEL */
1208                                         0,              /* CNT_POLARITY_GEN_EN */
1209                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1210                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1211                                         0,              /* COUNT UP */
1212                                         0               /* COUNT DOWN */
1213                                         );
1214
1215                         /* Field 0 VSYNC waveform */
1216                         _ipu_di_sync_config(ipu,
1217                                         disp,           /* display */
1218                                         6,              /* counter */
1219                                         v_total - 1,    /* run count */
1220                                         DI_SYNC_HSYNC,  /* run_resolution */
1221                                         0,              /* offset */
1222                                         DI_SYNC_NONE,   /* offset resolution */
1223                                         0,              /* repeat count */
1224                                         DI_SYNC_NONE,   /* CNT_CLR_SEL  */
1225                                         0,              /* CNT_POLARITY_GEN_EN */
1226                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1227                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1228                                         0,              /* COUNT UP */
1229                                         0               /* COUNT DOWN */
1230                                         );
1231
1232                         /* DC VSYNC waveform */
1233                         vsync_cnt = 7;
1234                         _ipu_di_sync_config(ipu,
1235                                         disp,           /* display */
1236                                         7,              /* counter */
1237                                         v_total/2 - 1,  /* run count */
1238                                         DI_SYNC_HSYNC,  /* run_resolution  */
1239                                         9,              /* offset  */
1240                                         DI_SYNC_HSYNC,  /* offset resolution */
1241                                         2,              /* repeat count */
1242                                         DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1243                                         0,              /* CNT_POLARITY_GEN_EN */
1244                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1245                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1246                                         0,              /* COUNT UP */
1247                                         0               /* COUNT DOWN */
1248                                         );
1249
1250                         /* active pixel waveform */
1251                         _ipu_di_sync_config(ipu,
1252                                         disp,           /* display */
1253                                         8,              /* counter */
1254                                         0,              /* run count  */
1255                                         DI_SYNC_CLK,    /* run_resolution */
1256                                         h_start_width,  /* offset  */
1257                                         DI_SYNC_CLK,    /* offset resolution */
1258                                         width,          /* repeat count  */
1259                                         5,              /* CNT_CLR_SEL  */
1260                                         0,              /* CNT_POLARITY_GEN_EN  */
1261                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1262                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL  */
1263                                         0,              /* COUNT UP  */
1264                                         0               /* COUNT DOWN */
1265                                         );
1266
1267                         /* Second VSYNC */
1268                         _ipu_di_sync_config(ipu,
1269                                         disp,           /* display */
1270                                         9,              /* counter */
1271                                         v_total - 1,    /* run count */
1272                                         DI_SYNC_INT_HSYNC,      /* run_resolution */
1273                                         v_total/2,              /* offset  */
1274                                         DI_SYNC_INT_HSYNC,      /* offset resolution  */
1275                                         0,              /* repeat count */
1276                                         DI_SYNC_HSYNC,  /* CNT_CLR_SEL */
1277                                         0,              /* CNT_POLARITY_GEN_EN  */
1278                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL  */
1279                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1280                                         0,              /* COUNT UP */
1281                                         2*div           /* COUNT DOWN */
1282                                         );
1283
1284                         /* set gentime select and tag sel */
1285                         reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
1286                         reg &= 0x1FFFFFFF;
1287                         reg |= (3-1)<<29 | 0x00008000;
1288                         ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
1289
1290                         ipu_di_write(ipu, disp, v_total / 2 - 1, DI_SCR_CONF);
1291
1292                         /* set y_sel = 1 */
1293                         di_gen |= 0x10000000;
1294                         di_gen |= DI_GEN_POLARITY_5;
1295                         di_gen |= DI_GEN_POLARITY_8;
1296                 } else {
1297                         /* Setup internal HSYNC waveform */
1298                         _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
1299                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1300                                         DI_SYNC_NONE, 0, 0);
1301
1302                         field1_offset = v_sync_width + v_start_width + height / 2 +
1303                                 v_end_width;
1304                         if (sig.odd_field_first) {
1305                                 field0_offset = field1_offset - 1;
1306                                 field1_offset = 0;
1307                         }
1308                         v_total += v_start_width + v_end_width;
1309
1310                         /* Field 1 VSYNC waveform */
1311                         _ipu_di_sync_config(ipu, disp, 2, v_total - 1, 1,
1312                                         field0_offset,
1313                                         field0_offset ? 1 : DI_SYNC_NONE,
1314                                         0, DI_SYNC_NONE, 0,
1315                                         DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
1316
1317                         /* Setup internal HSYNC waveform */
1318                         _ipu_di_sync_config(ipu, disp, 3, h_total - 1, DI_SYNC_CLK,
1319                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,
1320                                         DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
1321
1322                         /* Active Field ? */
1323                         _ipu_di_sync_config(ipu, disp, 4,
1324                                         field0_offset ?
1325                                         field0_offset : field1_offset - 2,
1326                                         1, v_start_width + v_sync_width, 1, 2, 2,
1327                                         0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
1328
1329                         /* Active Line */
1330                         _ipu_di_sync_config(ipu, disp, 5, 0, 1,
1331                                         0, DI_SYNC_NONE,
1332                                         height / 2, 4, 0, DI_SYNC_NONE,
1333                                         DI_SYNC_NONE, 0, 0);
1334
1335                         /* Field 0 VSYNC waveform */
1336                         _ipu_di_sync_config(ipu, disp, 6, v_total - 1, 1,
1337                                         0, DI_SYNC_NONE,
1338                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1339                                         DI_SYNC_NONE, 0, 0);
1340
1341                         /* DC VSYNC waveform */
1342                         vsync_cnt = 7;
1343                         _ipu_di_sync_config(ipu, disp, 7, 0, 1,
1344                                         field1_offset,
1345                                         field1_offset ? 1 : DI_SYNC_NONE,
1346                                         1, 2, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
1347
1348                         /* active pixel waveform */
1349                         _ipu_di_sync_config(ipu, disp, 8, 0, DI_SYNC_CLK,
1350                                         h_sync_width + h_start_width, DI_SYNC_CLK,
1351                                         width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE,
1352                                         0, 0);
1353
1354                         /* ??? */
1355                         _ipu_di_sync_config(ipu, disp, 9, v_total - 1, 2,
1356                                         0, DI_SYNC_NONE,
1357                                         0, DI_SYNC_NONE, 6, DI_SYNC_NONE,
1358                                         DI_SYNC_NONE, 0, 0);
1359
1360                         reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
1361                         reg |= 0x8000;
1362                         ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
1363
1364                         ipu_di_write(ipu, disp, v_sync_width + v_start_width +
1365                                         v_end_width + height / 2 - 1, DI_SCR_CONF);
1366                 }
1367
1368                 /* Init template microcode */
1369                 _ipu_dc_write_tmpl(ipu, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
1370
1371                 if (sig.Hsync_pol)
1372                         di_gen |= DI_GEN_POLARITY_3;
1373                 if (sig.Vsync_pol)
1374                         di_gen |= DI_GEN_POLARITY_2;
1375         } else {
1376                 /* Setup internal HSYNC waveform */
1377                 _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
1378                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1379                                         DI_SYNC_NONE, 0, 0);
1380
1381                 /* Setup external (delayed) HSYNC waveform */
1382                 _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,
1383                                     DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1384                                     0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1385                                     DI_SYNC_CLK, 0, h_sync_width * 2);
1386                 /* Setup VSYNC waveform */
1387                 vsync_cnt = DI_SYNC_VSYNC;
1388                 _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,
1389                                     DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1390                                     DI_SYNC_NONE, 1, DI_SYNC_NONE,
1391                                     DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1392                 ipu_di_write(ipu, disp, v_total - 1, DI_SCR_CONF);
1393
1394                 /* Setup active data waveform to sync with DC */
1395                 _ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC,
1396                                     v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
1397                                     DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1398                                     DI_SYNC_NONE, 0, 0);
1399                 _ipu_di_sync_config(ipu, disp, 5, 0, DI_SYNC_CLK,
1400                                     h_sync_width + h_start_width, DI_SYNC_CLK,
1401                                     width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1402                                     0);
1403
1404                 /* set VGA delayed hsync/vsync no matter VGA enabled */
1405                 if (disp) {
1406                         /* couter 7 for VGA delay HSYNC */
1407                         _ipu_di_sync_config(ipu, disp, 7,
1408                                         h_total - 1, DI_SYNC_CLK,
1409                                         18, DI_SYNC_CLK,
1410                                         0, DI_SYNC_NONE,
1411                                         1, DI_SYNC_NONE, DI_SYNC_CLK,
1412                                         0, h_sync_width * 2);
1413
1414                         /* couter 8 for VGA delay VSYNC */
1415                         _ipu_di_sync_config(ipu, disp, 8,
1416                                         v_total - 1, DI_SYNC_INT_HSYNC,
1417                                         1, DI_SYNC_INT_HSYNC,
1418                                         0, DI_SYNC_NONE,
1419                                         1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,
1420                                         0, v_sync_width * 2);
1421                 }
1422
1423                 /* reset all unused counters */
1424                 ipu_di_write(ipu, disp, 0, DI_SW_GEN0(6));
1425                 ipu_di_write(ipu, disp, 0, DI_SW_GEN1(6));
1426                 if (!disp) {
1427                         ipu_di_write(ipu, disp, 0, DI_SW_GEN0(7));
1428                         ipu_di_write(ipu, disp, 0, DI_SW_GEN1(7));
1429                         ipu_di_write(ipu, disp, 0, DI_STP_REP(7));
1430                         ipu_di_write(ipu, disp, 0, DI_SW_GEN0(8));
1431                         ipu_di_write(ipu, disp, 0, DI_SW_GEN1(8));
1432                         ipu_di_write(ipu, disp, 0, DI_STP_REP(8));
1433                 }
1434                 ipu_di_write(ipu, disp, 0, DI_SW_GEN0(9));
1435                 ipu_di_write(ipu, disp, 0, DI_SW_GEN1(9));
1436                 ipu_di_write(ipu, disp, 0, DI_STP_REP(9));
1437
1438                 reg = ipu_di_read(ipu, disp, DI_STP_REP(6));
1439                 reg &= 0x0000FFFF;
1440                 ipu_di_write(ipu, disp, reg, DI_STP_REP(6));
1441
1442                 /* Init template microcode */
1443                 if (disp) {
1444                         if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
1445                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
1446                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
1447                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
1448                                 _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
1449                                 _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1450                                 /* configure user events according to DISP NUM */
1451                                 ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
1452                         }
1453                         _ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
1454                         _ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
1455                         _ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1456                 } else {
1457                         if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
1458                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
1459                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
1460                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
1461                                 _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
1462                                 _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1463                                 /* configure user events according to DISP NUM */
1464                                 ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
1465                         }
1466                    _ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
1467                    _ipu_dc_write_tmpl(ipu, 6, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
1468                    _ipu_dc_write_tmpl(ipu, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1469                 }
1470
1471                 if (sig.Hsync_pol) {
1472                         di_gen |= DI_GEN_POLARITY_2;
1473                         if (disp)
1474                                 di_gen |= DI_GEN_POLARITY_7;
1475                 }
1476                 if (sig.Vsync_pol) {
1477                         di_gen |= DI_GEN_POLARITY_3;
1478                         if (disp)
1479                                 di_gen |= DI_GEN_POLARITY_8;
1480                 }
1481         }
1482         /* changinc DISP_CLK polarity: it can be wrong for some applications */
1483         if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
1484                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
1485                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
1486                 (pixel_fmt == IPU_PIX_FMT_VYUY))
1487                         di_gen |= 0x00020000;
1488
1489         if (!sig.clk_pol)
1490                 di_gen |= DI_GEN_POLARITY_DISP_CLK;
1491
1492         ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
1493
1494         ipu_di_write(ipu, disp, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1495                         0x00000002, DI_SYNC_AS_GEN);
1496         reg = ipu_di_read(ipu, disp, DI_POL);
1497         reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1498         if (sig.enable_pol)
1499                 reg |= DI_POL_DRDY_POLARITY_15;
1500         if (sig.data_pol)
1501                 reg |= DI_POL_DRDY_DATA_POLARITY;
1502         ipu_di_write(ipu, disp, reg, DI_POL);
1503
1504         ipu_dc_write(ipu, width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1505
1506         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1507
1508         return 0;
1509 }
1510 EXPORT_SYMBOL(ipu_init_sync_panel);
1511
1512 void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp)
1513 {
1514         unsigned long lock_flags;
1515         uint32_t reg;
1516         uint32_t di_gen;
1517
1518         if ((disp != 0) || (disp != 1))
1519                 return;
1520
1521         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1522
1523         di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
1524         di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
1525         ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
1526
1527         reg = ipu_di_read(ipu, disp, DI_POL);
1528         reg |= 0x3ffffff;
1529         ipu_di_write(ipu, disp, reg, DI_POL);
1530
1531         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1532 }
1533 EXPORT_SYMBOL(ipu_uninit_sync_panel);
1534
1535 int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
1536                          uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
1537 {
1538         unsigned long lock_flags;
1539         int map;
1540         u32 ser_conf = 0;
1541         u32 div;
1542         u32 di_clk = clk_get_rate(ipu->ipu_clk);
1543
1544         /* round up cycle_time, then calcalate the divider using scaled math */
1545         cycle_time += (1000000000UL / di_clk) - 1;
1546         div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);
1547
1548         map = _ipu_pixfmt_to_map(pixel_fmt);
1549         if (map < 0)
1550                 return -EINVAL;
1551
1552         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1553
1554         if (type == IPU_PANEL_SERIAL) {
1555                 ipu_di_write(ipu, disp, (div << 24) | ((sig.ifc_width - 1) << 4),
1556                              DI_DW_GEN(ASYNC_SER_WAVE));
1557
1558                 _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_CS,
1559                                         0, 0, (div * 2) + 1);
1560                 _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK,
1561                                         1, div, div * 2);
1562                 _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_RS,
1563                                         2, 0, 0);
1564
1565                 _ipu_dc_write_tmpl(ipu, 0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0, 1);
1566
1567                 /* Configure DC for serial panel */
1568                 ipu_dc_write(ipu, 0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL));
1569
1570                 if (sig.clk_pol)
1571                         ser_conf |= DI_SER_CONF_SERIAL_CLK_POL;
1572                 if (sig.data_pol)
1573                         ser_conf |= DI_SER_CONF_SERIAL_DATA_POL;
1574                 if (sig.rs_pol)
1575                         ser_conf |= DI_SER_CONF_SERIAL_RS_POL;
1576                 if (sig.cs_pol)
1577                         ser_conf |= DI_SER_CONF_SERIAL_CS_POL;
1578                 ipu_di_write(ipu, disp, ser_conf, DI_SER_CONF);
1579         }
1580
1581         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1582         return 0;
1583 }
1584 EXPORT_SYMBOL(ipu_init_async_panel);
1585
1586 /*!
1587  * This function sets the foreground and background plane global alpha blending
1588  * modes. This function also sets the DP graphic plane according to the
1589  * parameter of IPUv3 DP channel.
1590  *
1591  * @param       ipu             ipu handler
1592  * @param       channel         IPUv3 DP channel
1593  *
1594  * @param       enable          Boolean to enable or disable global alpha
1595  *                              blending. If disabled, local blending is used.
1596  *
1597  * @param       alpha           Global alpha value.
1598  *
1599  * @return      Returns 0 on success or negative error code on fail
1600  */
1601 int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel,
1602                                 bool enable, uint8_t alpha)
1603 {
1604         uint32_t reg;
1605         uint32_t flow;
1606         unsigned long lock_flags;
1607         bool bg_chan;
1608
1609         if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1610                 flow = DP_SYNC;
1611         else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1612                 flow = DP_ASYNC0;
1613         else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1614                 flow = DP_ASYNC1;
1615         else
1616                 return -EINVAL;
1617
1618         if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1619             channel == MEM_BG_ASYNC1)
1620                 bg_chan = true;
1621         else
1622                 bg_chan = false;
1623
1624         if (!ipu->clk_enabled)
1625                 clk_enable(ipu->ipu_clk);
1626         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1627
1628         if (bg_chan) {
1629                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1630                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
1631         } else {
1632                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1633                 ipu_dp_write(ipu, reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
1634         }
1635
1636         if (enable) {
1637                 reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
1638                 ipu_dp_write(ipu, reg | ((uint32_t) alpha << 24),
1639                              DP_GRAPH_WIND_CTRL(flow));
1640
1641                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1642                 ipu_dp_write(ipu, reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
1643         } else {
1644                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1645                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
1646         }
1647
1648         reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
1649         ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1650
1651         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1652         if (!ipu->clk_enabled)
1653                 clk_disable(ipu->ipu_clk);
1654
1655         return 0;
1656 }
1657 EXPORT_SYMBOL(ipu_disp_set_global_alpha);
1658
1659 /*!
1660  * This function sets the transparent color key for SDC graphic plane.
1661  *
1662  * @param       ipu             ipu handler
1663  * @param       channel         Input parameter for the logical channel ID.
1664  *
1665  * @param       enable          Boolean to enable or disable color key
1666  *
1667  * @param       colorKey        24-bit RGB color for transparent color key.
1668  *
1669  * @return      Returns 0 on success or negative error code on fail
1670  */
1671 int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel,
1672                                 bool enable, uint32_t color_key)
1673 {
1674         uint32_t reg, flow;
1675         int y, u, v;
1676         int red, green, blue;
1677         unsigned long lock_flags;
1678
1679         if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1680                 flow = DP_SYNC;
1681         else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1682                 flow = DP_ASYNC0;
1683         else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1684                 flow = DP_ASYNC1;
1685         else
1686                 return -EINVAL;
1687
1688         if (!ipu->clk_enabled)
1689                 clk_enable(ipu->ipu_clk);
1690
1691         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1692
1693         ipu->color_key_4rgb = true;
1694         /* Transform color key from rgb to yuv if CSC is enabled */
1695         if (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
1696                         ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
1697                         ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
1698                         ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB))) {
1699
1700                 dev_dbg(ipu->dev, "color key 0x%x need change to yuv fmt\n", color_key);
1701
1702                 red = (color_key >> 16) & 0xFF;
1703                 green = (color_key >> 8) & 0xFF;
1704                 blue = color_key & 0xFF;
1705
1706                 y = _rgb_to_yuv(0, red, green, blue);
1707                 u = _rgb_to_yuv(1, red, green, blue);
1708                 v = _rgb_to_yuv(2, red, green, blue);
1709                 color_key = (y << 16) | (u << 8) | v;
1710
1711                 ipu->color_key_4rgb = false;
1712
1713                 dev_dbg(ipu->dev, "color key change to yuv fmt 0x%x\n", color_key);
1714         }
1715
1716         if (enable) {
1717                 reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
1718                 ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(flow));
1719
1720                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1721                 ipu_dp_write(ipu, reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
1722         } else {
1723                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1724                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
1725         }
1726
1727         reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
1728         ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1729
1730         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1731         if (!ipu->clk_enabled)
1732                 clk_disable(ipu->ipu_clk);
1733
1734         return 0;
1735 }
1736 EXPORT_SYMBOL(ipu_disp_set_color_key);
1737
1738 /*!
1739  * This function sets the gamma correction for DP output.
1740  *
1741  * @param       ipu             ipu handler
1742  * @param       channel         Input parameter for the logical channel ID.
1743  *
1744  * @param       enable          Boolean to enable or disable gamma correction.
1745  *
1746  * @param       constk          Gamma piecewise linear approximation constk coeff.
1747  *
1748  * @param       slopek          Gamma piecewise linear approximation slopek coeff.
1749  *
1750  * @return      Returns 0 on success or negative error code on fail
1751  */
1752 int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, int constk[], int slopek[])
1753 {
1754         uint32_t reg, flow, i;
1755         unsigned long lock_flags;
1756
1757         if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1758                 flow = DP_SYNC;
1759         else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1760                 flow = DP_ASYNC0;
1761         else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1762                 flow = DP_ASYNC1;
1763         else
1764                 return -EINVAL;
1765
1766         if (!ipu->clk_enabled)
1767                 clk_enable(ipu->ipu_clk);
1768         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1769
1770         for (i = 0; i < 8; i++)
1771                 ipu_dp_write(ipu, (constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i));
1772         for (i = 0; i < 4; i++)
1773                 ipu_dp_write(ipu, (slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) |
1774                         ((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i));
1775
1776         reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1777         if (enable) {
1778                 if ((ipu->bg_csc_type == RGB2YUV) || (ipu->bg_csc_type == YUV2YUV))
1779                         reg |= DP_COM_CONF_GAMMA_YUV_EN;
1780                 else
1781                         reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
1782                 ipu_dp_write(ipu, reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
1783         } else
1784                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
1785
1786         reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
1787         ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1788
1789         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1790         if (!ipu->clk_enabled)
1791                 clk_disable(ipu->ipu_clk);
1792
1793         return 0;
1794 }
1795 EXPORT_SYMBOL(ipu_disp_set_gamma_correction);
1796
1797 /*!
1798  * This function sets the window position of the foreground or background plane.
1799  * modes.
1800  *
1801  * @param       ipu             ipu handler
1802  * @param       channel         Input parameter for the logical channel ID.
1803  *
1804  * @param       x_pos           The X coordinate position to place window at.
1805  *                              The position is relative to the top left corner.
1806  *
1807  * @param       y_pos           The Y coordinate position to place window at.
1808  *                              The position is relative to the top left corner.
1809  *
1810  * @return      Returns 0 on success or negative error code on fail
1811  */
1812 int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
1813                                 int16_t x_pos, int16_t y_pos)
1814 {
1815         u32 reg;
1816         unsigned long lock_flags;
1817         uint32_t flow = 0;
1818         uint32_t dp_srm_shift;
1819
1820         if ((channel == MEM_FG_SYNC) || (channel == MEM_BG_SYNC)) {
1821                 flow = DP_SYNC;
1822                 dp_srm_shift = 3;
1823         } else if (channel == MEM_FG_ASYNC0) {
1824                 flow = DP_ASYNC0;
1825                 dp_srm_shift = 5;
1826         } else if (channel == MEM_FG_ASYNC1) {
1827                 flow = DP_ASYNC1;
1828                 dp_srm_shift = 7;
1829         } else
1830                 return -EINVAL;
1831
1832         if (!ipu->clk_enabled)
1833                 clk_enable(ipu->ipu_clk);
1834
1835         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1836
1837         ipu_dp_write(ipu, (x_pos << 16) | y_pos, DP_FG_POS(flow));
1838
1839         if (ipu_is_channel_busy(ipu, channel)) {
1840                 /* controled by FSU if channel enabled */
1841                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
1842                 reg |= (0x1 << dp_srm_shift);
1843                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1844         } else {
1845                 /* disable auto swap, controled by MCU if channel disabled */
1846                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
1847                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1848         }
1849
1850         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1851         if (!ipu->clk_enabled)
1852                 clk_disable(ipu->ipu_clk);
1853
1854         return 0;
1855 }
1856 EXPORT_SYMBOL(ipu_disp_set_window_pos);
1857
1858 int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
1859                                 int16_t *x_pos, int16_t *y_pos)
1860 {
1861         u32 reg;
1862         unsigned long lock_flags;
1863         uint32_t flow = 0;
1864
1865         if (channel == MEM_FG_SYNC)
1866                 flow = DP_SYNC;
1867         else if (channel == MEM_FG_ASYNC0)
1868                 flow = DP_ASYNC0;
1869         else if (channel == MEM_FG_ASYNC1)
1870                 flow = DP_ASYNC1;
1871         else
1872                 return -EINVAL;
1873
1874         if (!ipu->clk_enabled)
1875                 clk_enable(ipu->ipu_clk);
1876         spin_lock_irqsave(&ipu->ipu_lock, lock_flags);
1877
1878         reg = ipu_dp_read(ipu, DP_FG_POS(flow));
1879
1880         *x_pos = (reg >> 16) & 0x7FF;
1881         *y_pos = reg & 0x7FF;
1882
1883         spin_unlock_irqrestore(&ipu->ipu_lock, lock_flags);
1884         if (!ipu->clk_enabled)
1885                 clk_disable(ipu->ipu_clk);
1886
1887         return 0;
1888 }
1889 EXPORT_SYMBOL(ipu_disp_get_window_pos);
1890
1891 void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset)
1892 {
1893         if (channel == DIRECT_ASYNC0)
1894                 writel(value, ipu->disp_base[0] + offset);
1895         else if (channel == DIRECT_ASYNC1)
1896                 writel(value, ipu->disp_base[1] + offset);
1897 }
1898 EXPORT_SYMBOL(ipu_disp_direct_write);
1899
1900 void ipu_reset_disp_panel(struct ipu_soc *ipu)
1901 {
1902         uint32_t tmp;
1903
1904         tmp = ipu_di_read(ipu, 1, DI_GENERAL);
1905         ipu_di_write(ipu, 1, tmp | 0x08, DI_GENERAL);
1906         msleep(10); /* tRES >= 100us */
1907         tmp = ipu_di_read(ipu, 1, DI_GENERAL);
1908         ipu_di_write(ipu, 1, tmp & ~0x08, DI_GENERAL);
1909         msleep(60);
1910
1911         return;
1912 }
1913 EXPORT_SYMBOL(ipu_reset_disp_panel);
1914
1915 void __devinit ipu_disp_init(struct ipu_soc *ipu)
1916 {
1917         ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
1918         ipu->color_key_4rgb = true;
1919         _ipu_init_dc_mappings(ipu);
1920         _ipu_dmfc_init(ipu, DMFC_NORMAL, 1);
1921 }