drivers/mxc/ipu3/ipu_disp.c

   1 /*
   2  * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /*!
  15  * @file ipu_disp.c
  16  *
  17  * @brief IPU display submodule API functions
  18  *
  19  * @ingroup IPU
  20  */
  21
  22 #include <linux/types.h>
  23 #include <linux/errno.h>
  24 #include <linux/delay.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/err.h>
  29 #include <asm/atomic.h>
  30 #include <mach/clock.h>
  31 #include <mach/ipu-v3.h>
  32 #include "ipu_prv.h"
  33 #include "ipu_regs.h"
  34 #include "ipu_param_mem.h"
  35
  36 struct dp_csc_param_t {
  37         int mode;
  38         void *coeff;
  39 };
  40
  41 #define SYNC_WAVE 0
  42 #define ASYNC_SER_WAVE 6
  43
  44 /* DC display ID assignments */
  45 #define DC_DISP_ID_SYNC(di)     (di)
  46 #define DC_DISP_ID_SERIAL       2
  47 #define DC_DISP_ID_ASYNC        3
  48
  49 static inline struct ipu_soc *pixelclk2ipu(struct clk *clk)
  50 {
  51         struct ipu_soc *ipu;
  52         struct clk *base = clk - clk->id;
  53
  54         ipu = container_of(base, struct ipu_soc, pixel_clk[0]);
  55
  56         return ipu;
  57 }
  58
  59 static unsigned long _ipu_pixel_clk_get_rate(struct clk *clk)
  60 {
  61         struct ipu_soc *ipu = pixelclk2ipu(clk);
  62         u32 div = ipu_di_read(ipu, clk->id, DI_BS_CLKGEN0);
  63         if (div == 0)
  64                 return 0;
  65         return  (clk_get_rate(clk->parent) * 16) / div;
  66 }
  67
  68 static unsigned long _ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate)
  69 {
  70         u32 div;
  71         u32 parent_rate = clk_get_rate(clk->parent) * 16;
  72         /*
  73          * Calculate divider
  74          * Fractional part is 4 bits,
  75          * so simply multiply by 2^4 to get fractional part.
  76          */
  77         div = parent_rate / rate;
  78
  79         if (div < 0x10)            /* Min DI disp clock divider is 1 */
  80                 div = 0x10;
  81         if (div & ~0xFEF)
  82                 div &= 0xFF8;
  83         else {
  84                 /* Round up divider if it gets us closer to desired pix clk */
  85                 if ((div & 0xC) == 0xC) {
  86                         div += 0x10;
  87                         div &= ~0xF;
  88                 }
  89         }
  90         return parent_rate / div;
  91 }
  92
  93 static int _ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
  94 {
  95         struct ipu_soc *ipu = pixelclk2ipu(clk);
  96         u32 div = (clk_get_rate(clk->parent) * 16) / rate;
  97
  98         /* Round up divider if it gets us closer to desired pix clk */
  99         if ((div & 0xC) == 0xC) {
 100                 div += 0x10;
 101                 div &= ~0xF;
 102         }
 103
 104         ipu_di_write(ipu, clk->id, div, DI_BS_CLKGEN0);
 105
 106         /* Setup pixel clock timing */
 107         /* FIXME: needs to be more flexible */
 108         /* Down time is half of period */
 109         ipu_di_write(ipu, clk->id, (div / 16) << 16, DI_BS_CLKGEN1);
 110
 111         return 0;
 112 }
 113
 114 static int _ipu_pixel_clk_enable(struct clk *clk)
 115 {
 116         struct ipu_soc *ipu = pixelclk2ipu(clk);
 117         u32 disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
 118         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 119         ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
 120
 121         return 0;
 122 }
 123
 124 static void _ipu_pixel_clk_disable(struct clk *clk)
 125 {
 126         struct ipu_soc *ipu = pixelclk2ipu(clk);
 127
 128         u32 disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
 129         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 130         ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
 131 }
 132
 133 static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 134 {
 135         struct ipu_soc *ipu = pixelclk2ipu(clk);
 136         u32 di_gen;
 137
 138         di_gen = ipu_di_read(ipu, clk->id, DI_GENERAL);
 139         if (parent == ipu->ipu_clk)
 140                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 141         else if (!IS_ERR(ipu->di_clk[clk->id]) && parent == ipu->di_clk[clk->id])
 142                 di_gen |= DI_GEN_DI_CLK_EXT;
 143         else {
 144                 return -EINVAL;
 145         }
 146
 147         ipu_di_write(ipu, clk->id, di_gen, DI_GENERAL);
 148         return 0;
 149 }
 150
 151 #ifdef CONFIG_CLK_DEBUG
 152 #define __INIT_CLK_DEBUG(n)    .name = #n,
 153 #else
 154 #define __INIT_CLK_DEBUG(n)
 155 #endif
 156 struct clk ipu_pixel_clk[] = {
 157         {
 158                 __INIT_CLK_DEBUG(pixel_clk_0)
 159                         .id = 0,
 160                 .get_rate = _ipu_pixel_clk_get_rate,
 161                 .set_rate = _ipu_pixel_clk_set_rate,
 162                 .round_rate = _ipu_pixel_clk_round_rate,
 163                 .set_parent = _ipu_pixel_clk_set_parent,
 164                 .enable = _ipu_pixel_clk_enable,
 165                 .disable = _ipu_pixel_clk_disable,
 166         },
 167         {
 168                 __INIT_CLK_DEBUG(pixel_clk_1)
 169                         .id = 1,
 170                 .get_rate = _ipu_pixel_clk_get_rate,
 171                 .set_rate = _ipu_pixel_clk_set_rate,
 172                 .round_rate = _ipu_pixel_clk_round_rate,
 173                 .set_parent = _ipu_pixel_clk_set_parent,
 174                 .enable = _ipu_pixel_clk_enable,
 175                 .disable = _ipu_pixel_clk_disable,
 176         },
 177 };
 178
 179 struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2] = {
 180         {
 181                 {
 182                         .con_id = "pixel_clk_0",
 183                 },
 184                 {
 185                         .con_id = "pixel_clk_1",
 186                 },
 187         },
 188         {
 189                 {
 190                         .con_id = "pixel_clk_0",
 191                 },
 192                 {
 193                         .con_id = "pixel_clk_1",
 194                 },
 195         },
 196 };
 197
 198 int dmfc_type_setup;
 199
 200 void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first)
 201 {
 202         u32 dmfc_wr_chan, dmfc_dp_chan;
 203
 204         if (first) {
 205                 if (dmfc_type_setup > dmfc_type)
 206                         dmfc_type = dmfc_type_setup;
 207                 else
 208                         dmfc_type_setup = dmfc_type;
 209
 210                 /* disable DMFC-IC channel*/
 211                 ipu_dmfc_write(ipu, 0x2, DMFC_IC_CTRL);
 212         } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
 213                 dev_dbg(ipu->dev, "DMFC high resolution has set, will not change\n");
 214                 return;
 215         } else
 216                 dmfc_type_setup = dmfc_type;
 217
 218         if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
 219                 /* 1 - segment 0~3;
 220                  * 5B - segement 4, 5;
 221                  * 5F - segement 6, 7;
 222                  * 1C, 2C and 6B, 6F unused;
 223                  */
 224                 dev_info(ipu->dev, "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
 225                 dmfc_wr_chan = 0x00000088;
 226                 dmfc_dp_chan = 0x00009694;
 227                 ipu->dmfc_size_28 = 256*4;
 228                 ipu->dmfc_size_29 = 0;
 229                 ipu->dmfc_size_24 = 0;
 230                 ipu->dmfc_size_27 = 128*4;
 231                 ipu->dmfc_size_23 = 128*4;
 232         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
 233                 /* 1 - segment 0, 1;
 234                  * 5B - segement 2~5;
 235                  * 5F - segement 6,7;
 236                  * 1C, 2C and 6B, 6F unused;
 237                  */
 238                 dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
 239                 dmfc_wr_chan = 0x00000090;
 240                 dmfc_dp_chan = 0x0000968a;
 241                 ipu->dmfc_size_28 = 128*4;
 242                 ipu->dmfc_size_29 = 0;
 243                 ipu->dmfc_size_24 = 0;
 244                 ipu->dmfc_size_27 = 128*4;
 245                 ipu->dmfc_size_23 = 256*4;
 246         } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
 247                 /* 5B - segement 0~3;
 248                  * 5F - segement 4~7;
 249                  * 1, 1C, 2C and 6B, 6F unused;
 250                  */
 251                 dev_info(ipu->dev, "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
 252                 dmfc_wr_chan = 0x00000000;
 253                 dmfc_dp_chan = 0x00008c88;
 254                 ipu->dmfc_size_28 = 0;
 255                 ipu->dmfc_size_29 = 0;
 256                 ipu->dmfc_size_24 = 0;
 257                 ipu->dmfc_size_27 = 256*4;
 258                 ipu->dmfc_size_23 = 256*4;
 259         } else {
 260                 /* 1 - segment 0, 1;
 261                  * 5B - segement 4, 5;
 262                  * 5F - segement 6, 7;
 263                  * 1C, 2C and 6B, 6F unused;
 264                  */
 265                 dev_info(ipu->dev, "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
 266                 dmfc_wr_chan = 0x00000090;
 267                 dmfc_dp_chan = 0x00009694;
 268                 ipu->dmfc_size_28 = 128*4;
 269                 ipu->dmfc_size_29 = 0;
 270                 ipu->dmfc_size_24 = 0;
 271                 ipu->dmfc_size_27 = 128*4;
 272                 ipu->dmfc_size_23 = 128*4;
 273         }
 274         ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
 275         ipu_dmfc_write(ipu, 0x202020F6, DMFC_WR_CHAN_DEF);
 276         ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
 277         /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
 278         ipu_dmfc_write(ipu, 0x2020F6F6, DMFC_DP_CHAN_DEF);
 279 }
 280
 281 static int __init dmfc_setup(char *options)
 282 {
 283         get_option(&options, &dmfc_type_setup);
 284         if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
 285                 dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
 286         return 1;
 287 }
 288 __setup("dmfc=", dmfc_setup);
 289
 290 void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width)
 291 {
 292         u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
 293
 294         if (width >= HIGH_RESOLUTION_WIDTH) {
 295                 if (dma_chan == 23)
 296                         _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
 297                 else if (dma_chan == 28)
 298                         _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DC, 0);
 299         }
 300
 301         if (dma_chan == 23) { /*5B*/
 302                 if (ipu->dmfc_size_23/width > 3)
 303                         dmfc_gen1 |= 1UL << 20;
 304                 else
 305                         dmfc_gen1 &= ~(1UL << 20);
 306         } else if (dma_chan == 24) { /*6B*/
 307                 if (ipu->dmfc_size_24/width > 1)
 308                         dmfc_gen1 |= 1UL << 22;
 309                 else
 310                         dmfc_gen1 &= ~(1UL << 22);
 311         } else if (dma_chan == 27) { /*5F*/
 312                 if (ipu->dmfc_size_27/width > 2)
 313                         dmfc_gen1 |= 1UL << 21;
 314                 else
 315                         dmfc_gen1 &= ~(1UL << 21);
 316         } else if (dma_chan == 28) { /*1*/
 317                 if (ipu->dmfc_size_28/width > 2)
 318                         dmfc_gen1 |= 1UL << 16;
 319                 else
 320                         dmfc_gen1 &= ~(1UL << 16);
 321         } else if (dma_chan == 29) { /*6F*/
 322                 if (ipu->dmfc_size_29/width > 1)
 323                         dmfc_gen1 |= 1UL << 23;
 324                 else
 325                         dmfc_gen1 &= ~(1UL << 23);
 326         }
 327
 328         ipu_dmfc_write(ipu, dmfc_gen1, DMFC_GENERAL1);
 329 }
 330
 331 void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size)
 332 {
 333         u32 dmfc_wr_chan = ipu_dmfc_read(ipu, DMFC_WR_CHAN);
 334         u32 dmfc_dp_chan = ipu_dmfc_read(ipu, DMFC_DP_CHAN);
 335         int dmfc_bs = 0;
 336
 337         switch (burst_size) {
 338         case 64:
 339                 dmfc_bs = 0x40;
 340                 break;
 341         case 32:
 342         case 20:
 343                 dmfc_bs = 0x80;
 344                 break;
 345         case 16:
 346                 dmfc_bs = 0xc0;
 347                 break;
 348         default:
 349                 dev_err(ipu->dev, "Unsupported burst size %d\n",
 350                         burst_size);
 351                 return;
 352         }
 353
 354         if (dma_chan == 23) { /*5B*/
 355                 dmfc_dp_chan &= ~(0xc0);
 356                 dmfc_dp_chan |= dmfc_bs;
 357         } else if (dma_chan == 27) { /*5F*/
 358                 dmfc_dp_chan &= ~(0xc000);
 359                 dmfc_dp_chan |= (dmfc_bs << 8);
 360         } else if (dma_chan == 28) { /*1*/
 361                 dmfc_wr_chan &= ~(0xc0);
 362                 dmfc_wr_chan |= dmfc_bs;
 363         }
 364
 365         ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
 366         ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
 367 }
 368
 369 static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
 370                                 int di, int wave_gen,
 371                                 int access_size, int component_size)
 372 {
 373         u32 reg;
 374         reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
 375             (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
 376         ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
 377 }
 378
 379 static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
 380                         int di, int wave_gen, int di_pin, int set,
 381                         int up, int down)
 382 {
 383         u32 reg;
 384
 385         reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
 386         reg &= ~(0x3 << (di_pin * 2));
 387         reg |= set << (di_pin * 2);
 388         ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
 389
 390         ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
 391 }
 392
 393 static void _ipu_di_sync_config(struct ipu_soc *ipu,
 394                                 int di, int wave_gen,
 395                                 int run_count, int run_src,
 396                                 int offset_count, int offset_src,
 397                                 int repeat_count, int cnt_clr_src,
 398                                 int cnt_polarity_gen_en,
 399                                 int cnt_polarity_clr_src,
 400                                 int cnt_polarity_trigger_src,
 401                                 int cnt_up, int cnt_down)
 402 {
 403         u32 reg;
 404
 405         if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
 406                 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
 407                 dev_err(ipu->dev, "DI%d counters out of range.\n", di);
 408                 return;
 409         }
 410
 411         reg = (run_count << 19) | (++run_src << 16) |
 412             (offset_count << 3) | ++offset_src;
 413         ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
 414         reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
 415             (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
 416         reg |= (cnt_down << 16) | cnt_up;
 417         if (repeat_count == 0) {
 418                 /* Enable auto reload */
 419                 reg |= 0x10000000;
 420         }
 421         ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
 422         reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
 423         reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
 424         reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
 425         ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
 426 }
 427
 428 static void _ipu_dc_map_link(struct ipu_soc *ipu,
 429                 int current_map,
 430                 int base_map_0, int buf_num_0,
 431                 int base_map_1, int buf_num_1,
 432                 int base_map_2, int buf_num_2)
 433 {
 434         int ptr_0 = base_map_0 * 3 + buf_num_0;
 435         int ptr_1 = base_map_1 * 3 + buf_num_1;
 436         int ptr_2 = base_map_2 * 3 + buf_num_2;
 437         int ptr;
 438         u32 reg;
 439         ptr = (ptr_2 << 10) +  (ptr_1 << 5) + ptr_0;
 440
 441         reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(current_map));
 442         reg &= ~(0x1F << ((16 * (current_map & 0x1))));
 443         reg |= ptr << ((16 * (current_map & 0x1)));
 444         ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(current_map));
 445 }
 446
 447 static void _ipu_dc_map_config(struct ipu_soc *ipu,
 448                 int map, int byte_num, int offset, int mask)
 449 {
 450         int ptr = map * 3 + byte_num;
 451         u32 reg;
 452
 453         reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
 454         reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
 455         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 456         ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
 457
 458         reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
 459         reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
 460         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 461         ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
 462 }
 463
 464 static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
 465 {
 466         u32 reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
 467         ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
 468                      DC_MAP_CONF_PTR(map));
 469 }
 470
 471 static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
 472                         int word, u32 opcode, u32 operand, int map,
 473                         int wave, int glue, int sync, int stop)
 474 {
 475         u32 reg;
 476
 477         if (opcode == WRG) {
 478                 reg = sync;
 479                 reg |= (glue << 4);
 480                 reg |= (++wave << 11);
 481                 reg |= ((operand & 0x1FFFF) << 15);
 482                 ipu_dc_tmpl_write(ipu, reg, word * 2);
 483
 484                 reg = (operand >> 17);
 485                 reg |= opcode << 7;
 486                 reg |= (stop << 9);
 487                 ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
 488         } else {
 489                 reg = sync;
 490                 reg |= (glue << 4);
 491                 reg |= (++wave << 11);
 492                 reg |= (++map << 15);
 493                 reg |= (operand << 20) & 0xFFF00000;
 494                 ipu_dc_tmpl_write(ipu, reg, word * 2);
 495
 496                 reg = (operand >> 12);
 497                 reg |= opcode << 4;
 498                 reg |= (stop << 9);
 499                 ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
 500         }
 501 }
 502
 503 static void _ipu_dc_link_event(struct ipu_soc *ipu,
 504                 int chan, int event, int addr, int priority)
 505 {
 506         u32 reg;
 507         u32 address_shift;
 508         if (event < DC_EVEN_UGDE0) {
 509                 reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
 510                 reg &= ~(0xFFFF << (16 * (event & 0x1)));
 511                 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 512                 ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
 513         } else {
 514                 reg = ipu_dc_read(ipu, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
 515                 if ((event - DC_EVEN_UGDE0) & 0x1) {
 516                         reg &= ~(0x2FF << 16);
 517                         reg |= (addr << 16);
 518                         reg |= priority ? (2 << 24) : 0x0;
 519                 } else {
 520                         reg &= ~0xFC00FFFF;
 521                         if (priority)
 522                                 chan = (chan >> 1) +
 523                                         ((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
 524                         else
 525                                 chan = 0x7;
 526                         address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
 527                         reg |= (addr << address_shift) | (priority << 3) | chan;
 528                 }
 529                 ipu_dc_write(ipu, reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
 530         }
 531 }
 532
 533 /*     Y = R *  1.200 + G *  2.343 + B *  .453 + 0.250;
 534        U = R * -.672 + G * -1.328 + B *  2.000 + 512.250.;
 535        V = R *  2.000 + G * -1.672 + B * -.328 + 512.250.;*/
 536 static const int rgb2ycbcr_coeff[5][3] = {
 537         {0x4D, 0x96, 0x1D},
 538         {-0x2B, -0x55, 0x80},
 539         {0x80, -0x6B, -0x15},
 540         {0x0000, 0x0200, 0x0200},       /* B0, B1, B2 */
 541         {0x2, 0x2, 0x2},        /* S0, S1, S2 */
 542 };
 543
 544 /*     R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
 545        G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
 546        B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
 547 static const int ycbcr2rgb_coeff[5][3] = {
 548         {0x095, 0x000, 0x0CC},
 549         {0x095, 0x3CE, 0x398},
 550         {0x095, 0x0FF, 0x000},
 551         {0x3E42, 0x010A, 0x3DD6},       /*B0,B1,B2 */
 552         {0x1, 0x1, 0x1},        /*S0,S1,S2 */
 553 };
 554
 555 #define mask_a(a) ((u32)(a) & 0x3FF)
 556 #define mask_b(b) ((u32)(b) & 0x3FFF)
 557
 558 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
 559 static int _rgb_to_yuv(int n, int red, int green, int blue)
 560 {
 561         int c;
 562         c = red * rgb2ycbcr_coeff[n][0];
 563         c += green * rgb2ycbcr_coeff[n][1];
 564         c += blue * rgb2ycbcr_coeff[n][2];
 565         c /= 16;
 566         c += rgb2ycbcr_coeff[3][n] * 4;
 567         c += 8;
 568         c /= 16;
 569         if (c < 0)
 570                 c = 0;
 571         if (c > 255)
 572                 c = 255;
 573         return c;
 574 }
 575
 576 /*
 577  * Row is for BG:       RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 578  * Column is for FG:    RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
 579  */
 580 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
 581 {{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} },
 582 {{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} },
 583 {{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} },
 584 {{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
 585 {{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }
 586 };
 587
 588 void __ipu_dp_csc_setup(struct ipu_soc *ipu,
 589                 int dp, struct dp_csc_param_t dp_csc_param,
 590                 bool srm_mode_update)
 591 {
 592         u32 reg;
 593         const int (*coeff)[5][3];
 594
 595         if (dp_csc_param.mode >= 0) {
 596                 reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
 597                 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 598                 reg |= dp_csc_param.mode;
 599                 ipu_dp_write(ipu, reg, DP_COM_CONF(dp));
 600         }
 601
 602         coeff = dp_csc_param.coeff;
 603
 604         if (coeff) {
 605                 ipu_dp_write(ipu, mask_a((*coeff)[0][0]) |
 606                                 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
 607                 ipu_dp_write(ipu, mask_a((*coeff)[0][2]) |
 608                                 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
 609                 ipu_dp_write(ipu, mask_a((*coeff)[1][1]) |
 610                                 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
 611                 ipu_dp_write(ipu, mask_a((*coeff)[2][0]) |
 612                                 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
 613                 ipu_dp_write(ipu, mask_a((*coeff)[2][2]) |
 614                                 (mask_b((*coeff)[3][0]) << 16) |
 615                                 ((*coeff)[4][0] << 30), DP_CSC_0(dp));
 616                 ipu_dp_write(ipu, mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
 617                                 (mask_b((*coeff)[3][2]) << 16) |
 618                                 ((*coeff)[4][2] << 30), DP_CSC_1(dp));
 619         }
 620
 621         if (srm_mode_update) {
 622                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
 623                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
 624         }
 625 }
 626
 627 int _ipu_dp_init(struct ipu_soc *ipu,
 628                 ipu_channel_t channel, uint32_t in_pixel_fmt,
 629                 uint32_t out_pixel_fmt)
 630 {
 631         int in_fmt, out_fmt;
 632         int dp;
 633         int partial = false;
 634         uint32_t reg;
 635
 636         if (channel == MEM_FG_SYNC) {
 637                 dp = DP_SYNC;
 638                 partial = true;
 639         } else if (channel == MEM_BG_SYNC) {
 640                 dp = DP_SYNC;
 641                 partial = false;
 642         } else if (channel == MEM_BG_ASYNC0) {
 643                 dp = DP_ASYNC0;
 644                 partial = false;
 645         } else {
 646                 return -EINVAL;
 647         }
 648
 649         in_fmt = format_to_colorspace(in_pixel_fmt);
 650         out_fmt = format_to_colorspace(out_pixel_fmt);
 651
 652         if (partial) {
 653                 if (in_fmt == RGB) {
 654                         if (out_fmt == RGB)
 655                                 ipu->fg_csc_type = RGB2RGB;
 656                         else
 657                                 ipu->fg_csc_type = RGB2YUV;
 658                 } else {
 659                         if (out_fmt == RGB)
 660                                 ipu->fg_csc_type = YUV2RGB;
 661                         else
 662                                 ipu->fg_csc_type = YUV2YUV;
 663                 }
 664         } else {
 665                 if (in_fmt == RGB) {
 666                         if (out_fmt == RGB)
 667                                 ipu->bg_csc_type = RGB2RGB;
 668                         else
 669                                 ipu->bg_csc_type = RGB2YUV;
 670                 } else {
 671                         if (out_fmt == RGB)
 672                                 ipu->bg_csc_type = YUV2RGB;
 673                         else
 674                                 ipu->bg_csc_type = YUV2YUV;
 675                 }
 676         }
 677
 678         /* Transform color key from rgb to yuv if CSC is enabled */
 679         reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
 680         if (ipu->color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
 681                         (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
 682                          ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
 683                          ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
 684                          ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB)))) {
 685                 int red, green, blue;
 686                 int y, u, v;
 687                 uint32_t color_key = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
 688
 689                 dev_dbg(ipu->dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
 690
 691                 red = (color_key >> 16) & 0xFF;
 692                 green = (color_key >> 8) & 0xFF;
 693                 blue = color_key & 0xFF;
 694
 695                 y = _rgb_to_yuv(0, red, green, blue);
 696                 u = _rgb_to_yuv(1, red, green, blue);
 697                 v = _rgb_to_yuv(2, red, green, blue);
 698                 color_key = (y << 16) | (u << 8) | v;
 699
 700                 reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
 701                 ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(dp));
 702                 ipu->color_key_4rgb = false;
 703
 704                 dev_dbg(ipu->dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
 705         }
 706
 707         __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], true);
 708
 709         return 0;
 710 }
 711
 712 void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel)
 713 {
 714         int dp;
 715         int partial = false;
 716
 717         if (channel == MEM_FG_SYNC) {
 718                 dp = DP_SYNC;
 719                 partial = true;
 720         } else if (channel == MEM_BG_SYNC) {
 721                 dp = DP_SYNC;
 722                 partial = false;
 723         } else if (channel == MEM_BG_ASYNC0) {
 724                 dp = DP_ASYNC0;
 725                 partial = false;
 726         } else {
 727                 return;
 728         }
 729
 730         if (partial)
 731                 ipu->fg_csc_type = CSC_NONE;
 732         else
 733                 ipu->bg_csc_type = CSC_NONE;
 734
 735         __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], false);
 736 }
 737
 738 void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
 739 {
 740         u32 reg = 0;
 741
 742         if ((dc_chan == 1) || (dc_chan == 5)) {
 743                 if (interlaced) {
 744                         _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 3);
 745                         _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 2);
 746                         _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 1);
 747                 } else {
 748                         if (di) {
 749                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);
 750                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);
 751                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 4, 1);
 752                                 if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
 753                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
 754                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
 755                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
 756                                         _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
 757                                         _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
 758                                 }
 759                         } else {
 760                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
 761                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
 762                                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 7, 1);
 763                                 if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
 764                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
 765                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
 766                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
 767                                         _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
 768                                         _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
 769                                 }
 770                         }
 771                 }
 772                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
 773                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
 774                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
 775                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
 776                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 777                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 778
 779                 reg = 0x2;
 780                 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 781                 reg |= di << 2;
 782                 if (interlaced)
 783                         reg |= DC_WR_CH_CONF_FIELD_MODE;
 784         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 785                 /* async channels */
 786                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
 787                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
 788
 789                 reg = 0x3;
 790                 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
 791         }
 792         ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 793
 794         ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
 795
 796         ipu_dc_write(ipu, 0x00000084, DC_GEN);
 797 }
 798
 799 void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
 800 {
 801         if ((dc_chan == 1) || (dc_chan == 5)) {
 802                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
 803                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
 804                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
 805                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
 806                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
 807                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
 808                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
 809                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
 810                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
 811                 _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 0, 0);
 812                 _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 0, 0);
 813                 _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 0, 0);
 814                 _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 0, 0);
 815         } else if ((dc_chan == 8) || (dc_chan == 9)) {
 816                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
 817                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
 818                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
 819                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
 820                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
 821                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
 822                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
 823                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
 824                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
 825                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
 826                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
 827                 _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
 828         }
 829 }
 830
 831 int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel)
 832 {
 833         if (channel == MEM_DC_SYNC)
 834                 return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_1) &
 835                           DC_WR_CH_CONF_FIELD_MODE);
 836         else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
 837                 return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_5) &
 838                           DC_WR_CH_CONF_FIELD_MODE);
 839         return 0;
 840 }
 841
 842 void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
 843 {
 844         int di;
 845         uint32_t reg;
 846         uint32_t dc_chan;
 847         int irq = 0;
 848
 849         if (channel == MEM_FG_SYNC)
 850                 irq = IPU_IRQ_DP_SF_END;
 851         else if (channel == MEM_DC_SYNC)
 852                 dc_chan = 1;
 853         else if (channel == MEM_BG_SYNC)
 854                 dc_chan = 5;
 855         else
 856                 return;
 857
 858         if (channel == MEM_FG_SYNC) {
 859                 /* Enable FG channel */
 860                 reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
 861                 ipu_dp_write(ipu, reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
 862
 863                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
 864                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
 865                 return;
 866         }
 867
 868         di = ipu->dc_di_assignment[dc_chan];
 869
 870         /* Make sure other DC sync channel is not assigned same DI */
 871         reg = ipu_dc_read(ipu, DC_WR_CH_CONF(6 - dc_chan));
 872         if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
 873                 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
 874                 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
 875                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
 876         }
 877
 878         reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
 879         reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
 880         ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 881
 882         clk_enable(&ipu->pixel_clk[di]);
 883 }
 884
 885 static irqreturn_t dc_irq_handler(int irq, void *dev_id)
 886 {
 887         struct ipu_soc *ipu = dev_id;
 888         struct completion *comp = &ipu->dc_comp;
 889         uint32_t reg;
 890         uint32_t dc_chan;
 891
 892         if (irq == IPU_IRQ_DC_FC_1)
 893                 dc_chan = 1;
 894         else
 895                 dc_chan = 5;
 896
 897         if (!ipu->dc_swap) {
 898                 reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
 899                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 900                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 901
 902                 reg = ipu_cm_read(ipu, IPU_DISP_GEN);
 903                 if (ipu->dc_di_assignment[dc_chan])
 904                         reg &= ~DI1_COUNTER_RELEASE;
 905                 else
 906                         reg &= ~DI0_COUNTER_RELEASE;
 907                 ipu_cm_write(ipu, reg, IPU_DISP_GEN);
 908         }
 909
 910         complete(comp);
 911         return IRQ_HANDLED;
 912 }
 913
 914 void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap)
 915 {
 916         int ret;
 917         uint32_t reg;
 918         uint32_t csc;
 919         uint32_t dc_chan;
 920         int irq = 0;
 921         int timeout = 50;
 922
 923         ipu->dc_swap = swap;
 924
 925         if (channel == MEM_DC_SYNC) {
 926                 dc_chan = 1;
 927                 irq = IPU_IRQ_DC_FC_1;
 928         } else if (channel == MEM_BG_SYNC) {
 929                 dc_chan = 5;
 930                 irq = IPU_IRQ_DP_SF_END;
 931         } else if (channel == MEM_FG_SYNC) {
 932                 /* Disable FG channel */
 933                 dc_chan = 5;
 934
 935                 reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
 936                 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
 937                 if (csc == DP_COM_CONF_CSC_DEF_FG)
 938                         reg &= ~DP_COM_CONF_CSC_DEF_MASK;
 939
 940                 reg &= ~DP_COM_CONF_FG_EN;
 941                 ipu_dp_write(ipu, reg, DP_COM_CONF(DP_SYNC));
 942
 943                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
 944                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
 945
 946                 if (ipu_is_channel_busy(ipu, MEM_BG_SYNC)) {
 947                         ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
 948                                         IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
 949                         while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
 950                                                 IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
 951                                 msleep(2);
 952                                 timeout -= 2;
 953                                 if (timeout <= 0)
 954                                         break;
 955                         }
 956                 }
 957                 return;
 958         } else {
 959                 return;
 960         }
 961
 962         init_completion(&ipu->dc_comp);
 963         ret = ipu_request_irq(ipu, irq, dc_irq_handler, 0, NULL, ipu);
 964         if (ret < 0) {
 965                 dev_err(ipu->dev, "DC irq %d in use\n", irq);
 966                 return;
 967         }
 968         ret = wait_for_completion_timeout(&ipu->dc_comp, msecs_to_jiffies(50));
 969         ipu_free_irq(ipu, irq, ipu);
 970         dev_dbg(ipu->dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
 971
 972         if (ipu->dc_swap) {
 973                 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
 974                 reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
 975                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
 976                 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 977                 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
 978                 ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
 979         } else
 980                 /* Clock is already off because it must be done quickly, but
 981                    we need to fix the ref count */
 982                 clk_disable(&ipu->pixel_clk[ipu->dc_di_assignment[dc_chan]]);
 983 }
 984
 985 void _ipu_init_dc_mappings(struct ipu_soc *ipu)
 986 {
 987         /* IPU_PIX_FMT_RGB24 */
 988         _ipu_dc_map_clear(ipu, 0);
 989         _ipu_dc_map_config(ipu, 0, 0, 7, 0xFF);
 990         _ipu_dc_map_config(ipu, 0, 1, 15, 0xFF);
 991         _ipu_dc_map_config(ipu, 0, 2, 23, 0xFF);
 992
 993         /* IPU_PIX_FMT_RGB666 */
 994         _ipu_dc_map_clear(ipu, 1);
 995         _ipu_dc_map_config(ipu, 1, 0, 5, 0xFC);
 996         _ipu_dc_map_config(ipu, 1, 1, 11, 0xFC);
 997         _ipu_dc_map_config(ipu, 1, 2, 17, 0xFC);
 998
 999         /* IPU_PIX_FMT_YUV444 */
1000         _ipu_dc_map_clear(ipu, 2);
1001         _ipu_dc_map_config(ipu, 2, 0, 15, 0xFF);
1002         _ipu_dc_map_config(ipu, 2, 1, 23, 0xFF);
1003         _ipu_dc_map_config(ipu, 2, 2, 7, 0xFF);
1004
1005         /* IPU_PIX_FMT_RGB565 */
1006         _ipu_dc_map_clear(ipu, 3);
1007         _ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
1008         _ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
1009         _ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);
1010
1011         /* IPU_PIX_FMT_LVDS666 */
1012         _ipu_dc_map_clear(ipu, 4);
1013         _ipu_dc_map_config(ipu, 4, 0, 5, 0xFC);
1014         _ipu_dc_map_config(ipu, 4, 1, 13, 0xFC);
1015         _ipu_dc_map_config(ipu, 4, 2, 21, 0xFC);
1016
1017         /* IPU_PIX_FMT_VYUY 16bit width */
1018         _ipu_dc_map_clear(ipu, 5);
1019         _ipu_dc_map_config(ipu, 5, 0, 7, 0xFF);
1020         _ipu_dc_map_config(ipu, 5, 1, 0, 0x0);
1021         _ipu_dc_map_config(ipu, 5, 2, 15, 0xFF);
1022         _ipu_dc_map_clear(ipu, 6);
1023         _ipu_dc_map_config(ipu, 6, 0, 0, 0x0);
1024         _ipu_dc_map_config(ipu, 6, 1, 7, 0xFF);
1025         _ipu_dc_map_config(ipu, 6, 2, 15, 0xFF);
1026
1027         /* IPU_PIX_FMT_UYUV 16bit width */
1028         _ipu_dc_map_clear(ipu, 7);
1029         _ipu_dc_map_link(ipu, 7, 6, 0, 6, 1, 6, 2);
1030         _ipu_dc_map_clear(ipu, 8);
1031         _ipu_dc_map_link(ipu, 8, 5, 0, 5, 1, 5, 2);
1032
1033         /* IPU_PIX_FMT_YUYV 16bit width */
1034         _ipu_dc_map_clear(ipu, 9);
1035         _ipu_dc_map_link(ipu, 9, 5, 2, 5, 1, 5, 0);
1036         _ipu_dc_map_clear(ipu, 10);
1037         _ipu_dc_map_link(ipu, 10, 5, 1, 5, 2, 5, 0);
1038
1039         /* IPU_PIX_FMT_YVYU 16bit width */
1040         _ipu_dc_map_clear(ipu, 11);
1041         _ipu_dc_map_link(ipu, 11, 5, 1, 5, 2, 5, 0);
1042         _ipu_dc_map_clear(ipu, 12);
1043         _ipu_dc_map_link(ipu, 12, 5, 2, 5, 1, 5, 0);
1044
1045         /* IPU_PIX_FMT_GBR24 */
1046         /* IPU_PIX_FMT_VYU444 */
1047         _ipu_dc_map_clear(ipu, 13);
1048         _ipu_dc_map_link(ipu, 13, 0, 2, 0, 0, 0, 1);
1049
1050         /* IPU_PIX_FMT_BGR24 */
1051         _ipu_dc_map_clear(ipu, 14);
1052         _ipu_dc_map_link(ipu, 14, 0, 2, 0, 1, 0, 0);
1053 }
1054
1055 int _ipu_pixfmt_to_map(uint32_t fmt)
1056 {
1057         switch (fmt) {
1058         case IPU_PIX_FMT_GENERIC:
1059         case IPU_PIX_FMT_RGB24:
1060                 return 0;
1061         case IPU_PIX_FMT_RGB666:
1062                 return 1;
1063         case IPU_PIX_FMT_YUV444:
1064                 return 2;
1065         case IPU_PIX_FMT_RGB565:
1066                 return 3;
1067         case IPU_PIX_FMT_LVDS666:
1068                 return 4;
1069         case IPU_PIX_FMT_VYUY:
1070                 return 6;
1071         case IPU_PIX_FMT_UYVY:
1072                 return 8;
1073         case IPU_PIX_FMT_YUYV:
1074                 return 10;
1075         case IPU_PIX_FMT_YVYU:
1076                 return 12;
1077         case IPU_PIX_FMT_GBR24:
1078         case IPU_PIX_FMT_VYU444:
1079                 return 13;
1080         case IPU_PIX_FMT_BGR24:
1081                 return 14;
1082         }
1083
1084         return -1;
1085 }
1086
1087 /*!
1088  * This function sets the colorspace for of dp.
1089  * modes.
1090  *
1091  * @param       ipu             ipu handler
1092  * @param       channel         Input parameter for the logical channel ID.
1093  *
1094  * @param       param           If it's not NULL, update the csc table
1095  *                              with this parameter.
1096  *
1097  * @return      N/A
1098  */
1099 void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
1100 {
1101         int dp;
1102         struct dp_csc_param_t dp_csc_param;
1103
1104         if (channel == MEM_FG_SYNC)
1105                 dp = DP_SYNC;
1106         else if (channel == MEM_BG_SYNC)
1107                 dp = DP_SYNC;
1108         else if (channel == MEM_BG_ASYNC0)
1109                 dp = DP_ASYNC0;
1110         else
1111                 return;
1112
1113         dp_csc_param.mode = -1;
1114         dp_csc_param.coeff = param;
1115         __ipu_dp_csc_setup(ipu, dp, dp_csc_param, true);
1116 }
1117
1118 void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
1119 {
1120         _ipu_dp_set_csc_coefficients(ipu, channel, param);
1121 }
1122 EXPORT_SYMBOL(ipu_set_csc_coefficients);
1123
1124 /*!
1125  * This function is called to adapt synchronous LCD panel to IPU restriction.
1126  *
1127  */
1128 void adapt_panel_to_ipu_restricitions(struct ipu_soc *ipu, uint16_t *v_start_width,
1129                                         uint16_t *v_sync_width,
1130                                         uint16_t *v_end_width)
1131 {
1132         if (*v_end_width < 2) {
1133                 uint16_t diff = 2 - *v_end_width;
1134                 if (*v_start_width >= diff) {
1135                         *v_end_width = 2;
1136                         *v_start_width = *v_start_width - diff;
1137                 } else if (*v_sync_width > diff) {
1138                         *v_end_width = 2;
1139                         *v_sync_width = *v_sync_width - diff;
1140                 } else
1141                         dev_err(ipu->dev, "WARNING: try to adapt timming, but failed\n");
1142                 dev_err(ipu->dev, "WARNING: adapt panel end blank lines\n");
1143         }
1144 }
1145
1146 /*!
1147  * This function is called to initialize a synchronous LCD panel.
1148  *
1149  * @param       ipu             ipu handler
1150  * @param       disp            The DI the panel is attached to.
1151  *
1152  * @param       pixel_clk       Desired pixel clock frequency in Hz.
1153  *
1154  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1155  *                              Pixel format is a FOURCC ASCII code.
1156  *
1157  * @param       width           The width of panel in pixels.
1158  *
1159  * @param       height          The height of panel in pixels.
1160  *
1161  * @param       hStartWidth     The number of pixel clocks between the HSYNC
1162  *                              signal pulse and the start of valid data.
1163  *
1164  * @param       hSyncWidth      The width of the HSYNC signal in units of pixel
1165  *                              clocks.
1166  *
1167  * @param       hEndWidth       The number of pixel clocks between the end of
1168  *                              valid data and the HSYNC signal for next line.
1169  *
1170  * @param       vStartWidth     The number of lines between the VSYNC
1171  *                              signal pulse and the start of valid data.
1172  *
1173  * @param       vSyncWidth      The width of the VSYNC signal in units of lines
1174  *
1175  * @param       vEndWidth       The number of lines between the end of valid
1176  *                              data and the VSYNC signal for next frame.
1177  *
1178  * @param       sig             Bitfield of signal polarities for LCD interface.
1179  *
1180  * @return      This function returns 0 on success or negative error code on
1181  *              fail.
1182  */
1183 int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
1184                             uint16_t width, uint16_t height,
1185                             uint32_t pixel_fmt,
1186                             uint16_t h_start_width, uint16_t h_sync_width,
1187                             uint16_t h_end_width, uint16_t v_start_width,
1188                             uint16_t v_sync_width, uint16_t v_end_width,
1189                             uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
1190 {
1191         uint32_t field0_offset = 0;
1192         uint32_t field1_offset;
1193         uint32_t reg;
1194         uint32_t di_gen, vsync_cnt;
1195         uint32_t div, rounded_pixel_clk, rounded_parent_clk;
1196         uint32_t h_total, v_total;
1197         int map;
1198         struct clk *di_parent;
1199
1200         dev_dbg(ipu->dev, "panel size = %d x %d\n", width, height);
1201
1202         if ((v_sync_width == 0) || (h_sync_width == 0))
1203                 return EINVAL;
1204
1205         adapt_panel_to_ipu_restricitions(ipu, &v_start_width, &v_sync_width, &v_end_width);
1206         h_total = width + h_sync_width + h_start_width + h_end_width;
1207         v_total = height + v_sync_width + v_start_width + v_end_width;
1208
1209         /* Init clocking */
1210         dev_dbg(ipu->dev, "pixel clk = %d\n", pixel_clk);
1211
1212         di_parent = clk_get_parent(ipu->di_clk[disp]);
1213         if (clk_get(NULL, "tve_clk") == di_parent ||
1214                 clk_get(NULL, "ldb_di0_clk") == di_parent ||
1215                 clk_get(NULL, "ldb_di1_clk") == di_parent) {
1216                 /* if di clk parent is tve/ldb, then keep it;*/
1217                 dev_dbg(ipu->dev, "use special clk parent\n");
1218                 clk_set_parent(&ipu->pixel_clk[disp], ipu->di_clk[disp]);
1219         } else {
1220                 /* try ipu clk first*/
1221                 dev_dbg(ipu->dev, "try ipu internal clk\n");
1222                 clk_set_parent(&ipu->pixel_clk[disp], ipu->ipu_clk);
1223                 rounded_pixel_clk = clk_round_rate(&ipu->pixel_clk[disp], pixel_clk);
1224                 /*
1225                  * we will only use 1/2 fraction for ipu clk,
1226                  * so if the clk rate is not fit, try ext clk.
1227                  */
1228                 if (!sig.int_clk &&
1229                         ((rounded_pixel_clk >= pixel_clk + pixel_clk/200) ||
1230                         (rounded_pixel_clk <= pixel_clk - pixel_clk/200))) {
1231                         dev_dbg(ipu->dev, "try ipu ext di clk\n");
1232                         if (clk_get_usecount(di_parent))
1233                                 dev_warn(ipu->dev,
1234                                         "ext di clk already in use, go back to internal clk\n");
1235                         else {
1236                                 rounded_pixel_clk = pixel_clk * 2;
1237                                 rounded_parent_clk = clk_round_rate(di_parent,
1238                                                         rounded_pixel_clk);
1239                                 while (rounded_pixel_clk < rounded_parent_clk) {
1240                                         /* the max divider from parent to di is 8 */
1241                                         if (rounded_parent_clk / pixel_clk < 8)
1242                                                 rounded_pixel_clk += pixel_clk * 2;
1243                                         else
1244                                                 rounded_pixel_clk *= 2;
1245                                 }
1246                                 clk_set_rate(di_parent, rounded_pixel_clk);
1247                                 rounded_pixel_clk =
1248                                         clk_round_rate(ipu->di_clk[disp], pixel_clk);
1249                                 clk_set_rate(ipu->di_clk[disp], rounded_pixel_clk);
1250                                 clk_set_parent(&ipu->pixel_clk[disp], ipu->di_clk[disp]);
1251                         }
1252                 }
1253         }
1254         rounded_pixel_clk = clk_round_rate(&ipu->pixel_clk[disp], pixel_clk);
1255         clk_set_rate(&ipu->pixel_clk[disp], rounded_pixel_clk);
1256         msleep(5);
1257         /* Get integer portion of divider */
1258         div = clk_get_rate(clk_get_parent(&ipu->pixel_clk[disp])) / rounded_pixel_clk;
1259
1260         _ipu_lock(ipu);
1261
1262         _ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);
1263         _ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
1264
1265         map = _ipu_pixfmt_to_map(pixel_fmt);
1266         if (map < 0) {
1267                 dev_dbg(ipu->dev, "IPU_DISP: No MAP\n");
1268                 _ipu_unlock(ipu);
1269                 return -EINVAL;
1270         }
1271
1272         /*clear DI*/
1273         di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
1274         ipu_di_write(ipu, disp,
1275                 di_gen & (0x3 << 20), DI_GENERAL);
1276
1277         if (sig.interlaced) {
1278                 if (g_ipu_hw_rev >= 2) {
1279                         /* Setup internal HSYNC waveform */
1280                         _ipu_di_sync_config(ipu,
1281                                         disp,           /* display */
1282                                         1,              /* counter */
1283                                         h_total/2 - 1,  /* run count */
1284                                         DI_SYNC_CLK,    /* run_resolution */
1285                                         0,              /* offset */
1286                                         DI_SYNC_NONE,   /* offset resolution */
1287                                         0,              /* repeat count */
1288                                         DI_SYNC_NONE,   /* CNT_CLR_SEL */
1289                                         0,              /* CNT_POLARITY_GEN_EN */
1290                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1291                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1292                                         0,              /* COUNT UP */
1293                                         0               /* COUNT DOWN */
1294                                         );
1295
1296                         /* Field 1 VSYNC waveform */
1297                         _ipu_di_sync_config(ipu,
1298                                         disp,           /* display */
1299                                         2,              /* counter */
1300                                         h_total - 1,    /* run count */
1301                                         DI_SYNC_CLK,    /* run_resolution */
1302                                         0,              /* offset */
1303                                         DI_SYNC_NONE,   /* offset resolution */
1304                                         0,              /* repeat count */
1305                                         DI_SYNC_NONE,   /* CNT_CLR_SEL */
1306                                         0,              /* CNT_POLARITY_GEN_EN */
1307                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1308                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1309                                         0,              /* COUNT UP */
1310                                         2*div           /* COUNT DOWN */
1311                                         );
1312
1313                         /* Setup internal HSYNC waveform */
1314                         _ipu_di_sync_config(ipu,
1315                                         disp,           /* display */
1316                                         3,              /* counter */
1317                                         v_total*2 - 1,  /* run count */
1318                                         DI_SYNC_INT_HSYNC,      /* run_resolution */
1319                                         1,                      /* offset */
1320                                         DI_SYNC_INT_HSYNC,      /* offset resolution */
1321                                         0,              /* repeat count */
1322                                         DI_SYNC_NONE,   /* CNT_CLR_SEL */
1323                                         0,              /* CNT_POLARITY_GEN_EN */
1324                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1325                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1326                                         0,              /* COUNT UP */
1327                                         2*div           /* COUNT DOWN */
1328                                         );
1329
1330                         /* Active Field ? */
1331                         _ipu_di_sync_config(ipu,
1332                                         disp,           /* display */
1333                                         4,              /* counter */
1334                                         v_total/2 - 1,  /* run count */
1335                                         DI_SYNC_HSYNC,  /* run_resolution */
1336                                         v_start_width,  /*  offset */
1337                                         DI_SYNC_HSYNC,  /* offset resolution */
1338                                         2,              /* repeat count */
1339                                         DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1340                                         0,              /* CNT_POLARITY_GEN_EN */
1341                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1342                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1343                                         0,              /* COUNT UP */
1344                                         0               /* COUNT DOWN */
1345                                         );
1346
1347                         /* Active Line */
1348                         _ipu_di_sync_config(ipu,
1349                                         disp,           /* display */
1350                                         5,              /* counter */
1351                                         0,              /* run count */
1352                                         DI_SYNC_HSYNC,  /* run_resolution */
1353                                         0,              /*  offset */
1354                                         DI_SYNC_NONE,   /* offset resolution */
1355                                         height/2,       /* repeat count */
1356                                         4,              /* CNT_CLR_SEL */
1357                                         0,              /* CNT_POLARITY_GEN_EN */
1358                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1359                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1360                                         0,              /* COUNT UP */
1361                                         0               /* COUNT DOWN */
1362                                         );
1363
1364                         /* Field 0 VSYNC waveform */
1365                         _ipu_di_sync_config(ipu,
1366                                         disp,           /* display */
1367                                         6,              /* counter */
1368                                         v_total - 1,    /* run count */
1369                                         DI_SYNC_HSYNC,  /* run_resolution */
1370                                         0,              /* offset */
1371                                         DI_SYNC_NONE,   /* offset resolution */
1372                                         0,              /* repeat count */
1373                                         DI_SYNC_NONE,   /* CNT_CLR_SEL  */
1374                                         0,              /* CNT_POLARITY_GEN_EN */
1375                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1376                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1377                                         0,              /* COUNT UP */
1378                                         0               /* COUNT DOWN */
1379                                         );
1380
1381                         /* DC VSYNC waveform */
1382                         vsync_cnt = 7;
1383                         _ipu_di_sync_config(ipu,
1384                                         disp,           /* display */
1385                                         7,              /* counter */
1386                                         v_total/2 - 1,  /* run count */
1387                                         DI_SYNC_HSYNC,  /* run_resolution  */
1388                                         9,              /* offset  */
1389                                         DI_SYNC_HSYNC,  /* offset resolution */
1390                                         2,              /* repeat count */
1391                                         DI_SYNC_VSYNC,  /* CNT_CLR_SEL */
1392                                         0,              /* CNT_POLARITY_GEN_EN */
1393                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1394                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1395                                         0,              /* COUNT UP */
1396                                         0               /* COUNT DOWN */
1397                                         );
1398
1399                         /* active pixel waveform */
1400                         _ipu_di_sync_config(ipu,
1401                                         disp,           /* display */
1402                                         8,              /* counter */
1403                                         0,              /* run count  */
1404                                         DI_SYNC_CLK,    /* run_resolution */
1405                                         h_start_width,  /* offset  */
1406                                         DI_SYNC_CLK,    /* offset resolution */
1407                                         width,          /* repeat count  */
1408                                         5,              /* CNT_CLR_SEL  */
1409                                         0,              /* CNT_POLARITY_GEN_EN  */
1410                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL */
1411                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL  */
1412                                         0,              /* COUNT UP  */
1413                                         0               /* COUNT DOWN */
1414                                         );
1415
1416                         /* Second VSYNC */
1417                         _ipu_di_sync_config(ipu,
1418                                         disp,           /* display */
1419                                         9,              /* counter */
1420                                         v_total - 1,    /* run count */
1421                                         DI_SYNC_INT_HSYNC,      /* run_resolution */
1422                                         v_total/2,              /* offset  */
1423                                         DI_SYNC_INT_HSYNC,      /* offset resolution  */
1424                                         0,              /* repeat count */
1425                                         DI_SYNC_HSYNC,  /* CNT_CLR_SEL */
1426                                         0,              /* CNT_POLARITY_GEN_EN  */
1427                                         DI_SYNC_NONE,   /* CNT_POLARITY_CLR_SEL  */
1428                                         DI_SYNC_NONE,   /* CNT_POLARITY_TRIGGER_SEL */
1429                                         0,              /* COUNT UP */
1430                                         2*div           /* COUNT DOWN */
1431                                         );
1432
1433                         /* set gentime select and tag sel */
1434                         reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
1435                         reg &= 0x1FFFFFFF;
1436                         reg |= (3-1)<<29 | 0x00008000;
1437                         ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
1438
1439                         ipu_di_write(ipu, disp, v_total / 2 - 1, DI_SCR_CONF);
1440
1441                         /* set y_sel = 1 */
1442                         di_gen |= 0x10000000;
1443                         di_gen |= DI_GEN_POLARITY_5;
1444                         di_gen |= DI_GEN_POLARITY_8;
1445                 } else {
1446                         /* Setup internal HSYNC waveform */
1447                         _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
1448                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1449                                         DI_SYNC_NONE, 0, 0);
1450
1451                         field1_offset = v_sync_width + v_start_width + height / 2 +
1452                                 v_end_width;
1453                         if (sig.odd_field_first) {
1454                                 field0_offset = field1_offset - 1;
1455                                 field1_offset = 0;
1456                         }
1457                         v_total += v_start_width + v_end_width;
1458
1459                         /* Field 1 VSYNC waveform */
1460                         _ipu_di_sync_config(ipu, disp, 2, v_total - 1, 1,
1461                                         field0_offset,
1462                                         field0_offset ? 1 : DI_SYNC_NONE,
1463                                         0, DI_SYNC_NONE, 0,
1464                                         DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
1465
1466                         /* Setup internal HSYNC waveform */
1467                         _ipu_di_sync_config(ipu, disp, 3, h_total - 1, DI_SYNC_CLK,
1468                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,
1469                                         DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
1470
1471                         /* Active Field ? */
1472                         _ipu_di_sync_config(ipu, disp, 4,
1473                                         field0_offset ?
1474                                         field0_offset : field1_offset - 2,
1475                                         1, v_start_width + v_sync_width, 1, 2, 2,
1476                                         0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
1477
1478                         /* Active Line */
1479                         _ipu_di_sync_config(ipu, disp, 5, 0, 1,
1480                                         0, DI_SYNC_NONE,
1481                                         height / 2, 4, 0, DI_SYNC_NONE,
1482                                         DI_SYNC_NONE, 0, 0);
1483
1484                         /* Field 0 VSYNC waveform */
1485                         _ipu_di_sync_config(ipu, disp, 6, v_total - 1, 1,
1486                                         0, DI_SYNC_NONE,
1487                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1488                                         DI_SYNC_NONE, 0, 0);
1489
1490                         /* DC VSYNC waveform */
1491                         vsync_cnt = 7;
1492                         _ipu_di_sync_config(ipu, disp, 7, 0, 1,
1493                                         field1_offset,
1494                                         field1_offset ? 1 : DI_SYNC_NONE,
1495                                         1, 2, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
1496
1497                         /* active pixel waveform */
1498                         _ipu_di_sync_config(ipu, disp, 8, 0, DI_SYNC_CLK,
1499                                         h_sync_width + h_start_width, DI_SYNC_CLK,
1500                                         width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE,
1501                                         0, 0);
1502
1503                         /* ??? */
1504                         _ipu_di_sync_config(ipu, disp, 9, v_total - 1, 2,
1505                                         0, DI_SYNC_NONE,
1506                                         0, DI_SYNC_NONE, 6, DI_SYNC_NONE,
1507                                         DI_SYNC_NONE, 0, 0);
1508
1509                         reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
1510                         reg |= 0x8000;
1511                         ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
1512
1513                         ipu_di_write(ipu, disp, v_sync_width + v_start_width +
1514                                         v_end_width + height / 2 - 1, DI_SCR_CONF);
1515                 }
1516
1517                 /* Init template microcode */
1518                 _ipu_dc_write_tmpl(ipu, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
1519
1520                 if (sig.Hsync_pol)
1521                         di_gen |= DI_GEN_POLARITY_3;
1522                 if (sig.Vsync_pol)
1523                         di_gen |= DI_GEN_POLARITY_2;
1524         } else {
1525                 /* Setup internal HSYNC waveform */
1526                 _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
1527                                         0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1528                                         DI_SYNC_NONE, 0, 0);
1529
1530                 /* Setup external (delayed) HSYNC waveform */
1531                 _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,
1532                                     DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1533                                     0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1534                                     DI_SYNC_CLK, 0, h_sync_width * 2);
1535                 /* Setup VSYNC waveform */
1536                 vsync_cnt = DI_SYNC_VSYNC;
1537                 _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,
1538                                     DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1539                                     DI_SYNC_NONE, 1, DI_SYNC_NONE,
1540                                     DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1541                 ipu_di_write(ipu, disp, v_total - 1, DI_SCR_CONF);
1542
1543                 /* Setup active data waveform to sync with DC */
1544                 _ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC,
1545                                     v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
1546                                     DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1547                                     DI_SYNC_NONE, 0, 0);
1548                 _ipu_di_sync_config(ipu, disp, 5, 0, DI_SYNC_CLK,
1549                                     h_sync_width + h_start_width, DI_SYNC_CLK,
1550                                     width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1551                                     0);
1552
1553                 /* set VGA delayed hsync/vsync no matter VGA enabled */
1554                 if (disp) {
1555                         /* couter 7 for VGA delay HSYNC */
1556                         _ipu_di_sync_config(ipu, disp, 7,
1557                                         h_total - 1, DI_SYNC_CLK,
1558                                         18, DI_SYNC_CLK,
1559                                         0, DI_SYNC_NONE,
1560                                         1, DI_SYNC_NONE, DI_SYNC_CLK,
1561                                         0, h_sync_width * 2);
1562
1563                         /* couter 8 for VGA delay VSYNC */
1564                         _ipu_di_sync_config(ipu, disp, 8,
1565                                         v_total - 1, DI_SYNC_INT_HSYNC,
1566                                         1, DI_SYNC_INT_HSYNC,
1567                                         0, DI_SYNC_NONE,
1568                                         1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,
1569                                         0, v_sync_width * 2);
1570                 }
1571
1572                 /* reset all unused counters */
1573                 ipu_di_write(ipu, disp, 0, DI_SW_GEN0(6));
1574                 ipu_di_write(ipu, disp, 0, DI_SW_GEN1(6));
1575                 if (!disp) {
1576                         ipu_di_write(ipu, disp, 0, DI_SW_GEN0(7));
1577                         ipu_di_write(ipu, disp, 0, DI_SW_GEN1(7));
1578                         ipu_di_write(ipu, disp, 0, DI_STP_REP(7));
1579                         ipu_di_write(ipu, disp, 0, DI_SW_GEN0(8));
1580                         ipu_di_write(ipu, disp, 0, DI_SW_GEN1(8));
1581                         ipu_di_write(ipu, disp, 0, DI_STP_REP(8));
1582                 }
1583                 ipu_di_write(ipu, disp, 0, DI_SW_GEN0(9));
1584                 ipu_di_write(ipu, disp, 0, DI_SW_GEN1(9));
1585                 ipu_di_write(ipu, disp, 0, DI_STP_REP(9));
1586
1587                 reg = ipu_di_read(ipu, disp, DI_STP_REP(6));
1588                 reg &= 0x0000FFFF;
1589                 ipu_di_write(ipu, disp, reg, DI_STP_REP(6));
1590
1591                 /* Init template microcode */
1592                 if (disp) {
1593                         if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
1594                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
1595                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
1596                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
1597                                 _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
1598                                 _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1599                                 /* configure user events according to DISP NUM */
1600                                 ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
1601                         }
1602                         _ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
1603                         _ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
1604                         _ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1605                 } else {
1606                         if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
1607                                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
1608                                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
1609                                 (pixel_fmt == IPU_PIX_FMT_VYUY)) {
1610                                 _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
1611                                 _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1612                                 /* configure user events according to DISP NUM */
1613                                 ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
1614                         }
1615                    _ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
1616                    _ipu_dc_write_tmpl(ipu, 6, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
1617                    _ipu_dc_write_tmpl(ipu, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
1618                 }
1619
1620                 if (sig.Hsync_pol) {
1621                         di_gen |= DI_GEN_POLARITY_2;
1622                         if (disp)
1623                                 di_gen |= DI_GEN_POLARITY_7;
1624                 }
1625                 if (sig.Vsync_pol) {
1626                         di_gen |= DI_GEN_POLARITY_3;
1627                         if (disp)
1628                                 di_gen |= DI_GEN_POLARITY_8;
1629                 }
1630         }
1631         /* changinc DISP_CLK polarity: it can be wrong for some applications */
1632         if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
1633                 (pixel_fmt == IPU_PIX_FMT_UYVY) ||
1634                 (pixel_fmt == IPU_PIX_FMT_YVYU) ||
1635                 (pixel_fmt == IPU_PIX_FMT_VYUY))
1636                         di_gen |= 0x00020000;
1637
1638         if (!sig.clk_pol)
1639                 di_gen |= DI_GEN_POLARITY_DISP_CLK;
1640
1641         ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
1642
1643         ipu_di_write(ipu, disp, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1644                         0x00000002, DI_SYNC_AS_GEN);
1645         reg = ipu_di_read(ipu, disp, DI_POL);
1646         reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1647         if (sig.enable_pol)
1648                 reg |= DI_POL_DRDY_POLARITY_15;
1649         if (sig.data_pol)
1650                 reg |= DI_POL_DRDY_DATA_POLARITY;
1651         ipu_di_write(ipu, disp, reg, DI_POL);
1652
1653         ipu_dc_write(ipu, width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1654
1655         _ipu_unlock(ipu);
1656
1657         return 0;
1658 }
1659 EXPORT_SYMBOL(ipu_init_sync_panel);
1660
1661 void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp)
1662 {
1663         uint32_t reg;
1664         uint32_t di_gen;
1665
1666         if ((disp != 0) || (disp != 1))
1667                 return;
1668
1669         _ipu_lock(ipu);
1670
1671         di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
1672         di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
1673         ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
1674
1675         reg = ipu_di_read(ipu, disp, DI_POL);
1676         reg |= 0x3ffffff;
1677         ipu_di_write(ipu, disp, reg, DI_POL);
1678
1679         _ipu_unlock(ipu);
1680 }
1681 EXPORT_SYMBOL(ipu_uninit_sync_panel);
1682
1683 int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
1684                          uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
1685 {
1686         int map;
1687         u32 ser_conf = 0;
1688         u32 div;
1689         u32 di_clk = clk_get_rate(ipu->ipu_clk);
1690
1691         /* round up cycle_time, then calcalate the divider using scaled math */
1692         cycle_time += (1000000000UL / di_clk) - 1;
1693         div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);
1694
1695         map = _ipu_pixfmt_to_map(pixel_fmt);
1696         if (map < 0)
1697                 return -EINVAL;
1698
1699         _ipu_lock(ipu);
1700
1701         if (type == IPU_PANEL_SERIAL) {
1702                 ipu_di_write(ipu, disp, (div << 24) | ((sig.ifc_width - 1) << 4),
1703                              DI_DW_GEN(ASYNC_SER_WAVE));
1704
1705                 _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_CS,
1706                                         0, 0, (div * 2) + 1);
1707                 _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK,
1708                                         1, div, div * 2);
1709                 _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_RS,
1710                                         2, 0, 0);
1711
1712                 _ipu_dc_write_tmpl(ipu, 0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0, 1);
1713
1714                 /* Configure DC for serial panel */
1715                 ipu_dc_write(ipu, 0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL));
1716
1717                 if (sig.clk_pol)
1718                         ser_conf |= DI_SER_CONF_SERIAL_CLK_POL;
1719                 if (sig.data_pol)
1720                         ser_conf |= DI_SER_CONF_SERIAL_DATA_POL;
1721                 if (sig.rs_pol)
1722                         ser_conf |= DI_SER_CONF_SERIAL_RS_POL;
1723                 if (sig.cs_pol)
1724                         ser_conf |= DI_SER_CONF_SERIAL_CS_POL;
1725                 ipu_di_write(ipu, disp, ser_conf, DI_SER_CONF);
1726         }
1727
1728         _ipu_unlock(ipu);
1729         return 0;
1730 }
1731 EXPORT_SYMBOL(ipu_init_async_panel);
1732
1733 /*!
1734  * This function sets the foreground and background plane global alpha blending
1735  * modes. This function also sets the DP graphic plane according to the
1736  * parameter of IPUv3 DP channel.
1737  *
1738  * @param       ipu             ipu handler
1739  * @param       channel         IPUv3 DP channel
1740  *
1741  * @param       enable          Boolean to enable or disable global alpha
1742  *                              blending. If disabled, local blending is used.
1743  *
1744  * @param       alpha           Global alpha value.
1745  *
1746  * @return      Returns 0 on success or negative error code on fail
1747  */
1748 int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel,
1749                                 bool enable, uint8_t alpha)
1750 {
1751         uint32_t reg;
1752         uint32_t flow;
1753         bool bg_chan;
1754
1755         if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1756                 flow = DP_SYNC;
1757         else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1758                 flow = DP_ASYNC0;
1759         else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1760                 flow = DP_ASYNC1;
1761         else
1762                 return -EINVAL;
1763
1764         if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1765             channel == MEM_BG_ASYNC1)
1766                 bg_chan = true;
1767         else
1768                 bg_chan = false;
1769
1770         _ipu_get(ipu);
1771
1772         _ipu_lock(ipu);
1773
1774         if (bg_chan) {
1775                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1776                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
1777         } else {
1778                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1779                 ipu_dp_write(ipu, reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
1780         }
1781
1782         if (enable) {
1783                 reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
1784                 ipu_dp_write(ipu, reg | ((uint32_t) alpha << 24),
1785                              DP_GRAPH_WIND_CTRL(flow));
1786
1787                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1788                 ipu_dp_write(ipu, reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
1789         } else {
1790                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1791                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
1792         }
1793
1794         reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
1795         ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1796
1797         _ipu_unlock(ipu);
1798
1799         _ipu_put(ipu);
1800
1801         return 0;
1802 }
1803 EXPORT_SYMBOL(ipu_disp_set_global_alpha);
1804
1805 /*!
1806  * This function sets the transparent color key for SDC graphic plane.
1807  *
1808  * @param       ipu             ipu handler
1809  * @param       channel         Input parameter for the logical channel ID.
1810  *
1811  * @param       enable          Boolean to enable or disable color key
1812  *
1813  * @param       colorKey        24-bit RGB color for transparent color key.
1814  *
1815  * @return      Returns 0 on success or negative error code on fail
1816  */
1817 int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel,
1818                                 bool enable, uint32_t color_key)
1819 {
1820         uint32_t reg, flow;
1821         int y, u, v;
1822         int red, green, blue;
1823
1824         if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1825                 flow = DP_SYNC;
1826         else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1827                 flow = DP_ASYNC0;
1828         else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1829                 flow = DP_ASYNC1;
1830         else
1831                 return -EINVAL;
1832
1833         _ipu_get(ipu);
1834
1835         _ipu_lock(ipu);
1836
1837         ipu->color_key_4rgb = true;
1838         /* Transform color key from rgb to yuv if CSC is enabled */
1839         if (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
1840                         ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
1841                         ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
1842                         ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB))) {
1843
1844                 dev_dbg(ipu->dev, "color key 0x%x need change to yuv fmt\n", color_key);
1845
1846                 red = (color_key >> 16) & 0xFF;
1847                 green = (color_key >> 8) & 0xFF;
1848                 blue = color_key & 0xFF;
1849
1850                 y = _rgb_to_yuv(0, red, green, blue);
1851                 u = _rgb_to_yuv(1, red, green, blue);
1852                 v = _rgb_to_yuv(2, red, green, blue);
1853                 color_key = (y << 16) | (u << 8) | v;
1854
1855                 ipu->color_key_4rgb = false;
1856
1857                 dev_dbg(ipu->dev, "color key change to yuv fmt 0x%x\n", color_key);
1858         }
1859
1860         if (enable) {
1861                 reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
1862                 ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(flow));
1863
1864                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1865                 ipu_dp_write(ipu, reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
1866         } else {
1867                 reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1868                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
1869         }
1870
1871         reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
1872         ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1873
1874         _ipu_unlock(ipu);
1875
1876         _ipu_put(ipu);
1877
1878         return 0;
1879 }
1880 EXPORT_SYMBOL(ipu_disp_set_color_key);
1881
1882 /*!
1883  * This function sets the gamma correction for DP output.
1884  *
1885  * @param       ipu             ipu handler
1886  * @param       channel         Input parameter for the logical channel ID.
1887  *
1888  * @param       enable          Boolean to enable or disable gamma correction.
1889  *
1890  * @param       constk          Gamma piecewise linear approximation constk coeff.
1891  *
1892  * @param       slopek          Gamma piecewise linear approximation slopek coeff.
1893  *
1894  * @return      Returns 0 on success or negative error code on fail
1895  */
1896 int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, int constk[], int slopek[])
1897 {
1898         uint32_t reg, flow, i;
1899
1900         if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
1901                 flow = DP_SYNC;
1902         else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
1903                 flow = DP_ASYNC0;
1904         else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
1905                 flow = DP_ASYNC1;
1906         else
1907                 return -EINVAL;
1908
1909         _ipu_get(ipu);
1910
1911         _ipu_lock(ipu);
1912
1913         for (i = 0; i < 8; i++)
1914                 ipu_dp_write(ipu, (constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i));
1915         for (i = 0; i < 4; i++)
1916                 ipu_dp_write(ipu, (slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) |
1917                         ((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i));
1918
1919         reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
1920         if (enable) {
1921                 if ((ipu->bg_csc_type == RGB2YUV) || (ipu->bg_csc_type == YUV2YUV))
1922                         reg |= DP_COM_CONF_GAMMA_YUV_EN;
1923                 else
1924                         reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
1925                 ipu_dp_write(ipu, reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
1926         } else
1927                 ipu_dp_write(ipu, reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
1928
1929         reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
1930         ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1931
1932         _ipu_unlock(ipu);
1933
1934         _ipu_put(ipu);
1935
1936         return 0;
1937 }
1938 EXPORT_SYMBOL(ipu_disp_set_gamma_correction);
1939
1940 /*!
1941  * This function sets the window position of the foreground or background plane.
1942  * modes.
1943  *
1944  * @param       ipu             ipu handler
1945  * @param       channel         Input parameter for the logical channel ID.
1946  *
1947  * @param       x_pos           The X coordinate position to place window at.
1948  *                              The position is relative to the top left corner.
1949  *
1950  * @param       y_pos           The Y coordinate position to place window at.
1951  *                              The position is relative to the top left corner.
1952  *
1953  * @return      Returns 0 on success or negative error code on fail
1954  */
1955 int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
1956                                 int16_t x_pos, int16_t y_pos)
1957 {
1958         u32 reg;
1959         uint32_t flow = 0;
1960         uint32_t dp_srm_shift;
1961
1962         if ((channel == MEM_FG_SYNC) || (channel == MEM_BG_SYNC)) {
1963                 flow = DP_SYNC;
1964                 dp_srm_shift = 3;
1965         } else if (channel == MEM_FG_ASYNC0) {
1966                 flow = DP_ASYNC0;
1967                 dp_srm_shift = 5;
1968         } else if (channel == MEM_FG_ASYNC1) {
1969                 flow = DP_ASYNC1;
1970                 dp_srm_shift = 7;
1971         } else
1972                 return -EINVAL;
1973
1974         ipu_dp_write(ipu, (x_pos << 16) | y_pos, DP_FG_POS(flow));
1975
1976         if (ipu_is_channel_busy(ipu, channel)) {
1977                 /* controled by FSU if channel enabled */
1978                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
1979                 reg |= (0x1 << dp_srm_shift);
1980                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1981         } else {
1982                 /* disable auto swap, controled by MCU if channel disabled */
1983                 reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
1984                 ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
1985         }
1986
1987         return 0;
1988 }
1989
1990 int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
1991                                 int16_t x_pos, int16_t y_pos)
1992 {
1993         int ret;
1994
1995         _ipu_get(ipu);
1996         _ipu_lock(ipu);
1997         ret = _ipu_disp_set_window_pos(ipu, channel, x_pos, y_pos);
1998         _ipu_unlock(ipu);
1999         _ipu_put(ipu);
2000         return ret;
2001 }
2002 EXPORT_SYMBOL(ipu_disp_set_window_pos);
2003
2004 int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
2005                                 int16_t *x_pos, int16_t *y_pos)
2006 {
2007         u32 reg;
2008         uint32_t flow = 0;
2009
2010         if (channel == MEM_FG_SYNC)
2011                 flow = DP_SYNC;
2012         else if (channel == MEM_FG_ASYNC0)
2013                 flow = DP_ASYNC0;
2014         else if (channel == MEM_FG_ASYNC1)
2015                 flow = DP_ASYNC1;
2016         else
2017                 return -EINVAL;
2018
2019         reg = ipu_dp_read(ipu, DP_FG_POS(flow));
2020
2021         *x_pos = (reg >> 16) & 0x7FF;
2022         *y_pos = reg & 0x7FF;
2023
2024         return 0;
2025 }
2026 int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
2027                                 int16_t *x_pos, int16_t *y_pos)
2028 {
2029         int ret;
2030
2031         _ipu_get(ipu);
2032         _ipu_lock(ipu);
2033         ret = _ipu_disp_get_window_pos(ipu, channel, x_pos, y_pos);
2034         _ipu_unlock(ipu);
2035         _ipu_put(ipu);
2036         return ret;
2037 }
2038 EXPORT_SYMBOL(ipu_disp_get_window_pos);
2039
2040 void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset)
2041 {
2042         if (channel == DIRECT_ASYNC0)
2043                 writel(value, ipu->disp_base[0] + offset);
2044         else if (channel == DIRECT_ASYNC1)
2045                 writel(value, ipu->disp_base[1] + offset);
2046 }
2047 EXPORT_SYMBOL(ipu_disp_direct_write);
2048
2049 void ipu_reset_disp_panel(struct ipu_soc *ipu)
2050 {
2051         uint32_t tmp;
2052
2053         tmp = ipu_di_read(ipu, 1, DI_GENERAL);
2054         ipu_di_write(ipu, 1, tmp | 0x08, DI_GENERAL);
2055         msleep(10); /* tRES >= 100us */
2056         tmp = ipu_di_read(ipu, 1, DI_GENERAL);
2057         ipu_di_write(ipu, 1, tmp & ~0x08, DI_GENERAL);
2058         msleep(60);
2059
2060         return;
2061 }
2062 EXPORT_SYMBOL(ipu_reset_disp_panel);
2063
2064 void __devinit ipu_disp_init(struct ipu_soc *ipu)
2065 {
2066         ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
2067         ipu->color_key_4rgb = true;
2068         _ipu_init_dc_mappings(ipu);
2069         _ipu_dmfc_init(ipu, DMFC_NORMAL, 1);
2070 }