2 * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
13 #ifndef __INCLUDE_IPU_PRV_H__
14 #define __INCLUDE_IPU_PRV_H__
16 #include <linux/clkdev.h>
17 #include <linux/device.h>
18 #include <linux/fsl_devices.h>
19 #include <linux/interrupt.h>
20 #include <linux/types.h>
22 #define MXC_IPU_MAX_NUM 2
23 #define MXC_DI_NUM_PER_IPU 2
26 extern int dmfc_type_setup;
28 #define IDMA_CHAN_INVALID 0xFF
29 #define HIGH_RESOLUTION_WIDTH 1024
32 irqreturn_t(*handler) (int, void *); /*!< the ISR */
33 const char *name; /*!< device associated with the interrupt */
34 void *dev_id; /*!< some unique information for the ISR */
35 __u32 flags; /*!< not used */
51 struct ipu_pltfm_data {
58 * Bypass reset to avoid display channel being
59 * stopped by probe since it may starts to work
67 struct ipu_pltfm_data *pdata;
71 struct clk *di_clk[2];
72 struct clk *di_clk_sel[2];
73 struct clk *pixel_clk[2];
74 struct clk *pixel_clk_sel[2];
75 struct clk *csi_clk[2];
80 struct ipu_irq_node irq_list[IPU_IRQ_COUNT];
100 ipu_channel_t csi_channel[2];
101 ipu_channel_t using_ic_dirct_ch;
102 unsigned char dc_di_assignment[10];
103 bool sec_chan_en[24];
104 bool thrd_chan_en[24];
105 bool chan_is_interlaced[52];
106 uint32_t channel_init_mask;
107 uint32_t channel_enable_mask;
118 int csi_use_count[2];
120 struct mutex mutex_lock;
121 spinlock_t int_reg_spin_lock;
122 spinlock_t rdy_reg_spin_lock;
130 enum csc_type_t fg_csc_type;
131 enum csc_type_t bg_csc_type;
134 struct completion dc_comp;
135 struct completion csi_comp;
144 struct task_struct *thread[2];
157 DMFC_HIGH_RESOLUTION_DC,
158 DMFC_HIGH_RESOLUTION_DP,
159 DMFC_HIGH_RESOLUTION_ONLY_DP,
162 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
164 return readl(ipu->cm_reg + offset);
167 static inline void ipu_cm_write(struct ipu_soc *ipu,
168 u32 value, unsigned offset)
170 writel(value, ipu->cm_reg + offset);
173 static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
175 return readl(ipu->idmac_reg + offset);
178 static inline void ipu_idmac_write(struct ipu_soc *ipu,
179 u32 value, unsigned offset)
181 writel(value, ipu->idmac_reg + offset);
184 static inline u32 ipu_dc_read(struct ipu_soc *ipu, unsigned offset)
186 return readl(ipu->dc_reg + offset);
189 static inline void ipu_dc_write(struct ipu_soc *ipu,
190 u32 value, unsigned offset)
192 writel(value, ipu->dc_reg + offset);
195 static inline u32 ipu_dc_tmpl_read(struct ipu_soc *ipu, unsigned offset)
197 return readl(ipu->dc_tmpl_reg + offset);
200 static inline void ipu_dc_tmpl_write(struct ipu_soc *ipu,
201 u32 value, unsigned offset)
203 writel(value, ipu->dc_tmpl_reg + offset);
206 static inline u32 ipu_dmfc_read(struct ipu_soc *ipu, unsigned offset)
208 return readl(ipu->dmfc_reg + offset);
211 static inline void ipu_dmfc_write(struct ipu_soc *ipu,
212 u32 value, unsigned offset)
214 writel(value, ipu->dmfc_reg + offset);
217 static inline u32 ipu_dp_read(struct ipu_soc *ipu, unsigned offset)
219 return readl(ipu->dp_reg + offset);
222 static inline void ipu_dp_write(struct ipu_soc *ipu,
223 u32 value, unsigned offset)
225 writel(value, ipu->dp_reg + offset);
228 static inline u32 ipu_di_read(struct ipu_soc *ipu, int di, unsigned offset)
230 return readl(ipu->di_reg[di] + offset);
233 static inline void ipu_di_write(struct ipu_soc *ipu, int di,
234 u32 value, unsigned offset)
236 writel(value, ipu->di_reg[di] + offset);
239 static inline u32 ipu_csi_read(struct ipu_soc *ipu, int csi, unsigned offset)
241 return readl(ipu->csi_reg[csi] + offset);
244 static inline void ipu_csi_write(struct ipu_soc *ipu, int csi,
245 u32 value, unsigned offset)
247 writel(value, ipu->csi_reg[csi] + offset);
250 static inline u32 ipu_smfc_read(struct ipu_soc *ipu, unsigned offset)
252 return readl(ipu->smfc_reg + offset);
255 static inline void ipu_smfc_write(struct ipu_soc *ipu,
256 u32 value, unsigned offset)
258 writel(value, ipu->smfc_reg + offset);
261 static inline u32 ipu_vdi_read(struct ipu_soc *ipu, unsigned offset)
263 return readl(ipu->vdi_reg + offset);
266 static inline void ipu_vdi_write(struct ipu_soc *ipu,
267 u32 value, unsigned offset)
269 writel(value, ipu->vdi_reg + offset);
272 static inline u32 ipu_ic_read(struct ipu_soc *ipu, unsigned offset)
274 return readl(ipu->ic_reg + offset);
277 static inline void ipu_ic_write(struct ipu_soc *ipu,
278 u32 value, unsigned offset)
280 writel(value, ipu->ic_reg + offset);
283 int register_ipu_device(struct ipu_soc *ipu, int id);
284 void unregister_ipu_device(struct ipu_soc *ipu, int id);
285 ipu_color_space_t format_to_colorspace(uint32_t fmt);
286 bool ipu_pixel_format_has_alpha(uint32_t fmt);
288 void ipu_dump_registers(struct ipu_soc *ipu);
290 uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
292 void ipu_disp_init(struct ipu_soc *ipu);
293 void _ipu_init_dc_mappings(struct ipu_soc *ipu);
294 int _ipu_dp_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t in_pixel_fmt,
295 uint32_t out_pixel_fmt);
296 void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel);
297 void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
298 void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan);
299 void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel);
300 void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap);
301 void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first);
302 void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width);
303 void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size);
304 int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel);
306 void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel);
307 void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel);
308 int _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params,
310 void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
311 void _ipu_vdi_uninit(struct ipu_soc *ipu);
312 void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu);
313 void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params);
314 void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu);
315 void _ipu_ic_init_csi(struct ipu_soc *ipu, ipu_channel_params_t *params);
316 void _ipu_ic_uninit_csi(struct ipu_soc *ipu);
317 int _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params,
319 void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu);
320 void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params);
321 void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu);
322 int _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
323 void _ipu_ic_uninit_pp(struct ipu_soc *ipu);
324 void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
325 void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu);
326 int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan, uint16_t width, uint16_t height,
327 int burst_size, ipu_rotate_mode_t rot);
328 void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu);
329 int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi);
330 int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi);
331 void ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
332 uint32_t g_value, uint32_t b_value,
333 uint32_t pix_clk, uint32_t csi);
334 void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi);
335 void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi);
336 void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel);
337 void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi);
338 void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs);
339 void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
340 int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
341 int16_t x_pos, int16_t y_pos);
342 int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
343 int16_t *x_pos, int16_t *y_pos);
344 void _ipu_get(struct ipu_soc *ipu);
345 void _ipu_put(struct ipu_soc *ipu);
347 struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
348 const char **parent_names, u8 num_parents, unsigned long flags,
349 u8 ipu_id, u8 di_id, u8 clk_mux_flags);
350 struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
351 const char *parent_name, unsigned long flags,
352 u8 ipu_id, u8 di_id, u8 clk_div_flags);
353 struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
354 const char *parent_name, unsigned long flags,
355 u8 ipu_id, u8 di_id, u8 clk_gate_flags);
356 #endif /* __INCLUDE_IPU_PRV_H__ */