1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/delay.h>
65 #include <linux/ethtool.h>
66 #include <linux/mii.h>
67 #include <linux/if_vlan.h>
68 #include <linux/crc32.h>
71 #include <linux/tcp.h>
72 #include <linux/udp.h>
73 #include <linux/cache.h>
76 #include <asm/uaccess.h>
78 /* VLAN tagging feature enable/disable */
79 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
80 #define CP_VLAN_TAG_USED 1
81 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
82 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
84 #define CP_VLAN_TAG_USED 0
85 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
86 do { (tx_desc)->opts2 = 0; } while (0)
89 /* These identify the driver base version and may not be removed. */
90 static char version[] =
91 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
95 MODULE_VERSION(DRV_VERSION);
96 MODULE_LICENSE("GPL");
98 static int debug = -1;
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
103 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
104 static int multicast_filter_limit = 32;
105 module_param(multicast_filter_limit, int, 0);
106 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108 #define PFX DRV_NAME ": "
112 #define TRUE (!FALSE)
115 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
119 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
120 #define CP_REGS_SIZE (0xff + 1)
121 #define CP_REGS_VER 1 /* version 1 */
122 #define CP_RX_RING_SIZE 64
123 #define CP_TX_RING_SIZE 64
124 #define CP_RING_BYTES \
125 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
126 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
128 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
129 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
130 #define TX_BUFFS_AVAIL(CP) \
131 (((CP)->tx_tail <= (CP)->tx_head) ? \
132 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
133 (CP)->tx_tail - (CP)->tx_head - 1)
135 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
137 #define CP_INTERNAL_PHY 32
139 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
140 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
141 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
142 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
143 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (6*HZ)
148 /* hardware minimum and maximum for a single frame's data payload */
149 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
150 #define CP_MAX_MTU 4096
153 /* NIC register offsets */
154 MAC0 = 0x00, /* Ethernet hardware address. */
155 MAR0 = 0x08, /* Multicast filter. */
156 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
157 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
158 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
159 Cmd = 0x37, /* Command register */
160 IntrMask = 0x3C, /* Interrupt mask */
161 IntrStatus = 0x3E, /* Interrupt status */
162 TxConfig = 0x40, /* Tx configuration */
163 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
164 RxConfig = 0x44, /* Rx configuration */
165 RxMissed = 0x4C, /* 24 bits valid, write clears */
166 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
167 Config1 = 0x52, /* Config1 */
168 Config3 = 0x59, /* Config3 */
169 Config4 = 0x5A, /* Config4 */
170 MultiIntr = 0x5C, /* Multiple interrupt select */
171 BasicModeCtrl = 0x62, /* MII BMCR */
172 BasicModeStatus = 0x64, /* MII BMSR */
173 NWayAdvert = 0x66, /* MII ADVERTISE */
174 NWayLPAR = 0x68, /* MII LPA */
175 NWayExpansion = 0x6A, /* MII Expansion */
176 Config5 = 0xD8, /* Config5 */
177 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
178 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
179 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
180 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
181 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
182 TxThresh = 0xEC, /* Early Tx threshold */
183 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
184 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186 /* Tx and Rx status descriptors */
187 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
188 RingEnd = (1 << 30), /* End of descriptor ring */
189 FirstFrag = (1 << 29), /* First segment of a packet */
190 LastFrag = (1 << 28), /* Final segment of a packet */
191 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
192 MSSShift = 16, /* MSS value position */
193 MSSMask = 0xfff, /* MSS value: 11 bits */
194 TxError = (1 << 23), /* Tx error summary */
195 RxError = (1 << 20), /* Rx error summary */
196 IPCS = (1 << 18), /* Calculate IP checksum */
197 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
198 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
199 TxVlanTag = (1 << 17), /* Add VLAN tag */
200 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
201 IPFail = (1 << 15), /* IP checksum failed */
202 UDPFail = (1 << 14), /* UDP/IP checksum failed */
203 TCPFail = (1 << 13), /* TCP/IP checksum failed */
204 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
205 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
206 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
210 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
211 TxOWC = (1 << 22), /* Tx Out-of-window collision */
212 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
213 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
214 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
215 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
216 RxErrFrame = (1 << 27), /* Rx frame alignment error */
217 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
218 RxErrCRC = (1 << 18), /* Rx CRC error */
219 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
220 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
221 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223 /* StatsAddr register */
224 DumpStats = (1 << 3), /* Begin stats dump */
226 /* RxConfig register */
227 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
228 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
229 AcceptErr = 0x20, /* Accept packets with CRC errors */
230 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
231 AcceptBroadcast = 0x08, /* Accept broadcast packets */
232 AcceptMulticast = 0x04, /* Accept multicast packets */
233 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
234 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236 /* IntrMask / IntrStatus registers */
237 PciErr = (1 << 15), /* System error on the PCI bus */
238 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
239 LenChg = (1 << 13), /* Cable length change */
240 SWInt = (1 << 8), /* Software-requested interrupt */
241 TxEmpty = (1 << 7), /* No Tx descriptors available */
242 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
243 LinkChg = (1 << 5), /* Packet underrun, or link change */
244 RxEmpty = (1 << 4), /* No Rx descriptors available */
245 TxErr = (1 << 3), /* Tx error */
246 TxOK = (1 << 2), /* Tx packet sent */
247 RxErr = (1 << 1), /* Rx error */
248 RxOK = (1 << 0), /* Rx packet received */
249 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
250 but hardware likes to raise it */
252 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
253 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
254 RxErr | RxOK | IntrResvd,
256 /* C mode command register */
257 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
258 RxOn = (1 << 3), /* Rx mode enable */
259 TxOn = (1 << 2), /* Tx mode enable */
261 /* C+ mode command register */
262 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
263 RxChkSum = (1 << 5), /* Rx checksum offload enable */
264 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
265 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
266 CpRxOn = (1 << 1), /* Rx mode enable */
267 CpTxOn = (1 << 0), /* Tx mode enable */
269 /* Cfg9436 EEPROM control register */
270 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
271 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273 /* TxConfig register */
274 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
275 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277 /* Early Tx Threshold register */
278 TxThreshMask = 0x3f, /* Mask bits 5-0 */
279 TxThreshMax = 2048, /* Max early Tx threshold */
281 /* Config1 register */
282 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
283 LWACT = (1 << 4), /* LWAKE active mode */
284 PMEnable = (1 << 0), /* Enable various PM features of chip */
286 /* Config3 register */
287 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
288 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
289 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291 /* Config4 register */
292 LWPTN = (1 << 1), /* LWAKE Pattern */
293 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295 /* Config5 register */
296 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
297 MWF = (1 << 5), /* Accept Multicast wakeup frame */
298 UWF = (1 << 4), /* Accept Unicast wakeup frame */
299 LANWake = (1 << 1), /* Enable LANWake signal */
300 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
303 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
304 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
307 static const unsigned int cp_rx_config =
308 (RX_FIFO_THRESH << RxCfgFIFOShift) |
309 (RX_DMA_BURST << RxCfgDMAShift);
317 struct cp_dma_stats {
331 } __attribute__((packed));
333 struct cp_extra_stats {
334 unsigned long rx_frags;
339 struct net_device *dev;
343 struct pci_dev *pdev;
347 struct net_device_stats net_stats;
348 struct cp_extra_stats cp_stats;
350 unsigned rx_head ____cacheline_aligned;
352 struct cp_desc *rx_ring;
353 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
355 unsigned tx_head ____cacheline_aligned;
357 struct cp_desc *tx_ring;
358 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
361 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
364 struct vlan_group *vlgrp;
368 struct mii_if_info mii_if;
371 #define cpr8(reg) readb(cp->regs + (reg))
372 #define cpr16(reg) readw(cp->regs + (reg))
373 #define cpr32(reg) readl(cp->regs + (reg))
374 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
375 #define cpw16(reg,val) writew((val), cp->regs + (reg))
376 #define cpw32(reg,val) writel((val), cp->regs + (reg))
377 #define cpw8_f(reg,val) do { \
378 writeb((val), cp->regs + (reg)); \
379 readb(cp->regs + (reg)); \
381 #define cpw16_f(reg,val) do { \
382 writew((val), cp->regs + (reg)); \
383 readw(cp->regs + (reg)); \
385 #define cpw32_f(reg,val) do { \
386 writel((val), cp->regs + (reg)); \
387 readl(cp->regs + (reg)); \
391 static void __cp_set_rx_mode (struct net_device *dev);
392 static void cp_tx (struct cp_private *cp);
393 static void cp_clean_rings (struct cp_private *cp);
394 #ifdef CONFIG_NET_POLL_CONTROLLER
395 static void cp_poll_controller(struct net_device *dev);
397 static int cp_get_eeprom_len(struct net_device *dev);
398 static int cp_get_eeprom(struct net_device *dev,
399 struct ethtool_eeprom *eeprom, u8 *data);
400 static int cp_set_eeprom(struct net_device *dev,
401 struct ethtool_eeprom *eeprom, u8 *data);
403 static struct pci_device_id cp_pci_tbl[] = {
404 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
405 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
408 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
411 const char str[ETH_GSTRING_LEN];
412 } ethtool_stats_keys[] = {
431 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
433 struct cp_private *cp = netdev_priv(dev);
436 spin_lock_irqsave(&cp->lock, flags);
438 cp->cpcmd |= RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
443 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
445 struct cp_private *cp = netdev_priv(dev);
448 spin_lock_irqsave(&cp->lock, flags);
449 cp->cpcmd &= ~RxVlanOn;
450 cpw16(CpCmd, cp->cpcmd);
452 cp->vlgrp->vlan_devices[vid] = NULL;
453 spin_unlock_irqrestore(&cp->lock, flags);
455 #endif /* CP_VLAN_TAG_USED */
457 static inline void cp_set_rxbufsize (struct cp_private *cp)
459 unsigned int mtu = cp->dev->mtu;
461 if (mtu > ETH_DATA_LEN)
462 /* MTU + ethernet header + FCS + optional VLAN tag */
463 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
465 cp->rx_buf_sz = PKT_BUF_SZ;
468 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
469 struct cp_desc *desc)
471 skb->protocol = eth_type_trans (skb, cp->dev);
473 cp->net_stats.rx_packets++;
474 cp->net_stats.rx_bytes += skb->len;
475 cp->dev->last_rx = jiffies;
478 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
479 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
480 be16_to_cpu(desc->opts2 & 0xffff));
483 netif_receive_skb(skb);
486 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
489 if (netif_msg_rx_err (cp))
491 "%s: rx err, slot %d status 0x%x len %d\n",
492 cp->dev->name, rx_tail, status, len);
493 cp->net_stats.rx_errors++;
494 if (status & RxErrFrame)
495 cp->net_stats.rx_frame_errors++;
496 if (status & RxErrCRC)
497 cp->net_stats.rx_crc_errors++;
498 if ((status & RxErrRunt) || (status & RxErrLong))
499 cp->net_stats.rx_length_errors++;
500 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
501 cp->net_stats.rx_length_errors++;
502 if (status & RxErrFIFO)
503 cp->net_stats.rx_fifo_errors++;
506 static inline unsigned int cp_rx_csum_ok (u32 status)
508 unsigned int protocol = (status >> 16) & 0x3;
510 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
512 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
514 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
519 static int cp_rx_poll (struct net_device *dev, int *budget)
521 struct cp_private *cp = netdev_priv(dev);
522 unsigned rx_tail = cp->rx_tail;
523 unsigned rx_work = dev->quota;
528 cpw16(IntrStatus, cp_rx_intr_mask);
533 struct sk_buff *skb, *new_skb;
534 struct cp_desc *desc;
537 skb = cp->rx_skb[rx_tail];
540 desc = &cp->rx_ring[rx_tail];
541 status = le32_to_cpu(desc->opts1);
542 if (status & DescOwn)
545 len = (status & 0x1fff) - 4;
546 mapping = le64_to_cpu(desc->addr);
548 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
549 /* we don't support incoming fragmented frames.
550 * instead, we attempt to ensure that the
551 * pre-allocated RX skbs are properly sized such
552 * that RX fragments are never encountered
554 cp_rx_err_acct(cp, rx_tail, status, len);
555 cp->net_stats.rx_dropped++;
556 cp->cp_stats.rx_frags++;
560 if (status & (RxError | RxErrFIFO)) {
561 cp_rx_err_acct(cp, rx_tail, status, len);
565 if (netif_msg_rx_status(cp))
566 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
567 dev->name, rx_tail, status, len);
569 buflen = cp->rx_buf_sz + RX_OFFSET;
570 new_skb = dev_alloc_skb (buflen);
572 cp->net_stats.rx_dropped++;
576 skb_reserve(new_skb, RX_OFFSET);
579 pci_unmap_single(cp->pdev, mapping,
580 buflen, PCI_DMA_FROMDEVICE);
582 /* Handle checksum offloading for incoming packets. */
583 if (cp_rx_csum_ok(status))
584 skb->ip_summed = CHECKSUM_UNNECESSARY;
586 skb->ip_summed = CHECKSUM_NONE;
590 mapping = pci_map_single(cp->pdev, new_skb->data, buflen,
592 cp->rx_skb[rx_tail] = new_skb;
594 cp_rx_skb(cp, skb, desc);
598 cp->rx_ring[rx_tail].opts2 = 0;
599 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
600 if (rx_tail == (CP_RX_RING_SIZE - 1))
601 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
604 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
605 rx_tail = NEXT_RX(rx_tail);
611 cp->rx_tail = rx_tail;
616 /* if we did not reach work limit, then we're done with
617 * this round of polling
620 if (cpr16(IntrStatus) & cp_rx_intr_mask)
624 cpw16_f(IntrMask, cp_intr_mask);
625 __netif_rx_complete(dev);
631 return 1; /* not done */
635 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
637 struct net_device *dev = dev_instance;
638 struct cp_private *cp;
641 if (unlikely(dev == NULL))
643 cp = netdev_priv(dev);
645 status = cpr16(IntrStatus);
646 if (!status || (status == 0xFFFF))
649 if (netif_msg_intr(cp))
650 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
651 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
653 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
655 spin_lock(&cp->lock);
657 /* close possible race's with dev_close */
658 if (unlikely(!netif_running(dev))) {
660 spin_unlock(&cp->lock);
664 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
665 if (netif_rx_schedule_prep(dev)) {
666 cpw16_f(IntrMask, cp_norx_intr_mask);
667 __netif_rx_schedule(dev);
670 if (status & (TxOK | TxErr | TxEmpty | SWInt))
672 if (status & LinkChg)
673 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
675 spin_unlock(&cp->lock);
677 if (status & PciErr) {
680 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
681 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
682 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
683 dev->name, status, pci_status);
685 /* TODO: reset hardware */
691 #ifdef CONFIG_NET_POLL_CONTROLLER
693 * Polling receive - used by netconsole and other diagnostic tools
694 * to allow network i/o with interrupts disabled.
696 static void cp_poll_controller(struct net_device *dev)
698 disable_irq(dev->irq);
699 cp_interrupt(dev->irq, dev, NULL);
700 enable_irq(dev->irq);
704 static void cp_tx (struct cp_private *cp)
706 unsigned tx_head = cp->tx_head;
707 unsigned tx_tail = cp->tx_tail;
709 while (tx_tail != tx_head) {
710 struct cp_desc *txd = cp->tx_ring + tx_tail;
715 status = le32_to_cpu(txd->opts1);
716 if (status & DescOwn)
719 skb = cp->tx_skb[tx_tail];
722 pci_unmap_single(cp->pdev, le64_to_cpu(txd->addr),
723 le32_to_cpu(txd->opts1) & 0xffff,
726 if (status & LastFrag) {
727 if (status & (TxError | TxFIFOUnder)) {
728 if (netif_msg_tx_err(cp))
729 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
730 cp->dev->name, status);
731 cp->net_stats.tx_errors++;
733 cp->net_stats.tx_window_errors++;
734 if (status & TxMaxCol)
735 cp->net_stats.tx_aborted_errors++;
736 if (status & TxLinkFail)
737 cp->net_stats.tx_carrier_errors++;
738 if (status & TxFIFOUnder)
739 cp->net_stats.tx_fifo_errors++;
741 cp->net_stats.collisions +=
742 ((status >> TxColCntShift) & TxColCntMask);
743 cp->net_stats.tx_packets++;
744 cp->net_stats.tx_bytes += skb->len;
745 if (netif_msg_tx_done(cp))
746 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
748 dev_kfree_skb_irq(skb);
751 cp->tx_skb[tx_tail] = NULL;
753 tx_tail = NEXT_TX(tx_tail);
756 cp->tx_tail = tx_tail;
758 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
759 netif_wake_queue(cp->dev);
762 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
764 struct cp_private *cp = netdev_priv(dev);
772 spin_lock_irq(&cp->lock);
774 /* This is a hard error, log it. */
775 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
776 netif_stop_queue(dev);
777 spin_unlock_irq(&cp->lock);
778 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
784 if (cp->vlgrp && vlan_tx_tag_present(skb))
785 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
789 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
790 if (dev->features & NETIF_F_TSO)
791 mss = skb_shinfo(skb)->gso_size;
793 if (skb_shinfo(skb)->nr_frags == 0) {
794 struct cp_desc *txd = &cp->tx_ring[entry];
799 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
800 CP_VLAN_TX_TAG(txd, vlan_tag);
801 txd->addr = cpu_to_le64(mapping);
804 flags = eor | len | DescOwn | FirstFrag | LastFrag;
807 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
808 else if (skb->ip_summed == CHECKSUM_HW) {
809 const struct iphdr *ip = skb->nh.iph;
810 if (ip->protocol == IPPROTO_TCP)
811 flags |= IPCS | TCPCS;
812 else if (ip->protocol == IPPROTO_UDP)
813 flags |= IPCS | UDPCS;
815 WARN_ON(1); /* we need a WARN() */
818 txd->opts1 = cpu_to_le32(flags);
821 cp->tx_skb[entry] = skb;
822 entry = NEXT_TX(entry);
825 u32 first_len, first_eor;
826 dma_addr_t first_mapping;
827 int frag, first_entry = entry;
828 const struct iphdr *ip = skb->nh.iph;
830 /* We must give this initial chunk to the device last.
831 * Otherwise we could race with the device.
834 first_len = skb_headlen(skb);
835 first_mapping = pci_map_single(cp->pdev, skb->data,
836 first_len, PCI_DMA_TODEVICE);
837 cp->tx_skb[entry] = skb;
838 entry = NEXT_TX(entry);
840 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
841 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
846 len = this_frag->size;
847 mapping = pci_map_single(cp->pdev,
848 ((void *) page_address(this_frag->page) +
849 this_frag->page_offset),
850 len, PCI_DMA_TODEVICE);
851 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
853 ctrl = eor | len | DescOwn;
857 ((mss & MSSMask) << MSSShift);
858 else if (skb->ip_summed == CHECKSUM_HW) {
859 if (ip->protocol == IPPROTO_TCP)
860 ctrl |= IPCS | TCPCS;
861 else if (ip->protocol == IPPROTO_UDP)
862 ctrl |= IPCS | UDPCS;
867 if (frag == skb_shinfo(skb)->nr_frags - 1)
870 txd = &cp->tx_ring[entry];
871 CP_VLAN_TX_TAG(txd, vlan_tag);
872 txd->addr = cpu_to_le64(mapping);
875 txd->opts1 = cpu_to_le32(ctrl);
878 cp->tx_skb[entry] = skb;
879 entry = NEXT_TX(entry);
882 txd = &cp->tx_ring[first_entry];
883 CP_VLAN_TX_TAG(txd, vlan_tag);
884 txd->addr = cpu_to_le64(first_mapping);
887 if (skb->ip_summed == CHECKSUM_HW) {
888 if (ip->protocol == IPPROTO_TCP)
889 txd->opts1 = cpu_to_le32(first_eor | first_len |
890 FirstFrag | DescOwn |
892 else if (ip->protocol == IPPROTO_UDP)
893 txd->opts1 = cpu_to_le32(first_eor | first_len |
894 FirstFrag | DescOwn |
899 txd->opts1 = cpu_to_le32(first_eor | first_len |
900 FirstFrag | DescOwn);
904 if (netif_msg_tx_queued(cp))
905 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
906 dev->name, entry, skb->len);
907 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
908 netif_stop_queue(dev);
910 spin_unlock_irq(&cp->lock);
912 cpw8(TxPoll, NormalTxPoll);
913 dev->trans_start = jiffies;
918 /* Set or clear the multicast filter for this adaptor.
919 This routine is not state sensitive and need not be SMP locked. */
921 static void __cp_set_rx_mode (struct net_device *dev)
923 struct cp_private *cp = netdev_priv(dev);
924 u32 mc_filter[2]; /* Multicast hash filter */
928 /* Note: do not reorder, GCC is clever about common statements. */
929 if (dev->flags & IFF_PROMISC) {
930 /* Unconditionally log net taps. */
931 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
934 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
936 mc_filter[1] = mc_filter[0] = 0xffffffff;
937 } else if ((dev->mc_count > multicast_filter_limit)
938 || (dev->flags & IFF_ALLMULTI)) {
939 /* Too many to filter perfectly -- accept all multicasts. */
940 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
941 mc_filter[1] = mc_filter[0] = 0xffffffff;
943 struct dev_mc_list *mclist;
944 rx_mode = AcceptBroadcast | AcceptMyPhys;
945 mc_filter[1] = mc_filter[0] = 0;
946 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
947 i++, mclist = mclist->next) {
948 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
950 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
951 rx_mode |= AcceptMulticast;
955 /* We can safely update without stopping the chip. */
956 tmp = cp_rx_config | rx_mode;
957 if (cp->rx_config != tmp) {
958 cpw32_f (RxConfig, tmp);
961 cpw32_f (MAR0 + 0, mc_filter[0]);
962 cpw32_f (MAR0 + 4, mc_filter[1]);
965 static void cp_set_rx_mode (struct net_device *dev)
968 struct cp_private *cp = netdev_priv(dev);
970 spin_lock_irqsave (&cp->lock, flags);
971 __cp_set_rx_mode(dev);
972 spin_unlock_irqrestore (&cp->lock, flags);
975 static void __cp_get_stats(struct cp_private *cp)
977 /* only lower 24 bits valid; write any value to clear */
978 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
982 static struct net_device_stats *cp_get_stats(struct net_device *dev)
984 struct cp_private *cp = netdev_priv(dev);
987 /* The chip only need report frame silently dropped. */
988 spin_lock_irqsave(&cp->lock, flags);
989 if (netif_running(dev) && netif_device_present(dev))
991 spin_unlock_irqrestore(&cp->lock, flags);
993 return &cp->net_stats;
996 static void cp_stop_hw (struct cp_private *cp)
998 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
999 cpw16_f(IntrMask, 0);
1002 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1005 cp->tx_head = cp->tx_tail = 0;
1008 static void cp_reset_hw (struct cp_private *cp)
1010 unsigned work = 1000;
1012 cpw8(Cmd, CmdReset);
1015 if (!(cpr8(Cmd) & CmdReset))
1018 schedule_timeout_uninterruptible(10);
1021 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1024 static inline void cp_start_hw (struct cp_private *cp)
1026 cpw16(CpCmd, cp->cpcmd);
1027 cpw8(Cmd, RxOn | TxOn);
1030 static void cp_init_hw (struct cp_private *cp)
1032 struct net_device *dev = cp->dev;
1033 dma_addr_t ring_dma;
1037 cpw8_f (Cfg9346, Cfg9346_Unlock);
1039 /* Restore our idea of the MAC address. */
1040 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1041 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1044 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1046 __cp_set_rx_mode(dev);
1047 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1049 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1050 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1051 cpw8(Config3, PARMEnable);
1052 cp->wol_enabled = 0;
1054 cpw8(Config5, cpr8(Config5) & PMEStatus);
1056 cpw32_f(HiTxRingAddr, 0);
1057 cpw32_f(HiTxRingAddr + 4, 0);
1059 ring_dma = cp->ring_dma;
1060 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1061 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1063 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1064 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1065 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1067 cpw16(MultiIntr, 0);
1069 cpw16_f(IntrMask, cp_intr_mask);
1071 cpw8_f(Cfg9346, Cfg9346_Lock);
1074 static int cp_refill_rx (struct cp_private *cp)
1078 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1079 struct sk_buff *skb;
1082 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1087 skb_reserve(skb, RX_OFFSET);
1089 mapping = pci_map_single(cp->pdev, skb->data, cp->rx_buf_sz,
1090 PCI_DMA_FROMDEVICE);
1091 cp->rx_skb[i] = skb;
1093 cp->rx_ring[i].opts2 = 0;
1094 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1095 if (i == (CP_RX_RING_SIZE - 1))
1096 cp->rx_ring[i].opts1 =
1097 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1099 cp->rx_ring[i].opts1 =
1100 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1110 static void cp_init_rings_index (struct cp_private *cp)
1113 cp->tx_head = cp->tx_tail = 0;
1116 static int cp_init_rings (struct cp_private *cp)
1118 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1119 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1121 cp_init_rings_index(cp);
1123 return cp_refill_rx (cp);
1126 static int cp_alloc_rings (struct cp_private *cp)
1130 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1135 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1137 return cp_init_rings(cp);
1140 static void cp_clean_rings (struct cp_private *cp)
1142 struct cp_desc *desc;
1145 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1146 if (cp->rx_skb[i]) {
1147 desc = cp->rx_ring + i;
1148 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1149 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1150 dev_kfree_skb(cp->rx_skb[i]);
1154 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1155 if (cp->tx_skb[i]) {
1156 struct sk_buff *skb = cp->tx_skb[i];
1158 desc = cp->tx_ring + i;
1159 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1160 le32_to_cpu(desc->opts1) & 0xffff,
1162 if (le32_to_cpu(desc->opts1) & LastFrag)
1164 cp->net_stats.tx_dropped++;
1168 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1169 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1171 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1172 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1175 static void cp_free_rings (struct cp_private *cp)
1178 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1183 static int cp_open (struct net_device *dev)
1185 struct cp_private *cp = netdev_priv(dev);
1188 if (netif_msg_ifup(cp))
1189 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1191 rc = cp_alloc_rings(cp);
1197 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1201 netif_carrier_off(dev);
1202 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1203 netif_start_queue(dev);
1213 static int cp_close (struct net_device *dev)
1215 struct cp_private *cp = netdev_priv(dev);
1216 unsigned long flags;
1218 if (netif_msg_ifdown(cp))
1219 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1221 spin_lock_irqsave(&cp->lock, flags);
1223 netif_stop_queue(dev);
1224 netif_carrier_off(dev);
1228 spin_unlock_irqrestore(&cp->lock, flags);
1230 synchronize_irq(dev->irq);
1231 free_irq(dev->irq, dev);
1238 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1240 struct cp_private *cp = netdev_priv(dev);
1242 unsigned long flags;
1244 /* check for invalid MTU, according to hardware limits */
1245 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1248 /* if network interface not up, no need for complexity */
1249 if (!netif_running(dev)) {
1251 cp_set_rxbufsize(cp); /* set new rx buf size */
1255 spin_lock_irqsave(&cp->lock, flags);
1257 cp_stop_hw(cp); /* stop h/w and free rings */
1261 cp_set_rxbufsize(cp); /* set new rx buf size */
1263 rc = cp_init_rings(cp); /* realloc and restart h/w */
1266 spin_unlock_irqrestore(&cp->lock, flags);
1272 static const char mii_2_8139_map[8] = {
1283 static int mdio_read(struct net_device *dev, int phy_id, int location)
1285 struct cp_private *cp = netdev_priv(dev);
1287 return location < 8 && mii_2_8139_map[location] ?
1288 readw(cp->regs + mii_2_8139_map[location]) : 0;
1292 static void mdio_write(struct net_device *dev, int phy_id, int location,
1295 struct cp_private *cp = netdev_priv(dev);
1297 if (location == 0) {
1298 cpw8(Cfg9346, Cfg9346_Unlock);
1299 cpw16(BasicModeCtrl, value);
1300 cpw8(Cfg9346, Cfg9346_Lock);
1301 } else if (location < 8 && mii_2_8139_map[location])
1302 cpw16(mii_2_8139_map[location], value);
1305 /* Set the ethtool Wake-on-LAN settings */
1306 static int netdev_set_wol (struct cp_private *cp,
1307 const struct ethtool_wolinfo *wol)
1311 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1312 /* If WOL is being disabled, no need for complexity */
1314 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1315 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1318 cpw8 (Cfg9346, Cfg9346_Unlock);
1319 cpw8 (Config3, options);
1320 cpw8 (Cfg9346, Cfg9346_Lock);
1322 options = 0; /* Paranoia setting */
1323 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1324 /* If WOL is being disabled, no need for complexity */
1326 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1327 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1328 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1331 cpw8 (Config5, options);
1333 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1338 /* Get the ethtool Wake-on-LAN settings */
1339 static void netdev_get_wol (struct cp_private *cp,
1340 struct ethtool_wolinfo *wol)
1344 wol->wolopts = 0; /* Start from scratch */
1345 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1346 WAKE_MCAST | WAKE_UCAST;
1347 /* We don't need to go on if WOL is disabled */
1348 if (!cp->wol_enabled) return;
1350 options = cpr8 (Config3);
1351 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1352 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1354 options = 0; /* Paranoia setting */
1355 options = cpr8 (Config5);
1356 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1357 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1358 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1361 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1363 struct cp_private *cp = netdev_priv(dev);
1365 strcpy (info->driver, DRV_NAME);
1366 strcpy (info->version, DRV_VERSION);
1367 strcpy (info->bus_info, pci_name(cp->pdev));
1370 static int cp_get_regs_len(struct net_device *dev)
1372 return CP_REGS_SIZE;
1375 static int cp_get_stats_count (struct net_device *dev)
1377 return CP_NUM_STATS;
1380 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1382 struct cp_private *cp = netdev_priv(dev);
1384 unsigned long flags;
1386 spin_lock_irqsave(&cp->lock, flags);
1387 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1388 spin_unlock_irqrestore(&cp->lock, flags);
1393 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1395 struct cp_private *cp = netdev_priv(dev);
1397 unsigned long flags;
1399 spin_lock_irqsave(&cp->lock, flags);
1400 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1401 spin_unlock_irqrestore(&cp->lock, flags);
1406 static int cp_nway_reset(struct net_device *dev)
1408 struct cp_private *cp = netdev_priv(dev);
1409 return mii_nway_restart(&cp->mii_if);
1412 static u32 cp_get_msglevel(struct net_device *dev)
1414 struct cp_private *cp = netdev_priv(dev);
1415 return cp->msg_enable;
1418 static void cp_set_msglevel(struct net_device *dev, u32 value)
1420 struct cp_private *cp = netdev_priv(dev);
1421 cp->msg_enable = value;
1424 static u32 cp_get_rx_csum(struct net_device *dev)
1426 struct cp_private *cp = netdev_priv(dev);
1427 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1430 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1432 struct cp_private *cp = netdev_priv(dev);
1433 u16 cmd = cp->cpcmd, newcmd;
1440 newcmd &= ~RxChkSum;
1442 if (newcmd != cmd) {
1443 unsigned long flags;
1445 spin_lock_irqsave(&cp->lock, flags);
1447 cpw16_f(CpCmd, newcmd);
1448 spin_unlock_irqrestore(&cp->lock, flags);
1454 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1457 struct cp_private *cp = netdev_priv(dev);
1458 unsigned long flags;
1460 if (regs->len < CP_REGS_SIZE)
1461 return /* -EINVAL */;
1463 regs->version = CP_REGS_VER;
1465 spin_lock_irqsave(&cp->lock, flags);
1466 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1467 spin_unlock_irqrestore(&cp->lock, flags);
1470 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1472 struct cp_private *cp = netdev_priv(dev);
1473 unsigned long flags;
1475 spin_lock_irqsave (&cp->lock, flags);
1476 netdev_get_wol (cp, wol);
1477 spin_unlock_irqrestore (&cp->lock, flags);
1480 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1482 struct cp_private *cp = netdev_priv(dev);
1483 unsigned long flags;
1486 spin_lock_irqsave (&cp->lock, flags);
1487 rc = netdev_set_wol (cp, wol);
1488 spin_unlock_irqrestore (&cp->lock, flags);
1493 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1495 switch (stringset) {
1497 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1505 static void cp_get_ethtool_stats (struct net_device *dev,
1506 struct ethtool_stats *estats, u64 *tmp_stats)
1508 struct cp_private *cp = netdev_priv(dev);
1509 struct cp_dma_stats *nic_stats;
1513 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1517 /* begin NIC statistics dump */
1518 cpw32(StatsAddr + 4, (u64)dma >> 32);
1519 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1522 for (i = 0; i < 1000; i++) {
1523 if ((cpr32(StatsAddr) & DumpStats) == 0)
1527 cpw32(StatsAddr, 0);
1528 cpw32(StatsAddr + 4, 0);
1532 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1533 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1534 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1535 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1536 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1537 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1538 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1539 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1540 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1542 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1543 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1544 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1545 tmp_stats[i++] = cp->cp_stats.rx_frags;
1546 BUG_ON(i != CP_NUM_STATS);
1548 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1551 static struct ethtool_ops cp_ethtool_ops = {
1552 .get_drvinfo = cp_get_drvinfo,
1553 .get_regs_len = cp_get_regs_len,
1554 .get_stats_count = cp_get_stats_count,
1555 .get_settings = cp_get_settings,
1556 .set_settings = cp_set_settings,
1557 .nway_reset = cp_nway_reset,
1558 .get_link = ethtool_op_get_link,
1559 .get_msglevel = cp_get_msglevel,
1560 .set_msglevel = cp_set_msglevel,
1561 .get_rx_csum = cp_get_rx_csum,
1562 .set_rx_csum = cp_set_rx_csum,
1563 .get_tx_csum = ethtool_op_get_tx_csum,
1564 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1565 .get_sg = ethtool_op_get_sg,
1566 .set_sg = ethtool_op_set_sg,
1567 .get_tso = ethtool_op_get_tso,
1568 .set_tso = ethtool_op_set_tso,
1569 .get_regs = cp_get_regs,
1570 .get_wol = cp_get_wol,
1571 .set_wol = cp_set_wol,
1572 .get_strings = cp_get_strings,
1573 .get_ethtool_stats = cp_get_ethtool_stats,
1574 .get_perm_addr = ethtool_op_get_perm_addr,
1575 .get_eeprom_len = cp_get_eeprom_len,
1576 .get_eeprom = cp_get_eeprom,
1577 .set_eeprom = cp_set_eeprom,
1580 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1582 struct cp_private *cp = netdev_priv(dev);
1584 unsigned long flags;
1586 if (!netif_running(dev))
1589 spin_lock_irqsave(&cp->lock, flags);
1590 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1591 spin_unlock_irqrestore(&cp->lock, flags);
1595 /* Serial EEPROM section. */
1597 /* EEPROM_Ctrl bits. */
1598 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1599 #define EE_CS 0x08 /* EEPROM chip select. */
1600 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1601 #define EE_WRITE_0 0x00
1602 #define EE_WRITE_1 0x02
1603 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1604 #define EE_ENB (0x80 | EE_CS)
1606 /* Delay between EEPROM clock transitions.
1607 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1610 #define eeprom_delay() readl(ee_addr)
1612 /* The EEPROM commands include the alway-set leading bit. */
1613 #define EE_EXTEND_CMD (4)
1614 #define EE_WRITE_CMD (5)
1615 #define EE_READ_CMD (6)
1616 #define EE_ERASE_CMD (7)
1618 #define EE_EWDS_ADDR (0)
1619 #define EE_WRAL_ADDR (1)
1620 #define EE_ERAL_ADDR (2)
1621 #define EE_EWEN_ADDR (3)
1623 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1625 static void eeprom_cmd_start(void __iomem *ee_addr)
1627 writeb (EE_ENB & ~EE_CS, ee_addr);
1628 writeb (EE_ENB, ee_addr);
1632 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1636 /* Shift the command bits out. */
1637 for (i = cmd_len - 1; i >= 0; i--) {
1638 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1639 writeb (EE_ENB | dataval, ee_addr);
1641 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1644 writeb (EE_ENB, ee_addr);
1648 static void eeprom_cmd_end(void __iomem *ee_addr)
1650 writeb (~EE_CS, ee_addr);
1654 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1657 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1659 eeprom_cmd_start(ee_addr);
1660 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1661 eeprom_cmd_end(ee_addr);
1664 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1668 void __iomem *ee_addr = ioaddr + Cfg9346;
1669 int read_cmd = location | (EE_READ_CMD << addr_len);
1671 eeprom_cmd_start(ee_addr);
1672 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1674 for (i = 16; i > 0; i--) {
1675 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1678 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1680 writeb (EE_ENB, ee_addr);
1684 eeprom_cmd_end(ee_addr);
1689 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1693 void __iomem *ee_addr = ioaddr + Cfg9346;
1694 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1696 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1698 eeprom_cmd_start(ee_addr);
1699 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1700 eeprom_cmd(ee_addr, val, 16);
1701 eeprom_cmd_end(ee_addr);
1703 eeprom_cmd_start(ee_addr);
1704 for (i = 0; i < 20000; i++)
1705 if (readb(ee_addr) & EE_DATA_READ)
1707 eeprom_cmd_end(ee_addr);
1709 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1712 static int cp_get_eeprom_len(struct net_device *dev)
1714 struct cp_private *cp = netdev_priv(dev);
1717 spin_lock_irq(&cp->lock);
1718 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1719 spin_unlock_irq(&cp->lock);
1724 static int cp_get_eeprom(struct net_device *dev,
1725 struct ethtool_eeprom *eeprom, u8 *data)
1727 struct cp_private *cp = netdev_priv(dev);
1728 unsigned int addr_len;
1730 u32 offset = eeprom->offset >> 1;
1731 u32 len = eeprom->len;
1734 eeprom->magic = CP_EEPROM_MAGIC;
1736 spin_lock_irq(&cp->lock);
1738 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1740 if (eeprom->offset & 1) {
1741 val = read_eeprom(cp->regs, offset, addr_len);
1742 data[i++] = (u8)(val >> 8);
1746 while (i < len - 1) {
1747 val = read_eeprom(cp->regs, offset, addr_len);
1748 data[i++] = (u8)val;
1749 data[i++] = (u8)(val >> 8);
1754 val = read_eeprom(cp->regs, offset, addr_len);
1758 spin_unlock_irq(&cp->lock);
1762 static int cp_set_eeprom(struct net_device *dev,
1763 struct ethtool_eeprom *eeprom, u8 *data)
1765 struct cp_private *cp = netdev_priv(dev);
1766 unsigned int addr_len;
1768 u32 offset = eeprom->offset >> 1;
1769 u32 len = eeprom->len;
1772 if (eeprom->magic != CP_EEPROM_MAGIC)
1775 spin_lock_irq(&cp->lock);
1777 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1779 if (eeprom->offset & 1) {
1780 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1781 val |= (u16)data[i++] << 8;
1782 write_eeprom(cp->regs, offset, val, addr_len);
1786 while (i < len - 1) {
1787 val = (u16)data[i++];
1788 val |= (u16)data[i++] << 8;
1789 write_eeprom(cp->regs, offset, val, addr_len);
1794 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1795 val |= (u16)data[i];
1796 write_eeprom(cp->regs, offset, val, addr_len);
1799 spin_unlock_irq(&cp->lock);
1803 /* Put the board into D3cold state and wait for WakeUp signal */
1804 static void cp_set_d3_state (struct cp_private *cp)
1806 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1807 pci_set_power_state (cp->pdev, PCI_D3hot);
1810 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1812 struct net_device *dev;
1813 struct cp_private *cp;
1816 resource_size_t pciaddr;
1817 unsigned int addr_len, i, pci_using_dac;
1821 static int version_printed;
1822 if (version_printed++ == 0)
1823 printk("%s", version);
1826 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1828 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1829 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1831 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1832 pdev->vendor, pdev->device, pci_rev);
1833 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1837 dev = alloc_etherdev(sizeof(struct cp_private));
1840 SET_MODULE_OWNER(dev);
1841 SET_NETDEV_DEV(dev, &pdev->dev);
1843 cp = netdev_priv(dev);
1846 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1847 spin_lock_init (&cp->lock);
1848 cp->mii_if.dev = dev;
1849 cp->mii_if.mdio_read = mdio_read;
1850 cp->mii_if.mdio_write = mdio_write;
1851 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1852 cp->mii_if.phy_id_mask = 0x1f;
1853 cp->mii_if.reg_num_mask = 0x1f;
1854 cp_set_rxbufsize(cp);
1856 rc = pci_enable_device(pdev);
1860 rc = pci_set_mwi(pdev);
1862 goto err_out_disable;
1864 rc = pci_request_regions(pdev, DRV_NAME);
1868 pciaddr = pci_resource_start(pdev, 1);
1871 dev_err(&pdev->dev, "no MMIO resource\n");
1874 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1876 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1877 (unsigned long long)pci_resource_len(pdev, 1));
1881 /* Configure DMA attributes. */
1882 if ((sizeof(dma_addr_t) > 4) &&
1883 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1884 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1889 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1892 "No usable DMA configuration, aborting.\n");
1895 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1898 "No usable consistent DMA configuration, "
1904 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1905 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1907 regs = ioremap(pciaddr, CP_REGS_SIZE);
1910 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1911 (unsigned long long)pci_resource_len(pdev, 1),
1912 (unsigned long long)pciaddr);
1915 dev->base_addr = (unsigned long) regs;
1920 /* read MAC address from EEPROM */
1921 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1922 for (i = 0; i < 3; i++)
1923 ((u16 *) (dev->dev_addr))[i] =
1924 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1925 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1927 dev->open = cp_open;
1928 dev->stop = cp_close;
1929 dev->set_multicast_list = cp_set_rx_mode;
1930 dev->hard_start_xmit = cp_start_xmit;
1931 dev->get_stats = cp_get_stats;
1932 dev->do_ioctl = cp_ioctl;
1933 dev->poll = cp_rx_poll;
1934 #ifdef CONFIG_NET_POLL_CONTROLLER
1935 dev->poll_controller = cp_poll_controller;
1937 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1939 dev->change_mtu = cp_change_mtu;
1941 dev->ethtool_ops = &cp_ethtool_ops;
1943 dev->tx_timeout = cp_tx_timeout;
1944 dev->watchdog_timeo = TX_TIMEOUT;
1947 #if CP_VLAN_TAG_USED
1948 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1949 dev->vlan_rx_register = cp_vlan_rx_register;
1950 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1954 dev->features |= NETIF_F_HIGHDMA;
1956 #if 0 /* disabled by default until verified */
1957 dev->features |= NETIF_F_TSO;
1960 dev->irq = pdev->irq;
1962 rc = register_netdev(dev);
1966 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1967 "%02x:%02x:%02x:%02x:%02x:%02x, "
1971 dev->dev_addr[0], dev->dev_addr[1],
1972 dev->dev_addr[2], dev->dev_addr[3],
1973 dev->dev_addr[4], dev->dev_addr[5],
1976 pci_set_drvdata(pdev, dev);
1978 /* enable busmastering and memory-write-invalidate */
1979 pci_set_master(pdev);
1981 if (cp->wol_enabled)
1982 cp_set_d3_state (cp);
1989 pci_release_regions(pdev);
1991 pci_clear_mwi(pdev);
1993 pci_disable_device(pdev);
1999 static void cp_remove_one (struct pci_dev *pdev)
2001 struct net_device *dev = pci_get_drvdata(pdev);
2002 struct cp_private *cp = netdev_priv(dev);
2004 unregister_netdev(dev);
2006 if (cp->wol_enabled)
2007 pci_set_power_state (pdev, PCI_D0);
2008 pci_release_regions(pdev);
2009 pci_clear_mwi(pdev);
2010 pci_disable_device(pdev);
2011 pci_set_drvdata(pdev, NULL);
2016 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2018 struct net_device *dev = pci_get_drvdata(pdev);
2019 struct cp_private *cp = netdev_priv(dev);
2020 unsigned long flags;
2022 if (!netif_running(dev))
2025 netif_device_detach (dev);
2026 netif_stop_queue (dev);
2028 spin_lock_irqsave (&cp->lock, flags);
2030 /* Disable Rx and Tx */
2031 cpw16 (IntrMask, 0);
2032 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2034 spin_unlock_irqrestore (&cp->lock, flags);
2036 pci_save_state(pdev);
2037 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2038 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2043 static int cp_resume (struct pci_dev *pdev)
2045 struct net_device *dev = pci_get_drvdata (pdev);
2046 struct cp_private *cp = netdev_priv(dev);
2047 unsigned long flags;
2049 if (!netif_running(dev))
2052 netif_device_attach (dev);
2054 pci_set_power_state(pdev, PCI_D0);
2055 pci_restore_state(pdev);
2056 pci_enable_wake(pdev, PCI_D0, 0);
2058 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2059 cp_init_rings_index (cp);
2061 netif_start_queue (dev);
2063 spin_lock_irqsave (&cp->lock, flags);
2065 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
2067 spin_unlock_irqrestore (&cp->lock, flags);
2071 #endif /* CONFIG_PM */
2073 static struct pci_driver cp_driver = {
2075 .id_table = cp_pci_tbl,
2076 .probe = cp_init_one,
2077 .remove = cp_remove_one,
2079 .resume = cp_resume,
2080 .suspend = cp_suspend,
2084 static int __init cp_init (void)
2087 printk("%s", version);
2089 return pci_module_init (&cp_driver);
2092 static void __exit cp_exit (void)
2094 pci_unregister_driver (&cp_driver);
2097 module_init(cp_init);
2098 module_exit(cp_exit);