2 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
37 AMD8111 based 10/100 Ethernet Controller Driver.
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
50 4. Dynamic IPG support
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
63 4. Modified amd8111e_rx() routine to receive all the received packets
64 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
72 #include <linux/module.h>
73 #include <linux/kernel.h>
74 #include <linux/types.h>
75 #include <linux/compiler.h>
76 #include <linux/slab.h>
77 #include <linux/delay.h>
78 #include <linux/init.h>
79 #include <linux/ioport.h>
80 #include <linux/pci.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/ethtool.h>
85 #include <linux/mii.h>
86 #include <linux/if_vlan.h>
87 #include <linux/ctype.h>
88 #include <linux/crc32.h>
89 #include <linux/dma-mapping.h>
91 #include <asm/system.h>
93 #include <asm/byteorder.h>
94 #include <asm/uaccess.h>
96 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
97 #define AMD8111E_VLAN_TAG_USED 1
99 #define AMD8111E_VLAN_TAG_USED 0
102 #include "amd8111e.h"
103 #define MODULE_NAME "amd8111e"
104 #define MODULE_VERS "3.0.7"
105 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
106 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
107 MODULE_LICENSE("GPL");
108 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
109 module_param_array(speed_duplex, int, NULL, 0);
110 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
111 module_param_array(coalesce, bool, NULL, 0);
112 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
113 module_param_array(dynamic_ipg, bool, NULL, 0);
114 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
116 static DEFINE_PCI_DEVICE_TABLE(amd8111e_pci_tbl) = {
118 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 This function will read the PHY registers.
126 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
128 void __iomem *mmio = lp->mmio;
129 unsigned int reg_val;
130 unsigned int repeat= REPEAT_CNT;
132 reg_val = readl(mmio + PHY_ACCESS);
133 while (reg_val & PHY_CMD_ACTIVE)
134 reg_val = readl( mmio + PHY_ACCESS );
136 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
137 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
139 reg_val = readl(mmio + PHY_ACCESS);
140 udelay(30); /* It takes 30 us to read/write data */
141 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
142 if(reg_val & PHY_RD_ERR)
145 *val = reg_val & 0xffff;
154 This function will write into PHY registers.
156 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
158 unsigned int repeat = REPEAT_CNT;
159 void __iomem *mmio = lp->mmio;
160 unsigned int reg_val;
162 reg_val = readl(mmio + PHY_ACCESS);
163 while (reg_val & PHY_CMD_ACTIVE)
164 reg_val = readl( mmio + PHY_ACCESS );
166 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
167 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
170 reg_val = readl(mmio + PHY_ACCESS);
171 udelay(30); /* It takes 30 us to read/write the data */
172 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
174 if(reg_val & PHY_RD_ERR)
184 This is the mii register read function provided to the mii interface.
186 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
188 struct amd8111e_priv* lp = netdev_priv(dev);
189 unsigned int reg_val;
191 amd8111e_read_phy(lp,phy_id,reg_num,®_val);
197 This is the mii register write function provided to the mii interface.
199 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
201 struct amd8111e_priv* lp = netdev_priv(dev);
203 amd8111e_write_phy(lp, phy_id, reg_num, val);
207 This function will set PHY speed. During initialization sets the original speed to 100 full.
209 static void amd8111e_set_ext_phy(struct net_device *dev)
211 struct amd8111e_priv *lp = netdev_priv(dev);
214 /* Determine mii register values to set the speed */
215 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
216 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
217 switch (lp->ext_phy_option){
220 case SPEED_AUTONEG: /* advertise all values */
221 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
222 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
225 tmp |= ADVERTISE_10HALF;
228 tmp |= ADVERTISE_10FULL;
231 tmp |= ADVERTISE_100HALF;
234 tmp |= ADVERTISE_100FULL;
239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
240 /* Restart auto negotiation */
241 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
242 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
243 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
248 This function will unmap skb->data space and will free
249 all transmit and receive skbuffs.
251 static int amd8111e_free_skbs(struct net_device *dev)
253 struct amd8111e_priv *lp = netdev_priv(dev);
254 struct sk_buff* rx_skbuff;
257 /* Freeing transmit skbs */
258 for(i = 0; i < NUM_TX_BUFFERS; i++){
259 if(lp->tx_skbuff[i]){
260 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
261 dev_kfree_skb (lp->tx_skbuff[i]);
262 lp->tx_skbuff[i] = NULL;
263 lp->tx_dma_addr[i] = 0;
266 /* Freeing previously allocated receive buffers */
267 for (i = 0; i < NUM_RX_BUFFERS; i++){
268 rx_skbuff = lp->rx_skbuff[i];
269 if(rx_skbuff != NULL){
270 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
271 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
272 dev_kfree_skb(lp->rx_skbuff[i]);
273 lp->rx_skbuff[i] = NULL;
274 lp->rx_dma_addr[i] = 0;
282 This will set the receive buffer length corresponding to the mtu size of networkinterface.
284 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
286 struct amd8111e_priv* lp = netdev_priv(dev);
287 unsigned int mtu = dev->mtu;
289 if (mtu > ETH_DATA_LEN){
290 /* MTU + ethernet header + FCS
291 + optional VLAN tag + skb reserve space 2 */
293 lp->rx_buff_len = mtu + ETH_HLEN + 10;
294 lp->options |= OPTION_JUMBO_ENABLE;
296 lp->rx_buff_len = PKT_BUFF_SZ;
297 lp->options &= ~OPTION_JUMBO_ENABLE;
302 This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
304 static int amd8111e_init_ring(struct net_device *dev)
306 struct amd8111e_priv *lp = netdev_priv(dev);
309 lp->rx_idx = lp->tx_idx = 0;
310 lp->tx_complete_idx = 0;
315 /* Free previously allocated transmit and receive skbs */
316 amd8111e_free_skbs(dev);
319 /* allocate the tx and rx descriptors */
320 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
321 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
322 &lp->tx_ring_dma_addr)) == NULL)
326 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
327 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
328 &lp->rx_ring_dma_addr)) == NULL)
330 goto err_free_tx_ring;
333 /* Set new receive buff size */
334 amd8111e_set_rx_buff_len(dev);
336 /* Allocating receive skbs */
337 for (i = 0; i < NUM_RX_BUFFERS; i++) {
339 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
340 /* Release previos allocated skbs */
341 for(--i; i >= 0 ;i--)
342 dev_kfree_skb(lp->rx_skbuff[i]);
343 goto err_free_rx_ring;
345 skb_reserve(lp->rx_skbuff[i],2);
347 /* Initilaizing receive descriptors */
348 for (i = 0; i < NUM_RX_BUFFERS; i++) {
349 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
350 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
352 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
353 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
355 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
358 /* Initializing transmit descriptors */
359 for (i = 0; i < NUM_TX_RING_DR; i++) {
360 lp->tx_ring[i].buff_phy_addr = 0;
361 lp->tx_ring[i].tx_flags = 0;
362 lp->tx_ring[i].buff_count = 0;
369 pci_free_consistent(lp->pci_dev,
370 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
371 lp->rx_ring_dma_addr);
375 pci_free_consistent(lp->pci_dev,
376 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
377 lp->tx_ring_dma_addr);
382 /* This function will set the interrupt coalescing according to the input arguments */
383 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
385 unsigned int timeout;
386 unsigned int event_count;
388 struct amd8111e_priv *lp = netdev_priv(dev);
389 void __iomem *mmio = lp->mmio;
390 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
396 timeout = coal_conf->rx_timeout;
397 event_count = coal_conf->rx_event_count;
398 if( timeout > MAX_TIMEOUT ||
399 event_count > MAX_EVENT_COUNT )
402 timeout = timeout * DELAY_TIMER_CONV;
403 writel(VAL0|STINTEN, mmio+INTEN0);
404 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
409 timeout = coal_conf->tx_timeout;
410 event_count = coal_conf->tx_event_count;
411 if( timeout > MAX_TIMEOUT ||
412 event_count > MAX_EVENT_COUNT )
416 timeout = timeout * DELAY_TIMER_CONV;
417 writel(VAL0|STINTEN,mmio+INTEN0);
418 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
423 writel(0,mmio+STVAL);
424 writel(STINTEN, mmio+INTEN0);
425 writel(0, mmio +DLY_INT_B);
426 writel(0, mmio+DLY_INT_A);
429 /* Start the timer */
430 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
431 writel(VAL0|STINTEN, mmio+INTEN0);
442 This function initializes the device registers and starts the device.
444 static int amd8111e_restart(struct net_device *dev)
446 struct amd8111e_priv *lp = netdev_priv(dev);
447 void __iomem *mmio = lp->mmio;
451 writel(RUN, mmio + CMD0);
453 if(amd8111e_init_ring(dev))
456 /* enable the port manager and set auto negotiation always */
457 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
458 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
460 amd8111e_set_ext_phy(dev);
462 /* set control registers */
463 reg_val = readl(mmio + CTRL1);
464 reg_val &= ~XMTSP_MASK;
465 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
467 /* enable interrupt */
468 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
469 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
470 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
472 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
474 /* initialize tx and rx ring base addresses */
475 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
476 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
478 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
479 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
481 /* set default IPG to 96 */
482 writew((u32)DEFAULT_IPG,mmio+IPG);
483 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
485 if(lp->options & OPTION_JUMBO_ENABLE){
486 writel((u32)VAL2|JUMBO, mmio + CMD3);
488 writel( REX_UFLO, mmio + CMD2);
489 /* Should not set REX_UFLO for jumbo frames */
490 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
492 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
493 writel((u32)JUMBO, mmio + CMD3);
496 #if AMD8111E_VLAN_TAG_USED
497 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
499 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
501 /* Setting the MAC address to the device */
502 for(i = 0; i < ETH_ADDR_LEN; i++)
503 writeb( dev->dev_addr[i], mmio + PADR + i );
505 /* Enable interrupt coalesce */
506 if(lp->options & OPTION_INTR_COAL_ENABLE){
507 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
509 amd8111e_set_coalesce(dev,ENABLE_COAL);
512 /* set RUN bit to start the chip */
513 writel(VAL2 | RDMD0, mmio + CMD0);
514 writel(VAL0 | INTREN | RUN, mmio + CMD0);
516 /* To avoid PCI posting bug */
521 This function clears necessary the device registers.
523 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
525 unsigned int reg_val;
526 unsigned int logic_filter[2] ={0,};
527 void __iomem *mmio = lp->mmio;
531 writel(RUN, mmio + CMD0);
533 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
534 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
536 /* Clear RCV_RING_BASE_ADDR */
537 writel(0, mmio + RCV_RING_BASE_ADDR0);
539 /* Clear XMT_RING_BASE_ADDR */
540 writel(0, mmio + XMT_RING_BASE_ADDR0);
541 writel(0, mmio + XMT_RING_BASE_ADDR1);
542 writel(0, mmio + XMT_RING_BASE_ADDR2);
543 writel(0, mmio + XMT_RING_BASE_ADDR3);
546 writel(CMD0_CLEAR,mmio + CMD0);
549 writel(CMD2_CLEAR, mmio +CMD2);
552 writel(CMD7_CLEAR , mmio + CMD7);
554 /* Clear DLY_INT_A and DLY_INT_B */
555 writel(0x0, mmio + DLY_INT_A);
556 writel(0x0, mmio + DLY_INT_B);
558 /* Clear FLOW_CONTROL */
559 writel(0x0, mmio + FLOW_CONTROL);
561 /* Clear INT0 write 1 to clear register */
562 reg_val = readl(mmio + INT0);
563 writel(reg_val, mmio + INT0);
566 writel(0x0, mmio + STVAL);
569 writel( INTEN0_CLEAR, mmio + INTEN0);
572 writel(0x0 , mmio + LADRF);
574 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
575 writel( 0x80010,mmio + SRAM_SIZE);
577 /* Clear RCV_RING0_LEN */
578 writel(0x0, mmio + RCV_RING_LEN0);
580 /* Clear XMT_RING0/1/2/3_LEN */
581 writel(0x0, mmio + XMT_RING_LEN0);
582 writel(0x0, mmio + XMT_RING_LEN1);
583 writel(0x0, mmio + XMT_RING_LEN2);
584 writel(0x0, mmio + XMT_RING_LEN3);
586 /* Clear XMT_RING_LIMIT */
587 writel(0x0, mmio + XMT_RING_LIMIT);
590 writew(MIB_CLEAR, mmio + MIB_ADDR);
593 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
595 /* SRAM_SIZE register */
596 reg_val = readl(mmio + SRAM_SIZE);
598 if(lp->options & OPTION_JUMBO_ENABLE)
599 writel( VAL2|JUMBO, mmio + CMD3);
600 #if AMD8111E_VLAN_TAG_USED
601 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
603 /* Set default value to CTRL1 Register */
604 writel(CTRL1_DEFAULT, mmio + CTRL1);
606 /* To avoid PCI posting bug */
612 This function disables the interrupt and clears all the pending
615 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
619 /* Disable interrupt */
620 writel(INTREN, lp->mmio + CMD0);
623 intr0 = readl(lp->mmio + INT0);
624 writel(intr0, lp->mmio + INT0);
626 /* To avoid PCI posting bug */
627 readl(lp->mmio + INT0);
632 This function stops the chip.
634 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
636 writel(RUN, lp->mmio + CMD0);
638 /* To avoid PCI posting bug */
639 readl(lp->mmio + CMD0);
643 This function frees the transmiter and receiver descriptor rings.
645 static void amd8111e_free_ring(struct amd8111e_priv* lp)
647 /* Free transmit and receive descriptor rings */
649 pci_free_consistent(lp->pci_dev,
650 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
651 lp->rx_ring, lp->rx_ring_dma_addr);
656 pci_free_consistent(lp->pci_dev,
657 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
658 lp->tx_ring, lp->tx_ring_dma_addr);
664 #if AMD8111E_VLAN_TAG_USED
666 This is the receive indication function for packets with vlan tag.
668 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
670 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
675 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
677 static int amd8111e_tx(struct net_device *dev)
679 struct amd8111e_priv* lp = netdev_priv(dev);
680 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
682 /* Complete all the transmit packet */
683 while (lp->tx_complete_idx != lp->tx_idx){
684 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
685 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
688 break; /* It still hasn't been Txed */
690 lp->tx_ring[tx_index].buff_phy_addr = 0;
692 /* We must free the original skb */
693 if (lp->tx_skbuff[tx_index]) {
694 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
695 lp->tx_skbuff[tx_index]->len,
697 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
698 lp->tx_skbuff[tx_index] = NULL;
699 lp->tx_dma_addr[tx_index] = 0;
701 lp->tx_complete_idx++;
702 /*COAL update tx coalescing parameters */
703 lp->coal_conf.tx_packets++;
704 lp->coal_conf.tx_bytes +=
705 le16_to_cpu(lp->tx_ring[tx_index].buff_count);
707 if (netif_queue_stopped(dev) &&
708 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
709 /* The ring is no longer full, clear tbusy. */
710 /* lp->tx_full = 0; */
711 netif_wake_queue (dev);
717 /* This function handles the driver receive operation in polling mode */
718 static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
720 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
721 struct net_device *dev = lp->amd8111e_net_dev;
722 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
723 void __iomem *mmio = lp->mmio;
724 struct sk_buff *skb,*new_skb;
725 int min_pkt_len, status;
729 #if AMD8111E_VLAN_TAG_USED
732 int rx_pkt_limit = budget;
736 /* process receive packets until we use the quota*/
737 /* If we own the next entry, it's a new packet. Send it up. */
739 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
740 if (status & OWN_BIT)
744 * There is a tricky error noted by John Murphy,
745 * <murf@perftech.com> to Russ Nelson: Even with
746 * full-sized * buffers it's possible for a
747 * jabber packet to use two buffers, with only
748 * the last correctly noting the error.
751 if(status & ERR_BIT) {
753 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
756 /* check for STP and ENP */
757 if(!((status & STP_BIT) && (status & ENP_BIT))){
759 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
762 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
764 #if AMD8111E_VLAN_TAG_USED
765 vtag = status & TT_MASK;
766 /*MAC will strip vlan tag*/
767 if(lp->vlgrp != NULL && vtag !=0)
768 min_pkt_len =MIN_PKT_LEN - 4;
771 min_pkt_len =MIN_PKT_LEN;
773 if (pkt_len < min_pkt_len) {
774 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
778 if(--rx_pkt_limit < 0)
780 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
781 /* if allocation fail,
782 ignore that pkt and go to next one */
783 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
788 skb_reserve(new_skb, 2);
789 skb = lp->rx_skbuff[rx_index];
790 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
791 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
792 skb_put(skb, pkt_len);
793 lp->rx_skbuff[rx_index] = new_skb;
794 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
799 skb->protocol = eth_type_trans(skb, dev);
801 #if AMD8111E_VLAN_TAG_USED
802 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
803 amd8111e_vlan_rx(lp, skb,
804 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
807 netif_receive_skb(skb);
808 /*COAL update rx coalescing parameters*/
809 lp->coal_conf.rx_packets++;
810 lp->coal_conf.rx_bytes += pkt_len;
814 lp->rx_ring[rx_index].buff_phy_addr
815 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
816 lp->rx_ring[rx_index].buff_count =
817 cpu_to_le16(lp->rx_buff_len-2);
819 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
820 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
822 /* Check the interrupt status register for more packets in the
823 mean time. Process them since we have not used up our quota.*/
825 intr0 = readl(mmio + INT0);
826 /*Ack receive packets */
827 writel(intr0 & RINT0,mmio + INT0);
829 } while(intr0 & RINT0);
831 if (rx_pkt_limit > 0) {
832 /* Receive descriptor is empty now */
833 spin_lock_irqsave(&lp->lock, flags);
834 __napi_complete(napi);
835 writel(VAL0|RINTEN0, mmio + INTEN0);
836 writel(VAL2 | RDMD0, mmio + CMD0);
837 spin_unlock_irqrestore(&lp->lock, flags);
845 This function will indicate the link status to the kernel.
847 static int amd8111e_link_change(struct net_device* dev)
849 struct amd8111e_priv *lp = netdev_priv(dev);
852 /* read the link change */
853 status0 = readl(lp->mmio + STAT0);
855 if(status0 & LINK_STATS){
856 if(status0 & AUTONEG_COMPLETE)
857 lp->link_config.autoneg = AUTONEG_ENABLE;
859 lp->link_config.autoneg = AUTONEG_DISABLE;
861 if(status0 & FULL_DPLX)
862 lp->link_config.duplex = DUPLEX_FULL;
864 lp->link_config.duplex = DUPLEX_HALF;
865 speed = (status0 & SPEED_MASK) >> 7;
866 if(speed == PHY_SPEED_10)
867 lp->link_config.speed = SPEED_10;
868 else if(speed == PHY_SPEED_100)
869 lp->link_config.speed = SPEED_100;
871 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
872 (lp->link_config.speed == SPEED_100) ? "100": "10",
873 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
874 netif_carrier_on(dev);
877 lp->link_config.speed = SPEED_INVALID;
878 lp->link_config.duplex = DUPLEX_INVALID;
879 lp->link_config.autoneg = AUTONEG_INVALID;
880 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
881 netif_carrier_off(dev);
887 This function reads the mib counters.
889 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
893 unsigned int repeat = REPEAT_CNT;
895 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
897 status = readw(mmio + MIB_ADDR);
898 udelay(2); /* controller takes MAX 2 us to get mib data */
900 while (--repeat && (status & MIB_CMD_ACTIVE));
902 data = readl(mmio + MIB_DATA);
907 This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
909 static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
911 struct amd8111e_priv *lp = netdev_priv(dev);
912 void __iomem *mmio = lp->mmio;
914 /* struct net_device_stats *prev_stats = &lp->prev_stats; */
915 struct net_device_stats* new_stats = &lp->stats;
919 spin_lock_irqsave (&lp->lock, flags);
921 /* stats.rx_packets */
922 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
923 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
924 amd8111e_read_mib(mmio, rcv_unicast_pkts);
926 /* stats.tx_packets */
927 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
930 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
933 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
935 /* stats.rx_errors */
936 /* hw errors + errors driver reported */
937 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
938 amd8111e_read_mib(mmio, rcv_fragments)+
939 amd8111e_read_mib(mmio, rcv_jabbers)+
940 amd8111e_read_mib(mmio, rcv_alignment_errors)+
941 amd8111e_read_mib(mmio, rcv_fcs_errors)+
942 amd8111e_read_mib(mmio, rcv_miss_pkts)+
945 /* stats.tx_errors */
946 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
948 /* stats.rx_dropped*/
949 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
951 /* stats.tx_dropped*/
952 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
955 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
957 /* stats.collisions*/
958 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
960 /* stats.rx_length_errors*/
961 new_stats->rx_length_errors =
962 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
963 amd8111e_read_mib(mmio, rcv_oversize_pkts);
965 /* stats.rx_over_errors*/
966 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
968 /* stats.rx_crc_errors*/
969 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
971 /* stats.rx_frame_errors*/
972 new_stats->rx_frame_errors =
973 amd8111e_read_mib(mmio, rcv_alignment_errors);
975 /* stats.rx_fifo_errors */
976 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
978 /* stats.rx_missed_errors */
979 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
981 /* stats.tx_aborted_errors*/
982 new_stats->tx_aborted_errors =
983 amd8111e_read_mib(mmio, xmt_excessive_collision);
985 /* stats.tx_carrier_errors*/
986 new_stats->tx_carrier_errors =
987 amd8111e_read_mib(mmio, xmt_loss_carrier);
989 /* stats.tx_fifo_errors*/
990 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
992 /* stats.tx_window_errors*/
993 new_stats->tx_window_errors =
994 amd8111e_read_mib(mmio, xmt_late_collision);
996 /* Reset the mibs for collecting new statistics */
997 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
999 spin_unlock_irqrestore (&lp->lock, flags);
1003 /* This function recalculate the interrupt coalescing mode on every interrupt
1004 according to the datarate and the packet rate.
1006 static int amd8111e_calc_coalesce(struct net_device *dev)
1008 struct amd8111e_priv *lp = netdev_priv(dev);
1009 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1017 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1018 coal_conf->tx_prev_packets = coal_conf->tx_packets;
1020 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1021 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
1023 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1024 coal_conf->rx_prev_packets = coal_conf->rx_packets;
1026 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1027 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
1029 if(rx_pkt_rate < 800){
1030 if(coal_conf->rx_coal_type != NO_COALESCE){
1032 coal_conf->rx_timeout = 0x0;
1033 coal_conf->rx_event_count = 0;
1034 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1035 coal_conf->rx_coal_type = NO_COALESCE;
1040 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1041 if (rx_pkt_size < 128){
1042 if(coal_conf->rx_coal_type != NO_COALESCE){
1044 coal_conf->rx_timeout = 0;
1045 coal_conf->rx_event_count = 0;
1046 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1047 coal_conf->rx_coal_type = NO_COALESCE;
1051 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1053 if(coal_conf->rx_coal_type != LOW_COALESCE){
1054 coal_conf->rx_timeout = 1;
1055 coal_conf->rx_event_count = 4;
1056 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1057 coal_conf->rx_coal_type = LOW_COALESCE;
1060 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1062 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1063 coal_conf->rx_timeout = 1;
1064 coal_conf->rx_event_count = 4;
1065 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1066 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1070 else if(rx_pkt_size >= 1024){
1071 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1072 coal_conf->rx_timeout = 2;
1073 coal_conf->rx_event_count = 3;
1074 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1075 coal_conf->rx_coal_type = HIGH_COALESCE;
1079 /* NOW FOR TX INTR COALESC */
1080 if(tx_pkt_rate < 800){
1081 if(coal_conf->tx_coal_type != NO_COALESCE){
1083 coal_conf->tx_timeout = 0x0;
1084 coal_conf->tx_event_count = 0;
1085 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1086 coal_conf->tx_coal_type = NO_COALESCE;
1091 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1092 if (tx_pkt_size < 128){
1094 if(coal_conf->tx_coal_type != NO_COALESCE){
1096 coal_conf->tx_timeout = 0;
1097 coal_conf->tx_event_count = 0;
1098 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1099 coal_conf->tx_coal_type = NO_COALESCE;
1103 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1105 if(coal_conf->tx_coal_type != LOW_COALESCE){
1106 coal_conf->tx_timeout = 1;
1107 coal_conf->tx_event_count = 2;
1108 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1109 coal_conf->tx_coal_type = LOW_COALESCE;
1113 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1115 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1116 coal_conf->tx_timeout = 2;
1117 coal_conf->tx_event_count = 5;
1118 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1119 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1123 else if(tx_pkt_size >= 1024){
1124 if (tx_pkt_size >= 1024){
1125 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1126 coal_conf->tx_timeout = 4;
1127 coal_conf->tx_event_count = 8;
1128 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1129 coal_conf->tx_coal_type = HIGH_COALESCE;
1138 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1140 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1143 struct net_device * dev = (struct net_device *) dev_id;
1144 struct amd8111e_priv *lp = netdev_priv(dev);
1145 void __iomem *mmio = lp->mmio;
1146 unsigned int intr0, intren0;
1147 unsigned int handled = 1;
1149 if(unlikely(dev == NULL))
1152 spin_lock(&lp->lock);
1154 /* disabling interrupt */
1155 writel(INTREN, mmio + CMD0);
1157 /* Read interrupt status */
1158 intr0 = readl(mmio + INT0);
1159 intren0 = readl(mmio + INTEN0);
1161 /* Process all the INT event until INTR bit is clear. */
1163 if (!(intr0 & INTR)){
1165 goto err_no_interrupt;
1168 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1169 writel(intr0, mmio + INT0);
1171 /* Check if Receive Interrupt has occurred. */
1172 if (intr0 & RINT0) {
1173 if (napi_schedule_prep(&lp->napi)) {
1174 /* Disable receive interupts */
1175 writel(RINTEN0, mmio + INTEN0);
1176 /* Schedule a polling routine */
1177 __napi_schedule(&lp->napi);
1178 } else if (intren0 & RINTEN0) {
1179 printk("************Driver bug! interrupt while in poll\n");
1180 /* Fix by disable receive interrupts */
1181 writel(RINTEN0, mmio + INTEN0);
1185 /* Check if Transmit Interrupt has occurred. */
1189 /* Check if Link Change Interrupt has occurred. */
1191 amd8111e_link_change(dev);
1193 /* Check if Hardware Timer Interrupt has occurred. */
1195 amd8111e_calc_coalesce(dev);
1198 writel( VAL0 | INTREN,mmio + CMD0);
1200 spin_unlock(&lp->lock);
1202 return IRQ_RETVAL(handled);
1205 #ifdef CONFIG_NET_POLL_CONTROLLER
1206 static void amd8111e_poll(struct net_device *dev)
1208 unsigned long flags;
1209 local_irq_save(flags);
1210 amd8111e_interrupt(0, dev);
1211 local_irq_restore(flags);
1217 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1219 static int amd8111e_close(struct net_device * dev)
1221 struct amd8111e_priv *lp = netdev_priv(dev);
1222 netif_stop_queue(dev);
1224 napi_disable(&lp->napi);
1226 spin_lock_irq(&lp->lock);
1228 amd8111e_disable_interrupt(lp);
1229 amd8111e_stop_chip(lp);
1231 /* Free transmit and receive skbs */
1232 amd8111e_free_skbs(lp->amd8111e_net_dev);
1234 netif_carrier_off(lp->amd8111e_net_dev);
1236 /* Delete ipg timer */
1237 if(lp->options & OPTION_DYN_IPG_ENABLE)
1238 del_timer_sync(&lp->ipg_data.ipg_timer);
1240 spin_unlock_irq(&lp->lock);
1241 free_irq(dev->irq, dev);
1242 amd8111e_free_ring(lp);
1244 /* Update the statistics before closing */
1245 amd8111e_get_stats(dev);
1249 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1251 static int amd8111e_open(struct net_device * dev )
1253 struct amd8111e_priv *lp = netdev_priv(dev);
1255 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
1259 napi_enable(&lp->napi);
1261 spin_lock_irq(&lp->lock);
1263 amd8111e_init_hw_default(lp);
1265 if(amd8111e_restart(dev)){
1266 spin_unlock_irq(&lp->lock);
1267 napi_disable(&lp->napi);
1269 free_irq(dev->irq, dev);
1272 /* Start ipg timer */
1273 if(lp->options & OPTION_DYN_IPG_ENABLE){
1274 add_timer(&lp->ipg_data.ipg_timer);
1275 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1280 spin_unlock_irq(&lp->lock);
1282 netif_start_queue(dev);
1287 This function checks if there is any transmit descriptors available to queue more packet.
1289 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1291 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1292 if (lp->tx_skbuff[tx_index])
1299 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1302 static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1303 struct net_device * dev)
1305 struct amd8111e_priv *lp = netdev_priv(dev);
1307 unsigned long flags;
1309 spin_lock_irqsave(&lp->lock, flags);
1311 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1313 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1315 lp->tx_skbuff[tx_index] = skb;
1316 lp->tx_ring[tx_index].tx_flags = 0;
1318 #if AMD8111E_VLAN_TAG_USED
1319 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
1320 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1321 cpu_to_le16(TCC_VLAN_INSERT);
1322 lp->tx_ring[tx_index].tag_ctrl_info =
1323 cpu_to_le16(vlan_tx_tag_get(skb));
1327 lp->tx_dma_addr[tx_index] =
1328 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1329 lp->tx_ring[tx_index].buff_phy_addr =
1330 cpu_to_le32(lp->tx_dma_addr[tx_index]);
1332 /* Set FCS and LTINT bits */
1334 lp->tx_ring[tx_index].tx_flags |=
1335 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1339 /* Trigger an immediate send poll. */
1340 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1341 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1343 dev->trans_start = jiffies;
1345 if(amd8111e_tx_queue_avail(lp) < 0){
1346 netif_stop_queue(dev);
1348 spin_unlock_irqrestore(&lp->lock, flags);
1349 return NETDEV_TX_OK;
1352 This function returns all the memory mapped registers of the device.
1354 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1356 void __iomem *mmio = lp->mmio;
1357 /* Read only necessary registers */
1358 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1359 buf[1] = readl(mmio + XMT_RING_LEN0);
1360 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1361 buf[3] = readl(mmio + RCV_RING_LEN0);
1362 buf[4] = readl(mmio + CMD0);
1363 buf[5] = readl(mmio + CMD2);
1364 buf[6] = readl(mmio + CMD3);
1365 buf[7] = readl(mmio + CMD7);
1366 buf[8] = readl(mmio + INT0);
1367 buf[9] = readl(mmio + INTEN0);
1368 buf[10] = readl(mmio + LADRF);
1369 buf[11] = readl(mmio + LADRF+4);
1370 buf[12] = readl(mmio + STAT0);
1375 This function sets promiscuos mode, all-multi mode or the multicast address
1378 static void amd8111e_set_multicast_list(struct net_device *dev)
1380 struct dev_mc_list* mc_ptr;
1381 struct amd8111e_priv *lp = netdev_priv(dev);
1384 if(dev->flags & IFF_PROMISC){
1385 writel( VAL2 | PROM, lp->mmio + CMD2);
1389 writel( PROM, lp->mmio + CMD2);
1390 if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1391 /* get all multicast packet */
1392 mc_filter[1] = mc_filter[0] = 0xffffffff;
1393 lp->mc_list = dev->mc_list;
1394 lp->options |= OPTION_MULTICAST_ENABLE;
1395 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1398 if( dev->mc_count == 0 ){
1399 /* get only own packets */
1400 mc_filter[1] = mc_filter[0] = 0;
1402 lp->options &= ~OPTION_MULTICAST_ENABLE;
1403 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1404 /* disable promiscous mode */
1405 writel(PROM, lp->mmio + CMD2);
1408 /* load all the multicast addresses in the logic filter */
1409 lp->options |= OPTION_MULTICAST_ENABLE;
1410 lp->mc_list = dev->mc_list;
1411 mc_filter[1] = mc_filter[0] = 0;
1412 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1413 i++, mc_ptr = mc_ptr->next) {
1414 bit_num = (ether_crc_le(ETH_ALEN, mc_ptr->dmi_addr) >> 26) & 0x3f;
1415 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1417 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1419 /* To eliminate PCI posting bug */
1420 readl(lp->mmio + CMD2);
1424 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1426 struct amd8111e_priv *lp = netdev_priv(dev);
1427 struct pci_dev *pci_dev = lp->pci_dev;
1428 strcpy (info->driver, MODULE_NAME);
1429 strcpy (info->version, MODULE_VERS);
1430 sprintf(info->fw_version,"%u",chip_version);
1431 strcpy (info->bus_info, pci_name(pci_dev));
1434 static int amd8111e_get_regs_len(struct net_device *dev)
1436 return AMD8111E_REG_DUMP_LEN;
1439 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1441 struct amd8111e_priv *lp = netdev_priv(dev);
1443 amd8111e_read_regs(lp, buf);
1446 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1448 struct amd8111e_priv *lp = netdev_priv(dev);
1449 spin_lock_irq(&lp->lock);
1450 mii_ethtool_gset(&lp->mii_if, ecmd);
1451 spin_unlock_irq(&lp->lock);
1455 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1457 struct amd8111e_priv *lp = netdev_priv(dev);
1459 spin_lock_irq(&lp->lock);
1460 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1461 spin_unlock_irq(&lp->lock);
1465 static int amd8111e_nway_reset(struct net_device *dev)
1467 struct amd8111e_priv *lp = netdev_priv(dev);
1468 return mii_nway_restart(&lp->mii_if);
1471 static u32 amd8111e_get_link(struct net_device *dev)
1473 struct amd8111e_priv *lp = netdev_priv(dev);
1474 return mii_link_ok(&lp->mii_if);
1477 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1479 struct amd8111e_priv *lp = netdev_priv(dev);
1480 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1481 if (lp->options & OPTION_WOL_ENABLE)
1482 wol_info->wolopts = WAKE_MAGIC;
1485 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1487 struct amd8111e_priv *lp = netdev_priv(dev);
1488 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1490 spin_lock_irq(&lp->lock);
1491 if (wol_info->wolopts & WAKE_MAGIC)
1493 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1494 else if(wol_info->wolopts & WAKE_PHY)
1496 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1498 lp->options &= ~OPTION_WOL_ENABLE;
1499 spin_unlock_irq(&lp->lock);
1503 static const struct ethtool_ops ops = {
1504 .get_drvinfo = amd8111e_get_drvinfo,
1505 .get_regs_len = amd8111e_get_regs_len,
1506 .get_regs = amd8111e_get_regs,
1507 .get_settings = amd8111e_get_settings,
1508 .set_settings = amd8111e_set_settings,
1509 .nway_reset = amd8111e_nway_reset,
1510 .get_link = amd8111e_get_link,
1511 .get_wol = amd8111e_get_wol,
1512 .set_wol = amd8111e_set_wol,
1516 This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1519 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1521 struct mii_ioctl_data *data = if_mii(ifr);
1522 struct amd8111e_priv *lp = netdev_priv(dev);
1528 data->phy_id = lp->ext_phy_addr;
1533 spin_lock_irq(&lp->lock);
1534 err = amd8111e_read_phy(lp, data->phy_id,
1535 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1536 spin_unlock_irq(&lp->lock);
1538 data->val_out = mii_regval;
1543 spin_lock_irq(&lp->lock);
1544 err = amd8111e_write_phy(lp, data->phy_id,
1545 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1546 spin_unlock_irq(&lp->lock);
1556 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1558 struct amd8111e_priv *lp = netdev_priv(dev);
1560 struct sockaddr *addr = p;
1562 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1563 spin_lock_irq(&lp->lock);
1564 /* Setting the MAC address to the device */
1565 for(i = 0; i < ETH_ADDR_LEN; i++)
1566 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1568 spin_unlock_irq(&lp->lock);
1574 This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
1576 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1578 struct amd8111e_priv *lp = netdev_priv(dev);
1581 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1584 if (!netif_running(dev)) {
1585 /* new_mtu will be used
1586 when device starts netxt time */
1591 spin_lock_irq(&lp->lock);
1594 writel(RUN, lp->mmio + CMD0);
1598 err = amd8111e_restart(dev);
1599 spin_unlock_irq(&lp->lock);
1601 netif_start_queue(dev);
1605 #if AMD8111E_VLAN_TAG_USED
1606 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1608 struct amd8111e_priv *lp = netdev_priv(dev);
1609 spin_lock_irq(&lp->lock);
1611 spin_unlock_irq(&lp->lock);
1615 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1617 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1618 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1620 /* To eliminate PCI posting bug */
1621 readl(lp->mmio + CMD7);
1625 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1628 /* Adapter is already stoped/suspended/interrupt-disabled */
1629 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1631 /* To eliminate PCI posting bug */
1632 readl(lp->mmio + CMD7);
1637 * This function is called when a packet transmission fails to complete
1638 * within a reasonable period, on the assumption that an interrupt have
1639 * failed or the interface is locked up. This function will reinitialize
1642 static void amd8111e_tx_timeout(struct net_device *dev)
1644 struct amd8111e_priv* lp = netdev_priv(dev);
1647 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1649 spin_lock_irq(&lp->lock);
1650 err = amd8111e_restart(dev);
1651 spin_unlock_irq(&lp->lock);
1653 netif_wake_queue(dev);
1655 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
1657 struct net_device *dev = pci_get_drvdata(pci_dev);
1658 struct amd8111e_priv *lp = netdev_priv(dev);
1660 if (!netif_running(dev))
1663 /* disable the interrupt */
1664 spin_lock_irq(&lp->lock);
1665 amd8111e_disable_interrupt(lp);
1666 spin_unlock_irq(&lp->lock);
1668 netif_device_detach(dev);
1671 spin_lock_irq(&lp->lock);
1672 if(lp->options & OPTION_DYN_IPG_ENABLE)
1673 del_timer_sync(&lp->ipg_data.ipg_timer);
1674 amd8111e_stop_chip(lp);
1675 spin_unlock_irq(&lp->lock);
1677 if(lp->options & OPTION_WOL_ENABLE){
1679 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1680 amd8111e_enable_magicpkt(lp);
1681 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1682 amd8111e_enable_link_change(lp);
1684 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1685 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1689 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1690 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1693 pci_save_state(pci_dev);
1694 pci_set_power_state(pci_dev, PCI_D3hot);
1698 static int amd8111e_resume(struct pci_dev *pci_dev)
1700 struct net_device *dev = pci_get_drvdata(pci_dev);
1701 struct amd8111e_priv *lp = netdev_priv(dev);
1703 if (!netif_running(dev))
1706 pci_set_power_state(pci_dev, PCI_D0);
1707 pci_restore_state(pci_dev);
1709 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1710 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1712 netif_device_attach(dev);
1714 spin_lock_irq(&lp->lock);
1715 amd8111e_restart(dev);
1716 /* Restart ipg timer */
1717 if(lp->options & OPTION_DYN_IPG_ENABLE)
1718 mod_timer(&lp->ipg_data.ipg_timer,
1719 jiffies + IPG_CONVERGE_JIFFIES);
1720 spin_unlock_irq(&lp->lock);
1726 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1728 struct net_device *dev = pci_get_drvdata(pdev);
1730 unregister_netdev(dev);
1731 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1733 pci_release_regions(pdev);
1734 pci_disable_device(pdev);
1735 pci_set_drvdata(pdev, NULL);
1738 static void amd8111e_config_ipg(struct net_device* dev)
1740 struct amd8111e_priv *lp = netdev_priv(dev);
1741 struct ipg_info* ipg_data = &lp->ipg_data;
1742 void __iomem *mmio = lp->mmio;
1743 unsigned int prev_col_cnt = ipg_data->col_cnt;
1744 unsigned int total_col_cnt;
1745 unsigned int tmp_ipg;
1747 if(lp->link_config.duplex == DUPLEX_FULL){
1748 ipg_data->ipg = DEFAULT_IPG;
1752 if(ipg_data->ipg_state == SSTATE){
1754 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1756 ipg_data->timer_tick = 0;
1757 ipg_data->ipg = MIN_IPG - IPG_STEP;
1758 ipg_data->current_ipg = MIN_IPG;
1759 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1760 ipg_data->ipg_state = CSTATE;
1763 ipg_data->timer_tick++;
1766 if(ipg_data->ipg_state == CSTATE){
1768 /* Get the current collision count */
1770 total_col_cnt = ipg_data->col_cnt =
1771 amd8111e_read_mib(mmio, xmt_collisions);
1773 if ((total_col_cnt - prev_col_cnt) <
1774 (ipg_data->diff_col_cnt)){
1776 ipg_data->diff_col_cnt =
1777 total_col_cnt - prev_col_cnt ;
1779 ipg_data->ipg = ipg_data->current_ipg;
1782 ipg_data->current_ipg += IPG_STEP;
1784 if (ipg_data->current_ipg <= MAX_IPG)
1785 tmp_ipg = ipg_data->current_ipg;
1787 tmp_ipg = ipg_data->ipg;
1788 ipg_data->ipg_state = SSTATE;
1790 writew((u32)tmp_ipg, mmio + IPG);
1791 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1793 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1798 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1800 struct amd8111e_priv *lp = netdev_priv(dev);
1803 for (i = 0x1e; i >= 0; i--) {
1806 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1808 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1810 lp->ext_phy_id = (id1 << 16) | id2;
1811 lp->ext_phy_addr = i;
1815 lp->ext_phy_addr = 1;
1818 static const struct net_device_ops amd8111e_netdev_ops = {
1819 .ndo_open = amd8111e_open,
1820 .ndo_stop = amd8111e_close,
1821 .ndo_start_xmit = amd8111e_start_xmit,
1822 .ndo_tx_timeout = amd8111e_tx_timeout,
1823 .ndo_get_stats = amd8111e_get_stats,
1824 .ndo_set_multicast_list = amd8111e_set_multicast_list,
1825 .ndo_validate_addr = eth_validate_addr,
1826 .ndo_set_mac_address = amd8111e_set_mac_address,
1827 .ndo_do_ioctl = amd8111e_ioctl,
1828 .ndo_change_mtu = amd8111e_change_mtu,
1829 #if AMD8111E_VLAN_TAG_USED
1830 .ndo_vlan_rx_register = amd8111e_vlan_rx_register,
1832 #ifdef CONFIG_NET_POLL_CONTROLLER
1833 .ndo_poll_controller = amd8111e_poll,
1837 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1838 const struct pci_device_id *ent)
1841 unsigned long reg_addr,reg_len;
1842 struct amd8111e_priv* lp;
1843 struct net_device* dev;
1845 err = pci_enable_device(pdev);
1847 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, "
1852 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1853 printk(KERN_ERR "amd8111e: Cannot find PCI base address, "
1856 goto err_disable_pdev;
1859 err = pci_request_regions(pdev, MODULE_NAME);
1861 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1863 goto err_disable_pdev;
1866 pci_set_master(pdev);
1868 /* Find power-management capability. */
1869 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1870 printk(KERN_ERR "amd8111e: No Power Management capability, "
1875 /* Initialize DMA */
1876 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) {
1877 printk(KERN_ERR "amd8111e: DMA not supported,"
1882 reg_addr = pci_resource_start(pdev, 0);
1883 reg_len = pci_resource_len(pdev, 0);
1885 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1887 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1892 SET_NETDEV_DEV(dev, &pdev->dev);
1894 #if AMD8111E_VLAN_TAG_USED
1895 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
1898 lp = netdev_priv(dev);
1900 lp->amd8111e_net_dev = dev;
1901 lp->pm_cap = pm_cap;
1903 spin_lock_init(&lp->lock);
1905 lp->mmio = ioremap(reg_addr, reg_len);
1907 printk(KERN_ERR "amd8111e: Cannot map device registers, "
1913 /* Initializing MAC address */
1914 for(i = 0; i < ETH_ADDR_LEN; i++)
1915 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
1917 /* Setting user defined parametrs */
1918 lp->ext_phy_option = speed_duplex[card_idx];
1919 if(coalesce[card_idx])
1920 lp->options |= OPTION_INTR_COAL_ENABLE;
1921 if(dynamic_ipg[card_idx++])
1922 lp->options |= OPTION_DYN_IPG_ENABLE;
1925 /* Initialize driver entry points */
1926 dev->netdev_ops = &amd8111e_netdev_ops;
1927 SET_ETHTOOL_OPS(dev, &ops);
1928 dev->irq =pdev->irq;
1929 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1930 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1932 #if AMD8111E_VLAN_TAG_USED
1933 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1935 /* Probe the external PHY */
1936 amd8111e_probe_ext_phy(dev);
1938 /* setting mii default values */
1939 lp->mii_if.dev = dev;
1940 lp->mii_if.mdio_read = amd8111e_mdio_read;
1941 lp->mii_if.mdio_write = amd8111e_mdio_write;
1942 lp->mii_if.phy_id = lp->ext_phy_addr;
1944 /* Set receive buffer length and set jumbo option*/
1945 amd8111e_set_rx_buff_len(dev);
1948 err = register_netdev(dev);
1950 printk(KERN_ERR "amd8111e: Cannot register net device, "
1955 pci_set_drvdata(pdev, dev);
1957 /* Initialize software ipg timer */
1958 if(lp->options & OPTION_DYN_IPG_ENABLE){
1959 init_timer(&lp->ipg_data.ipg_timer);
1960 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
1961 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
1962 lp->ipg_data.ipg_timer.expires = jiffies +
1963 IPG_CONVERGE_JIFFIES;
1964 lp->ipg_data.ipg = DEFAULT_IPG;
1965 lp->ipg_data.ipg_state = CSTATE;
1968 /* display driver and device information */
1970 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
1971 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",
1972 dev->name,MODULE_VERS);
1973 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1974 dev->name, chip_version, dev->dev_addr);
1976 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
1977 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
1979 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
1989 pci_release_regions(pdev);
1992 pci_disable_device(pdev);
1993 pci_set_drvdata(pdev, NULL);
1998 static struct pci_driver amd8111e_driver = {
1999 .name = MODULE_NAME,
2000 .id_table = amd8111e_pci_tbl,
2001 .probe = amd8111e_probe_one,
2002 .remove = __devexit_p(amd8111e_remove_one),
2003 .suspend = amd8111e_suspend,
2004 .resume = amd8111e_resume
2007 static int __init amd8111e_init(void)
2009 return pci_register_driver(&amd8111e_driver);
2012 static void __exit amd8111e_cleanup(void)
2014 pci_unregister_driver(&amd8111e_driver);
2017 module_init(amd8111e_init);
2018 module_exit(amd8111e_cleanup);