2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/mii.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/init.h>
22 #include <linux/moduleparam.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
27 #include <mach/hardware.h>
29 #define DRV_MODULE_NAME "ep93xx-eth"
30 #define DRV_MODULE_VERSION "0.1"
32 #define RX_QUEUE_ENTRIES 64
33 #define TX_QUEUE_ENTRIES 8
35 #define MAX_PKT_SIZE 2044
36 #define PKT_BUF_SIZE 2048
38 #define REG_RXCTL 0x0000
39 #define REG_RXCTL_DEFAULT 0x00073800
40 #define REG_TXCTL 0x0004
41 #define REG_TXCTL_ENABLE 0x00000001
42 #define REG_MIICMD 0x0010
43 #define REG_MIICMD_READ 0x00008000
44 #define REG_MIICMD_WRITE 0x00004000
45 #define REG_MIIDATA 0x0014
46 #define REG_MIISTS 0x0018
47 #define REG_MIISTS_BUSY 0x00000001
48 #define REG_SELFCTL 0x0020
49 #define REG_SELFCTL_RESET 0x00000001
50 #define REG_INTEN 0x0024
51 #define REG_INTEN_TX 0x00000008
52 #define REG_INTEN_RX 0x00000007
53 #define REG_INTSTSP 0x0028
54 #define REG_INTSTS_TX 0x00000008
55 #define REG_INTSTS_RX 0x00000004
56 #define REG_INTSTSC 0x002c
57 #define REG_AFP 0x004c
58 #define REG_INDAD0 0x0050
59 #define REG_INDAD1 0x0051
60 #define REG_INDAD2 0x0052
61 #define REG_INDAD3 0x0053
62 #define REG_INDAD4 0x0054
63 #define REG_INDAD5 0x0055
64 #define REG_GIINTMSK 0x0064
65 #define REG_GIINTMSK_ENABLE 0x00008000
66 #define REG_BMCTL 0x0080
67 #define REG_BMCTL_ENABLE_TX 0x00000100
68 #define REG_BMCTL_ENABLE_RX 0x00000001
69 #define REG_BMSTS 0x0084
70 #define REG_BMSTS_RX_ACTIVE 0x00000008
71 #define REG_RXDQBADD 0x0090
72 #define REG_RXDQBLEN 0x0094
73 #define REG_RXDCURADD 0x0098
74 #define REG_RXDENQ 0x009c
75 #define REG_RXSTSQBADD 0x00a0
76 #define REG_RXSTSQBLEN 0x00a4
77 #define REG_RXSTSQCURADD 0x00a8
78 #define REG_RXSTSENQ 0x00ac
79 #define REG_TXDQBADD 0x00b0
80 #define REG_TXDQBLEN 0x00b4
81 #define REG_TXDQCURADD 0x00b8
82 #define REG_TXDENQ 0x00bc
83 #define REG_TXSTSQBADD 0x00c0
84 #define REG_TXSTSQBLEN 0x00c4
85 #define REG_TXSTSQCURADD 0x00c8
86 #define REG_MAXFRMLEN 0x00e8
94 #define RDESC1_NSOF 0x80000000
95 #define RDESC1_BUFFER_INDEX 0x7fff0000
96 #define RDESC1_BUFFER_LENGTH 0x0000ffff
104 #define RSTAT0_RFP 0x80000000
105 #define RSTAT0_RWE 0x40000000
106 #define RSTAT0_EOF 0x20000000
107 #define RSTAT0_EOB 0x10000000
108 #define RSTAT0_AM 0x00c00000
109 #define RSTAT0_RX_ERR 0x00200000
110 #define RSTAT0_OE 0x00100000
111 #define RSTAT0_FE 0x00080000
112 #define RSTAT0_RUNT 0x00040000
113 #define RSTAT0_EDATA 0x00020000
114 #define RSTAT0_CRCE 0x00010000
115 #define RSTAT0_CRCI 0x00008000
116 #define RSTAT0_HTI 0x00003f00
117 #define RSTAT1_RFP 0x80000000
118 #define RSTAT1_BUFFER_INDEX 0x7fff0000
119 #define RSTAT1_FRAME_LENGTH 0x0000ffff
127 #define TDESC1_EOF 0x80000000
128 #define TDESC1_BUFFER_INDEX 0x7fff0000
129 #define TDESC1_BUFFER_ABORT 0x00008000
130 #define TDESC1_BUFFER_LENGTH 0x00000fff
137 #define TSTAT0_TXFP 0x80000000
138 #define TSTAT0_TXWE 0x40000000
139 #define TSTAT0_FA 0x20000000
140 #define TSTAT0_LCRS 0x10000000
141 #define TSTAT0_OW 0x04000000
142 #define TSTAT0_TXU 0x02000000
143 #define TSTAT0_ECOLL 0x01000000
144 #define TSTAT0_NCOLL 0x001f0000
145 #define TSTAT0_BUFFER_INDEX 0x00007fff
149 struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
150 struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
151 struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
152 struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
157 struct resource *res;
158 void __iomem *base_addr;
161 struct ep93xx_descs *descs;
162 dma_addr_t descs_dma_addr;
164 void *rx_buf[RX_QUEUE_ENTRIES];
165 void *tx_buf[TX_QUEUE_ENTRIES];
168 unsigned int rx_pointer;
169 unsigned int tx_clean_pointer;
170 unsigned int tx_pointer;
171 spinlock_t tx_pending_lock;
172 unsigned int tx_pending;
174 struct net_device *dev;
175 struct napi_struct napi;
177 struct net_device_stats stats;
179 struct mii_if_info mii;
183 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
184 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
185 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
186 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
187 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
188 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
190 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
192 struct ep93xx_priv *ep = netdev_priv(dev);
196 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
198 for (i = 0; i < 10; i++) {
199 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
205 pr_info("mdio read timed out\n");
208 data = rdl(ep, REG_MIIDATA);
214 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
216 struct ep93xx_priv *ep = netdev_priv(dev);
219 wrl(ep, REG_MIIDATA, data);
220 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
222 for (i = 0; i < 10; i++) {
223 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
229 pr_info("mdio write timed out\n");
232 static struct net_device_stats *ep93xx_get_stats(struct net_device *dev)
234 struct ep93xx_priv *ep = netdev_priv(dev);
238 static int ep93xx_rx(struct net_device *dev, int processed, int budget)
240 struct ep93xx_priv *ep = netdev_priv(dev);
242 while (processed < budget) {
244 struct ep93xx_rstat *rstat;
250 entry = ep->rx_pointer;
251 rstat = ep->descs->rstat + entry;
253 rstat0 = rstat->rstat0;
254 rstat1 = rstat->rstat1;
255 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
261 if (!(rstat0 & RSTAT0_EOF))
262 pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
263 if (!(rstat0 & RSTAT0_EOB))
264 pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
265 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
266 pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
268 if (!(rstat0 & RSTAT0_RWE)) {
269 ep->stats.rx_errors++;
270 if (rstat0 & RSTAT0_OE)
271 ep->stats.rx_fifo_errors++;
272 if (rstat0 & RSTAT0_FE)
273 ep->stats.rx_frame_errors++;
274 if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
275 ep->stats.rx_length_errors++;
276 if (rstat0 & RSTAT0_CRCE)
277 ep->stats.rx_crc_errors++;
281 length = rstat1 & RSTAT1_FRAME_LENGTH;
282 if (length > MAX_PKT_SIZE) {
283 pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
288 if (rstat0 & RSTAT0_CRCI)
291 skb = dev_alloc_skb(length + 2);
292 if (likely(skb != NULL)) {
294 dma_sync_single_for_cpu(NULL, ep->descs->rdesc[entry].buf_addr,
295 length, DMA_FROM_DEVICE);
296 skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
297 skb_put(skb, length);
298 skb->protocol = eth_type_trans(skb, dev);
300 netif_receive_skb(skb);
302 ep->stats.rx_packets++;
303 ep->stats.rx_bytes += length;
305 ep->stats.rx_dropped++;
309 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
314 wrw(ep, REG_RXDENQ, processed);
315 wrw(ep, REG_RXSTSENQ, processed);
321 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
323 struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
324 return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
327 static int ep93xx_poll(struct napi_struct *napi, int budget)
329 struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
330 struct net_device *dev = ep->dev;
334 rx = ep93xx_rx(dev, rx, budget);
338 spin_lock_irq(&ep->rx_lock);
339 __napi_complete(napi);
340 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
341 if (ep93xx_have_more_rx(ep)) {
342 wrl(ep, REG_INTEN, REG_INTEN_TX);
343 wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
346 spin_unlock_irq(&ep->rx_lock);
348 if (more && napi_reschedule(napi))
355 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
357 struct ep93xx_priv *ep = netdev_priv(dev);
360 if (unlikely(skb->len > MAX_PKT_SIZE)) {
361 ep->stats.tx_dropped++;
366 entry = ep->tx_pointer;
367 ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
369 ep->descs->tdesc[entry].tdesc1 =
370 TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
371 skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
372 dma_sync_single_for_cpu(NULL, ep->descs->tdesc[entry].buf_addr,
373 skb->len, DMA_TO_DEVICE);
376 dev->trans_start = jiffies;
378 spin_lock_irq(&ep->tx_pending_lock);
380 if (ep->tx_pending == TX_QUEUE_ENTRIES)
381 netif_stop_queue(dev);
382 spin_unlock_irq(&ep->tx_pending_lock);
384 wrl(ep, REG_TXDENQ, 1);
389 static void ep93xx_tx_complete(struct net_device *dev)
391 struct ep93xx_priv *ep = netdev_priv(dev);
396 spin_lock(&ep->tx_pending_lock);
399 struct ep93xx_tstat *tstat;
402 entry = ep->tx_clean_pointer;
403 tstat = ep->descs->tstat + entry;
405 tstat0 = tstat->tstat0;
406 if (!(tstat0 & TSTAT0_TXFP))
411 if (tstat0 & TSTAT0_FA)
412 pr_crit("frame aborted %.8x\n", tstat0);
413 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
414 pr_crit("entry mismatch %.8x\n", tstat0);
416 if (tstat0 & TSTAT0_TXWE) {
417 int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
419 ep->stats.tx_packets++;
420 ep->stats.tx_bytes += length;
422 ep->stats.tx_errors++;
425 if (tstat0 & TSTAT0_OW)
426 ep->stats.tx_window_errors++;
427 if (tstat0 & TSTAT0_TXU)
428 ep->stats.tx_fifo_errors++;
429 ep->stats.collisions += (tstat0 >> 16) & 0x1f;
431 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
432 if (ep->tx_pending == TX_QUEUE_ENTRIES)
436 spin_unlock(&ep->tx_pending_lock);
439 netif_wake_queue(dev);
442 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
444 struct net_device *dev = dev_id;
445 struct ep93xx_priv *ep = netdev_priv(dev);
448 status = rdl(ep, REG_INTSTSC);
452 if (status & REG_INTSTS_RX) {
453 spin_lock(&ep->rx_lock);
454 if (likely(napi_schedule_prep(&ep->napi))) {
455 wrl(ep, REG_INTEN, REG_INTEN_TX);
456 __napi_schedule(&ep->napi);
458 spin_unlock(&ep->rx_lock);
461 if (status & REG_INTSTS_TX)
462 ep93xx_tx_complete(dev);
467 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
471 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
474 d = ep->descs->rdesc[i].buf_addr;
476 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE);
478 if (ep->rx_buf[i] != NULL)
479 free_page((unsigned long)ep->rx_buf[i]);
482 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
485 d = ep->descs->tdesc[i].buf_addr;
487 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE);
489 if (ep->tx_buf[i] != NULL)
490 free_page((unsigned long)ep->tx_buf[i]);
493 dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs,
498 * The hardware enforces a sub-2K maximum packet size, so we put
499 * two buffers on every hardware page.
501 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
505 ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs),
506 &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA);
507 if (ep->descs == NULL)
510 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
514 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
518 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE);
519 if (dma_mapping_error(NULL, d)) {
520 free_page((unsigned long)page);
524 ep->rx_buf[i] = page;
525 ep->descs->rdesc[i].buf_addr = d;
526 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
528 ep->rx_buf[i + 1] = page + PKT_BUF_SIZE;
529 ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
530 ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE;
533 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
537 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
541 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE);
542 if (dma_mapping_error(NULL, d)) {
543 free_page((unsigned long)page);
547 ep->tx_buf[i] = page;
548 ep->descs->tdesc[i].buf_addr = d;
550 ep->tx_buf[i + 1] = page + PKT_BUF_SIZE;
551 ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
557 ep93xx_free_buffers(ep);
561 static int ep93xx_start_hw(struct net_device *dev)
563 struct ep93xx_priv *ep = netdev_priv(dev);
567 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
568 for (i = 0; i < 10; i++) {
569 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
575 pr_crit("hw failed to reset\n");
579 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
581 /* Does the PHY support preamble suppress? */
582 if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
583 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
585 /* Receive descriptor ring. */
586 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
587 wrl(ep, REG_RXDQBADD, addr);
588 wrl(ep, REG_RXDCURADD, addr);
589 wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
591 /* Receive status ring. */
592 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
593 wrl(ep, REG_RXSTSQBADD, addr);
594 wrl(ep, REG_RXSTSQCURADD, addr);
595 wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
597 /* Transmit descriptor ring. */
598 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
599 wrl(ep, REG_TXDQBADD, addr);
600 wrl(ep, REG_TXDQCURADD, addr);
601 wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
603 /* Transmit status ring. */
604 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
605 wrl(ep, REG_TXSTSQBADD, addr);
606 wrl(ep, REG_TXSTSQCURADD, addr);
607 wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
609 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
610 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
611 wrl(ep, REG_GIINTMSK, 0);
613 for (i = 0; i < 10; i++) {
614 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
620 pr_crit("hw failed to start\n");
624 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
625 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
627 wrb(ep, REG_INDAD0, dev->dev_addr[0]);
628 wrb(ep, REG_INDAD1, dev->dev_addr[1]);
629 wrb(ep, REG_INDAD2, dev->dev_addr[2]);
630 wrb(ep, REG_INDAD3, dev->dev_addr[3]);
631 wrb(ep, REG_INDAD4, dev->dev_addr[4]);
632 wrb(ep, REG_INDAD5, dev->dev_addr[5]);
635 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
637 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
638 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
643 static void ep93xx_stop_hw(struct net_device *dev)
645 struct ep93xx_priv *ep = netdev_priv(dev);
648 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
649 for (i = 0; i < 10; i++) {
650 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
656 pr_crit("hw failed to reset\n");
659 static int ep93xx_open(struct net_device *dev)
661 struct ep93xx_priv *ep = netdev_priv(dev);
664 if (ep93xx_alloc_buffers(ep))
667 napi_enable(&ep->napi);
669 if (ep93xx_start_hw(dev)) {
670 napi_disable(&ep->napi);
671 ep93xx_free_buffers(ep);
675 spin_lock_init(&ep->rx_lock);
677 ep->tx_clean_pointer = 0;
679 spin_lock_init(&ep->tx_pending_lock);
682 err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
684 napi_disable(&ep->napi);
686 ep93xx_free_buffers(ep);
690 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
692 netif_start_queue(dev);
697 static int ep93xx_close(struct net_device *dev)
699 struct ep93xx_priv *ep = netdev_priv(dev);
701 napi_disable(&ep->napi);
702 netif_stop_queue(dev);
704 wrl(ep, REG_GIINTMSK, 0);
705 free_irq(ep->irq, dev);
707 ep93xx_free_buffers(ep);
712 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
714 struct ep93xx_priv *ep = netdev_priv(dev);
715 struct mii_ioctl_data *data = if_mii(ifr);
717 return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
720 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
722 strcpy(info->driver, DRV_MODULE_NAME);
723 strcpy(info->version, DRV_MODULE_VERSION);
726 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
728 struct ep93xx_priv *ep = netdev_priv(dev);
729 return mii_ethtool_gset(&ep->mii, cmd);
732 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
734 struct ep93xx_priv *ep = netdev_priv(dev);
735 return mii_ethtool_sset(&ep->mii, cmd);
738 static int ep93xx_nway_reset(struct net_device *dev)
740 struct ep93xx_priv *ep = netdev_priv(dev);
741 return mii_nway_restart(&ep->mii);
744 static u32 ep93xx_get_link(struct net_device *dev)
746 struct ep93xx_priv *ep = netdev_priv(dev);
747 return mii_link_ok(&ep->mii);
750 static const struct ethtool_ops ep93xx_ethtool_ops = {
751 .get_drvinfo = ep93xx_get_drvinfo,
752 .get_settings = ep93xx_get_settings,
753 .set_settings = ep93xx_set_settings,
754 .nway_reset = ep93xx_nway_reset,
755 .get_link = ep93xx_get_link,
758 static const struct net_device_ops ep93xx_netdev_ops = {
759 .ndo_open = ep93xx_open,
760 .ndo_stop = ep93xx_close,
761 .ndo_start_xmit = ep93xx_xmit,
762 .ndo_get_stats = ep93xx_get_stats,
763 .ndo_do_ioctl = ep93xx_ioctl,
764 .ndo_validate_addr = eth_validate_addr,
765 .ndo_change_mtu = eth_change_mtu,
766 .ndo_set_mac_address = eth_mac_addr,
769 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
771 struct net_device *dev;
773 dev = alloc_etherdev(sizeof(struct ep93xx_priv));
777 memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
779 dev->ethtool_ops = &ep93xx_ethtool_ops;
780 dev->netdev_ops = &ep93xx_netdev_ops;
782 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
788 static int ep93xx_eth_remove(struct platform_device *pdev)
790 struct net_device *dev;
791 struct ep93xx_priv *ep;
793 dev = platform_get_drvdata(pdev);
796 platform_set_drvdata(pdev, NULL);
798 ep = netdev_priv(dev);
800 /* @@@ Force down. */
801 unregister_netdev(dev);
802 ep93xx_free_buffers(ep);
804 if (ep->base_addr != NULL)
805 iounmap(ep->base_addr);
807 if (ep->res != NULL) {
808 release_resource(ep->res);
817 static int ep93xx_eth_probe(struct platform_device *pdev)
819 struct ep93xx_eth_data *data;
820 struct net_device *dev;
821 struct ep93xx_priv *ep;
822 struct resource *mem;
828 data = pdev->dev.platform_data;
830 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
831 irq = platform_get_irq(pdev, 0);
835 dev = ep93xx_dev_alloc(data);
840 ep = netdev_priv(dev);
842 netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
844 platform_set_drvdata(pdev, dev);
846 ep->res = request_mem_region(mem->start, resource_size(mem),
847 dev_name(&pdev->dev));
848 if (ep->res == NULL) {
849 dev_err(&pdev->dev, "Could not reserve memory region\n");
854 ep->base_addr = ioremap(mem->start, resource_size(mem));
855 if (ep->base_addr == NULL) {
856 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
862 ep->mii.phy_id = data->phy_id;
863 ep->mii.phy_id_mask = 0x1f;
864 ep->mii.reg_num_mask = 0x1f;
866 ep->mii.mdio_read = ep93xx_mdio_read;
867 ep->mii.mdio_write = ep93xx_mdio_write;
868 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
870 if (is_zero_ether_addr(dev->dev_addr))
871 random_ether_addr(dev->dev_addr);
873 err = register_netdev(dev);
875 dev_err(&pdev->dev, "Failed to register netdev\n");
879 printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
880 dev->name, ep->irq, dev->dev_addr);
885 ep93xx_eth_remove(pdev);
890 static struct platform_driver ep93xx_eth_driver = {
891 .probe = ep93xx_eth_probe,
892 .remove = ep93xx_eth_remove,
894 .name = "ep93xx-eth",
895 .owner = THIS_MODULE,
899 static int __init ep93xx_eth_init_module(void)
901 printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
902 return platform_driver_register(&ep93xx_eth_driver);
905 static void __exit ep93xx_eth_cleanup_module(void)
907 platform_driver_unregister(&ep93xx_eth_driver);
910 module_init(ep93xx_eth_init_module);
911 module_exit(ep93xx_eth_cleanup_module);
912 MODULE_LICENSE("GPL");
913 MODULE_ALIAS("platform:ep93xx-eth");