2 * Copyright (c) 2008-2009 Nuvoton technology corporation.
4 * Wan ZongShun <mcuos.com@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation;version 2 of the License.
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/mii.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/skbuff.h>
18 #include <linux/ethtool.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
22 #define DRV_MODULE_NAME "w90p910-emc"
23 #define DRV_MODULE_VERSION "0.1"
25 /* Ethernet MAC Registers */
26 #define REG_CAMCMR 0x00
27 #define REG_CAMEN 0x04
28 #define REG_CAMM_BASE 0x08
29 #define REG_CAML_BASE 0x0c
30 #define REG_TXDLSA 0x88
31 #define REG_RXDLSA 0x8C
32 #define REG_MCMDR 0x90
34 #define REG_MIIDA 0x98
35 #define REG_FFTCR 0x9C
38 #define REG_DMARFC 0xa8
40 #define REG_MISTA 0xb0
41 #define REG_CTXDSA 0xcc
42 #define REG_CTXBSA 0xd0
43 #define REG_CRXDSA 0xd4
44 #define REG_CRXBSA 0xd8
46 /* mac controller bit */
47 #define MCMDR_RXON 0x01
48 #define MCMDR_ACP (0x01 << 3)
49 #define MCMDR_SPCRC (0x01 << 5)
50 #define MCMDR_TXON (0x01 << 8)
51 #define MCMDR_FDUP (0x01 << 18)
52 #define MCMDR_ENMDC (0x01 << 19)
53 #define MCMDR_OPMOD (0x01 << 20)
54 #define SWR (0x01 << 24)
56 /* cam command regiser */
57 #define CAMCMR_AUP 0x01
58 #define CAMCMR_AMP (0x01 << 1)
59 #define CAMCMR_ABP (0x01 << 2)
60 #define CAMCMR_CCAM (0x01 << 3)
61 #define CAMCMR_ECMP (0x01 << 4)
64 /* mac mii controller bit */
65 #define MDCCR (0x0a << 20)
66 #define PHYAD (0x01 << 8)
67 #define PHYWR (0x01 << 16)
68 #define PHYBUSY (0x01 << 17)
69 #define PHYPRESP (0x01 << 18)
70 #define CAM_ENTRY_SIZE 0x08
72 /* rx and tx status */
73 #define TXDS_TXCP (0x01 << 19)
74 #define RXDS_CRCE (0x01 << 17)
75 #define RXDS_PTLE (0x01 << 19)
76 #define RXDS_RXGD (0x01 << 20)
77 #define RXDS_ALIE (0x01 << 21)
78 #define RXDS_RP (0x01 << 22)
80 /* mac interrupt status*/
81 #define MISTA_EXDEF (0x01 << 19)
82 #define MISTA_TXBERR (0x01 << 24)
83 #define MISTA_TDU (0x01 << 23)
84 #define MISTA_RDU (0x01 << 10)
85 #define MISTA_RXBERR (0x01 << 11)
89 #define ENRXGD (0x01 << 4)
90 #define ENRXBERR (0x01 << 11)
91 #define ENTXINTR (0x01 << 16)
92 #define ENTXCP (0x01 << 18)
93 #define ENTXABT (0x01 << 21)
94 #define ENTXBERR (0x01 << 24)
95 #define ENMDC (0x01 << 19)
96 #define PHYBUSY (0x01 << 17)
97 #define MDCCR_VAL 0xa00000
99 /* rx and tx owner bit */
100 #define RX_OWEN_DMA (0x01 << 31)
101 #define RX_OWEN_CPU (~(0x03 << 30))
102 #define TX_OWEN_DMA (0x01 << 31)
103 #define TX_OWEN_CPU (~(0x01 << 31))
105 /* tx frame desc controller bit */
106 #define MACTXINTEN 0x04
108 #define PADDINGMODE 0x01
110 /* fftcr controller bit */
111 #define TXTHD (0x03 << 8)
112 #define BLENGTH (0x01 << 20)
114 /* global setting for driver */
115 #define RX_DESC_SIZE 50
116 #define TX_DESC_SIZE 10
117 #define MAX_RBUFF_SZ 0x600
118 #define MAX_TBUFF_SZ 0x600
119 #define TX_TIMEOUT 50
123 static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
125 struct w90p910_rxbd {
128 unsigned int reserved;
132 struct w90p910_txbd {
140 struct w90p910_rxbd desclist[RX_DESC_SIZE];
141 char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
145 struct w90p910_txbd desclist[TX_DESC_SIZE];
146 char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
149 struct w90p910_ether {
150 struct recv_pdesc *rdesc;
151 struct tran_pdesc *tdesc;
152 dma_addr_t rdesc_phys;
153 dma_addr_t tdesc_phys;
154 struct net_device_stats stats;
155 struct platform_device *pdev;
156 struct resource *res;
160 struct mii_if_info mii;
161 struct timer_list check_timer;
167 unsigned int finish_tx;
168 unsigned int rx_packets;
169 unsigned int rx_bytes;
170 unsigned int start_tx_ptr;
171 unsigned int start_rx_ptr;
172 unsigned int linkflag;
175 static void update_linkspeed_register(struct net_device *dev,
176 unsigned int speed, unsigned int duplex)
178 struct w90p910_ether *ether = netdev_priv(dev);
181 val = __raw_readl(ether->reg + REG_MCMDR);
183 if (speed == SPEED_100) {
184 /* 100 full/half duplex */
185 if (duplex == DUPLEX_FULL) {
186 val |= (MCMDR_OPMOD | MCMDR_FDUP);
192 /* 10 full/half duplex */
193 if (duplex == DUPLEX_FULL) {
197 val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
201 __raw_writel(val, ether->reg + REG_MCMDR);
204 static void update_linkspeed(struct net_device *dev)
206 struct w90p910_ether *ether = netdev_priv(dev);
207 struct platform_device *pdev;
208 unsigned int bmsr, bmcr, lpa, speed, duplex;
212 if (!mii_link_ok(ðer->mii)) {
213 ether->linkflag = 0x0;
214 netif_carrier_off(dev);
215 dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
219 if (ether->linkflag == 1)
222 bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
223 bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
225 if (bmcr & BMCR_ANENABLE) {
226 if (!(bmsr & BMSR_ANEGCOMPLETE))
229 lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
231 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
236 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
237 duplex = DUPLEX_FULL;
239 duplex = DUPLEX_HALF;
242 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
243 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
246 update_linkspeed_register(dev, speed, duplex);
248 dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
249 (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
250 ether->linkflag = 0x01;
252 netif_carrier_on(dev);
255 static void w90p910_check_link(unsigned long dev_id)
257 struct net_device *dev = (struct net_device *) dev_id;
258 struct w90p910_ether *ether = netdev_priv(dev);
260 update_linkspeed(dev);
261 mod_timer(ðer->check_timer, jiffies + msecs_to_jiffies(1000));
264 static void w90p910_write_cam(struct net_device *dev,
265 unsigned int x, unsigned char *pval)
267 struct w90p910_ether *ether = netdev_priv(dev);
268 unsigned int msw, lsw;
270 msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
272 lsw = (pval[4] << 24) | (pval[5] << 16);
274 __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
275 __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
278 static int w90p910_init_desc(struct net_device *dev)
280 struct w90p910_ether *ether;
281 struct w90p910_txbd *tdesc;
282 struct w90p910_rxbd *rdesc;
283 struct platform_device *pdev;
286 ether = netdev_priv(dev);
289 ether->tdesc = (struct tran_pdesc *)
290 dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
291 ðer->tdesc_phys, GFP_KERNEL);
294 dev_err(&pdev->dev, "Failed to allocate memory for tx desc\n");
298 ether->rdesc = (struct recv_pdesc *)
299 dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
300 ðer->rdesc_phys, GFP_KERNEL);
303 dev_err(&pdev->dev, "Failed to allocate memory for rx desc\n");
304 dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
305 ether->tdesc, ether->tdesc_phys);
309 for (i = 0; i < TX_DESC_SIZE; i++) {
312 tdesc = &(ether->tdesc->desclist[i]);
314 if (i == TX_DESC_SIZE - 1)
315 offset = offsetof(struct tran_pdesc, desclist[0]);
317 offset = offsetof(struct tran_pdesc, desclist[i + 1]);
319 tdesc->next = ether->tdesc_phys + offset;
320 tdesc->buffer = ether->tdesc_phys +
321 offsetof(struct tran_pdesc, tran_buf[i]);
326 ether->start_tx_ptr = ether->tdesc_phys;
328 for (i = 0; i < RX_DESC_SIZE; i++) {
331 rdesc = &(ether->rdesc->desclist[i]);
333 if (i == RX_DESC_SIZE - 1)
334 offset = offsetof(struct recv_pdesc, desclist[0]);
336 offset = offsetof(struct recv_pdesc, desclist[i + 1]);
338 rdesc->next = ether->rdesc_phys + offset;
339 rdesc->sl = RX_OWEN_DMA;
340 rdesc->buffer = ether->rdesc_phys +
341 offsetof(struct recv_pdesc, recv_buf[i]);
344 ether->start_rx_ptr = ether->rdesc_phys;
349 static void w90p910_set_fifo_threshold(struct net_device *dev)
351 struct w90p910_ether *ether = netdev_priv(dev);
354 val = TXTHD | BLENGTH;
355 __raw_writel(val, ether->reg + REG_FFTCR);
358 static void w90p910_return_default_idle(struct net_device *dev)
360 struct w90p910_ether *ether = netdev_priv(dev);
363 val = __raw_readl(ether->reg + REG_MCMDR);
365 __raw_writel(val, ether->reg + REG_MCMDR);
368 static void w90p910_trigger_rx(struct net_device *dev)
370 struct w90p910_ether *ether = netdev_priv(dev);
372 __raw_writel(ENSTART, ether->reg + REG_RSDR);
375 static void w90p910_trigger_tx(struct net_device *dev)
377 struct w90p910_ether *ether = netdev_priv(dev);
379 __raw_writel(ENSTART, ether->reg + REG_TSDR);
382 static void w90p910_enable_mac_interrupt(struct net_device *dev)
384 struct w90p910_ether *ether = netdev_priv(dev);
387 val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
388 val |= ENTXBERR | ENRXBERR | ENTXABT;
390 __raw_writel(val, ether->reg + REG_MIEN);
393 static void w90p910_get_and_clear_int(struct net_device *dev,
396 struct w90p910_ether *ether = netdev_priv(dev);
398 *val = __raw_readl(ether->reg + REG_MISTA);
399 __raw_writel(*val, ether->reg + REG_MISTA);
402 static void w90p910_set_global_maccmd(struct net_device *dev)
404 struct w90p910_ether *ether = netdev_priv(dev);
407 val = __raw_readl(ether->reg + REG_MCMDR);
408 val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
409 __raw_writel(val, ether->reg + REG_MCMDR);
412 static void w90p910_enable_cam(struct net_device *dev)
414 struct w90p910_ether *ether = netdev_priv(dev);
417 w90p910_write_cam(dev, CAM0, dev->dev_addr);
419 val = __raw_readl(ether->reg + REG_CAMEN);
421 __raw_writel(val, ether->reg + REG_CAMEN);
424 static void w90p910_enable_cam_command(struct net_device *dev)
426 struct w90p910_ether *ether = netdev_priv(dev);
429 val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
430 __raw_writel(val, ether->reg + REG_CAMCMR);
433 static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
435 struct w90p910_ether *ether = netdev_priv(dev);
438 val = __raw_readl(ether->reg + REG_MCMDR);
445 __raw_writel(val, ether->reg + REG_MCMDR);
448 static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
450 struct w90p910_ether *ether = netdev_priv(dev);
453 val = __raw_readl(ether->reg + REG_MCMDR);
460 __raw_writel(val, ether->reg + REG_MCMDR);
463 static void w90p910_set_curdest(struct net_device *dev)
465 struct w90p910_ether *ether = netdev_priv(dev);
467 __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
468 __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
471 static void w90p910_reset_mac(struct net_device *dev)
473 struct w90p910_ether *ether = netdev_priv(dev);
475 w90p910_enable_tx(dev, 0);
476 w90p910_enable_rx(dev, 0);
477 w90p910_set_fifo_threshold(dev);
478 w90p910_return_default_idle(dev);
480 if (!netif_queue_stopped(dev))
481 netif_stop_queue(dev);
483 w90p910_init_desc(dev);
485 dev->trans_start = jiffies;
487 ether->finish_tx = 0x0;
490 w90p910_set_curdest(dev);
491 w90p910_enable_cam(dev);
492 w90p910_enable_cam_command(dev);
493 w90p910_enable_mac_interrupt(dev);
494 w90p910_enable_tx(dev, 1);
495 w90p910_enable_rx(dev, 1);
496 w90p910_trigger_tx(dev);
497 w90p910_trigger_rx(dev);
499 dev->trans_start = jiffies;
501 if (netif_queue_stopped(dev))
502 netif_wake_queue(dev);
505 static void w90p910_mdio_write(struct net_device *dev,
506 int phy_id, int reg, int data)
508 struct w90p910_ether *ether = netdev_priv(dev);
509 struct platform_device *pdev;
514 __raw_writel(data, ether->reg + REG_MIID);
516 val = (phy_id << 0x08) | reg;
517 val |= PHYBUSY | PHYWR | MDCCR_VAL;
518 __raw_writel(val, ether->reg + REG_MIIDA);
520 for (i = 0; i < DELAY; i++) {
521 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
526 dev_warn(&pdev->dev, "mdio write timed out\n");
529 static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
531 struct w90p910_ether *ether = netdev_priv(dev);
532 struct platform_device *pdev;
533 unsigned int val, i, data;
537 val = (phy_id << 0x08) | reg;
538 val |= PHYBUSY | MDCCR_VAL;
539 __raw_writel(val, ether->reg + REG_MIIDA);
541 for (i = 0; i < DELAY; i++) {
542 if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
547 dev_warn(&pdev->dev, "mdio read timed out\n");
550 data = __raw_readl(ether->reg + REG_MIID);
556 static int w90p910_set_mac_address(struct net_device *dev, void *addr)
558 struct sockaddr *address = addr;
560 if (!is_valid_ether_addr(address->sa_data))
561 return -EADDRNOTAVAIL;
563 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
564 w90p910_write_cam(dev, CAM0, dev->dev_addr);
569 static int w90p910_ether_close(struct net_device *dev)
571 struct w90p910_ether *ether = netdev_priv(dev);
572 struct platform_device *pdev;
576 dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
577 ether->rdesc, ether->rdesc_phys);
578 dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
579 ether->tdesc, ether->tdesc_phys);
581 netif_stop_queue(dev);
583 del_timer_sync(ðer->check_timer);
584 clk_disable(ether->rmiiclk);
585 clk_disable(ether->clk);
587 free_irq(ether->txirq, dev);
588 free_irq(ether->rxirq, dev);
593 static struct net_device_stats *w90p910_ether_stats(struct net_device *dev)
595 struct w90p910_ether *ether;
597 ether = netdev_priv(dev);
599 return ðer->stats;
602 static int w90p910_send_frame(struct net_device *dev,
603 unsigned char *data, int length)
605 struct w90p910_ether *ether;
606 struct w90p910_txbd *txbd;
607 struct platform_device *pdev;
608 unsigned char *buffer;
610 ether = netdev_priv(dev);
613 txbd = ðer->tdesc->desclist[ether->cur_tx];
614 buffer = ether->tdesc->tran_buf[ether->cur_tx];
617 dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
621 txbd->sl = length & 0xFFFF;
623 memcpy(buffer, data, length);
625 txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
627 w90p910_enable_tx(dev, 1);
629 w90p910_trigger_tx(dev);
631 if (++ether->cur_tx >= TX_DESC_SIZE)
634 txbd = ðer->tdesc->desclist[ether->cur_tx];
636 dev->trans_start = jiffies;
638 if (txbd->mode & TX_OWEN_DMA)
639 netif_stop_queue(dev);
644 static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
646 struct w90p910_ether *ether = netdev_priv(dev);
648 if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
650 dev_kfree_skb_irq(skb);
656 static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
658 struct w90p910_ether *ether;
659 struct w90p910_txbd *txbd;
660 struct platform_device *pdev;
661 struct net_device *dev;
662 unsigned int cur_entry, entry, status;
665 ether = netdev_priv(dev);
668 w90p910_get_and_clear_int(dev, &status);
670 cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
672 entry = ether->tdesc_phys +
673 offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
675 while (entry != cur_entry) {
676 txbd = ðer->tdesc->desclist[ether->finish_tx];
678 if (++ether->finish_tx >= TX_DESC_SIZE)
679 ether->finish_tx = 0;
681 if (txbd->sl & TXDS_TXCP) {
682 ether->stats.tx_packets++;
683 ether->stats.tx_bytes += txbd->sl & 0xFFFF;
685 ether->stats.tx_errors++;
691 if (netif_queue_stopped(dev))
692 netif_wake_queue(dev);
694 entry = ether->tdesc_phys +
695 offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
698 if (status & MISTA_EXDEF) {
699 dev_err(&pdev->dev, "emc defer exceed interrupt\n");
700 } else if (status & MISTA_TXBERR) {
701 dev_err(&pdev->dev, "emc bus error interrupt\n");
702 w90p910_reset_mac(dev);
703 } else if (status & MISTA_TDU) {
704 if (netif_queue_stopped(dev))
705 netif_wake_queue(dev);
711 static void netdev_rx(struct net_device *dev)
713 struct w90p910_ether *ether;
714 struct w90p910_rxbd *rxbd;
715 struct platform_device *pdev;
718 unsigned int length, status, val, entry;
720 ether = netdev_priv(dev);
723 rxbd = ðer->rdesc->desclist[ether->cur_rx];
726 val = __raw_readl(ether->reg + REG_CRXDSA);
728 entry = ether->rdesc_phys +
729 offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
735 length = status & 0xFFFF;
737 if (status & RXDS_RXGD) {
738 data = ether->rdesc->recv_buf[ether->cur_rx];
739 skb = dev_alloc_skb(length+2);
741 dev_err(&pdev->dev, "get skb buffer error\n");
742 ether->stats.rx_dropped++;
748 skb_put(skb, length);
749 skb_copy_to_linear_data(skb, data, length);
750 skb->protocol = eth_type_trans(skb, dev);
751 ether->stats.rx_packets++;
752 ether->stats.rx_bytes += length;
755 ether->stats.rx_errors++;
757 if (status & RXDS_RP) {
758 dev_err(&pdev->dev, "rx runt err\n");
759 ether->stats.rx_length_errors++;
760 } else if (status & RXDS_CRCE) {
761 dev_err(&pdev->dev, "rx crc err\n");
762 ether->stats.rx_crc_errors++;
763 } else if (status & RXDS_ALIE) {
764 dev_err(&pdev->dev, "rx aligment err\n");
765 ether->stats.rx_frame_errors++;
766 } else if (status & RXDS_PTLE) {
767 dev_err(&pdev->dev, "rx longer err\n");
768 ether->stats.rx_over_errors++;
772 rxbd->sl = RX_OWEN_DMA;
773 rxbd->reserved = 0x0;
775 if (++ether->cur_rx >= RX_DESC_SIZE)
778 rxbd = ðer->rdesc->desclist[ether->cur_rx];
783 static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
785 struct net_device *dev;
786 struct w90p910_ether *ether;
787 struct platform_device *pdev;
791 ether = netdev_priv(dev);
794 w90p910_get_and_clear_int(dev, &status);
796 if (status & MISTA_RDU) {
798 w90p910_trigger_rx(dev);
801 } else if (status & MISTA_RXBERR) {
802 dev_err(&pdev->dev, "emc rx bus error\n");
803 w90p910_reset_mac(dev);
810 static int w90p910_ether_open(struct net_device *dev)
812 struct w90p910_ether *ether;
813 struct platform_device *pdev;
815 ether = netdev_priv(dev);
818 w90p910_reset_mac(dev);
819 w90p910_set_fifo_threshold(dev);
820 w90p910_set_curdest(dev);
821 w90p910_enable_cam(dev);
822 w90p910_enable_cam_command(dev);
823 w90p910_enable_mac_interrupt(dev);
824 w90p910_set_global_maccmd(dev);
825 w90p910_enable_rx(dev, 1);
827 ether->rx_packets = 0x0;
828 ether->rx_bytes = 0x0;
830 if (request_irq(ether->txirq, w90p910_tx_interrupt,
831 0x0, pdev->name, dev)) {
832 dev_err(&pdev->dev, "register irq tx failed\n");
836 if (request_irq(ether->rxirq, w90p910_rx_interrupt,
837 0x0, pdev->name, dev)) {
838 dev_err(&pdev->dev, "register irq rx failed\n");
839 free_irq(ether->txirq, dev);
843 mod_timer(ðer->check_timer, jiffies + msecs_to_jiffies(1000));
844 netif_start_queue(dev);
845 w90p910_trigger_rx(dev);
847 dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
852 static void w90p910_ether_set_multicast_list(struct net_device *dev)
854 struct w90p910_ether *ether;
855 unsigned int rx_mode;
857 ether = netdev_priv(dev);
859 if (dev->flags & IFF_PROMISC)
860 rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
861 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_list)
862 rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
864 rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
865 __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
868 static int w90p910_ether_ioctl(struct net_device *dev,
869 struct ifreq *ifr, int cmd)
871 struct w90p910_ether *ether = netdev_priv(dev);
872 struct mii_ioctl_data *data = if_mii(ifr);
874 return generic_mii_ioctl(ðer->mii, data, cmd, NULL);
877 static void w90p910_get_drvinfo(struct net_device *dev,
878 struct ethtool_drvinfo *info)
880 strcpy(info->driver, DRV_MODULE_NAME);
881 strcpy(info->version, DRV_MODULE_VERSION);
884 static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
886 struct w90p910_ether *ether = netdev_priv(dev);
887 return mii_ethtool_gset(ðer->mii, cmd);
890 static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
892 struct w90p910_ether *ether = netdev_priv(dev);
893 return mii_ethtool_sset(ðer->mii, cmd);
896 static int w90p910_nway_reset(struct net_device *dev)
898 struct w90p910_ether *ether = netdev_priv(dev);
899 return mii_nway_restart(ðer->mii);
902 static u32 w90p910_get_link(struct net_device *dev)
904 struct w90p910_ether *ether = netdev_priv(dev);
905 return mii_link_ok(ðer->mii);
908 static const struct ethtool_ops w90p910_ether_ethtool_ops = {
909 .get_settings = w90p910_get_settings,
910 .set_settings = w90p910_set_settings,
911 .get_drvinfo = w90p910_get_drvinfo,
912 .nway_reset = w90p910_nway_reset,
913 .get_link = w90p910_get_link,
916 static const struct net_device_ops w90p910_ether_netdev_ops = {
917 .ndo_open = w90p910_ether_open,
918 .ndo_stop = w90p910_ether_close,
919 .ndo_start_xmit = w90p910_ether_start_xmit,
920 .ndo_get_stats = w90p910_ether_stats,
921 .ndo_set_multicast_list = w90p910_ether_set_multicast_list,
922 .ndo_set_mac_address = w90p910_set_mac_address,
923 .ndo_do_ioctl = w90p910_ether_ioctl,
924 .ndo_validate_addr = eth_validate_addr,
925 .ndo_change_mtu = eth_change_mtu,
928 static void __init get_mac_address(struct net_device *dev)
930 struct w90p910_ether *ether = netdev_priv(dev);
931 struct platform_device *pdev;
943 if (is_valid_ether_addr(addr))
944 memcpy(dev->dev_addr, &addr, 0x06);
946 dev_err(&pdev->dev, "invalid mac address\n");
949 static int w90p910_ether_setup(struct net_device *dev)
951 struct w90p910_ether *ether = netdev_priv(dev);
954 dev->netdev_ops = &w90p910_ether_netdev_ops;
955 dev->ethtool_ops = &w90p910_ether_ethtool_ops;
957 dev->tx_queue_len = 16;
959 dev->watchdog_timeo = TX_TIMEOUT;
961 get_mac_address(dev);
965 ether->finish_tx = 0x0;
966 ether->linkflag = 0x0;
967 ether->mii.phy_id = 0x01;
968 ether->mii.phy_id_mask = 0x1f;
969 ether->mii.reg_num_mask = 0x1f;
970 ether->mii.dev = dev;
971 ether->mii.mdio_read = w90p910_mdio_read;
972 ether->mii.mdio_write = w90p910_mdio_write;
974 setup_timer(ðer->check_timer, w90p910_check_link,
980 static int __devinit w90p910_ether_probe(struct platform_device *pdev)
982 struct w90p910_ether *ether;
983 struct net_device *dev;
986 dev = alloc_etherdev(sizeof(struct w90p910_ether));
990 ether = netdev_priv(dev);
992 ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
993 if (ether->res == NULL) {
994 dev_err(&pdev->dev, "failed to get I/O memory\n");
999 if (!request_mem_region(ether->res->start,
1000 resource_size(ether->res), pdev->name)) {
1001 dev_err(&pdev->dev, "failed to request I/O memory\n");
1006 ether->reg = ioremap(ether->res->start, resource_size(ether->res));
1007 if (ether->reg == NULL) {
1008 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1010 goto failed_free_mem;
1013 ether->txirq = platform_get_irq(pdev, 0);
1014 if (ether->txirq < 0) {
1015 dev_err(&pdev->dev, "failed to get ether tx irq\n");
1017 goto failed_free_io;
1020 ether->rxirq = platform_get_irq(pdev, 1);
1021 if (ether->rxirq < 0) {
1022 dev_err(&pdev->dev, "failed to get ether rx irq\n");
1024 goto failed_free_txirq;
1027 platform_set_drvdata(pdev, dev);
1029 ether->clk = clk_get(&pdev->dev, NULL);
1030 if (IS_ERR(ether->clk)) {
1031 dev_err(&pdev->dev, "failed to get ether clock\n");
1032 error = PTR_ERR(ether->clk);
1033 goto failed_free_rxirq;
1036 ether->rmiiclk = clk_get(&pdev->dev, "RMII");
1037 if (IS_ERR(ether->rmiiclk)) {
1038 dev_err(&pdev->dev, "failed to get ether clock\n");
1039 error = PTR_ERR(ether->rmiiclk);
1040 goto failed_put_clk;
1045 w90p910_ether_setup(dev);
1047 error = register_netdev(dev);
1049 dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n");
1051 goto failed_put_rmiiclk;
1056 clk_put(ether->rmiiclk);
1058 clk_put(ether->clk);
1060 free_irq(ether->rxirq, pdev);
1061 platform_set_drvdata(pdev, NULL);
1063 free_irq(ether->txirq, pdev);
1065 iounmap(ether->reg);
1067 release_mem_region(ether->res->start, resource_size(ether->res));
1073 static int __devexit w90p910_ether_remove(struct platform_device *pdev)
1075 struct net_device *dev = platform_get_drvdata(pdev);
1076 struct w90p910_ether *ether = netdev_priv(dev);
1078 unregister_netdev(dev);
1080 clk_put(ether->rmiiclk);
1081 clk_put(ether->clk);
1083 iounmap(ether->reg);
1084 release_mem_region(ether->res->start, resource_size(ether->res));
1086 free_irq(ether->txirq, dev);
1087 free_irq(ether->rxirq, dev);
1089 del_timer_sync(ðer->check_timer);
1090 platform_set_drvdata(pdev, NULL);
1096 static struct platform_driver w90p910_ether_driver = {
1097 .probe = w90p910_ether_probe,
1098 .remove = __devexit_p(w90p910_ether_remove),
1100 .name = "nuc900-emc",
1101 .owner = THIS_MODULE,
1105 static int __init w90p910_ether_init(void)
1107 return platform_driver_register(&w90p910_ether_driver);
1110 static void __exit w90p910_ether_exit(void)
1112 platform_driver_unregister(&w90p910_ether_driver);
1115 module_init(w90p910_ether_init);
1116 module_exit(w90p910_ether_exit);
1118 MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
1119 MODULE_DESCRIPTION("w90p910 MAC driver!");
1120 MODULE_LICENSE("GPL");
1121 MODULE_ALIAS("platform:nuc900-emc");