1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
10 * Distribute under GPL.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/types.h>
19 #include <linux/netdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/mii.h>
22 #include <linux/if_ether.h>
23 #include <linux/if_vlan.h>
24 #include <linux/etherdevice.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/ssb/ssb.h>
31 #include <asm/uaccess.h>
38 #define DRV_MODULE_NAME "b44"
39 #define DRV_MODULE_VERSION "2.0"
41 #define B44_DEF_MSG_ENABLE \
51 /* length of time before we decide the hardware is borked,
52 * and dev->tx_timeout() should be called to fix the problem
54 #define B44_TX_TIMEOUT (5 * HZ)
56 /* hardware minimum and maximum for a single frame's data payload */
57 #define B44_MIN_MTU 60
58 #define B44_MAX_MTU 1500
60 #define B44_RX_RING_SIZE 512
61 #define B44_DEF_RX_RING_PENDING 200
62 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
64 #define B44_TX_RING_SIZE 512
65 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
66 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
69 #define TX_RING_GAP(BP) \
70 (B44_TX_RING_SIZE - (BP)->tx_pending)
71 #define TX_BUFFS_AVAIL(BP) \
72 (((BP)->tx_cons <= (BP)->tx_prod) ? \
73 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
74 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
75 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
77 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
78 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
80 /* minimum number of free TX descriptors required to wake up TX process */
81 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
83 /* b44 internal pattern match filter info */
84 #define B44_PATTERN_BASE 0x400
85 #define B44_PATTERN_SIZE 0x80
86 #define B44_PMASK_BASE 0x600
87 #define B44_PMASK_SIZE 0x10
88 #define B44_MAX_PATTERNS 16
89 #define B44_ETHIPV6UDP_HLEN 62
90 #define B44_ETHIPV4UDP_HLEN 42
92 static char version[] __devinitdata =
93 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
95 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
96 MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
97 MODULE_LICENSE("GPL");
98 MODULE_VERSION(DRV_MODULE_VERSION);
100 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
101 module_param(b44_debug, int, 0);
102 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
105 #ifdef CONFIG_B44_PCI
106 static DEFINE_PCI_DEVICE_TABLE(b44_pci_tbl) = {
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
110 { 0 } /* terminate list with empty entry */
112 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
114 static struct pci_driver b44_pci_driver = {
115 .name = DRV_MODULE_NAME,
116 .id_table = b44_pci_tbl,
118 #endif /* CONFIG_B44_PCI */
120 static const struct ssb_device_id b44_ssb_tbl[] = {
121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
124 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
126 static void b44_halt(struct b44 *);
127 static void b44_init_rings(struct b44 *);
129 #define B44_FULL_RESET 1
130 #define B44_FULL_RESET_SKIP_PHY 2
131 #define B44_PARTIAL_RESET 3
132 #define B44_CHIP_RESET_FULL 4
133 #define B44_CHIP_RESET_PARTIAL 5
135 static void b44_init_hw(struct b44 *, int);
137 static int dma_desc_align_mask;
138 static int dma_desc_sync_size;
141 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
142 #define _B44(x...) # x,
147 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
149 unsigned long offset,
150 enum dma_data_direction dir)
152 ssb_dma_sync_single_range_for_device(sdev, dma_base,
153 offset & dma_desc_align_mask,
154 dma_desc_sync_size, dir);
157 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
159 unsigned long offset,
160 enum dma_data_direction dir)
162 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
163 offset & dma_desc_align_mask,
164 dma_desc_sync_size, dir);
167 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
169 return ssb_read32(bp->sdev, reg);
172 static inline void bw32(const struct b44 *bp,
173 unsigned long reg, unsigned long val)
175 ssb_write32(bp->sdev, reg, val);
178 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
179 u32 bit, unsigned long timeout, const int clear)
183 for (i = 0; i < timeout; i++) {
184 u32 val = br32(bp, reg);
186 if (clear && !(val & bit))
188 if (!clear && (val & bit))
194 netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
195 bit, reg, clear ? "clear" : "set");
202 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
206 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
207 (index << CAM_CTRL_INDEX_SHIFT)));
209 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
211 val = br32(bp, B44_CAM_DATA_LO);
213 data[2] = (val >> 24) & 0xFF;
214 data[3] = (val >> 16) & 0xFF;
215 data[4] = (val >> 8) & 0xFF;
216 data[5] = (val >> 0) & 0xFF;
218 val = br32(bp, B44_CAM_DATA_HI);
220 data[0] = (val >> 8) & 0xFF;
221 data[1] = (val >> 0) & 0xFF;
224 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
228 val = ((u32) data[2]) << 24;
229 val |= ((u32) data[3]) << 16;
230 val |= ((u32) data[4]) << 8;
231 val |= ((u32) data[5]) << 0;
232 bw32(bp, B44_CAM_DATA_LO, val);
233 val = (CAM_DATA_HI_VALID |
234 (((u32) data[0]) << 8) |
235 (((u32) data[1]) << 0));
236 bw32(bp, B44_CAM_DATA_HI, val);
237 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
238 (index << CAM_CTRL_INDEX_SHIFT)));
239 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
242 static inline void __b44_disable_ints(struct b44 *bp)
244 bw32(bp, B44_IMASK, 0);
247 static void b44_disable_ints(struct b44 *bp)
249 __b44_disable_ints(bp);
251 /* Flush posted writes. */
255 static void b44_enable_ints(struct b44 *bp)
257 bw32(bp, B44_IMASK, bp->imask);
260 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
264 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
265 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
266 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
267 (phy_addr << MDIO_DATA_PMD_SHIFT) |
268 (reg << MDIO_DATA_RA_SHIFT) |
269 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
270 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
271 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
276 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
278 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
279 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
280 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
281 (phy_addr << MDIO_DATA_PMD_SHIFT) |
282 (reg << MDIO_DATA_RA_SHIFT) |
283 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
284 (val & MDIO_DATA_DATA)));
285 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
288 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
290 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
293 return __b44_readphy(bp, bp->phy_addr, reg, val);
296 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
298 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
301 return __b44_writephy(bp, bp->phy_addr, reg, val);
304 /* miilib interface */
305 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
308 struct b44 *bp = netdev_priv(dev);
309 int rc = __b44_readphy(bp, phy_id, location, &val);
315 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
318 struct b44 *bp = netdev_priv(dev);
319 __b44_writephy(bp, phy_id, location, val);
322 static int b44_phy_reset(struct b44 *bp)
327 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
329 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
333 err = b44_readphy(bp, MII_BMCR, &val);
335 if (val & BMCR_RESET) {
336 netdev_err(bp->dev, "PHY Reset would not complete\n");
344 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
348 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
349 bp->flags |= pause_flags;
351 val = br32(bp, B44_RXCONFIG);
352 if (pause_flags & B44_FLAG_RX_PAUSE)
353 val |= RXCONFIG_FLOW;
355 val &= ~RXCONFIG_FLOW;
356 bw32(bp, B44_RXCONFIG, val);
358 val = br32(bp, B44_MAC_FLOW);
359 if (pause_flags & B44_FLAG_TX_PAUSE)
360 val |= (MAC_FLOW_PAUSE_ENAB |
361 (0xc0 & MAC_FLOW_RX_HI_WATER));
363 val &= ~MAC_FLOW_PAUSE_ENAB;
364 bw32(bp, B44_MAC_FLOW, val);
367 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
371 /* The driver supports only rx pause by default because
372 the b44 mac tx pause mechanism generates excessive
374 Use ethtool to turn on b44 tx pause if necessary.
376 if ((local & ADVERTISE_PAUSE_CAP) &&
377 (local & ADVERTISE_PAUSE_ASYM)){
378 if ((remote & LPA_PAUSE_ASYM) &&
379 !(remote & LPA_PAUSE_CAP))
380 pause_enab |= B44_FLAG_RX_PAUSE;
383 __b44_set_flow_ctrl(bp, pause_enab);
386 #ifdef SSB_DRIVER_MIPS
387 extern char *nvram_get(char *name);
388 static void b44_wap54g10_workaround(struct b44 *bp)
395 * workaround for bad hardware design in Linksys WAP54G v1.0
396 * see https://dev.openwrt.org/ticket/146
397 * check and reset bit "isolate"
399 str = nvram_get("boardnum");
402 if (simple_strtoul(str, NULL, 0) == 2) {
403 err = __b44_readphy(bp, 0, MII_BMCR, &val);
406 if (!(val & BMCR_ISOLATE))
408 val &= ~BMCR_ISOLATE;
409 err = __b44_writephy(bp, 0, MII_BMCR, val);
415 pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
418 static inline void b44_wap54g10_workaround(struct b44 *bp)
423 static int b44_setup_phy(struct b44 *bp)
428 b44_wap54g10_workaround(bp);
430 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
432 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
434 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
435 val & MII_ALEDCTRL_ALLMSK)) != 0)
437 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
439 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
440 val | MII_TLEDCTRL_ENABLE)) != 0)
443 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
444 u32 adv = ADVERTISE_CSMA;
446 if (bp->flags & B44_FLAG_ADV_10HALF)
447 adv |= ADVERTISE_10HALF;
448 if (bp->flags & B44_FLAG_ADV_10FULL)
449 adv |= ADVERTISE_10FULL;
450 if (bp->flags & B44_FLAG_ADV_100HALF)
451 adv |= ADVERTISE_100HALF;
452 if (bp->flags & B44_FLAG_ADV_100FULL)
453 adv |= ADVERTISE_100FULL;
455 if (bp->flags & B44_FLAG_PAUSE_AUTO)
456 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
458 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
460 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
461 BMCR_ANRESTART))) != 0)
466 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
468 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
469 if (bp->flags & B44_FLAG_100_BASE_T)
470 bmcr |= BMCR_SPEED100;
471 if (bp->flags & B44_FLAG_FULL_DUPLEX)
472 bmcr |= BMCR_FULLDPLX;
473 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
476 /* Since we will not be negotiating there is no safe way
477 * to determine if the link partner supports flow control
478 * or not. So just disable it completely in this case.
480 b44_set_flow_ctrl(bp, 0, 0);
487 static void b44_stats_update(struct b44 *bp)
492 val = &bp->hw_stats.tx_good_octets;
493 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
494 *val++ += br32(bp, reg);
500 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
501 *val++ += br32(bp, reg);
505 static void b44_link_report(struct b44 *bp)
507 if (!netif_carrier_ok(bp->dev)) {
508 netdev_info(bp->dev, "Link is down\n");
510 netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
511 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
512 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
514 netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
515 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
516 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
520 static void b44_check_phy(struct b44 *bp)
524 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
525 bp->flags |= B44_FLAG_100_BASE_T;
526 bp->flags |= B44_FLAG_FULL_DUPLEX;
527 if (!netif_carrier_ok(bp->dev)) {
528 u32 val = br32(bp, B44_TX_CTRL);
529 val |= TX_CTRL_DUPLEX;
530 bw32(bp, B44_TX_CTRL, val);
531 netif_carrier_on(bp->dev);
537 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
538 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
540 if (aux & MII_AUXCTRL_SPEED)
541 bp->flags |= B44_FLAG_100_BASE_T;
543 bp->flags &= ~B44_FLAG_100_BASE_T;
544 if (aux & MII_AUXCTRL_DUPLEX)
545 bp->flags |= B44_FLAG_FULL_DUPLEX;
547 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
549 if (!netif_carrier_ok(bp->dev) &&
550 (bmsr & BMSR_LSTATUS)) {
551 u32 val = br32(bp, B44_TX_CTRL);
552 u32 local_adv, remote_adv;
554 if (bp->flags & B44_FLAG_FULL_DUPLEX)
555 val |= TX_CTRL_DUPLEX;
557 val &= ~TX_CTRL_DUPLEX;
558 bw32(bp, B44_TX_CTRL, val);
560 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
561 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
562 !b44_readphy(bp, MII_LPA, &remote_adv))
563 b44_set_flow_ctrl(bp, local_adv, remote_adv);
566 netif_carrier_on(bp->dev);
568 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
570 netif_carrier_off(bp->dev);
574 if (bmsr & BMSR_RFAULT)
575 netdev_warn(bp->dev, "Remote fault detected in PHY\n");
577 netdev_warn(bp->dev, "Jabber detected in PHY\n");
581 static void b44_timer(unsigned long __opaque)
583 struct b44 *bp = (struct b44 *) __opaque;
585 spin_lock_irq(&bp->lock);
589 b44_stats_update(bp);
591 spin_unlock_irq(&bp->lock);
593 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
596 static void b44_tx(struct b44 *bp)
600 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
601 cur /= sizeof(struct dma_desc);
603 /* XXX needs updating when NETIF_F_SG is supported */
604 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
605 struct ring_info *rp = &bp->tx_buffers[cons];
606 struct sk_buff *skb = rp->skb;
610 ssb_dma_unmap_single(bp->sdev,
615 dev_kfree_skb_irq(skb);
619 if (netif_queue_stopped(bp->dev) &&
620 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
621 netif_wake_queue(bp->dev);
623 bw32(bp, B44_GPTIMER, 0);
626 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
627 * before the DMA address you give it. So we allocate 30 more bytes
628 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
629 * point the chip at 30 bytes past where the rx_header will go.
631 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
634 struct ring_info *src_map, *map;
635 struct rx_header *rh;
643 src_map = &bp->rx_buffers[src_idx];
644 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
645 map = &bp->rx_buffers[dest_idx];
646 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
650 mapping = ssb_dma_map_single(bp->sdev, skb->data,
654 /* Hardware bug work-around, the chip is unable to do PCI DMA
655 to/from anything above 1GB :-( */
656 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
657 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
659 if (!ssb_dma_mapping_error(bp->sdev, mapping))
660 ssb_dma_unmap_single(bp->sdev, mapping,
661 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
662 dev_kfree_skb_any(skb);
663 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
666 mapping = ssb_dma_map_single(bp->sdev, skb->data,
669 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
670 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
671 if (!ssb_dma_mapping_error(bp->sdev, mapping))
672 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
673 dev_kfree_skb_any(skb);
676 bp->force_copybreak = 1;
679 rh = (struct rx_header *) skb->data;
685 map->mapping = mapping;
690 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
691 if (dest_idx == (B44_RX_RING_SIZE - 1))
692 ctrl |= DESC_CTRL_EOT;
694 dp = &bp->rx_ring[dest_idx];
695 dp->ctrl = cpu_to_le32(ctrl);
696 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
698 if (bp->flags & B44_FLAG_RX_RING_HACK)
699 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
700 dest_idx * sizeof(*dp),
703 return RX_PKT_BUF_SZ;
706 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
708 struct dma_desc *src_desc, *dest_desc;
709 struct ring_info *src_map, *dest_map;
710 struct rx_header *rh;
714 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
715 dest_desc = &bp->rx_ring[dest_idx];
716 dest_map = &bp->rx_buffers[dest_idx];
717 src_desc = &bp->rx_ring[src_idx];
718 src_map = &bp->rx_buffers[src_idx];
720 dest_map->skb = src_map->skb;
721 rh = (struct rx_header *) src_map->skb->data;
724 dest_map->mapping = src_map->mapping;
726 if (bp->flags & B44_FLAG_RX_RING_HACK)
727 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
728 src_idx * sizeof(*src_desc),
731 ctrl = src_desc->ctrl;
732 if (dest_idx == (B44_RX_RING_SIZE - 1))
733 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
735 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
737 dest_desc->ctrl = ctrl;
738 dest_desc->addr = src_desc->addr;
742 if (bp->flags & B44_FLAG_RX_RING_HACK)
743 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
744 dest_idx * sizeof(*dest_desc),
747 ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
752 static int b44_rx(struct b44 *bp, int budget)
758 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
759 prod /= sizeof(struct dma_desc);
762 while (cons != prod && budget > 0) {
763 struct ring_info *rp = &bp->rx_buffers[cons];
764 struct sk_buff *skb = rp->skb;
765 dma_addr_t map = rp->mapping;
766 struct rx_header *rh;
769 ssb_dma_sync_single_for_cpu(bp->sdev, map,
772 rh = (struct rx_header *) skb->data;
773 len = le16_to_cpu(rh->len);
774 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
775 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
777 b44_recycle_rx(bp, cons, bp->rx_prod);
779 bp->dev->stats.rx_dropped++;
789 len = le16_to_cpu(rh->len);
790 } while (len == 0 && i++ < 5);
798 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
800 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
803 ssb_dma_unmap_single(bp->sdev, map,
804 skb_size, DMA_FROM_DEVICE);
805 /* Leave out rx_header */
806 skb_put(skb, len + RX_PKT_OFFSET);
807 skb_pull(skb, RX_PKT_OFFSET);
809 struct sk_buff *copy_skb;
811 b44_recycle_rx(bp, cons, bp->rx_prod);
812 copy_skb = netdev_alloc_skb(bp->dev, len + 2);
813 if (copy_skb == NULL)
814 goto drop_it_no_recycle;
816 skb_reserve(copy_skb, 2);
817 skb_put(copy_skb, len);
818 /* DMA sync done above, copy just the actual packet */
819 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
820 copy_skb->data, len);
823 skb->ip_summed = CHECKSUM_NONE;
824 skb->protocol = eth_type_trans(skb, bp->dev);
825 netif_receive_skb(skb);
829 bp->rx_prod = (bp->rx_prod + 1) &
830 (B44_RX_RING_SIZE - 1);
831 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
835 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
840 static int b44_poll(struct napi_struct *napi, int budget)
842 struct b44 *bp = container_of(napi, struct b44, napi);
846 spin_lock_irqsave(&bp->lock, flags);
848 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
849 /* spin_lock(&bp->tx_lock); */
851 /* spin_unlock(&bp->tx_lock); */
853 spin_unlock_irqrestore(&bp->lock, flags);
856 if (bp->istat & ISTAT_RX)
857 work_done += b44_rx(bp, budget);
859 if (bp->istat & ISTAT_ERRORS) {
860 spin_lock_irqsave(&bp->lock, flags);
863 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
864 netif_wake_queue(bp->dev);
865 spin_unlock_irqrestore(&bp->lock, flags);
869 if (work_done < budget) {
877 static irqreturn_t b44_interrupt(int irq, void *dev_id)
879 struct net_device *dev = dev_id;
880 struct b44 *bp = netdev_priv(dev);
884 spin_lock(&bp->lock);
886 istat = br32(bp, B44_ISTAT);
887 imask = br32(bp, B44_IMASK);
889 /* The interrupt mask register controls which interrupt bits
890 * will actually raise an interrupt to the CPU when set by hw/firmware,
891 * but doesn't mask off the bits.
897 if (unlikely(!netif_running(dev))) {
898 netdev_info(dev, "late interrupt\n");
902 if (napi_schedule_prep(&bp->napi)) {
903 /* NOTE: These writes are posted by the readback of
904 * the ISTAT register below.
907 __b44_disable_ints(bp);
908 __napi_schedule(&bp->napi);
912 bw32(bp, B44_ISTAT, istat);
915 spin_unlock(&bp->lock);
916 return IRQ_RETVAL(handled);
919 static void b44_tx_timeout(struct net_device *dev)
921 struct b44 *bp = netdev_priv(dev);
923 netdev_err(dev, "transmit timed out, resetting\n");
925 spin_lock_irq(&bp->lock);
929 b44_init_hw(bp, B44_FULL_RESET);
931 spin_unlock_irq(&bp->lock);
935 netif_wake_queue(dev);
938 static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
940 struct b44 *bp = netdev_priv(dev);
941 int rc = NETDEV_TX_OK;
943 u32 len, entry, ctrl;
947 spin_lock_irqsave(&bp->lock, flags);
949 /* This is a hard error, log it. */
950 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
951 netif_stop_queue(dev);
952 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
956 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
957 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
958 struct sk_buff *bounce_skb;
960 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
961 if (!ssb_dma_mapping_error(bp->sdev, mapping))
962 ssb_dma_unmap_single(bp->sdev, mapping, len,
965 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
969 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
971 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
972 if (!ssb_dma_mapping_error(bp->sdev, mapping))
973 ssb_dma_unmap_single(bp->sdev, mapping,
975 dev_kfree_skb_any(bounce_skb);
979 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
980 dev_kfree_skb_any(skb);
985 bp->tx_buffers[entry].skb = skb;
986 bp->tx_buffers[entry].mapping = mapping;
988 ctrl = (len & DESC_CTRL_LEN);
989 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
990 if (entry == (B44_TX_RING_SIZE - 1))
991 ctrl |= DESC_CTRL_EOT;
993 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
994 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
996 if (bp->flags & B44_FLAG_TX_RING_HACK)
997 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
998 entry * sizeof(bp->tx_ring[0]),
1001 entry = NEXT_TX(entry);
1003 bp->tx_prod = entry;
1007 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1008 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1009 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1010 if (bp->flags & B44_FLAG_REORDER_BUG)
1011 br32(bp, B44_DMATX_PTR);
1013 if (TX_BUFFS_AVAIL(bp) < 1)
1014 netif_stop_queue(dev);
1016 dev->trans_start = jiffies;
1019 spin_unlock_irqrestore(&bp->lock, flags);
1024 rc = NETDEV_TX_BUSY;
1028 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1030 struct b44 *bp = netdev_priv(dev);
1032 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1035 if (!netif_running(dev)) {
1036 /* We'll just catch it later when the
1043 spin_lock_irq(&bp->lock);
1047 b44_init_hw(bp, B44_FULL_RESET);
1048 spin_unlock_irq(&bp->lock);
1050 b44_enable_ints(bp);
1055 /* Free up pending packets in all rx/tx rings.
1057 * The chip has been shut down and the driver detached from
1058 * the networking, so no interrupts or new tx packets will
1059 * end up in the driver. bp->lock is not held and we are not
1060 * in an interrupt context and thus may sleep.
1062 static void b44_free_rings(struct b44 *bp)
1064 struct ring_info *rp;
1067 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1068 rp = &bp->rx_buffers[i];
1070 if (rp->skb == NULL)
1072 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1074 dev_kfree_skb_any(rp->skb);
1078 /* XXX needs changes once NETIF_F_SG is set... */
1079 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1080 rp = &bp->tx_buffers[i];
1082 if (rp->skb == NULL)
1084 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1086 dev_kfree_skb_any(rp->skb);
1091 /* Initialize tx/rx rings for packet processing.
1093 * The chip has been shut down and the driver detached from
1094 * the networking, so no interrupts or new tx packets will
1095 * end up in the driver.
1097 static void b44_init_rings(struct b44 *bp)
1103 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1104 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1106 if (bp->flags & B44_FLAG_RX_RING_HACK)
1107 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1111 if (bp->flags & B44_FLAG_TX_RING_HACK)
1112 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1116 for (i = 0; i < bp->rx_pending; i++) {
1117 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1123 * Must not be invoked with interrupt sources disabled and
1124 * the hardware shutdown down.
1126 static void b44_free_consistent(struct b44 *bp)
1128 kfree(bp->rx_buffers);
1129 bp->rx_buffers = NULL;
1130 kfree(bp->tx_buffers);
1131 bp->tx_buffers = NULL;
1133 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1134 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1139 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1140 bp->rx_ring, bp->rx_ring_dma,
1143 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1146 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1147 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1152 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1153 bp->tx_ring, bp->tx_ring_dma,
1156 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1161 * Must not be invoked with interrupt sources disabled and
1162 * the hardware shutdown down. Can sleep.
1164 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1168 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1169 bp->rx_buffers = kzalloc(size, gfp);
1170 if (!bp->rx_buffers)
1173 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1174 bp->tx_buffers = kzalloc(size, gfp);
1175 if (!bp->tx_buffers)
1178 size = DMA_TABLE_BYTES;
1179 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
1181 /* Allocation may have failed due to pci_alloc_consistent
1182 insisting on use of GFP_DMA, which is more restrictive
1183 than necessary... */
1184 struct dma_desc *rx_ring;
1185 dma_addr_t rx_ring_dma;
1187 rx_ring = kzalloc(size, gfp);
1191 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1195 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
1196 rx_ring_dma + size > DMA_BIT_MASK(30)) {
1201 bp->rx_ring = rx_ring;
1202 bp->rx_ring_dma = rx_ring_dma;
1203 bp->flags |= B44_FLAG_RX_RING_HACK;
1206 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
1208 /* Allocation may have failed due to ssb_dma_alloc_consistent
1209 insisting on use of GFP_DMA, which is more restrictive
1210 than necessary... */
1211 struct dma_desc *tx_ring;
1212 dma_addr_t tx_ring_dma;
1214 tx_ring = kzalloc(size, gfp);
1218 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
1222 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
1223 tx_ring_dma + size > DMA_BIT_MASK(30)) {
1228 bp->tx_ring = tx_ring;
1229 bp->tx_ring_dma = tx_ring_dma;
1230 bp->flags |= B44_FLAG_TX_RING_HACK;
1236 b44_free_consistent(bp);
1240 /* bp->lock is held. */
1241 static void b44_clear_stats(struct b44 *bp)
1245 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1246 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1248 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1252 /* bp->lock is held. */
1253 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1255 struct ssb_device *sdev = bp->sdev;
1258 was_enabled = ssb_device_is_enabled(bp->sdev);
1260 ssb_device_enable(bp->sdev, 0);
1261 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1264 bw32(bp, B44_RCV_LAZY, 0);
1265 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1266 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1267 bw32(bp, B44_DMATX_CTRL, 0);
1268 bp->tx_prod = bp->tx_cons = 0;
1269 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1270 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1273 bw32(bp, B44_DMARX_CTRL, 0);
1274 bp->rx_prod = bp->rx_cons = 0;
1277 b44_clear_stats(bp);
1280 * Don't enable PHY if we are doing a partial reset
1281 * we are probably going to power down
1283 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1286 switch (sdev->bus->bustype) {
1287 case SSB_BUSTYPE_SSB:
1288 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1289 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1291 & MDIO_CTRL_MAXF_MASK)));
1293 case SSB_BUSTYPE_PCI:
1294 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1295 (0x0d & MDIO_CTRL_MAXF_MASK)));
1297 case SSB_BUSTYPE_PCMCIA:
1298 case SSB_BUSTYPE_SDIO:
1299 WARN_ON(1); /* A device with this bus does not exist. */
1303 br32(bp, B44_MDIO_CTRL);
1305 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1306 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1307 br32(bp, B44_ENET_CTRL);
1308 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1310 u32 val = br32(bp, B44_DEVCTRL);
1312 if (val & DEVCTRL_EPR) {
1313 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1314 br32(bp, B44_DEVCTRL);
1317 bp->flags |= B44_FLAG_INTERNAL_PHY;
1321 /* bp->lock is held. */
1322 static void b44_halt(struct b44 *bp)
1324 b44_disable_ints(bp);
1327 /* power down PHY */
1328 netdev_info(bp->dev, "powering down PHY\n");
1329 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1330 /* now reset the chip, but without enabling the MAC&PHY
1331 * part of it. This has to be done _after_ we shut down the PHY */
1332 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1335 /* bp->lock is held. */
1336 static void __b44_set_mac_addr(struct b44 *bp)
1338 bw32(bp, B44_CAM_CTRL, 0);
1339 if (!(bp->dev->flags & IFF_PROMISC)) {
1342 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1343 val = br32(bp, B44_CAM_CTRL);
1344 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1348 static int b44_set_mac_addr(struct net_device *dev, void *p)
1350 struct b44 *bp = netdev_priv(dev);
1351 struct sockaddr *addr = p;
1354 if (netif_running(dev))
1357 if (!is_valid_ether_addr(addr->sa_data))
1360 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1362 spin_lock_irq(&bp->lock);
1364 val = br32(bp, B44_RXCONFIG);
1365 if (!(val & RXCONFIG_CAM_ABSENT))
1366 __b44_set_mac_addr(bp);
1368 spin_unlock_irq(&bp->lock);
1373 /* Called at device open time to get the chip ready for
1374 * packet processing. Invoked with bp->lock held.
1376 static void __b44_set_rx_mode(struct net_device *);
1377 static void b44_init_hw(struct b44 *bp, int reset_kind)
1381 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1382 if (reset_kind == B44_FULL_RESET) {
1387 /* Enable CRC32, set proper LED modes and power on PHY */
1388 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1389 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1391 /* This sets the MAC address too. */
1392 __b44_set_rx_mode(bp->dev);
1394 /* MTU + eth header + possible VLAN tag + struct rx_header */
1395 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1396 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1398 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1399 if (reset_kind == B44_PARTIAL_RESET) {
1400 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1401 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1403 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1404 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1405 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1406 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1407 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1409 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1410 bp->rx_prod = bp->rx_pending;
1412 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1415 val = br32(bp, B44_ENET_CTRL);
1416 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1419 static int b44_open(struct net_device *dev)
1421 struct b44 *bp = netdev_priv(dev);
1424 err = b44_alloc_consistent(bp, GFP_KERNEL);
1428 napi_enable(&bp->napi);
1431 b44_init_hw(bp, B44_FULL_RESET);
1435 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1436 if (unlikely(err < 0)) {
1437 napi_disable(&bp->napi);
1438 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1440 b44_free_consistent(bp);
1444 init_timer(&bp->timer);
1445 bp->timer.expires = jiffies + HZ;
1446 bp->timer.data = (unsigned long) bp;
1447 bp->timer.function = b44_timer;
1448 add_timer(&bp->timer);
1450 b44_enable_ints(bp);
1451 netif_start_queue(dev);
1456 #ifdef CONFIG_NET_POLL_CONTROLLER
1458 * Polling receive - used by netconsole and other diagnostic tools
1459 * to allow network i/o with interrupts disabled.
1461 static void b44_poll_controller(struct net_device *dev)
1463 disable_irq(dev->irq);
1464 b44_interrupt(dev->irq, dev);
1465 enable_irq(dev->irq);
1469 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1472 u32 *pattern = (u32 *) pp;
1474 for (i = 0; i < bytes; i += sizeof(u32)) {
1475 bw32(bp, B44_FILT_ADDR, table_offset + i);
1476 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1480 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1483 int k, j, len = offset;
1484 int ethaddr_bytes = ETH_ALEN;
1486 memset(ppattern + offset, 0xff, magicsync);
1487 for (j = 0; j < magicsync; j++)
1488 set_bit(len++, (unsigned long *) pmask);
1490 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1491 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1492 ethaddr_bytes = ETH_ALEN;
1494 ethaddr_bytes = B44_PATTERN_SIZE - len;
1495 if (ethaddr_bytes <=0)
1497 for (k = 0; k< ethaddr_bytes; k++) {
1498 ppattern[offset + magicsync +
1499 (j * ETH_ALEN) + k] = macaddr[k];
1500 set_bit(len++, (unsigned long *) pmask);
1506 /* Setup magic packet patterns in the b44 WOL
1507 * pattern matching filter.
1509 static void b44_setup_pseudo_magicp(struct b44 *bp)
1513 int plen0, plen1, plen2;
1515 u8 pwol_mask[B44_PMASK_SIZE];
1517 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1518 if (!pwol_pattern) {
1519 pr_err("Memory not available for WOL\n");
1523 /* Ipv4 magic packet pattern - pattern 0.*/
1524 memset(pwol_mask, 0, B44_PMASK_SIZE);
1525 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1526 B44_ETHIPV4UDP_HLEN);
1528 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1529 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1531 /* Raw ethernet II magic packet pattern - pattern 1 */
1532 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1533 memset(pwol_mask, 0, B44_PMASK_SIZE);
1534 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1537 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1538 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1539 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1540 B44_PMASK_BASE + B44_PMASK_SIZE);
1542 /* Ipv6 magic packet pattern - pattern 2 */
1543 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1544 memset(pwol_mask, 0, B44_PMASK_SIZE);
1545 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1546 B44_ETHIPV6UDP_HLEN);
1548 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1549 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1550 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1551 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1553 kfree(pwol_pattern);
1555 /* set these pattern's lengths: one less than each real length */
1556 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1557 bw32(bp, B44_WKUP_LEN, val);
1559 /* enable wakeup pattern matching */
1560 val = br32(bp, B44_DEVCTRL);
1561 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1565 #ifdef CONFIG_B44_PCI
1566 static void b44_setup_wol_pci(struct b44 *bp)
1570 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1571 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1572 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1573 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1577 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1578 #endif /* CONFIG_B44_PCI */
1580 static void b44_setup_wol(struct b44 *bp)
1584 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1586 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1588 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1590 val = bp->dev->dev_addr[2] << 24 |
1591 bp->dev->dev_addr[3] << 16 |
1592 bp->dev->dev_addr[4] << 8 |
1593 bp->dev->dev_addr[5];
1594 bw32(bp, B44_ADDR_LO, val);
1596 val = bp->dev->dev_addr[0] << 8 |
1597 bp->dev->dev_addr[1];
1598 bw32(bp, B44_ADDR_HI, val);
1600 val = br32(bp, B44_DEVCTRL);
1601 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1604 b44_setup_pseudo_magicp(bp);
1606 b44_setup_wol_pci(bp);
1609 static int b44_close(struct net_device *dev)
1611 struct b44 *bp = netdev_priv(dev);
1613 netif_stop_queue(dev);
1615 napi_disable(&bp->napi);
1617 del_timer_sync(&bp->timer);
1619 spin_lock_irq(&bp->lock);
1623 netif_carrier_off(dev);
1625 spin_unlock_irq(&bp->lock);
1627 free_irq(dev->irq, dev);
1629 if (bp->flags & B44_FLAG_WOL_ENABLE) {
1630 b44_init_hw(bp, B44_PARTIAL_RESET);
1634 b44_free_consistent(bp);
1639 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1641 struct b44 *bp = netdev_priv(dev);
1642 struct net_device_stats *nstat = &dev->stats;
1643 struct b44_hw_stats *hwstat = &bp->hw_stats;
1645 /* Convert HW stats into netdevice stats. */
1646 nstat->rx_packets = hwstat->rx_pkts;
1647 nstat->tx_packets = hwstat->tx_pkts;
1648 nstat->rx_bytes = hwstat->rx_octets;
1649 nstat->tx_bytes = hwstat->tx_octets;
1650 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1651 hwstat->tx_oversize_pkts +
1652 hwstat->tx_underruns +
1653 hwstat->tx_excessive_cols +
1654 hwstat->tx_late_cols);
1655 nstat->multicast = hwstat->tx_multicast_pkts;
1656 nstat->collisions = hwstat->tx_total_cols;
1658 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1659 hwstat->rx_undersize);
1660 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1661 nstat->rx_frame_errors = hwstat->rx_align_errs;
1662 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1663 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1664 hwstat->rx_oversize_pkts +
1665 hwstat->rx_missed_pkts +
1666 hwstat->rx_crc_align_errs +
1667 hwstat->rx_undersize +
1668 hwstat->rx_crc_errs +
1669 hwstat->rx_align_errs +
1670 hwstat->rx_symbol_errs);
1672 nstat->tx_aborted_errors = hwstat->tx_underruns;
1674 /* Carrier lost counter seems to be broken for some devices */
1675 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1681 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1683 struct dev_mc_list *mclist;
1686 num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
1687 mclist = dev->mc_list;
1688 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1689 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1694 static void __b44_set_rx_mode(struct net_device *dev)
1696 struct b44 *bp = netdev_priv(dev);
1699 val = br32(bp, B44_RXCONFIG);
1700 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1701 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1702 val |= RXCONFIG_PROMISC;
1703 bw32(bp, B44_RXCONFIG, val);
1705 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1708 __b44_set_mac_addr(bp);
1710 if ((dev->flags & IFF_ALLMULTI) ||
1711 (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
1712 val |= RXCONFIG_ALLMULTI;
1714 i = __b44_load_mcast(bp, dev);
1717 __b44_cam_write(bp, zero, i);
1719 bw32(bp, B44_RXCONFIG, val);
1720 val = br32(bp, B44_CAM_CTRL);
1721 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1725 static void b44_set_rx_mode(struct net_device *dev)
1727 struct b44 *bp = netdev_priv(dev);
1729 spin_lock_irq(&bp->lock);
1730 __b44_set_rx_mode(dev);
1731 spin_unlock_irq(&bp->lock);
1734 static u32 b44_get_msglevel(struct net_device *dev)
1736 struct b44 *bp = netdev_priv(dev);
1737 return bp->msg_enable;
1740 static void b44_set_msglevel(struct net_device *dev, u32 value)
1742 struct b44 *bp = netdev_priv(dev);
1743 bp->msg_enable = value;
1746 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1748 struct b44 *bp = netdev_priv(dev);
1749 struct ssb_bus *bus = bp->sdev->bus;
1751 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1752 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1753 switch (bus->bustype) {
1754 case SSB_BUSTYPE_PCI:
1755 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1757 case SSB_BUSTYPE_SSB:
1758 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
1760 case SSB_BUSTYPE_PCMCIA:
1761 case SSB_BUSTYPE_SDIO:
1762 WARN_ON(1); /* A device with this bus does not exist. */
1767 static int b44_nway_reset(struct net_device *dev)
1769 struct b44 *bp = netdev_priv(dev);
1773 spin_lock_irq(&bp->lock);
1774 b44_readphy(bp, MII_BMCR, &bmcr);
1775 b44_readphy(bp, MII_BMCR, &bmcr);
1777 if (bmcr & BMCR_ANENABLE) {
1778 b44_writephy(bp, MII_BMCR,
1779 bmcr | BMCR_ANRESTART);
1782 spin_unlock_irq(&bp->lock);
1787 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1789 struct b44 *bp = netdev_priv(dev);
1791 cmd->supported = (SUPPORTED_Autoneg);
1792 cmd->supported |= (SUPPORTED_100baseT_Half |
1793 SUPPORTED_100baseT_Full |
1794 SUPPORTED_10baseT_Half |
1795 SUPPORTED_10baseT_Full |
1798 cmd->advertising = 0;
1799 if (bp->flags & B44_FLAG_ADV_10HALF)
1800 cmd->advertising |= ADVERTISED_10baseT_Half;
1801 if (bp->flags & B44_FLAG_ADV_10FULL)
1802 cmd->advertising |= ADVERTISED_10baseT_Full;
1803 if (bp->flags & B44_FLAG_ADV_100HALF)
1804 cmd->advertising |= ADVERTISED_100baseT_Half;
1805 if (bp->flags & B44_FLAG_ADV_100FULL)
1806 cmd->advertising |= ADVERTISED_100baseT_Full;
1807 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1808 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1809 SPEED_100 : SPEED_10;
1810 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1811 DUPLEX_FULL : DUPLEX_HALF;
1813 cmd->phy_address = bp->phy_addr;
1814 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1815 XCVR_INTERNAL : XCVR_EXTERNAL;
1816 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1817 AUTONEG_DISABLE : AUTONEG_ENABLE;
1818 if (cmd->autoneg == AUTONEG_ENABLE)
1819 cmd->advertising |= ADVERTISED_Autoneg;
1820 if (!netif_running(dev)){
1829 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1831 struct b44 *bp = netdev_priv(dev);
1833 /* We do not support gigabit. */
1834 if (cmd->autoneg == AUTONEG_ENABLE) {
1835 if (cmd->advertising &
1836 (ADVERTISED_1000baseT_Half |
1837 ADVERTISED_1000baseT_Full))
1839 } else if ((cmd->speed != SPEED_100 &&
1840 cmd->speed != SPEED_10) ||
1841 (cmd->duplex != DUPLEX_HALF &&
1842 cmd->duplex != DUPLEX_FULL)) {
1846 spin_lock_irq(&bp->lock);
1848 if (cmd->autoneg == AUTONEG_ENABLE) {
1849 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1850 B44_FLAG_100_BASE_T |
1851 B44_FLAG_FULL_DUPLEX |
1852 B44_FLAG_ADV_10HALF |
1853 B44_FLAG_ADV_10FULL |
1854 B44_FLAG_ADV_100HALF |
1855 B44_FLAG_ADV_100FULL);
1856 if (cmd->advertising == 0) {
1857 bp->flags |= (B44_FLAG_ADV_10HALF |
1858 B44_FLAG_ADV_10FULL |
1859 B44_FLAG_ADV_100HALF |
1860 B44_FLAG_ADV_100FULL);
1862 if (cmd->advertising & ADVERTISED_10baseT_Half)
1863 bp->flags |= B44_FLAG_ADV_10HALF;
1864 if (cmd->advertising & ADVERTISED_10baseT_Full)
1865 bp->flags |= B44_FLAG_ADV_10FULL;
1866 if (cmd->advertising & ADVERTISED_100baseT_Half)
1867 bp->flags |= B44_FLAG_ADV_100HALF;
1868 if (cmd->advertising & ADVERTISED_100baseT_Full)
1869 bp->flags |= B44_FLAG_ADV_100FULL;
1872 bp->flags |= B44_FLAG_FORCE_LINK;
1873 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1874 if (cmd->speed == SPEED_100)
1875 bp->flags |= B44_FLAG_100_BASE_T;
1876 if (cmd->duplex == DUPLEX_FULL)
1877 bp->flags |= B44_FLAG_FULL_DUPLEX;
1880 if (netif_running(dev))
1883 spin_unlock_irq(&bp->lock);
1888 static void b44_get_ringparam(struct net_device *dev,
1889 struct ethtool_ringparam *ering)
1891 struct b44 *bp = netdev_priv(dev);
1893 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1894 ering->rx_pending = bp->rx_pending;
1896 /* XXX ethtool lacks a tx_max_pending, oops... */
1899 static int b44_set_ringparam(struct net_device *dev,
1900 struct ethtool_ringparam *ering)
1902 struct b44 *bp = netdev_priv(dev);
1904 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1905 (ering->rx_mini_pending != 0) ||
1906 (ering->rx_jumbo_pending != 0) ||
1907 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1910 spin_lock_irq(&bp->lock);
1912 bp->rx_pending = ering->rx_pending;
1913 bp->tx_pending = ering->tx_pending;
1917 b44_init_hw(bp, B44_FULL_RESET);
1918 netif_wake_queue(bp->dev);
1919 spin_unlock_irq(&bp->lock);
1921 b44_enable_ints(bp);
1926 static void b44_get_pauseparam(struct net_device *dev,
1927 struct ethtool_pauseparam *epause)
1929 struct b44 *bp = netdev_priv(dev);
1932 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1934 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1936 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1939 static int b44_set_pauseparam(struct net_device *dev,
1940 struct ethtool_pauseparam *epause)
1942 struct b44 *bp = netdev_priv(dev);
1944 spin_lock_irq(&bp->lock);
1945 if (epause->autoneg)
1946 bp->flags |= B44_FLAG_PAUSE_AUTO;
1948 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1949 if (epause->rx_pause)
1950 bp->flags |= B44_FLAG_RX_PAUSE;
1952 bp->flags &= ~B44_FLAG_RX_PAUSE;
1953 if (epause->tx_pause)
1954 bp->flags |= B44_FLAG_TX_PAUSE;
1956 bp->flags &= ~B44_FLAG_TX_PAUSE;
1957 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1960 b44_init_hw(bp, B44_FULL_RESET);
1962 __b44_set_flow_ctrl(bp, bp->flags);
1964 spin_unlock_irq(&bp->lock);
1966 b44_enable_ints(bp);
1971 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1975 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1980 static int b44_get_sset_count(struct net_device *dev, int sset)
1984 return ARRAY_SIZE(b44_gstrings);
1990 static void b44_get_ethtool_stats(struct net_device *dev,
1991 struct ethtool_stats *stats, u64 *data)
1993 struct b44 *bp = netdev_priv(dev);
1994 u32 *val = &bp->hw_stats.tx_good_octets;
1997 spin_lock_irq(&bp->lock);
1999 b44_stats_update(bp);
2001 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2004 spin_unlock_irq(&bp->lock);
2007 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2009 struct b44 *bp = netdev_priv(dev);
2011 wol->supported = WAKE_MAGIC;
2012 if (bp->flags & B44_FLAG_WOL_ENABLE)
2013 wol->wolopts = WAKE_MAGIC;
2016 memset(&wol->sopass, 0, sizeof(wol->sopass));
2019 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2021 struct b44 *bp = netdev_priv(dev);
2023 spin_lock_irq(&bp->lock);
2024 if (wol->wolopts & WAKE_MAGIC)
2025 bp->flags |= B44_FLAG_WOL_ENABLE;
2027 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2028 spin_unlock_irq(&bp->lock);
2033 static const struct ethtool_ops b44_ethtool_ops = {
2034 .get_drvinfo = b44_get_drvinfo,
2035 .get_settings = b44_get_settings,
2036 .set_settings = b44_set_settings,
2037 .nway_reset = b44_nway_reset,
2038 .get_link = ethtool_op_get_link,
2039 .get_wol = b44_get_wol,
2040 .set_wol = b44_set_wol,
2041 .get_ringparam = b44_get_ringparam,
2042 .set_ringparam = b44_set_ringparam,
2043 .get_pauseparam = b44_get_pauseparam,
2044 .set_pauseparam = b44_set_pauseparam,
2045 .get_msglevel = b44_get_msglevel,
2046 .set_msglevel = b44_set_msglevel,
2047 .get_strings = b44_get_strings,
2048 .get_sset_count = b44_get_sset_count,
2049 .get_ethtool_stats = b44_get_ethtool_stats,
2052 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2054 struct mii_ioctl_data *data = if_mii(ifr);
2055 struct b44 *bp = netdev_priv(dev);
2058 if (!netif_running(dev))
2061 spin_lock_irq(&bp->lock);
2062 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2063 spin_unlock_irq(&bp->lock);
2068 static int __devinit b44_get_invariants(struct b44 *bp)
2070 struct ssb_device *sdev = bp->sdev;
2074 bp->dma_offset = ssb_dma_translation(sdev);
2076 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2078 addr = sdev->bus->sprom.et1mac;
2079 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2081 addr = sdev->bus->sprom.et0mac;
2082 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2084 /* Some ROMs have buggy PHY addresses with the high
2085 * bits set (sign extension?). Truncate them to a
2086 * valid PHY address. */
2087 bp->phy_addr &= 0x1F;
2089 memcpy(bp->dev->dev_addr, addr, 6);
2091 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2092 pr_err("Invalid MAC address found in EEPROM\n");
2096 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
2098 bp->imask = IMASK_DEF;
2100 /* XXX - really required?
2101 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2104 if (bp->sdev->id.revision >= 7)
2105 bp->flags |= B44_FLAG_B0_ANDLATER;
2110 static const struct net_device_ops b44_netdev_ops = {
2111 .ndo_open = b44_open,
2112 .ndo_stop = b44_close,
2113 .ndo_start_xmit = b44_start_xmit,
2114 .ndo_get_stats = b44_get_stats,
2115 .ndo_set_multicast_list = b44_set_rx_mode,
2116 .ndo_set_mac_address = b44_set_mac_addr,
2117 .ndo_validate_addr = eth_validate_addr,
2118 .ndo_do_ioctl = b44_ioctl,
2119 .ndo_tx_timeout = b44_tx_timeout,
2120 .ndo_change_mtu = b44_change_mtu,
2121 #ifdef CONFIG_NET_POLL_CONTROLLER
2122 .ndo_poll_controller = b44_poll_controller,
2126 static int __devinit b44_init_one(struct ssb_device *sdev,
2127 const struct ssb_device_id *ent)
2129 static int b44_version_printed = 0;
2130 struct net_device *dev;
2136 if (b44_version_printed++ == 0)
2137 pr_info("%s", version);
2140 dev = alloc_etherdev(sizeof(*bp));
2142 dev_err(sdev->dev, "Etherdev alloc failed, aborting\n");
2147 SET_NETDEV_DEV(dev, sdev->dev);
2149 /* No interesting netdevice features in this card... */
2152 bp = netdev_priv(dev);
2155 bp->force_copybreak = 0;
2157 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2159 spin_lock_init(&bp->lock);
2161 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2162 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2164 dev->netdev_ops = &b44_netdev_ops;
2165 netif_napi_add(dev, &bp->napi, b44_poll, 64);
2166 dev->watchdog_timeo = B44_TX_TIMEOUT;
2167 dev->irq = sdev->irq;
2168 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2170 netif_carrier_off(dev);
2172 err = ssb_bus_powerup(sdev->bus, 0);
2175 "Failed to powerup the bus\n");
2176 goto err_out_free_dev;
2178 err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
2181 "Required 30BIT DMA mask unsupported by the system\n");
2182 goto err_out_powerdown;
2184 err = b44_get_invariants(bp);
2187 "Problem fetching invariants of chip, aborting\n");
2188 goto err_out_powerdown;
2191 bp->mii_if.dev = dev;
2192 bp->mii_if.mdio_read = b44_mii_read;
2193 bp->mii_if.mdio_write = b44_mii_write;
2194 bp->mii_if.phy_id = bp->phy_addr;
2195 bp->mii_if.phy_id_mask = 0x1f;
2196 bp->mii_if.reg_num_mask = 0x1f;
2198 /* By default, advertise all speed/duplex settings. */
2199 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2200 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2202 /* By default, auto-negotiate PAUSE. */
2203 bp->flags |= B44_FLAG_PAUSE_AUTO;
2205 err = register_netdev(dev);
2207 dev_err(sdev->dev, "Cannot register net device, aborting\n");
2208 goto err_out_powerdown;
2211 ssb_set_drvdata(sdev, dev);
2213 /* Chip reset provides power to the b44 MAC & PCI cores, which
2214 * is necessary for MAC register access.
2216 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2218 /* do a phy reset to test if there is an active phy */
2219 if (b44_phy_reset(bp) < 0)
2220 bp->phy_addr = B44_PHY_ADDR_NO_PHY;
2222 netdev_info(dev, "Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2228 ssb_bus_may_powerdown(sdev->bus);
2237 static void __devexit b44_remove_one(struct ssb_device *sdev)
2239 struct net_device *dev = ssb_get_drvdata(sdev);
2241 unregister_netdev(dev);
2242 ssb_device_disable(sdev, 0);
2243 ssb_bus_may_powerdown(sdev->bus);
2245 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2246 ssb_set_drvdata(sdev, NULL);
2249 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2251 struct net_device *dev = ssb_get_drvdata(sdev);
2252 struct b44 *bp = netdev_priv(dev);
2254 if (!netif_running(dev))
2257 del_timer_sync(&bp->timer);
2259 spin_lock_irq(&bp->lock);
2262 netif_carrier_off(bp->dev);
2263 netif_device_detach(bp->dev);
2266 spin_unlock_irq(&bp->lock);
2268 free_irq(dev->irq, dev);
2269 if (bp->flags & B44_FLAG_WOL_ENABLE) {
2270 b44_init_hw(bp, B44_PARTIAL_RESET);
2274 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2278 static int b44_resume(struct ssb_device *sdev)
2280 struct net_device *dev = ssb_get_drvdata(sdev);
2281 struct b44 *bp = netdev_priv(dev);
2284 rc = ssb_bus_powerup(sdev->bus, 0);
2287 "Failed to powerup the bus\n");
2291 if (!netif_running(dev))
2294 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2296 netdev_err(dev, "request_irq failed\n");
2300 spin_lock_irq(&bp->lock);
2303 b44_init_hw(bp, B44_FULL_RESET);
2304 netif_device_attach(bp->dev);
2305 spin_unlock_irq(&bp->lock);
2307 b44_enable_ints(bp);
2308 netif_wake_queue(dev);
2310 mod_timer(&bp->timer, jiffies + 1);
2315 static struct ssb_driver b44_ssb_driver = {
2316 .name = DRV_MODULE_NAME,
2317 .id_table = b44_ssb_tbl,
2318 .probe = b44_init_one,
2319 .remove = __devexit_p(b44_remove_one),
2320 .suspend = b44_suspend,
2321 .resume = b44_resume,
2324 static inline int b44_pci_init(void)
2327 #ifdef CONFIG_B44_PCI
2328 err = ssb_pcihost_register(&b44_pci_driver);
2333 static inline void b44_pci_exit(void)
2335 #ifdef CONFIG_B44_PCI
2336 ssb_pcihost_unregister(&b44_pci_driver);
2340 static int __init b44_init(void)
2342 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2345 /* Setup paramaters for syncing RX/TX DMA descriptors */
2346 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2347 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2349 err = b44_pci_init();
2352 err = ssb_driver_register(&b44_ssb_driver);
2358 static void __exit b44_cleanup(void)
2360 ssb_driver_unregister(&b44_ssb_driver);
2364 module_init(b44_init);
2365 module_exit(b44_cleanup);