drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 /* Must be a power of 2 or else MODULO will BUG_ON */
  22 static int be_get_temp_freq = 32;
  23
  24 static void be_mcc_notify(struct be_adapter *adapter)
  25 {
  26         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  27         u32 val = 0;
  28
  29         if (adapter->eeh_err) {
  30                 dev_info(&adapter->pdev->dev,
  31                         "Error in Card Detected! Cannot issue commands\n");
  32                 return;
  33         }
  34
  35         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  36         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  37
  38         wmb();
  39         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  40 }
  41
  42 /* To check if valid bit is set, check the entire word as we don't know
  43  * the endianness of the data (old entry is host endian while a new entry is
  44  * little endian) */
  45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  46 {
  47         if (compl->flags != 0) {
  48                 compl->flags = le32_to_cpu(compl->flags);
  49                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  50                 return true;
  51         } else {
  52                 return false;
  53         }
  54 }
  55
  56 /* Need to reset the entire word that houses the valid bit */
  57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  58 {
  59         compl->flags = 0;
  60 }
  61
  62 static int be_mcc_compl_process(struct be_adapter *adapter,
  63         struct be_mcc_compl *compl)
  64 {
  65         u16 compl_status, extd_status;
  66
  67         /* Just swap the status to host endian; mcc tag is opaquely copied
  68          * from mcc_wrb */
  69         be_dws_le_to_cpu(compl, 4);
  70
  71         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  72                                 CQE_STATUS_COMPL_MASK;
  73
  74         if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
  75                 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
  76                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  77                 adapter->flash_status = compl_status;
  78                 complete(&adapter->flash_compl);
  79         }
  80
  81         if (compl_status == MCC_STATUS_SUCCESS) {
  82                 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
  83                          (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
  84                         (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
  85                         if (adapter->generation == BE_GEN3) {
  86                                 if (lancer_chip(adapter)) {
  87                                         struct lancer_cmd_resp_pport_stats
  88                                                 *resp = adapter->stats_cmd.va;
  89                                         be_dws_le_to_cpu(&resp->pport_stats,
  90                                                 sizeof(resp->pport_stats));
  91                                 } else {
  92                                         struct be_cmd_resp_get_stats_v1 *resp =
  93                                                         adapter->stats_cmd.va;
  94
  95                                 be_dws_le_to_cpu(&resp->hw_stats,
  96                                                         sizeof(resp->hw_stats));
  97                                 }
  98                         } else {
  99                                 struct be_cmd_resp_get_stats_v0 *resp =
 100                                                         adapter->stats_cmd.va;
 101
 102                                 be_dws_le_to_cpu(&resp->hw_stats,
 103                                                         sizeof(resp->hw_stats));
 104                         }
 105                         be_parse_stats(adapter);
 106                         netdev_stats_update(adapter);
 107                         adapter->stats_cmd_sent = false;
 108                 }
 109         } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
 110                    (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
 111                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 112                                 CQE_STATUS_EXTD_MASK;
 113                 dev_warn(&adapter->pdev->dev,
 114                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
 115                         compl->tag0, compl_status, extd_status);
 116         }
 117         return compl_status;
 118 }
 119
 120 /* Link state evt is a string of bytes; no need for endian swapping */
 121 static void be_async_link_state_process(struct be_adapter *adapter,
 122                 struct be_async_event_link_state *evt)
 123 {
 124         be_link_status_update(adapter,
 125                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
 126 }
 127
 128 /* Grp5 CoS Priority evt */
 129 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 130                 struct be_async_event_grp5_cos_priority *evt)
 131 {
 132         if (evt->valid) {
 133                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 134                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 135                 adapter->recommended_prio =
 136                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 137         }
 138 }
 139
 140 /* Grp5 QOS Speed evt */
 141 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 142                 struct be_async_event_grp5_qos_link_speed *evt)
 143 {
 144         if (evt->physical_port == adapter->port_num) {
 145                 /* qos_link_speed is in units of 10 Mbps */
 146                 adapter->link_speed = evt->qos_link_speed * 10;
 147         }
 148 }
 149
 150 /*Grp5 PVID evt*/
 151 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 152                 struct be_async_event_grp5_pvid_state *evt)
 153 {
 154         if (evt->enabled)
 155                 adapter->pvid = le16_to_cpu(evt->tag);
 156         else
 157                 adapter->pvid = 0;
 158 }
 159
 160 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 161                 u32 trailer, struct be_mcc_compl *evt)
 162 {
 163         u8 event_type = 0;
 164
 165         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 166                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 167
 168         switch (event_type) {
 169         case ASYNC_EVENT_COS_PRIORITY:
 170                 be_async_grp5_cos_priority_process(adapter,
 171                 (struct be_async_event_grp5_cos_priority *)evt);
 172         break;
 173         case ASYNC_EVENT_QOS_SPEED:
 174                 be_async_grp5_qos_speed_process(adapter,
 175                 (struct be_async_event_grp5_qos_link_speed *)evt);
 176         break;
 177         case ASYNC_EVENT_PVID_STATE:
 178                 be_async_grp5_pvid_state_process(adapter,
 179                 (struct be_async_event_grp5_pvid_state *)evt);
 180         break;
 181         default:
 182                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 183                 break;
 184         }
 185 }
 186
 187 static inline bool is_link_state_evt(u32 trailer)
 188 {
 189         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 190                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 191                                 ASYNC_EVENT_CODE_LINK_STATE;
 192 }
 193
 194 static inline bool is_grp5_evt(u32 trailer)
 195 {
 196         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 197                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 198                                 ASYNC_EVENT_CODE_GRP_5);
 199 }
 200
 201 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 202 {
 203         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 204         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 205
 206         if (be_mcc_compl_is_new(compl)) {
 207                 queue_tail_inc(mcc_cq);
 208                 return compl;
 209         }
 210         return NULL;
 211 }
 212
 213 void be_async_mcc_enable(struct be_adapter *adapter)
 214 {
 215         spin_lock_bh(&adapter->mcc_cq_lock);
 216
 217         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 218         adapter->mcc_obj.rearm_cq = true;
 219
 220         spin_unlock_bh(&adapter->mcc_cq_lock);
 221 }
 222
 223 void be_async_mcc_disable(struct be_adapter *adapter)
 224 {
 225         adapter->mcc_obj.rearm_cq = false;
 226 }
 227
 228 int be_process_mcc(struct be_adapter *adapter, int *status)
 229 {
 230         struct be_mcc_compl *compl;
 231         int num = 0;
 232         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 233
 234         spin_lock_bh(&adapter->mcc_cq_lock);
 235         while ((compl = be_mcc_compl_get(adapter))) {
 236                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 237                         /* Interpret flags as an async trailer */
 238                         if (is_link_state_evt(compl->flags))
 239                                 be_async_link_state_process(adapter,
 240                                 (struct be_async_event_link_state *) compl);
 241                         else if (is_grp5_evt(compl->flags))
 242                                 be_async_grp5_evt_process(adapter,
 243                                 compl->flags, compl);
 244                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 245                                 *status = be_mcc_compl_process(adapter, compl);
 246                                 atomic_dec(&mcc_obj->q.used);
 247                 }
 248                 be_mcc_compl_use(compl);
 249                 num++;
 250         }
 251
 252         spin_unlock_bh(&adapter->mcc_cq_lock);
 253         return num;
 254 }
 255
 256 /* Wait till no more pending mcc requests are present */
 257 static int be_mcc_wait_compl(struct be_adapter *adapter)
 258 {
 259 #define mcc_timeout             120000 /* 12s timeout */
 260         int i, num, status = 0;
 261         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 262
 263         if (adapter->eeh_err)
 264                 return -EIO;
 265
 266         for (i = 0; i < mcc_timeout; i++) {
 267                 num = be_process_mcc(adapter, &status);
 268                 if (num)
 269                         be_cq_notify(adapter, mcc_obj->cq.id,
 270                                 mcc_obj->rearm_cq, num);
 271
 272                 if (atomic_read(&mcc_obj->q.used) == 0)
 273                         break;
 274                 udelay(100);
 275         }
 276         if (i == mcc_timeout) {
 277                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 278                 return -1;
 279         }
 280         return status;
 281 }
 282
 283 /* Notify MCC requests and wait for completion */
 284 static int be_mcc_notify_wait(struct be_adapter *adapter)
 285 {
 286         be_mcc_notify(adapter);
 287         return be_mcc_wait_compl(adapter);
 288 }
 289
 290 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 291 {
 292         int msecs = 0;
 293         u32 ready;
 294
 295         if (adapter->eeh_err) {
 296                 dev_err(&adapter->pdev->dev,
 297                         "Error detected in card.Cannot issue commands\n");
 298                 return -EIO;
 299         }
 300
 301         do {
 302                 ready = ioread32(db);
 303                 if (ready == 0xffffffff) {
 304                         dev_err(&adapter->pdev->dev,
 305                                 "pci slot disconnected\n");
 306                         return -1;
 307                 }
 308
 309                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 310                 if (ready)
 311                         break;
 312
 313                 if (msecs > 4000) {
 314                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 315                         if (!lancer_chip(adapter))
 316                                 be_detect_dump_ue(adapter);
 317                         return -1;
 318                 }
 319
 320                 msleep(1);
 321                 msecs++;
 322         } while (true);
 323
 324         return 0;
 325 }
 326
 327 /*
 328  * Insert the mailbox address into the doorbell in two steps
 329  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 330  */
 331 static int be_mbox_notify_wait(struct be_adapter *adapter)
 332 {
 333         int status;
 334         u32 val = 0;
 335         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 336         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 337         struct be_mcc_mailbox *mbox = mbox_mem->va;
 338         struct be_mcc_compl *compl = &mbox->compl;
 339
 340         /* wait for ready to be set */
 341         status = be_mbox_db_ready_wait(adapter, db);
 342         if (status != 0)
 343                 return status;
 344
 345         val |= MPU_MAILBOX_DB_HI_MASK;
 346         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 347         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 348         iowrite32(val, db);
 349
 350         /* wait for ready to be set */
 351         status = be_mbox_db_ready_wait(adapter, db);
 352         if (status != 0)
 353                 return status;
 354
 355         val = 0;
 356         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 357         val |= (u32)(mbox_mem->dma >> 4) << 2;
 358         iowrite32(val, db);
 359
 360         status = be_mbox_db_ready_wait(adapter, db);
 361         if (status != 0)
 362                 return status;
 363
 364         /* A cq entry has been made now */
 365         if (be_mcc_compl_is_new(compl)) {
 366                 status = be_mcc_compl_process(adapter, &mbox->compl);
 367                 be_mcc_compl_use(compl);
 368                 if (status)
 369                         return status;
 370         } else {
 371                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 372                 return -1;
 373         }
 374         return 0;
 375 }
 376
 377 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 378 {
 379         u32 sem;
 380
 381         if (lancer_chip(adapter))
 382                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 383         else
 384                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 385
 386         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 387         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 388                 return -1;
 389         else
 390                 return 0;
 391 }
 392
 393 int be_cmd_POST(struct be_adapter *adapter)
 394 {
 395         u16 stage;
 396         int status, timeout = 0;
 397         struct device *dev = &adapter->pdev->dev;
 398
 399         do {
 400                 status = be_POST_stage_get(adapter, &stage);
 401                 if (status) {
 402                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 403                         return -1;
 404                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 405                         if (msleep_interruptible(2000)) {
 406                                 dev_err(dev, "Waiting for POST aborted\n");
 407                                 return -EINTR;
 408                         }
 409                         timeout += 2;
 410                 } else {
 411                         return 0;
 412                 }
 413         } while (timeout < 40);
 414
 415         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 416         return -1;
 417 }
 418
 419 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 420 {
 421         return wrb->payload.embedded_payload;
 422 }
 423
 424 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 425 {
 426         return &wrb->payload.sgl[0];
 427 }
 428
 429 /* Don't touch the hdr after it's prepared */
 430 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 431                                 bool embedded, u8 sge_cnt, u32 opcode)
 432 {
 433         if (embedded)
 434                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 435         else
 436                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 437                                 MCC_WRB_SGE_CNT_SHIFT;
 438         wrb->payload_length = payload_len;
 439         wrb->tag0 = opcode;
 440         be_dws_cpu_to_le(wrb, 8);
 441 }
 442
 443 /* Don't touch the hdr after it's prepared */
 444 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 445                                 u8 subsystem, u8 opcode, int cmd_len)
 446 {
 447         req_hdr->opcode = opcode;
 448         req_hdr->subsystem = subsystem;
 449         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 450         req_hdr->version = 0;
 451 }
 452
 453 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 454                         struct be_dma_mem *mem)
 455 {
 456         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 457         u64 dma = (u64)mem->dma;
 458
 459         for (i = 0; i < buf_pages; i++) {
 460                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 461                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 462                 dma += PAGE_SIZE_4K;
 463         }
 464 }
 465
 466 /* Converts interrupt delay in microseconds to multiplier value */
 467 static u32 eq_delay_to_mult(u32 usec_delay)
 468 {
 469 #define MAX_INTR_RATE                   651042
 470         const u32 round = 10;
 471         u32 multiplier;
 472
 473         if (usec_delay == 0)
 474                 multiplier = 0;
 475         else {
 476                 u32 interrupt_rate = 1000000 / usec_delay;
 477                 /* Max delay, corresponding to the lowest interrupt rate */
 478                 if (interrupt_rate == 0)
 479                         multiplier = 1023;
 480                 else {
 481                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 482                         multiplier /= interrupt_rate;
 483                         /* Round the multiplier to the closest value.*/
 484                         multiplier = (multiplier + round/2) / round;
 485                         multiplier = min(multiplier, (u32)1023);
 486                 }
 487         }
 488         return multiplier;
 489 }
 490
 491 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 492 {
 493         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 494         struct be_mcc_wrb *wrb
 495                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 496         memset(wrb, 0, sizeof(*wrb));
 497         return wrb;
 498 }
 499
 500 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 501 {
 502         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 503         struct be_mcc_wrb *wrb;
 504
 505         if (atomic_read(&mccq->used) >= mccq->len) {
 506                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 507                 return NULL;
 508         }
 509
 510         wrb = queue_head_node(mccq);
 511         queue_head_inc(mccq);
 512         atomic_inc(&mccq->used);
 513         memset(wrb, 0, sizeof(*wrb));
 514         return wrb;
 515 }
 516
 517 /* Tell fw we're about to start firing cmds by writing a
 518  * special pattern across the wrb hdr; uses mbox
 519  */
 520 int be_cmd_fw_init(struct be_adapter *adapter)
 521 {
 522         u8 *wrb;
 523         int status;
 524
 525         if (mutex_lock_interruptible(&adapter->mbox_lock))
 526                 return -1;
 527
 528         wrb = (u8 *)wrb_from_mbox(adapter);
 529         *wrb++ = 0xFF;
 530         *wrb++ = 0x12;
 531         *wrb++ = 0x34;
 532         *wrb++ = 0xFF;
 533         *wrb++ = 0xFF;
 534         *wrb++ = 0x56;
 535         *wrb++ = 0x78;
 536         *wrb = 0xFF;
 537
 538         status = be_mbox_notify_wait(adapter);
 539
 540         mutex_unlock(&adapter->mbox_lock);
 541         return status;
 542 }
 543
 544 /* Tell fw we're done with firing cmds by writing a
 545  * special pattern across the wrb hdr; uses mbox
 546  */
 547 int be_cmd_fw_clean(struct be_adapter *adapter)
 548 {
 549         u8 *wrb;
 550         int status;
 551
 552         if (adapter->eeh_err)
 553                 return -EIO;
 554
 555         if (mutex_lock_interruptible(&adapter->mbox_lock))
 556                 return -1;
 557
 558         wrb = (u8 *)wrb_from_mbox(adapter);
 559         *wrb++ = 0xFF;
 560         *wrb++ = 0xAA;
 561         *wrb++ = 0xBB;
 562         *wrb++ = 0xFF;
 563         *wrb++ = 0xFF;
 564         *wrb++ = 0xCC;
 565         *wrb++ = 0xDD;
 566         *wrb = 0xFF;
 567
 568         status = be_mbox_notify_wait(adapter);
 569
 570         mutex_unlock(&adapter->mbox_lock);
 571         return status;
 572 }
 573 int be_cmd_eq_create(struct be_adapter *adapter,
 574                 struct be_queue_info *eq, int eq_delay)
 575 {
 576         struct be_mcc_wrb *wrb;
 577         struct be_cmd_req_eq_create *req;
 578         struct be_dma_mem *q_mem = &eq->dma_mem;
 579         int status;
 580
 581         if (mutex_lock_interruptible(&adapter->mbox_lock))
 582                 return -1;
 583
 584         wrb = wrb_from_mbox(adapter);
 585         req = embedded_payload(wrb);
 586
 587         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 588
 589         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 590                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 591
 592         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 593
 594         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 595         /* 4byte eqe*/
 596         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 597         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 598                         __ilog2_u32(eq->len/256));
 599         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 600                         eq_delay_to_mult(eq_delay));
 601         be_dws_cpu_to_le(req->context, sizeof(req->context));
 602
 603         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 604
 605         status = be_mbox_notify_wait(adapter);
 606         if (!status) {
 607                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 608                 eq->id = le16_to_cpu(resp->eq_id);
 609                 eq->created = true;
 610         }
 611
 612         mutex_unlock(&adapter->mbox_lock);
 613         return status;
 614 }
 615
 616 /* Uses mbox */
 617 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 618                         u8 type, bool permanent, u32 if_handle)
 619 {
 620         struct be_mcc_wrb *wrb;
 621         struct be_cmd_req_mac_query *req;
 622         int status;
 623
 624         if (mutex_lock_interruptible(&adapter->mbox_lock))
 625                 return -1;
 626
 627         wrb = wrb_from_mbox(adapter);
 628         req = embedded_payload(wrb);
 629
 630         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 631                         OPCODE_COMMON_NTWK_MAC_QUERY);
 632
 633         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 634                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 635
 636         req->type = type;
 637         if (permanent) {
 638                 req->permanent = 1;
 639         } else {
 640                 req->if_id = cpu_to_le16((u16) if_handle);
 641                 req->permanent = 0;
 642         }
 643
 644         status = be_mbox_notify_wait(adapter);
 645         if (!status) {
 646                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 647                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 648         }
 649
 650         mutex_unlock(&adapter->mbox_lock);
 651         return status;
 652 }
 653
 654 /* Uses synchronous MCCQ */
 655 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 656                 u32 if_id, u32 *pmac_id, u32 domain)
 657 {
 658         struct be_mcc_wrb *wrb;
 659         struct be_cmd_req_pmac_add *req;
 660         int status;
 661
 662         spin_lock_bh(&adapter->mcc_lock);
 663
 664         wrb = wrb_from_mccq(adapter);
 665         if (!wrb) {
 666                 status = -EBUSY;
 667                 goto err;
 668         }
 669         req = embedded_payload(wrb);
 670
 671         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 672                         OPCODE_COMMON_NTWK_PMAC_ADD);
 673
 674         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 675                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 676
 677         req->hdr.domain = domain;
 678         req->if_id = cpu_to_le32(if_id);
 679         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 680
 681         status = be_mcc_notify_wait(adapter);
 682         if (!status) {
 683                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 684                 *pmac_id = le32_to_cpu(resp->pmac_id);
 685         }
 686
 687 err:
 688         spin_unlock_bh(&adapter->mcc_lock);
 689         return status;
 690 }
 691
 692 /* Uses synchronous MCCQ */
 693 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
 694 {
 695         struct be_mcc_wrb *wrb;
 696         struct be_cmd_req_pmac_del *req;
 697         int status;
 698
 699         spin_lock_bh(&adapter->mcc_lock);
 700
 701         wrb = wrb_from_mccq(adapter);
 702         if (!wrb) {
 703                 status = -EBUSY;
 704                 goto err;
 705         }
 706         req = embedded_payload(wrb);
 707
 708         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 709                         OPCODE_COMMON_NTWK_PMAC_DEL);
 710
 711         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 712                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 713
 714         req->hdr.domain = dom;
 715         req->if_id = cpu_to_le32(if_id);
 716         req->pmac_id = cpu_to_le32(pmac_id);
 717
 718         status = be_mcc_notify_wait(adapter);
 719
 720 err:
 721         spin_unlock_bh(&adapter->mcc_lock);
 722         return status;
 723 }
 724
 725 /* Uses Mbox */
 726 int be_cmd_cq_create(struct be_adapter *adapter,
 727                 struct be_queue_info *cq, struct be_queue_info *eq,
 728                 bool sol_evts, bool no_delay, int coalesce_wm)
 729 {
 730         struct be_mcc_wrb *wrb;
 731         struct be_cmd_req_cq_create *req;
 732         struct be_dma_mem *q_mem = &cq->dma_mem;
 733         void *ctxt;
 734         int status;
 735
 736         if (mutex_lock_interruptible(&adapter->mbox_lock))
 737                 return -1;
 738
 739         wrb = wrb_from_mbox(adapter);
 740         req = embedded_payload(wrb);
 741         ctxt = &req->context;
 742
 743         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 744                         OPCODE_COMMON_CQ_CREATE);
 745
 746         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 747                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 748
 749         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 750         if (lancer_chip(adapter)) {
 751                 req->hdr.version = 2;
 752                 req->page_size = 1; /* 1 for 4K */
 753                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 754                                                                 no_delay);
 755                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 756                                                 __ilog2_u32(cq->len/256));
 757                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 758                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 759                                                                 ctxt, 1);
 760                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 761                                                                 ctxt, eq->id);
 762                 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
 763         } else {
 764                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 765                                                                 coalesce_wm);
 766                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 767                                                                 ctxt, no_delay);
 768                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 769                                                 __ilog2_u32(cq->len/256));
 770                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 771                 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
 772                                                                 ctxt, sol_evts);
 773                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 774                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 775                 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
 776         }
 777
 778         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 779
 780         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 781
 782         status = be_mbox_notify_wait(adapter);
 783         if (!status) {
 784                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 785                 cq->id = le16_to_cpu(resp->cq_id);
 786                 cq->created = true;
 787         }
 788
 789         mutex_unlock(&adapter->mbox_lock);
 790
 791         return status;
 792 }
 793
 794 static u32 be_encoded_q_len(int q_len)
 795 {
 796         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 797         if (len_encoded == 16)
 798                 len_encoded = 0;
 799         return len_encoded;
 800 }
 801
 802 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 803                         struct be_queue_info *mccq,
 804                         struct be_queue_info *cq)
 805 {
 806         struct be_mcc_wrb *wrb;
 807         struct be_cmd_req_mcc_ext_create *req;
 808         struct be_dma_mem *q_mem = &mccq->dma_mem;
 809         void *ctxt;
 810         int status;
 811
 812         if (mutex_lock_interruptible(&adapter->mbox_lock))
 813                 return -1;
 814
 815         wrb = wrb_from_mbox(adapter);
 816         req = embedded_payload(wrb);
 817         ctxt = &req->context;
 818
 819         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 820                         OPCODE_COMMON_MCC_CREATE_EXT);
 821
 822         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 823                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
 824
 825         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 826         if (lancer_chip(adapter)) {
 827                 req->hdr.version = 1;
 828                 req->cq_id = cpu_to_le16(cq->id);
 829
 830                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 831                                                 be_encoded_q_len(mccq->len));
 832                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 833                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 834                                                                 ctxt, cq->id);
 835                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 836                                                                  ctxt, 1);
 837
 838         } else {
 839                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 840                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 841                                                 be_encoded_q_len(mccq->len));
 842                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 843         }
 844
 845         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 846         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 847         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 848
 849         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 850
 851         status = be_mbox_notify_wait(adapter);
 852         if (!status) {
 853                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 854                 mccq->id = le16_to_cpu(resp->id);
 855                 mccq->created = true;
 856         }
 857         mutex_unlock(&adapter->mbox_lock);
 858
 859         return status;
 860 }
 861
 862 int be_cmd_mccq_org_create(struct be_adapter *adapter,
 863                         struct be_queue_info *mccq,
 864                         struct be_queue_info *cq)
 865 {
 866         struct be_mcc_wrb *wrb;
 867         struct be_cmd_req_mcc_create *req;
 868         struct be_dma_mem *q_mem = &mccq->dma_mem;
 869         void *ctxt;
 870         int status;
 871
 872         if (mutex_lock_interruptible(&adapter->mbox_lock))
 873                 return -1;
 874
 875         wrb = wrb_from_mbox(adapter);
 876         req = embedded_payload(wrb);
 877         ctxt = &req->context;
 878
 879         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 880                         OPCODE_COMMON_MCC_CREATE);
 881
 882         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 883                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
 884
 885         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 886
 887         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 888         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 889                         be_encoded_q_len(mccq->len));
 890         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 891
 892         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 893
 894         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 895
 896         status = be_mbox_notify_wait(adapter);
 897         if (!status) {
 898                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 899                 mccq->id = le16_to_cpu(resp->id);
 900                 mccq->created = true;
 901         }
 902
 903         mutex_unlock(&adapter->mbox_lock);
 904         return status;
 905 }
 906
 907 int be_cmd_mccq_create(struct be_adapter *adapter,
 908                         struct be_queue_info *mccq,
 909                         struct be_queue_info *cq)
 910 {
 911         int status;
 912
 913         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
 914         if (status && !lancer_chip(adapter)) {
 915                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
 916                         "or newer to avoid conflicting priorities between NIC "
 917                         "and FCoE traffic");
 918                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
 919         }
 920         return status;
 921 }
 922
 923 int be_cmd_txq_create(struct be_adapter *adapter,
 924                         struct be_queue_info *txq,
 925                         struct be_queue_info *cq)
 926 {
 927         struct be_mcc_wrb *wrb;
 928         struct be_cmd_req_eth_tx_create *req;
 929         struct be_dma_mem *q_mem = &txq->dma_mem;
 930         void *ctxt;
 931         int status;
 932
 933         if (mutex_lock_interruptible(&adapter->mbox_lock))
 934                 return -1;
 935
 936         wrb = wrb_from_mbox(adapter);
 937         req = embedded_payload(wrb);
 938         ctxt = &req->context;
 939
 940         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 941                         OPCODE_ETH_TX_CREATE);
 942
 943         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 944                 sizeof(*req));
 945
 946         if (lancer_chip(adapter)) {
 947                 req->hdr.version = 1;
 948                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
 949                                         adapter->if_handle);
 950         }
 951
 952         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 953         req->ulp_num = BE_ULP1_NUM;
 954         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 955
 956         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 957                 be_encoded_q_len(txq->len));
 958         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 959         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 960
 961         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 962
 963         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 964
 965         status = be_mbox_notify_wait(adapter);
 966         if (!status) {
 967                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 968                 txq->id = le16_to_cpu(resp->cid);
 969                 txq->created = true;
 970         }
 971
 972         mutex_unlock(&adapter->mbox_lock);
 973
 974         return status;
 975 }
 976
 977 /* Uses mbox */
 978 int be_cmd_rxq_create(struct be_adapter *adapter,
 979                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 980                 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
 981 {
 982         struct be_mcc_wrb *wrb;
 983         struct be_cmd_req_eth_rx_create *req;
 984         struct be_dma_mem *q_mem = &rxq->dma_mem;
 985         int status;
 986
 987         if (mutex_lock_interruptible(&adapter->mbox_lock))
 988                 return -1;
 989
 990         wrb = wrb_from_mbox(adapter);
 991         req = embedded_payload(wrb);
 992
 993         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 994                         OPCODE_ETH_RX_CREATE);
 995
 996         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 997                 sizeof(*req));
 998
 999         req->cq_id = cpu_to_le16(cq_id);
1000         req->frag_size = fls(frag_size) - 1;
1001         req->num_pages = 2;
1002         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1003         req->interface_id = cpu_to_le32(if_id);
1004         req->max_frame_size = cpu_to_le16(max_frame_size);
1005         req->rss_queue = cpu_to_le32(rss);
1006
1007         status = be_mbox_notify_wait(adapter);
1008         if (!status) {
1009                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1010                 rxq->id = le16_to_cpu(resp->id);
1011                 rxq->created = true;
1012                 *rss_id = resp->rss_id;
1013         }
1014
1015         mutex_unlock(&adapter->mbox_lock);
1016
1017         return status;
1018 }
1019
1020 /* Generic destroyer function for all types of queues
1021  * Uses Mbox
1022  */
1023 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1024                 int queue_type)
1025 {
1026         struct be_mcc_wrb *wrb;
1027         struct be_cmd_req_q_destroy *req;
1028         u8 subsys = 0, opcode = 0;
1029         int status;
1030
1031         if (adapter->eeh_err)
1032                 return -EIO;
1033
1034         if (mutex_lock_interruptible(&adapter->mbox_lock))
1035                 return -1;
1036
1037         wrb = wrb_from_mbox(adapter);
1038         req = embedded_payload(wrb);
1039
1040         switch (queue_type) {
1041         case QTYPE_EQ:
1042                 subsys = CMD_SUBSYSTEM_COMMON;
1043                 opcode = OPCODE_COMMON_EQ_DESTROY;
1044                 break;
1045         case QTYPE_CQ:
1046                 subsys = CMD_SUBSYSTEM_COMMON;
1047                 opcode = OPCODE_COMMON_CQ_DESTROY;
1048                 break;
1049         case QTYPE_TXQ:
1050                 subsys = CMD_SUBSYSTEM_ETH;
1051                 opcode = OPCODE_ETH_TX_DESTROY;
1052                 break;
1053         case QTYPE_RXQ:
1054                 subsys = CMD_SUBSYSTEM_ETH;
1055                 opcode = OPCODE_ETH_RX_DESTROY;
1056                 break;
1057         case QTYPE_MCCQ:
1058                 subsys = CMD_SUBSYSTEM_COMMON;
1059                 opcode = OPCODE_COMMON_MCC_DESTROY;
1060                 break;
1061         default:
1062                 BUG();
1063         }
1064
1065         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
1066
1067         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1068         req->id = cpu_to_le16(q->id);
1069
1070         status = be_mbox_notify_wait(adapter);
1071
1072         mutex_unlock(&adapter->mbox_lock);
1073
1074         return status;
1075 }
1076
1077 /* Create an rx filtering policy configuration on an i/f
1078  * Uses mbox
1079  */
1080 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1081                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1082                 u32 domain)
1083 {
1084         struct be_mcc_wrb *wrb;
1085         struct be_cmd_req_if_create *req;
1086         int status;
1087
1088         if (mutex_lock_interruptible(&adapter->mbox_lock))
1089                 return -1;
1090
1091         wrb = wrb_from_mbox(adapter);
1092         req = embedded_payload(wrb);
1093
1094         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1095                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1096
1097         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1098                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1099
1100         req->hdr.domain = domain;
1101         req->capability_flags = cpu_to_le32(cap_flags);
1102         req->enable_flags = cpu_to_le32(en_flags);
1103         req->pmac_invalid = pmac_invalid;
1104         if (!pmac_invalid)
1105                 memcpy(req->mac_addr, mac, ETH_ALEN);
1106
1107         status = be_mbox_notify_wait(adapter);
1108         if (!status) {
1109                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1110                 *if_handle = le32_to_cpu(resp->interface_id);
1111                 if (!pmac_invalid)
1112                         *pmac_id = le32_to_cpu(resp->pmac_id);
1113         }
1114
1115         mutex_unlock(&adapter->mbox_lock);
1116         return status;
1117 }
1118
1119 /* Uses mbox */
1120 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1121 {
1122         struct be_mcc_wrb *wrb;
1123         struct be_cmd_req_if_destroy *req;
1124         int status;
1125
1126         if (adapter->eeh_err)
1127                 return -EIO;
1128
1129         if (mutex_lock_interruptible(&adapter->mbox_lock))
1130                 return -1;
1131
1132         wrb = wrb_from_mbox(adapter);
1133         req = embedded_payload(wrb);
1134
1135         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1136                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1137
1138         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1139                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1140
1141         req->hdr.domain = domain;
1142         req->interface_id = cpu_to_le32(interface_id);
1143
1144         status = be_mbox_notify_wait(adapter);
1145
1146         mutex_unlock(&adapter->mbox_lock);
1147
1148         return status;
1149 }
1150
1151 /* Get stats is a non embedded command: the request is not embedded inside
1152  * WRB but is a separate dma memory block
1153  * Uses asynchronous MCC
1154  */
1155 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1156 {
1157         struct be_mcc_wrb *wrb;
1158         struct be_cmd_req_hdr *hdr;
1159         struct be_sge *sge;
1160         int status = 0;
1161
1162         if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1163                 be_cmd_get_die_temperature(adapter);
1164
1165         spin_lock_bh(&adapter->mcc_lock);
1166
1167         wrb = wrb_from_mccq(adapter);
1168         if (!wrb) {
1169                 status = -EBUSY;
1170                 goto err;
1171         }
1172         hdr = nonemb_cmd->va;
1173         sge = nonembedded_sgl(wrb);
1174
1175         be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1176                         OPCODE_ETH_GET_STATISTICS);
1177
1178         be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1179                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size);
1180
1181         if (adapter->generation == BE_GEN3)
1182                 hdr->version = 1;
1183
1184         wrb->tag1 = CMD_SUBSYSTEM_ETH;
1185         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1186         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1187         sge->len = cpu_to_le32(nonemb_cmd->size);
1188
1189         be_mcc_notify(adapter);
1190         adapter->stats_cmd_sent = true;
1191
1192 err:
1193         spin_unlock_bh(&adapter->mcc_lock);
1194         return status;
1195 }
1196
1197 /* Lancer Stats */
1198 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1199                                 struct be_dma_mem *nonemb_cmd)
1200 {
1201
1202         struct be_mcc_wrb *wrb;
1203         struct lancer_cmd_req_pport_stats *req;
1204         struct be_sge *sge;
1205         int status = 0;
1206
1207         spin_lock_bh(&adapter->mcc_lock);
1208
1209         wrb = wrb_from_mccq(adapter);
1210         if (!wrb) {
1211                 status = -EBUSY;
1212                 goto err;
1213         }
1214         req = nonemb_cmd->va;
1215         sge = nonembedded_sgl(wrb);
1216
1217         be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1218                         OPCODE_ETH_GET_PPORT_STATS);
1219
1220         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1221                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size);
1222
1223
1224         req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1225         req->cmd_params.params.reset_stats = 0;
1226
1227         wrb->tag1 = CMD_SUBSYSTEM_ETH;
1228         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1229         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1230         sge->len = cpu_to_le32(nonemb_cmd->size);
1231
1232         be_mcc_notify(adapter);
1233         adapter->stats_cmd_sent = true;
1234
1235 err:
1236         spin_unlock_bh(&adapter->mcc_lock);
1237         return status;
1238 }
1239
1240 /* Uses synchronous mcc */
1241 int be_cmd_link_status_query(struct be_adapter *adapter,
1242                         bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom)
1243 {
1244         struct be_mcc_wrb *wrb;
1245         struct be_cmd_req_link_status *req;
1246         int status;
1247
1248         spin_lock_bh(&adapter->mcc_lock);
1249
1250         wrb = wrb_from_mccq(adapter);
1251         if (!wrb) {
1252                 status = -EBUSY;
1253                 goto err;
1254         }
1255         req = embedded_payload(wrb);
1256
1257         *link_up = false;
1258
1259         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1260                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1261
1262         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1263                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1264
1265         status = be_mcc_notify_wait(adapter);
1266         if (!status) {
1267                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1268                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1269                         *link_up = true;
1270                         *link_speed = le16_to_cpu(resp->link_speed);
1271                         *mac_speed = resp->mac_speed;
1272                 }
1273         }
1274
1275 err:
1276         spin_unlock_bh(&adapter->mcc_lock);
1277         return status;
1278 }
1279
1280 /* Uses synchronous mcc */
1281 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1282 {
1283         struct be_mcc_wrb *wrb;
1284         struct be_cmd_req_get_cntl_addnl_attribs *req;
1285         int status;
1286
1287         spin_lock_bh(&adapter->mcc_lock);
1288
1289         wrb = wrb_from_mccq(adapter);
1290         if (!wrb) {
1291                 status = -EBUSY;
1292                 goto err;
1293         }
1294         req = embedded_payload(wrb);
1295
1296         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1297                         OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1298
1299         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1300                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1301
1302         status = be_mcc_notify_wait(adapter);
1303         if (!status) {
1304                 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
1305                                                 embedded_payload(wrb);
1306                 adapter->drv_stats.be_on_die_temperature =
1307                                                 resp->on_die_temperature;
1308         }
1309         /* If IOCTL fails once, do not bother issuing it again */
1310         else
1311                 be_get_temp_freq = 0;
1312
1313 err:
1314         spin_unlock_bh(&adapter->mcc_lock);
1315         return status;
1316 }
1317
1318 /* Uses synchronous mcc */
1319 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1320 {
1321         struct be_mcc_wrb *wrb;
1322         struct be_cmd_req_get_fat *req;
1323         int status;
1324
1325         spin_lock_bh(&adapter->mcc_lock);
1326
1327         wrb = wrb_from_mccq(adapter);
1328         if (!wrb) {
1329                 status = -EBUSY;
1330                 goto err;
1331         }
1332         req = embedded_payload(wrb);
1333
1334         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1335                         OPCODE_COMMON_MANAGE_FAT);
1336
1337         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1338                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1339         req->fat_operation = cpu_to_le32(QUERY_FAT);
1340         status = be_mcc_notify_wait(adapter);
1341         if (!status) {
1342                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1343                 if (log_size && resp->log_size)
1344                         *log_size = le32_to_cpu(resp->log_size) -
1345                                         sizeof(u32);
1346         }
1347 err:
1348         spin_unlock_bh(&adapter->mcc_lock);
1349         return status;
1350 }
1351
1352 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1353 {
1354         struct be_dma_mem get_fat_cmd;
1355         struct be_mcc_wrb *wrb;
1356         struct be_cmd_req_get_fat *req;
1357         struct be_sge *sge;
1358         u32 offset = 0, total_size, buf_size,
1359                                 log_offset = sizeof(u32), payload_len;
1360         int status;
1361
1362         if (buf_len == 0)
1363                 return;
1364
1365         total_size = buf_len;
1366
1367         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1368         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1369                         get_fat_cmd.size,
1370                         &get_fat_cmd.dma);
1371         if (!get_fat_cmd.va) {
1372                 status = -ENOMEM;
1373                 dev_err(&adapter->pdev->dev,
1374                 "Memory allocation failure while retrieving FAT data\n");
1375                 return;
1376         }
1377
1378         spin_lock_bh(&adapter->mcc_lock);
1379
1380         while (total_size) {
1381                 buf_size = min(total_size, (u32)60*1024);
1382                 total_size -= buf_size;
1383
1384                 wrb = wrb_from_mccq(adapter);
1385                 if (!wrb) {
1386                         status = -EBUSY;
1387                         goto err;
1388                 }
1389                 req = get_fat_cmd.va;
1390                 sge = nonembedded_sgl(wrb);
1391
1392                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1393                 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
1394                                 OPCODE_COMMON_MANAGE_FAT);
1395
1396                 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1397                                 OPCODE_COMMON_MANAGE_FAT, payload_len);
1398
1399                 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
1400                 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1401                 sge->len = cpu_to_le32(get_fat_cmd.size);
1402
1403                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1404                 req->read_log_offset = cpu_to_le32(log_offset);
1405                 req->read_log_length = cpu_to_le32(buf_size);
1406                 req->data_buffer_size = cpu_to_le32(buf_size);
1407
1408                 status = be_mcc_notify_wait(adapter);
1409                 if (!status) {
1410                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1411                         memcpy(buf + offset,
1412                                 resp->data_buffer,
1413                                 resp->read_log_length);
1414                 } else {
1415                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1416                         goto err;
1417                 }
1418                 offset += buf_size;
1419                 log_offset += buf_size;
1420         }
1421 err:
1422         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1423                         get_fat_cmd.va,
1424                         get_fat_cmd.dma);
1425         spin_unlock_bh(&adapter->mcc_lock);
1426 }
1427
1428 /* Uses Mbox */
1429 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1430 {
1431         struct be_mcc_wrb *wrb;
1432         struct be_cmd_req_get_fw_version *req;
1433         int status;
1434
1435         if (mutex_lock_interruptible(&adapter->mbox_lock))
1436                 return -1;
1437
1438         wrb = wrb_from_mbox(adapter);
1439         req = embedded_payload(wrb);
1440
1441         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1442                         OPCODE_COMMON_GET_FW_VERSION);
1443
1444         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1445                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1446
1447         status = be_mbox_notify_wait(adapter);
1448         if (!status) {
1449                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1450                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1451         }
1452
1453         mutex_unlock(&adapter->mbox_lock);
1454         return status;
1455 }
1456
1457 /* set the EQ delay interval of an EQ to specified value
1458  * Uses async mcc
1459  */
1460 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1461 {
1462         struct be_mcc_wrb *wrb;
1463         struct be_cmd_req_modify_eq_delay *req;
1464         int status = 0;
1465
1466         spin_lock_bh(&adapter->mcc_lock);
1467
1468         wrb = wrb_from_mccq(adapter);
1469         if (!wrb) {
1470                 status = -EBUSY;
1471                 goto err;
1472         }
1473         req = embedded_payload(wrb);
1474
1475         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1476                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1477
1478         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1479                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1480
1481         req->num_eq = cpu_to_le32(1);
1482         req->delay[0].eq_id = cpu_to_le32(eq_id);
1483         req->delay[0].phase = 0;
1484         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1485
1486         be_mcc_notify(adapter);
1487
1488 err:
1489         spin_unlock_bh(&adapter->mcc_lock);
1490         return status;
1491 }
1492
1493 /* Uses sycnhronous mcc */
1494 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1495                         u32 num, bool untagged, bool promiscuous)
1496 {
1497         struct be_mcc_wrb *wrb;
1498         struct be_cmd_req_vlan_config *req;
1499         int status;
1500
1501         spin_lock_bh(&adapter->mcc_lock);
1502
1503         wrb = wrb_from_mccq(adapter);
1504         if (!wrb) {
1505                 status = -EBUSY;
1506                 goto err;
1507         }
1508         req = embedded_payload(wrb);
1509
1510         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1511                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1512
1513         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1514                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1515
1516         req->interface_id = if_id;
1517         req->promiscuous = promiscuous;
1518         req->untagged = untagged;
1519         req->num_vlan = num;
1520         if (!promiscuous) {
1521                 memcpy(req->normal_vlan, vtag_array,
1522                         req->num_vlan * sizeof(vtag_array[0]));
1523         }
1524
1525         status = be_mcc_notify_wait(adapter);
1526
1527 err:
1528         spin_unlock_bh(&adapter->mcc_lock);
1529         return status;
1530 }
1531
1532 /* Uses MCC for this command as it may be called in BH context
1533  * Uses synchronous mcc
1534  */
1535 int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en)
1536 {
1537         struct be_mcc_wrb *wrb;
1538         struct be_cmd_req_rx_filter *req;
1539         struct be_dma_mem promiscous_cmd;
1540         struct be_sge *sge;
1541         int status;
1542
1543         memset(&promiscous_cmd, 0, sizeof(struct be_dma_mem));
1544         promiscous_cmd.size = sizeof(struct be_cmd_req_rx_filter);
1545         promiscous_cmd.va = pci_alloc_consistent(adapter->pdev,
1546                                 promiscous_cmd.size, &promiscous_cmd.dma);
1547         if (!promiscous_cmd.va) {
1548                 dev_err(&adapter->pdev->dev,
1549                                 "Memory allocation failure\n");
1550                 return -ENOMEM;
1551         }
1552
1553         spin_lock_bh(&adapter->mcc_lock);
1554
1555         wrb = wrb_from_mccq(adapter);
1556         if (!wrb) {
1557                 status = -EBUSY;
1558                 goto err;
1559         }
1560
1561         req = promiscous_cmd.va;
1562         sge = nonembedded_sgl(wrb);
1563
1564         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1565                                         OPCODE_COMMON_NTWK_RX_FILTER);
1566         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1567                         OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req));
1568
1569         req->if_id = cpu_to_le32(adapter->if_handle);
1570         req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1571         if (en)
1572                 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1573
1574         sge->pa_hi = cpu_to_le32(upper_32_bits(promiscous_cmd.dma));
1575         sge->pa_lo = cpu_to_le32(promiscous_cmd.dma & 0xFFFFFFFF);
1576         sge->len = cpu_to_le32(promiscous_cmd.size);
1577
1578         status = be_mcc_notify_wait(adapter);
1579
1580 err:
1581         spin_unlock_bh(&adapter->mcc_lock);
1582         pci_free_consistent(adapter->pdev, promiscous_cmd.size,
1583                         promiscous_cmd.va, promiscous_cmd.dma);
1584         return status;
1585 }
1586
1587 /*
1588  * Uses MCC for this command as it may be called in BH context
1589  * (mc == NULL) => multicast promiscuous
1590  */
1591 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1592                 struct net_device *netdev, struct be_dma_mem *mem)
1593 {
1594         struct be_mcc_wrb *wrb;
1595         struct be_cmd_req_mcast_mac_config *req = mem->va;
1596         struct be_sge *sge;
1597         int status;
1598
1599         spin_lock_bh(&adapter->mcc_lock);
1600
1601         wrb = wrb_from_mccq(adapter);
1602         if (!wrb) {
1603                 status = -EBUSY;
1604                 goto err;
1605         }
1606         sge = nonembedded_sgl(wrb);
1607         memset(req, 0, sizeof(*req));
1608
1609         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1610                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1611         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1612         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1613         sge->len = cpu_to_le32(mem->size);
1614
1615         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1616                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1617
1618         req->interface_id = if_id;
1619         if (netdev) {
1620                 int i;
1621                 struct netdev_hw_addr *ha;
1622
1623                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1624
1625                 i = 0;
1626                 netdev_for_each_mc_addr(ha, netdev)
1627                         memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1628         } else {
1629                 req->promiscuous = 1;
1630         }
1631
1632         status = be_mcc_notify_wait(adapter);
1633
1634 err:
1635         spin_unlock_bh(&adapter->mcc_lock);
1636         return status;
1637 }
1638
1639 /* Uses synchrounous mcc */
1640 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1641 {
1642         struct be_mcc_wrb *wrb;
1643         struct be_cmd_req_set_flow_control *req;
1644         int status;
1645
1646         spin_lock_bh(&adapter->mcc_lock);
1647
1648         wrb = wrb_from_mccq(adapter);
1649         if (!wrb) {
1650                 status = -EBUSY;
1651                 goto err;
1652         }
1653         req = embedded_payload(wrb);
1654
1655         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1656                         OPCODE_COMMON_SET_FLOW_CONTROL);
1657
1658         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1659                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1660
1661         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1662         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1663
1664         status = be_mcc_notify_wait(adapter);
1665
1666 err:
1667         spin_unlock_bh(&adapter->mcc_lock);
1668         return status;
1669 }
1670
1671 /* Uses sycn mcc */
1672 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1673 {
1674         struct be_mcc_wrb *wrb;
1675         struct be_cmd_req_get_flow_control *req;
1676         int status;
1677
1678         spin_lock_bh(&adapter->mcc_lock);
1679
1680         wrb = wrb_from_mccq(adapter);
1681         if (!wrb) {
1682                 status = -EBUSY;
1683                 goto err;
1684         }
1685         req = embedded_payload(wrb);
1686
1687         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1688                         OPCODE_COMMON_GET_FLOW_CONTROL);
1689
1690         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1691                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1692
1693         status = be_mcc_notify_wait(adapter);
1694         if (!status) {
1695                 struct be_cmd_resp_get_flow_control *resp =
1696                                                 embedded_payload(wrb);
1697                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1698                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1699         }
1700
1701 err:
1702         spin_unlock_bh(&adapter->mcc_lock);
1703         return status;
1704 }
1705
1706 /* Uses mbox */
1707 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1708                 u32 *mode, u32 *caps)
1709 {
1710         struct be_mcc_wrb *wrb;
1711         struct be_cmd_req_query_fw_cfg *req;
1712         int status;
1713
1714         if (mutex_lock_interruptible(&adapter->mbox_lock))
1715                 return -1;
1716
1717         wrb = wrb_from_mbox(adapter);
1718         req = embedded_payload(wrb);
1719
1720         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1721                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1722
1723         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1724                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1725
1726         status = be_mbox_notify_wait(adapter);
1727         if (!status) {
1728                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1729                 *port_num = le32_to_cpu(resp->phys_port);
1730                 *mode = le32_to_cpu(resp->function_mode);
1731                 *caps = le32_to_cpu(resp->function_caps);
1732         }
1733
1734         mutex_unlock(&adapter->mbox_lock);
1735         return status;
1736 }
1737
1738 /* Uses mbox */
1739 int be_cmd_reset_function(struct be_adapter *adapter)
1740 {
1741         struct be_mcc_wrb *wrb;
1742         struct be_cmd_req_hdr *req;
1743         int status;
1744
1745         if (mutex_lock_interruptible(&adapter->mbox_lock))
1746                 return -1;
1747
1748         wrb = wrb_from_mbox(adapter);
1749         req = embedded_payload(wrb);
1750
1751         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1752                         OPCODE_COMMON_FUNCTION_RESET);
1753
1754         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1755                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1756
1757         status = be_mbox_notify_wait(adapter);
1758
1759         mutex_unlock(&adapter->mbox_lock);
1760         return status;
1761 }
1762
1763 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1764 {
1765         struct be_mcc_wrb *wrb;
1766         struct be_cmd_req_rss_config *req;
1767         u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
1768                         0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
1769         int status;
1770
1771         if (mutex_lock_interruptible(&adapter->mbox_lock))
1772                 return -1;
1773
1774         wrb = wrb_from_mbox(adapter);
1775         req = embedded_payload(wrb);
1776
1777         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1778                 OPCODE_ETH_RSS_CONFIG);
1779
1780         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1781                 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1782
1783         req->if_id = cpu_to_le32(adapter->if_handle);
1784         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1785         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1786         memcpy(req->cpu_table, rsstable, table_size);
1787         memcpy(req->hash, myhash, sizeof(myhash));
1788         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1789
1790         status = be_mbox_notify_wait(adapter);
1791
1792         mutex_unlock(&adapter->mbox_lock);
1793         return status;
1794 }
1795
1796 /* Uses sync mcc */
1797 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1798                         u8 bcn, u8 sts, u8 state)
1799 {
1800         struct be_mcc_wrb *wrb;
1801         struct be_cmd_req_enable_disable_beacon *req;
1802         int status;
1803
1804         spin_lock_bh(&adapter->mcc_lock);
1805
1806         wrb = wrb_from_mccq(adapter);
1807         if (!wrb) {
1808                 status = -EBUSY;
1809                 goto err;
1810         }
1811         req = embedded_payload(wrb);
1812
1813         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1814                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1815
1816         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1817                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1818
1819         req->port_num = port_num;
1820         req->beacon_state = state;
1821         req->beacon_duration = bcn;
1822         req->status_duration = sts;
1823
1824         status = be_mcc_notify_wait(adapter);
1825
1826 err:
1827         spin_unlock_bh(&adapter->mcc_lock);
1828         return status;
1829 }
1830
1831 /* Uses sync mcc */
1832 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1833 {
1834         struct be_mcc_wrb *wrb;
1835         struct be_cmd_req_get_beacon_state *req;
1836         int status;
1837
1838         spin_lock_bh(&adapter->mcc_lock);
1839
1840         wrb = wrb_from_mccq(adapter);
1841         if (!wrb) {
1842                 status = -EBUSY;
1843                 goto err;
1844         }
1845         req = embedded_payload(wrb);
1846
1847         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1848                         OPCODE_COMMON_GET_BEACON_STATE);
1849
1850         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1851                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1852
1853         req->port_num = port_num;
1854
1855         status = be_mcc_notify_wait(adapter);
1856         if (!status) {
1857                 struct be_cmd_resp_get_beacon_state *resp =
1858                                                 embedded_payload(wrb);
1859                 *state = resp->beacon_state;
1860         }
1861
1862 err:
1863         spin_unlock_bh(&adapter->mcc_lock);
1864         return status;
1865 }
1866
1867 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1868                         u32 data_size, u32 data_offset, const char *obj_name,
1869                         u32 *data_written, u8 *addn_status)
1870 {
1871         struct be_mcc_wrb *wrb;
1872         struct lancer_cmd_req_write_object *req;
1873         struct lancer_cmd_resp_write_object *resp;
1874         void *ctxt = NULL;
1875         int status;
1876
1877         spin_lock_bh(&adapter->mcc_lock);
1878         adapter->flash_status = 0;
1879
1880         wrb = wrb_from_mccq(adapter);
1881         if (!wrb) {
1882                 status = -EBUSY;
1883                 goto err_unlock;
1884         }
1885
1886         req = embedded_payload(wrb);
1887
1888         be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object),
1889                         true, 1, OPCODE_COMMON_WRITE_OBJECT);
1890         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1891
1892         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1893                                 OPCODE_COMMON_WRITE_OBJECT,
1894                                 sizeof(struct lancer_cmd_req_write_object));
1895
1896         ctxt = &req->context;
1897         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1898                         write_length, ctxt, data_size);
1899
1900         if (data_size == 0)
1901                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1902                                 eof, ctxt, 1);
1903         else
1904                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1905                                 eof, ctxt, 0);
1906
1907         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1908         req->write_offset = cpu_to_le32(data_offset);
1909         strcpy(req->object_name, obj_name);
1910         req->descriptor_count = cpu_to_le32(1);
1911         req->buf_len = cpu_to_le32(data_size);
1912         req->addr_low = cpu_to_le32((cmd->dma +
1913                                 sizeof(struct lancer_cmd_req_write_object))
1914                                 & 0xFFFFFFFF);
1915         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1916                                 sizeof(struct lancer_cmd_req_write_object)));
1917
1918         be_mcc_notify(adapter);
1919         spin_unlock_bh(&adapter->mcc_lock);
1920
1921         if (!wait_for_completion_timeout(&adapter->flash_compl,
1922                         msecs_to_jiffies(12000)))
1923                 status = -1;
1924         else
1925                 status = adapter->flash_status;
1926
1927         resp = embedded_payload(wrb);
1928         if (!status) {
1929                 *data_written = le32_to_cpu(resp->actual_write_len);
1930         } else {
1931                 *addn_status = resp->additional_status;
1932                 status = resp->status;
1933         }
1934
1935         return status;
1936
1937 err_unlock:
1938         spin_unlock_bh(&adapter->mcc_lock);
1939         return status;
1940 }
1941
1942 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1943                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1944 {
1945         struct be_mcc_wrb *wrb;
1946         struct be_cmd_write_flashrom *req;
1947         struct be_sge *sge;
1948         int status;
1949
1950         spin_lock_bh(&adapter->mcc_lock);
1951         adapter->flash_status = 0;
1952
1953         wrb = wrb_from_mccq(adapter);
1954         if (!wrb) {
1955                 status = -EBUSY;
1956                 goto err_unlock;
1957         }
1958         req = cmd->va;
1959         sge = nonembedded_sgl(wrb);
1960
1961         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1962                         OPCODE_COMMON_WRITE_FLASHROM);
1963         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1964
1965         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1966                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1967         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1968         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1969         sge->len = cpu_to_le32(cmd->size);
1970
1971         req->params.op_type = cpu_to_le32(flash_type);
1972         req->params.op_code = cpu_to_le32(flash_opcode);
1973         req->params.data_buf_size = cpu_to_le32(buf_size);
1974
1975         be_mcc_notify(adapter);
1976         spin_unlock_bh(&adapter->mcc_lock);
1977
1978         if (!wait_for_completion_timeout(&adapter->flash_compl,
1979                         msecs_to_jiffies(12000)))
1980                 status = -1;
1981         else
1982                 status = adapter->flash_status;
1983
1984         return status;
1985
1986 err_unlock:
1987         spin_unlock_bh(&adapter->mcc_lock);
1988         return status;
1989 }
1990
1991 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1992                          int offset)
1993 {
1994         struct be_mcc_wrb *wrb;
1995         struct be_cmd_write_flashrom *req;
1996         int status;
1997
1998         spin_lock_bh(&adapter->mcc_lock);
1999
2000         wrb = wrb_from_mccq(adapter);
2001         if (!wrb) {
2002                 status = -EBUSY;
2003                 goto err;
2004         }
2005         req = embedded_payload(wrb);
2006
2007         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
2008                         OPCODE_COMMON_READ_FLASHROM);
2009
2010         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2011                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
2012
2013         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
2014         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2015         req->params.offset = cpu_to_le32(offset);
2016         req->params.data_buf_size = cpu_to_le32(0x4);
2017
2018         status = be_mcc_notify_wait(adapter);
2019         if (!status)
2020                 memcpy(flashed_crc, req->params.data_buf, 4);
2021
2022 err:
2023         spin_unlock_bh(&adapter->mcc_lock);
2024         return status;
2025 }
2026
2027 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2028                                 struct be_dma_mem *nonemb_cmd)
2029 {
2030         struct be_mcc_wrb *wrb;
2031         struct be_cmd_req_acpi_wol_magic_config *req;
2032         struct be_sge *sge;
2033         int status;
2034
2035         spin_lock_bh(&adapter->mcc_lock);
2036
2037         wrb = wrb_from_mccq(adapter);
2038         if (!wrb) {
2039                 status = -EBUSY;
2040                 goto err;
2041         }
2042         req = nonemb_cmd->va;
2043         sge = nonembedded_sgl(wrb);
2044
2045         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2046                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
2047
2048         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2049                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
2050         memcpy(req->magic_mac, mac, ETH_ALEN);
2051
2052         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2053         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2054         sge->len = cpu_to_le32(nonemb_cmd->size);
2055
2056         status = be_mcc_notify_wait(adapter);
2057
2058 err:
2059         spin_unlock_bh(&adapter->mcc_lock);
2060         return status;
2061 }
2062
2063 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2064                         u8 loopback_type, u8 enable)
2065 {
2066         struct be_mcc_wrb *wrb;
2067         struct be_cmd_req_set_lmode *req;
2068         int status;
2069
2070         spin_lock_bh(&adapter->mcc_lock);
2071
2072         wrb = wrb_from_mccq(adapter);
2073         if (!wrb) {
2074                 status = -EBUSY;
2075                 goto err;
2076         }
2077
2078         req = embedded_payload(wrb);
2079
2080         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2081                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
2082
2083         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2084                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
2085                         sizeof(*req));
2086
2087         req->src_port = port_num;
2088         req->dest_port = port_num;
2089         req->loopback_type = loopback_type;
2090         req->loopback_state = enable;
2091
2092         status = be_mcc_notify_wait(adapter);
2093 err:
2094         spin_unlock_bh(&adapter->mcc_lock);
2095         return status;
2096 }
2097
2098 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2099                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2100 {
2101         struct be_mcc_wrb *wrb;
2102         struct be_cmd_req_loopback_test *req;
2103         int status;
2104
2105         spin_lock_bh(&adapter->mcc_lock);
2106
2107         wrb = wrb_from_mccq(adapter);
2108         if (!wrb) {
2109                 status = -EBUSY;
2110                 goto err;
2111         }
2112
2113         req = embedded_payload(wrb);
2114
2115         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2116                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
2117
2118         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2119                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
2120         req->hdr.timeout = cpu_to_le32(4);
2121
2122         req->pattern = cpu_to_le64(pattern);
2123         req->src_port = cpu_to_le32(port_num);
2124         req->dest_port = cpu_to_le32(port_num);
2125         req->pkt_size = cpu_to_le32(pkt_size);
2126         req->num_pkts = cpu_to_le32(num_pkts);
2127         req->loopback_type = cpu_to_le32(loopback_type);
2128
2129         status = be_mcc_notify_wait(adapter);
2130         if (!status) {
2131                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2132                 status = le32_to_cpu(resp->status);
2133         }
2134
2135 err:
2136         spin_unlock_bh(&adapter->mcc_lock);
2137         return status;
2138 }
2139
2140 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2141                                 u32 byte_cnt, struct be_dma_mem *cmd)
2142 {
2143         struct be_mcc_wrb *wrb;
2144         struct be_cmd_req_ddrdma_test *req;
2145         struct be_sge *sge;
2146         int status;
2147         int i, j = 0;
2148
2149         spin_lock_bh(&adapter->mcc_lock);
2150
2151         wrb = wrb_from_mccq(adapter);
2152         if (!wrb) {
2153                 status = -EBUSY;
2154                 goto err;
2155         }
2156         req = cmd->va;
2157         sge = nonembedded_sgl(wrb);
2158         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
2159                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
2160         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2161                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
2162
2163         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2164         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2165         sge->len = cpu_to_le32(cmd->size);
2166
2167         req->pattern = cpu_to_le64(pattern);
2168         req->byte_count = cpu_to_le32(byte_cnt);
2169         for (i = 0; i < byte_cnt; i++) {
2170                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2171                 j++;
2172                 if (j > 7)
2173                         j = 0;
2174         }
2175
2176         status = be_mcc_notify_wait(adapter);
2177
2178         if (!status) {
2179                 struct be_cmd_resp_ddrdma_test *resp;
2180                 resp = cmd->va;
2181                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2182                                 resp->snd_err) {
2183                         status = -1;
2184                 }
2185         }
2186
2187 err:
2188         spin_unlock_bh(&adapter->mcc_lock);
2189         return status;
2190 }
2191
2192 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2193                                 struct be_dma_mem *nonemb_cmd)
2194 {
2195         struct be_mcc_wrb *wrb;
2196         struct be_cmd_req_seeprom_read *req;
2197         struct be_sge *sge;
2198         int status;
2199
2200         spin_lock_bh(&adapter->mcc_lock);
2201
2202         wrb = wrb_from_mccq(adapter);
2203         if (!wrb) {
2204                 status = -EBUSY;
2205                 goto err;
2206         }
2207         req = nonemb_cmd->va;
2208         sge = nonembedded_sgl(wrb);
2209
2210         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2211                         OPCODE_COMMON_SEEPROM_READ);
2212
2213         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2214                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
2215
2216         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2217         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2218         sge->len = cpu_to_le32(nonemb_cmd->size);
2219
2220         status = be_mcc_notify_wait(adapter);
2221
2222 err:
2223         spin_unlock_bh(&adapter->mcc_lock);
2224         return status;
2225 }
2226
2227 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
2228 {
2229         struct be_mcc_wrb *wrb;
2230         struct be_cmd_req_get_phy_info *req;
2231         struct be_sge *sge;
2232         int status;
2233
2234         spin_lock_bh(&adapter->mcc_lock);
2235
2236         wrb = wrb_from_mccq(adapter);
2237         if (!wrb) {
2238                 status = -EBUSY;
2239                 goto err;
2240         }
2241
2242         req = cmd->va;
2243         sge = nonembedded_sgl(wrb);
2244
2245         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2246                                 OPCODE_COMMON_GET_PHY_DETAILS);
2247
2248         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2249                         OPCODE_COMMON_GET_PHY_DETAILS,
2250                         sizeof(*req));
2251
2252         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2253         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2254         sge->len = cpu_to_le32(cmd->size);
2255
2256         status = be_mcc_notify_wait(adapter);
2257 err:
2258         spin_unlock_bh(&adapter->mcc_lock);
2259         return status;
2260 }
2261
2262 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2263 {
2264         struct be_mcc_wrb *wrb;
2265         struct be_cmd_req_set_qos *req;
2266         int status;
2267
2268         spin_lock_bh(&adapter->mcc_lock);
2269
2270         wrb = wrb_from_mccq(adapter);
2271         if (!wrb) {
2272                 status = -EBUSY;
2273                 goto err;
2274         }
2275
2276         req = embedded_payload(wrb);
2277
2278         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2279                                 OPCODE_COMMON_SET_QOS);
2280
2281         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2282                         OPCODE_COMMON_SET_QOS, sizeof(*req));
2283
2284         req->hdr.domain = domain;
2285         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2286         req->max_bps_nic = cpu_to_le32(bps);
2287
2288         status = be_mcc_notify_wait(adapter);
2289
2290 err:
2291         spin_unlock_bh(&adapter->mcc_lock);
2292         return status;
2293 }
2294
2295 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2296 {
2297         struct be_mcc_wrb *wrb;
2298         struct be_cmd_req_cntl_attribs *req;
2299         struct be_cmd_resp_cntl_attribs *resp;
2300         struct be_sge *sge;
2301         int status;
2302         int payload_len = max(sizeof(*req), sizeof(*resp));
2303         struct mgmt_controller_attrib *attribs;
2304         struct be_dma_mem attribs_cmd;
2305
2306         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2307         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2308         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2309                                                 &attribs_cmd.dma);
2310         if (!attribs_cmd.va) {
2311                 dev_err(&adapter->pdev->dev,
2312                                 "Memory allocation failure\n");
2313                 return -ENOMEM;
2314         }
2315
2316         if (mutex_lock_interruptible(&adapter->mbox_lock))
2317                 return -1;
2318
2319         wrb = wrb_from_mbox(adapter);
2320         if (!wrb) {
2321                 status = -EBUSY;
2322                 goto err;
2323         }
2324         req = attribs_cmd.va;
2325         sge = nonembedded_sgl(wrb);
2326
2327         be_wrb_hdr_prepare(wrb, payload_len, false, 1,
2328                         OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
2329         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2330                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2331         sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2332         sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2333         sge->len = cpu_to_le32(attribs_cmd.size);
2334
2335         status = be_mbox_notify_wait(adapter);
2336         if (!status) {
2337                 attribs = (struct mgmt_controller_attrib *)( attribs_cmd.va +
2338                                         sizeof(struct be_cmd_resp_hdr));
2339                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2340         }
2341
2342 err:
2343         mutex_unlock(&adapter->mbox_lock);
2344         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2345                                         attribs_cmd.dma);
2346         return status;
2347 }
2348
2349 /* Uses mbox */
2350 int be_cmd_check_native_mode(struct be_adapter *adapter)
2351 {
2352         struct be_mcc_wrb *wrb;
2353         struct be_cmd_req_set_func_cap *req;
2354         int status;
2355
2356         if (mutex_lock_interruptible(&adapter->mbox_lock))
2357                 return -1;
2358
2359         wrb = wrb_from_mbox(adapter);
2360         if (!wrb) {
2361                 status = -EBUSY;
2362                 goto err;
2363         }
2364
2365         req = embedded_payload(wrb);
2366
2367         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2368                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2369
2370         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2371                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2372
2373         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2374                                 CAPABILITY_BE3_NATIVE_ERX_API);
2375         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2376
2377         status = be_mbox_notify_wait(adapter);
2378         if (!status) {
2379                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2380                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2381                                         CAPABILITY_BE3_NATIVE_ERX_API;
2382         }
2383 err:
2384         mutex_unlock(&adapter->mbox_lock);
2385         return status;
2386 }