2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 static void be_mcc_notify(struct be_adapter *adapter)
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
30 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
33 /* To check if valid bit is set, check the entire word as we don't know
34 * the endianness of the data (old entry is host endian while a new entry is
36 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
38 if (compl->flags != 0) {
39 compl->flags = le32_to_cpu(compl->flags);
40 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
47 /* Need to reset the entire word that houses the valid bit */
48 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
53 static int be_mcc_compl_process(struct be_adapter *adapter,
54 struct be_mcc_compl *compl)
56 u16 compl_status, extd_status;
58 /* Just swap the status to host endian; mcc tag is opaquely copied
60 be_dws_le_to_cpu(compl, 4);
62 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
63 CQE_STATUS_COMPL_MASK;
65 if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
66 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
67 adapter->flash_status = compl_status;
68 complete(&adapter->flash_compl);
71 if (compl_status == MCC_STATUS_SUCCESS) {
72 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
73 struct be_cmd_resp_get_stats *resp =
74 adapter->stats_cmd.va;
75 be_dws_le_to_cpu(&resp->hw_stats,
76 sizeof(resp->hw_stats));
77 netdev_stats_update(adapter);
78 adapter->stats_ioctl_sent = false;
80 } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
81 (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
82 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
84 dev_warn(&adapter->pdev->dev,
85 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
86 compl->tag0, compl_status, extd_status);
91 /* Link state evt is a string of bytes; no need for endian swapping */
92 static void be_async_link_state_process(struct be_adapter *adapter,
93 struct be_async_event_link_state *evt)
95 be_link_status_update(adapter,
96 evt->port_link_status == ASYNC_EVENT_LINK_UP);
99 /* Grp5 CoS Priority evt */
100 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
101 struct be_async_event_grp5_cos_priority *evt)
104 adapter->vlan_prio_bmap = evt->available_priority_bmap;
105 adapter->recommended_prio =
106 evt->reco_default_priority << VLAN_PRIO_SHIFT;
110 /* Grp5 QOS Speed evt */
111 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
112 struct be_async_event_grp5_qos_link_speed *evt)
114 if (evt->physical_port == adapter->port_num) {
115 /* qos_link_speed is in units of 10 Mbps */
116 adapter->link_speed = evt->qos_link_speed * 10;
120 static void be_async_grp5_evt_process(struct be_adapter *adapter,
121 u32 trailer, struct be_mcc_compl *evt)
125 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
126 ASYNC_TRAILER_EVENT_TYPE_MASK;
128 switch (event_type) {
129 case ASYNC_EVENT_COS_PRIORITY:
130 be_async_grp5_cos_priority_process(adapter,
131 (struct be_async_event_grp5_cos_priority *)evt);
133 case ASYNC_EVENT_QOS_SPEED:
134 be_async_grp5_qos_speed_process(adapter,
135 (struct be_async_event_grp5_qos_link_speed *)evt);
138 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
143 static inline bool is_link_state_evt(u32 trailer)
145 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
146 ASYNC_TRAILER_EVENT_CODE_MASK) ==
147 ASYNC_EVENT_CODE_LINK_STATE;
150 static inline bool is_grp5_evt(u32 trailer)
152 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
153 ASYNC_TRAILER_EVENT_CODE_MASK) ==
154 ASYNC_EVENT_CODE_GRP_5);
157 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
159 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
160 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
162 if (be_mcc_compl_is_new(compl)) {
163 queue_tail_inc(mcc_cq);
169 void be_async_mcc_enable(struct be_adapter *adapter)
171 spin_lock_bh(&adapter->mcc_cq_lock);
173 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
174 adapter->mcc_obj.rearm_cq = true;
176 spin_unlock_bh(&adapter->mcc_cq_lock);
179 void be_async_mcc_disable(struct be_adapter *adapter)
181 adapter->mcc_obj.rearm_cq = false;
184 int be_process_mcc(struct be_adapter *adapter, int *status)
186 struct be_mcc_compl *compl;
188 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
190 spin_lock_bh(&adapter->mcc_cq_lock);
191 while ((compl = be_mcc_compl_get(adapter))) {
192 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
193 /* Interpret flags as an async trailer */
194 if (is_link_state_evt(compl->flags))
195 be_async_link_state_process(adapter,
196 (struct be_async_event_link_state *) compl);
197 else if (is_grp5_evt(compl->flags))
198 be_async_grp5_evt_process(adapter,
199 compl->flags, compl);
200 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
201 *status = be_mcc_compl_process(adapter, compl);
202 atomic_dec(&mcc_obj->q.used);
204 be_mcc_compl_use(compl);
208 spin_unlock_bh(&adapter->mcc_cq_lock);
212 /* Wait till no more pending mcc requests are present */
213 static int be_mcc_wait_compl(struct be_adapter *adapter)
215 #define mcc_timeout 120000 /* 12s timeout */
216 int i, num, status = 0;
217 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
219 for (i = 0; i < mcc_timeout; i++) {
220 num = be_process_mcc(adapter, &status);
222 be_cq_notify(adapter, mcc_obj->cq.id,
223 mcc_obj->rearm_cq, num);
225 if (atomic_read(&mcc_obj->q.used) == 0)
229 if (i == mcc_timeout) {
230 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
236 /* Notify MCC requests and wait for completion */
237 static int be_mcc_notify_wait(struct be_adapter *adapter)
239 be_mcc_notify(adapter);
240 return be_mcc_wait_compl(adapter);
243 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
249 ready = ioread32(db);
250 if (ready == 0xffffffff) {
251 dev_err(&adapter->pdev->dev,
252 "pci slot disconnected\n");
256 ready &= MPU_MAILBOX_DB_RDY_MASK;
261 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
262 be_detect_dump_ue(adapter);
266 set_current_state(TASK_INTERRUPTIBLE);
267 schedule_timeout(msecs_to_jiffies(1));
275 * Insert the mailbox address into the doorbell in two steps
276 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
278 static int be_mbox_notify_wait(struct be_adapter *adapter)
282 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
283 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
284 struct be_mcc_mailbox *mbox = mbox_mem->va;
285 struct be_mcc_compl *compl = &mbox->compl;
287 /* wait for ready to be set */
288 status = be_mbox_db_ready_wait(adapter, db);
292 val |= MPU_MAILBOX_DB_HI_MASK;
293 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
294 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
297 /* wait for ready to be set */
298 status = be_mbox_db_ready_wait(adapter, db);
303 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
304 val |= (u32)(mbox_mem->dma >> 4) << 2;
307 status = be_mbox_db_ready_wait(adapter, db);
311 /* A cq entry has been made now */
312 if (be_mcc_compl_is_new(compl)) {
313 status = be_mcc_compl_process(adapter, &mbox->compl);
314 be_mcc_compl_use(compl);
318 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
324 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
326 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
328 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
329 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
335 int be_cmd_POST(struct be_adapter *adapter)
338 int status, timeout = 0;
341 status = be_POST_stage_get(adapter, &stage);
343 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
346 } else if (stage != POST_STAGE_ARMFW_RDY) {
347 set_current_state(TASK_INTERRUPTIBLE);
348 schedule_timeout(2 * HZ);
353 } while (timeout < 40);
355 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
359 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
361 return wrb->payload.embedded_payload;
364 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
366 return &wrb->payload.sgl[0];
369 /* Don't touch the hdr after it's prepared */
370 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
371 bool embedded, u8 sge_cnt, u32 opcode)
374 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
376 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
377 MCC_WRB_SGE_CNT_SHIFT;
378 wrb->payload_length = payload_len;
380 be_dws_cpu_to_le(wrb, 8);
383 /* Don't touch the hdr after it's prepared */
384 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
385 u8 subsystem, u8 opcode, int cmd_len)
387 req_hdr->opcode = opcode;
388 req_hdr->subsystem = subsystem;
389 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
390 req_hdr->version = 0;
393 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
394 struct be_dma_mem *mem)
396 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
397 u64 dma = (u64)mem->dma;
399 for (i = 0; i < buf_pages; i++) {
400 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
401 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
406 /* Converts interrupt delay in microseconds to multiplier value */
407 static u32 eq_delay_to_mult(u32 usec_delay)
409 #define MAX_INTR_RATE 651042
410 const u32 round = 10;
416 u32 interrupt_rate = 1000000 / usec_delay;
417 /* Max delay, corresponding to the lowest interrupt rate */
418 if (interrupt_rate == 0)
421 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
422 multiplier /= interrupt_rate;
423 /* Round the multiplier to the closest value.*/
424 multiplier = (multiplier + round/2) / round;
425 multiplier = min(multiplier, (u32)1023);
431 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
433 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
434 struct be_mcc_wrb *wrb
435 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
436 memset(wrb, 0, sizeof(*wrb));
440 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
442 struct be_queue_info *mccq = &adapter->mcc_obj.q;
443 struct be_mcc_wrb *wrb;
445 if (atomic_read(&mccq->used) >= mccq->len) {
446 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
450 wrb = queue_head_node(mccq);
451 queue_head_inc(mccq);
452 atomic_inc(&mccq->used);
453 memset(wrb, 0, sizeof(*wrb));
457 /* Tell fw we're about to start firing cmds by writing a
458 * special pattern across the wrb hdr; uses mbox
460 int be_cmd_fw_init(struct be_adapter *adapter)
465 if (mutex_lock_interruptible(&adapter->mbox_lock))
468 wrb = (u8 *)wrb_from_mbox(adapter);
478 status = be_mbox_notify_wait(adapter);
480 mutex_unlock(&adapter->mbox_lock);
484 /* Tell fw we're done with firing cmds by writing a
485 * special pattern across the wrb hdr; uses mbox
487 int be_cmd_fw_clean(struct be_adapter *adapter)
492 if (adapter->eeh_err)
495 if (mutex_lock_interruptible(&adapter->mbox_lock))
498 wrb = (u8 *)wrb_from_mbox(adapter);
508 status = be_mbox_notify_wait(adapter);
510 mutex_unlock(&adapter->mbox_lock);
513 int be_cmd_eq_create(struct be_adapter *adapter,
514 struct be_queue_info *eq, int eq_delay)
516 struct be_mcc_wrb *wrb;
517 struct be_cmd_req_eq_create *req;
518 struct be_dma_mem *q_mem = &eq->dma_mem;
521 if (mutex_lock_interruptible(&adapter->mbox_lock))
524 wrb = wrb_from_mbox(adapter);
525 req = embedded_payload(wrb);
527 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
529 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
530 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
532 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
534 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
536 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
537 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
538 __ilog2_u32(eq->len/256));
539 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
540 eq_delay_to_mult(eq_delay));
541 be_dws_cpu_to_le(req->context, sizeof(req->context));
543 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
545 status = be_mbox_notify_wait(adapter);
547 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
548 eq->id = le16_to_cpu(resp->eq_id);
552 mutex_unlock(&adapter->mbox_lock);
557 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
558 u8 type, bool permanent, u32 if_handle)
560 struct be_mcc_wrb *wrb;
561 struct be_cmd_req_mac_query *req;
564 if (mutex_lock_interruptible(&adapter->mbox_lock))
567 wrb = wrb_from_mbox(adapter);
568 req = embedded_payload(wrb);
570 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
571 OPCODE_COMMON_NTWK_MAC_QUERY);
573 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
574 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
580 req->if_id = cpu_to_le16((u16) if_handle);
584 status = be_mbox_notify_wait(adapter);
586 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
587 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
590 mutex_unlock(&adapter->mbox_lock);
594 /* Uses synchronous MCCQ */
595 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
596 u32 if_id, u32 *pmac_id)
598 struct be_mcc_wrb *wrb;
599 struct be_cmd_req_pmac_add *req;
602 spin_lock_bh(&adapter->mcc_lock);
604 wrb = wrb_from_mccq(adapter);
609 req = embedded_payload(wrb);
611 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
612 OPCODE_COMMON_NTWK_PMAC_ADD);
614 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
615 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
617 req->if_id = cpu_to_le32(if_id);
618 memcpy(req->mac_address, mac_addr, ETH_ALEN);
620 status = be_mcc_notify_wait(adapter);
622 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
623 *pmac_id = le32_to_cpu(resp->pmac_id);
627 spin_unlock_bh(&adapter->mcc_lock);
631 /* Uses synchronous MCCQ */
632 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
634 struct be_mcc_wrb *wrb;
635 struct be_cmd_req_pmac_del *req;
638 spin_lock_bh(&adapter->mcc_lock);
640 wrb = wrb_from_mccq(adapter);
645 req = embedded_payload(wrb);
647 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
648 OPCODE_COMMON_NTWK_PMAC_DEL);
650 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
651 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
653 req->if_id = cpu_to_le32(if_id);
654 req->pmac_id = cpu_to_le32(pmac_id);
656 status = be_mcc_notify_wait(adapter);
659 spin_unlock_bh(&adapter->mcc_lock);
664 int be_cmd_cq_create(struct be_adapter *adapter,
665 struct be_queue_info *cq, struct be_queue_info *eq,
666 bool sol_evts, bool no_delay, int coalesce_wm)
668 struct be_mcc_wrb *wrb;
669 struct be_cmd_req_cq_create *req;
670 struct be_dma_mem *q_mem = &cq->dma_mem;
674 if (mutex_lock_interruptible(&adapter->mbox_lock))
677 wrb = wrb_from_mbox(adapter);
678 req = embedded_payload(wrb);
679 ctxt = &req->context;
681 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
682 OPCODE_COMMON_CQ_CREATE);
684 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
685 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
687 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
689 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
690 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
691 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
692 __ilog2_u32(cq->len/256));
693 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
694 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
695 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
696 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
697 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
698 be_dws_cpu_to_le(ctxt, sizeof(req->context));
700 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
702 status = be_mbox_notify_wait(adapter);
704 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
705 cq->id = le16_to_cpu(resp->cq_id);
709 mutex_unlock(&adapter->mbox_lock);
714 static u32 be_encoded_q_len(int q_len)
716 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
717 if (len_encoded == 16)
722 int be_cmd_mccq_create(struct be_adapter *adapter,
723 struct be_queue_info *mccq,
724 struct be_queue_info *cq)
726 struct be_mcc_wrb *wrb;
727 struct be_cmd_req_mcc_create *req;
728 struct be_dma_mem *q_mem = &mccq->dma_mem;
732 if (mutex_lock_interruptible(&adapter->mbox_lock))
735 wrb = wrb_from_mbox(adapter);
736 req = embedded_payload(wrb);
737 ctxt = &req->context;
739 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
740 OPCODE_COMMON_MCC_CREATE_EXT);
742 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
743 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
745 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
747 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
748 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
749 be_encoded_q_len(mccq->len));
750 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
751 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
752 req->async_event_bitmap[0] |= 0x00000022;
753 be_dws_cpu_to_le(ctxt, sizeof(req->context));
755 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
757 status = be_mbox_notify_wait(adapter);
759 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
760 mccq->id = le16_to_cpu(resp->id);
761 mccq->created = true;
763 mutex_unlock(&adapter->mbox_lock);
768 int be_cmd_txq_create(struct be_adapter *adapter,
769 struct be_queue_info *txq,
770 struct be_queue_info *cq)
772 struct be_mcc_wrb *wrb;
773 struct be_cmd_req_eth_tx_create *req;
774 struct be_dma_mem *q_mem = &txq->dma_mem;
778 if (mutex_lock_interruptible(&adapter->mbox_lock))
781 wrb = wrb_from_mbox(adapter);
782 req = embedded_payload(wrb);
783 ctxt = &req->context;
785 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
786 OPCODE_ETH_TX_CREATE);
788 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
791 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
792 req->ulp_num = BE_ULP1_NUM;
793 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
795 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
796 be_encoded_q_len(txq->len));
797 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
798 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
800 be_dws_cpu_to_le(ctxt, sizeof(req->context));
802 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
804 status = be_mbox_notify_wait(adapter);
806 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
807 txq->id = le16_to_cpu(resp->cid);
811 mutex_unlock(&adapter->mbox_lock);
817 int be_cmd_rxq_create(struct be_adapter *adapter,
818 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
819 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
821 struct be_mcc_wrb *wrb;
822 struct be_cmd_req_eth_rx_create *req;
823 struct be_dma_mem *q_mem = &rxq->dma_mem;
826 if (mutex_lock_interruptible(&adapter->mbox_lock))
829 wrb = wrb_from_mbox(adapter);
830 req = embedded_payload(wrb);
832 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
833 OPCODE_ETH_RX_CREATE);
835 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
838 req->cq_id = cpu_to_le16(cq_id);
839 req->frag_size = fls(frag_size) - 1;
841 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
842 req->interface_id = cpu_to_le32(if_id);
843 req->max_frame_size = cpu_to_le16(max_frame_size);
844 req->rss_queue = cpu_to_le32(rss);
846 status = be_mbox_notify_wait(adapter);
848 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
849 rxq->id = le16_to_cpu(resp->id);
851 *rss_id = resp->rss_id;
854 mutex_unlock(&adapter->mbox_lock);
859 /* Generic destroyer function for all types of queues
862 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
865 struct be_mcc_wrb *wrb;
866 struct be_cmd_req_q_destroy *req;
867 u8 subsys = 0, opcode = 0;
870 if (adapter->eeh_err)
873 if (mutex_lock_interruptible(&adapter->mbox_lock))
876 wrb = wrb_from_mbox(adapter);
877 req = embedded_payload(wrb);
879 switch (queue_type) {
881 subsys = CMD_SUBSYSTEM_COMMON;
882 opcode = OPCODE_COMMON_EQ_DESTROY;
885 subsys = CMD_SUBSYSTEM_COMMON;
886 opcode = OPCODE_COMMON_CQ_DESTROY;
889 subsys = CMD_SUBSYSTEM_ETH;
890 opcode = OPCODE_ETH_TX_DESTROY;
893 subsys = CMD_SUBSYSTEM_ETH;
894 opcode = OPCODE_ETH_RX_DESTROY;
897 subsys = CMD_SUBSYSTEM_COMMON;
898 opcode = OPCODE_COMMON_MCC_DESTROY;
904 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
906 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
907 req->id = cpu_to_le16(q->id);
909 status = be_mbox_notify_wait(adapter);
911 mutex_unlock(&adapter->mbox_lock);
916 /* Create an rx filtering policy configuration on an i/f
919 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
920 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
923 struct be_mcc_wrb *wrb;
924 struct be_cmd_req_if_create *req;
927 if (mutex_lock_interruptible(&adapter->mbox_lock))
930 wrb = wrb_from_mbox(adapter);
931 req = embedded_payload(wrb);
933 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
934 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
936 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
937 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
939 req->hdr.domain = domain;
940 req->capability_flags = cpu_to_le32(cap_flags);
941 req->enable_flags = cpu_to_le32(en_flags);
942 req->pmac_invalid = pmac_invalid;
944 memcpy(req->mac_addr, mac, ETH_ALEN);
946 status = be_mbox_notify_wait(adapter);
948 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
949 *if_handle = le32_to_cpu(resp->interface_id);
951 *pmac_id = le32_to_cpu(resp->pmac_id);
954 mutex_unlock(&adapter->mbox_lock);
959 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
961 struct be_mcc_wrb *wrb;
962 struct be_cmd_req_if_destroy *req;
965 if (adapter->eeh_err)
968 if (mutex_lock_interruptible(&adapter->mbox_lock))
971 wrb = wrb_from_mbox(adapter);
972 req = embedded_payload(wrb);
974 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
975 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
977 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
978 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
980 req->interface_id = cpu_to_le32(interface_id);
982 status = be_mbox_notify_wait(adapter);
984 mutex_unlock(&adapter->mbox_lock);
989 /* Get stats is a non embedded command: the request is not embedded inside
990 * WRB but is a separate dma memory block
991 * Uses asynchronous MCC
993 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
995 struct be_mcc_wrb *wrb;
996 struct be_cmd_req_get_stats *req;
1000 spin_lock_bh(&adapter->mcc_lock);
1002 wrb = wrb_from_mccq(adapter);
1007 req = nonemb_cmd->va;
1008 sge = nonembedded_sgl(wrb);
1010 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1011 OPCODE_ETH_GET_STATISTICS);
1013 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1014 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
1015 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1016 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1017 sge->len = cpu_to_le32(nonemb_cmd->size);
1019 be_mcc_notify(adapter);
1020 adapter->stats_ioctl_sent = true;
1023 spin_unlock_bh(&adapter->mcc_lock);
1027 /* Uses synchronous mcc */
1028 int be_cmd_link_status_query(struct be_adapter *adapter,
1029 bool *link_up, u8 *mac_speed, u16 *link_speed)
1031 struct be_mcc_wrb *wrb;
1032 struct be_cmd_req_link_status *req;
1035 spin_lock_bh(&adapter->mcc_lock);
1037 wrb = wrb_from_mccq(adapter);
1042 req = embedded_payload(wrb);
1046 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1047 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1049 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1050 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1052 status = be_mcc_notify_wait(adapter);
1054 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1055 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1057 *link_speed = le16_to_cpu(resp->link_speed);
1058 *mac_speed = resp->mac_speed;
1063 spin_unlock_bh(&adapter->mcc_lock);
1068 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1070 struct be_mcc_wrb *wrb;
1071 struct be_cmd_req_get_fw_version *req;
1074 if (mutex_lock_interruptible(&adapter->mbox_lock))
1077 wrb = wrb_from_mbox(adapter);
1078 req = embedded_payload(wrb);
1080 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1081 OPCODE_COMMON_GET_FW_VERSION);
1083 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1084 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1086 status = be_mbox_notify_wait(adapter);
1088 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1089 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1092 mutex_unlock(&adapter->mbox_lock);
1096 /* set the EQ delay interval of an EQ to specified value
1099 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1101 struct be_mcc_wrb *wrb;
1102 struct be_cmd_req_modify_eq_delay *req;
1105 spin_lock_bh(&adapter->mcc_lock);
1107 wrb = wrb_from_mccq(adapter);
1112 req = embedded_payload(wrb);
1114 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1115 OPCODE_COMMON_MODIFY_EQ_DELAY);
1117 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1118 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1120 req->num_eq = cpu_to_le32(1);
1121 req->delay[0].eq_id = cpu_to_le32(eq_id);
1122 req->delay[0].phase = 0;
1123 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1125 be_mcc_notify(adapter);
1128 spin_unlock_bh(&adapter->mcc_lock);
1132 /* Uses sycnhronous mcc */
1133 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1134 u32 num, bool untagged, bool promiscuous)
1136 struct be_mcc_wrb *wrb;
1137 struct be_cmd_req_vlan_config *req;
1140 spin_lock_bh(&adapter->mcc_lock);
1142 wrb = wrb_from_mccq(adapter);
1147 req = embedded_payload(wrb);
1149 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1150 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1152 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1153 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1155 req->interface_id = if_id;
1156 req->promiscuous = promiscuous;
1157 req->untagged = untagged;
1158 req->num_vlan = num;
1160 memcpy(req->normal_vlan, vtag_array,
1161 req->num_vlan * sizeof(vtag_array[0]));
1164 status = be_mcc_notify_wait(adapter);
1167 spin_unlock_bh(&adapter->mcc_lock);
1171 /* Uses MCC for this command as it may be called in BH context
1172 * Uses synchronous mcc
1174 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1176 struct be_mcc_wrb *wrb;
1177 struct be_cmd_req_promiscuous_config *req;
1180 spin_lock_bh(&adapter->mcc_lock);
1182 wrb = wrb_from_mccq(adapter);
1187 req = embedded_payload(wrb);
1189 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1191 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1192 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1194 /* In FW versions X.102.149/X.101.487 and later,
1195 * the port setting associated only with the
1196 * issuing pci function will take effect
1199 req->port1_promiscuous = en;
1201 req->port0_promiscuous = en;
1203 status = be_mcc_notify_wait(adapter);
1206 spin_unlock_bh(&adapter->mcc_lock);
1211 * Uses MCC for this command as it may be called in BH context
1212 * (mc == NULL) => multicast promiscous
1214 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1215 struct net_device *netdev, struct be_dma_mem *mem)
1217 struct be_mcc_wrb *wrb;
1218 struct be_cmd_req_mcast_mac_config *req = mem->va;
1222 spin_lock_bh(&adapter->mcc_lock);
1224 wrb = wrb_from_mccq(adapter);
1229 sge = nonembedded_sgl(wrb);
1230 memset(req, 0, sizeof(*req));
1232 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1233 OPCODE_COMMON_NTWK_MULTICAST_SET);
1234 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1235 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1236 sge->len = cpu_to_le32(mem->size);
1238 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1239 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1241 req->interface_id = if_id;
1244 struct netdev_hw_addr *ha;
1246 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1249 netdev_for_each_mc_addr(ha, netdev)
1250 memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1252 req->promiscuous = 1;
1255 status = be_mcc_notify_wait(adapter);
1258 spin_unlock_bh(&adapter->mcc_lock);
1262 /* Uses synchrounous mcc */
1263 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1265 struct be_mcc_wrb *wrb;
1266 struct be_cmd_req_set_flow_control *req;
1269 spin_lock_bh(&adapter->mcc_lock);
1271 wrb = wrb_from_mccq(adapter);
1276 req = embedded_payload(wrb);
1278 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1279 OPCODE_COMMON_SET_FLOW_CONTROL);
1281 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1282 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1284 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1285 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1287 status = be_mcc_notify_wait(adapter);
1290 spin_unlock_bh(&adapter->mcc_lock);
1295 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1297 struct be_mcc_wrb *wrb;
1298 struct be_cmd_req_get_flow_control *req;
1301 spin_lock_bh(&adapter->mcc_lock);
1303 wrb = wrb_from_mccq(adapter);
1308 req = embedded_payload(wrb);
1310 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1311 OPCODE_COMMON_GET_FLOW_CONTROL);
1313 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1314 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1316 status = be_mcc_notify_wait(adapter);
1318 struct be_cmd_resp_get_flow_control *resp =
1319 embedded_payload(wrb);
1320 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1321 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1325 spin_unlock_bh(&adapter->mcc_lock);
1330 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1331 u32 *mode, u32 *caps)
1333 struct be_mcc_wrb *wrb;
1334 struct be_cmd_req_query_fw_cfg *req;
1337 if (mutex_lock_interruptible(&adapter->mbox_lock))
1340 wrb = wrb_from_mbox(adapter);
1341 req = embedded_payload(wrb);
1343 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1344 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1346 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1347 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1349 status = be_mbox_notify_wait(adapter);
1351 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1352 *port_num = le32_to_cpu(resp->phys_port);
1353 *mode = le32_to_cpu(resp->function_mode);
1354 *caps = le32_to_cpu(resp->function_caps);
1357 mutex_unlock(&adapter->mbox_lock);
1362 int be_cmd_reset_function(struct be_adapter *adapter)
1364 struct be_mcc_wrb *wrb;
1365 struct be_cmd_req_hdr *req;
1368 if (mutex_lock_interruptible(&adapter->mbox_lock))
1371 wrb = wrb_from_mbox(adapter);
1372 req = embedded_payload(wrb);
1374 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1375 OPCODE_COMMON_FUNCTION_RESET);
1377 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1378 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1380 status = be_mbox_notify_wait(adapter);
1382 mutex_unlock(&adapter->mbox_lock);
1386 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1388 struct be_mcc_wrb *wrb;
1389 struct be_cmd_req_rss_config *req;
1393 if (mutex_lock_interruptible(&adapter->mbox_lock))
1396 wrb = wrb_from_mbox(adapter);
1397 req = embedded_payload(wrb);
1399 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1400 OPCODE_ETH_RSS_CONFIG);
1402 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1403 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1405 req->if_id = cpu_to_le32(adapter->if_handle);
1406 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1407 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1408 memcpy(req->cpu_table, rsstable, table_size);
1409 memcpy(req->hash, myhash, sizeof(myhash));
1410 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1412 status = be_mbox_notify_wait(adapter);
1414 mutex_unlock(&adapter->mbox_lock);
1419 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1420 u8 bcn, u8 sts, u8 state)
1422 struct be_mcc_wrb *wrb;
1423 struct be_cmd_req_enable_disable_beacon *req;
1426 spin_lock_bh(&adapter->mcc_lock);
1428 wrb = wrb_from_mccq(adapter);
1433 req = embedded_payload(wrb);
1435 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1436 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1438 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1439 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1441 req->port_num = port_num;
1442 req->beacon_state = state;
1443 req->beacon_duration = bcn;
1444 req->status_duration = sts;
1446 status = be_mcc_notify_wait(adapter);
1449 spin_unlock_bh(&adapter->mcc_lock);
1454 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1456 struct be_mcc_wrb *wrb;
1457 struct be_cmd_req_get_beacon_state *req;
1460 spin_lock_bh(&adapter->mcc_lock);
1462 wrb = wrb_from_mccq(adapter);
1467 req = embedded_payload(wrb);
1469 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1470 OPCODE_COMMON_GET_BEACON_STATE);
1472 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1473 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1475 req->port_num = port_num;
1477 status = be_mcc_notify_wait(adapter);
1479 struct be_cmd_resp_get_beacon_state *resp =
1480 embedded_payload(wrb);
1481 *state = resp->beacon_state;
1485 spin_unlock_bh(&adapter->mcc_lock);
1489 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1490 u32 flash_type, u32 flash_opcode, u32 buf_size)
1492 struct be_mcc_wrb *wrb;
1493 struct be_cmd_write_flashrom *req;
1497 spin_lock_bh(&adapter->mcc_lock);
1498 adapter->flash_status = 0;
1500 wrb = wrb_from_mccq(adapter);
1506 sge = nonembedded_sgl(wrb);
1508 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1509 OPCODE_COMMON_WRITE_FLASHROM);
1510 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1512 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1513 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1514 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1515 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1516 sge->len = cpu_to_le32(cmd->size);
1518 req->params.op_type = cpu_to_le32(flash_type);
1519 req->params.op_code = cpu_to_le32(flash_opcode);
1520 req->params.data_buf_size = cpu_to_le32(buf_size);
1522 be_mcc_notify(adapter);
1523 spin_unlock_bh(&adapter->mcc_lock);
1525 if (!wait_for_completion_timeout(&adapter->flash_compl,
1526 msecs_to_jiffies(12000)))
1529 status = adapter->flash_status;
1534 spin_unlock_bh(&adapter->mcc_lock);
1538 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1541 struct be_mcc_wrb *wrb;
1542 struct be_cmd_write_flashrom *req;
1545 spin_lock_bh(&adapter->mcc_lock);
1547 wrb = wrb_from_mccq(adapter);
1552 req = embedded_payload(wrb);
1554 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1555 OPCODE_COMMON_READ_FLASHROM);
1557 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1558 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1560 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1561 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1562 req->params.offset = cpu_to_le32(offset);
1563 req->params.data_buf_size = cpu_to_le32(0x4);
1565 status = be_mcc_notify_wait(adapter);
1567 memcpy(flashed_crc, req->params.data_buf, 4);
1570 spin_unlock_bh(&adapter->mcc_lock);
1574 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1575 struct be_dma_mem *nonemb_cmd)
1577 struct be_mcc_wrb *wrb;
1578 struct be_cmd_req_acpi_wol_magic_config *req;
1582 spin_lock_bh(&adapter->mcc_lock);
1584 wrb = wrb_from_mccq(adapter);
1589 req = nonemb_cmd->va;
1590 sge = nonembedded_sgl(wrb);
1592 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1593 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1595 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1596 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1597 memcpy(req->magic_mac, mac, ETH_ALEN);
1599 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1600 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1601 sge->len = cpu_to_le32(nonemb_cmd->size);
1603 status = be_mcc_notify_wait(adapter);
1606 spin_unlock_bh(&adapter->mcc_lock);
1610 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1611 u8 loopback_type, u8 enable)
1613 struct be_mcc_wrb *wrb;
1614 struct be_cmd_req_set_lmode *req;
1617 spin_lock_bh(&adapter->mcc_lock);
1619 wrb = wrb_from_mccq(adapter);
1625 req = embedded_payload(wrb);
1627 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1628 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1630 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1631 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1634 req->src_port = port_num;
1635 req->dest_port = port_num;
1636 req->loopback_type = loopback_type;
1637 req->loopback_state = enable;
1639 status = be_mcc_notify_wait(adapter);
1641 spin_unlock_bh(&adapter->mcc_lock);
1645 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1646 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1648 struct be_mcc_wrb *wrb;
1649 struct be_cmd_req_loopback_test *req;
1652 spin_lock_bh(&adapter->mcc_lock);
1654 wrb = wrb_from_mccq(adapter);
1660 req = embedded_payload(wrb);
1662 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1663 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1665 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1666 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1667 req->hdr.timeout = cpu_to_le32(4);
1669 req->pattern = cpu_to_le64(pattern);
1670 req->src_port = cpu_to_le32(port_num);
1671 req->dest_port = cpu_to_le32(port_num);
1672 req->pkt_size = cpu_to_le32(pkt_size);
1673 req->num_pkts = cpu_to_le32(num_pkts);
1674 req->loopback_type = cpu_to_le32(loopback_type);
1676 status = be_mcc_notify_wait(adapter);
1678 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1679 status = le32_to_cpu(resp->status);
1683 spin_unlock_bh(&adapter->mcc_lock);
1687 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1688 u32 byte_cnt, struct be_dma_mem *cmd)
1690 struct be_mcc_wrb *wrb;
1691 struct be_cmd_req_ddrdma_test *req;
1696 spin_lock_bh(&adapter->mcc_lock);
1698 wrb = wrb_from_mccq(adapter);
1704 sge = nonembedded_sgl(wrb);
1705 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1706 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1707 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1708 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1710 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1711 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1712 sge->len = cpu_to_le32(cmd->size);
1714 req->pattern = cpu_to_le64(pattern);
1715 req->byte_count = cpu_to_le32(byte_cnt);
1716 for (i = 0; i < byte_cnt; i++) {
1717 req->snd_buff[i] = (u8)(pattern >> (j*8));
1723 status = be_mcc_notify_wait(adapter);
1726 struct be_cmd_resp_ddrdma_test *resp;
1728 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1735 spin_unlock_bh(&adapter->mcc_lock);
1739 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1740 struct be_dma_mem *nonemb_cmd)
1742 struct be_mcc_wrb *wrb;
1743 struct be_cmd_req_seeprom_read *req;
1747 spin_lock_bh(&adapter->mcc_lock);
1749 wrb = wrb_from_mccq(adapter);
1750 req = nonemb_cmd->va;
1751 sge = nonembedded_sgl(wrb);
1753 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1754 OPCODE_COMMON_SEEPROM_READ);
1756 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1757 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1759 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1760 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1761 sge->len = cpu_to_le32(nonemb_cmd->size);
1763 status = be_mcc_notify_wait(adapter);
1765 spin_unlock_bh(&adapter->mcc_lock);
1769 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1771 struct be_mcc_wrb *wrb;
1772 struct be_cmd_req_get_phy_info *req;
1776 spin_lock_bh(&adapter->mcc_lock);
1778 wrb = wrb_from_mccq(adapter);
1785 sge = nonembedded_sgl(wrb);
1787 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1788 OPCODE_COMMON_GET_PHY_DETAILS);
1790 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1791 OPCODE_COMMON_GET_PHY_DETAILS,
1794 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1795 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1796 sge->len = cpu_to_le32(cmd->size);
1798 status = be_mcc_notify_wait(adapter);
1800 spin_unlock_bh(&adapter->mcc_lock);
1804 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1806 struct be_mcc_wrb *wrb;
1807 struct be_cmd_req_set_qos *req;
1810 spin_lock_bh(&adapter->mcc_lock);
1812 wrb = wrb_from_mccq(adapter);
1818 req = embedded_payload(wrb);
1820 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1821 OPCODE_COMMON_SET_QOS);
1823 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1824 OPCODE_COMMON_SET_QOS, sizeof(*req));
1826 req->hdr.domain = domain;
1827 req->valid_bits = BE_QOS_BITS_NIC;
1828 req->max_bps_nic = bps;
1830 status = be_mcc_notify_wait(adapter);
1833 spin_unlock_bh(&adapter->mcc_lock);