2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
52 /* Completion Status */
54 MCC_STATUS_SUCCESS = 0x0,
55 /* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57 /* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59 /* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61 /* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63 /* The command is completing with a DMA error */
64 MCC_STATUS_DMA_FAILED = 0x5,
65 MCC_STATUS_NOT_SUPPORTED = 66
68 #define CQE_STATUS_COMPL_MASK 0xFFFF
69 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70 #define CQE_STATUS_EXTD_MASK 0xFFFF
71 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
80 /* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
86 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
87 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
88 #define ASYNC_EVENT_CODE_GRP_5 0x5
89 #define ASYNC_EVENT_QOS_SPEED 0x1
90 #define ASYNC_EVENT_COS_PRIORITY 0x2
91 #define ASYNC_EVENT_PVID_STATE 0x3
92 struct be_async_event_trailer {
97 ASYNC_EVENT_LINK_DOWN = 0x0,
98 ASYNC_EVENT_LINK_UP = 0x1
101 /* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
104 struct be_async_event_link_state {
111 struct be_async_event_trailer trailer;
114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
117 struct be_async_event_grp5_qos_link_speed {
122 struct be_async_event_trailer trailer;
125 /* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
128 struct be_async_event_grp5_cos_priority {
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
135 struct be_async_event_trailer trailer;
138 /* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
141 struct be_async_event_grp5_pvid_state {
147 struct be_async_event_trailer trailer;
150 struct be_mcc_mailbox {
151 struct be_mcc_wrb wrb;
152 struct be_mcc_compl compl;
155 #define CMD_SUBSYSTEM_COMMON 0x1
156 #define CMD_SUBSYSTEM_ETH 0x3
157 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
159 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
160 #define OPCODE_COMMON_NTWK_MAC_SET 2
161 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
162 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
163 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
164 #define OPCODE_COMMON_READ_FLASHROM 6
165 #define OPCODE_COMMON_WRITE_FLASHROM 7
166 #define OPCODE_COMMON_CQ_CREATE 12
167 #define OPCODE_COMMON_EQ_CREATE 13
168 #define OPCODE_COMMON_MCC_CREATE 21
169 #define OPCODE_COMMON_SET_QOS 28
170 #define OPCODE_COMMON_MCC_CREATE_EXT 90
171 #define OPCODE_COMMON_SEEPROM_READ 30
172 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
173 #define OPCODE_COMMON_NTWK_RX_FILTER 34
174 #define OPCODE_COMMON_GET_FW_VERSION 35
175 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
176 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
177 #define OPCODE_COMMON_SET_FRAME_SIZE 39
178 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
179 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
180 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
181 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
182 #define OPCODE_COMMON_MCC_DESTROY 53
183 #define OPCODE_COMMON_CQ_DESTROY 54
184 #define OPCODE_COMMON_EQ_DESTROY 55
185 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
186 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
187 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
188 #define OPCODE_COMMON_FUNCTION_RESET 61
189 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
190 #define OPCODE_COMMON_GET_BEACON_STATE 70
191 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
192 #define OPCODE_COMMON_GET_PHY_DETAILS 102
193 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
195 #define OPCODE_ETH_RSS_CONFIG 1
196 #define OPCODE_ETH_ACPI_CONFIG 2
197 #define OPCODE_ETH_PROMISCUOUS 3
198 #define OPCODE_ETH_GET_STATISTICS 4
199 #define OPCODE_ETH_TX_CREATE 7
200 #define OPCODE_ETH_RX_CREATE 8
201 #define OPCODE_ETH_TX_DESTROY 9
202 #define OPCODE_ETH_RX_DESTROY 10
203 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
205 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
206 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
207 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
209 struct be_cmd_req_hdr {
210 u8 opcode; /* dword 0 */
211 u8 subsystem; /* dword 0 */
212 u8 port_number; /* dword 0 */
213 u8 domain; /* dword 0 */
214 u32 timeout; /* dword 1 */
215 u32 request_length; /* dword 2 */
216 u8 version; /* dword 3 */
217 u8 rsvd[3]; /* dword 3 */
220 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
221 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
222 struct be_cmd_resp_hdr {
223 u32 info; /* dword 0 */
224 u32 status; /* dword 1 */
225 u32 response_length; /* dword 2 */
226 u32 actual_resp_len; /* dword 3 */
234 /**************************
235 * BE Command definitions *
236 **************************/
238 /* Pseudo amap definition in which each bit of the actual structure is defined
239 * as a byte: used to calculate offset/shift/mask of each field */
240 struct amap_eq_context {
241 u8 cidx[13]; /* dword 0*/
242 u8 rsvd0[3]; /* dword 0*/
243 u8 epidx[13]; /* dword 0*/
244 u8 valid; /* dword 0*/
245 u8 rsvd1; /* dword 0*/
246 u8 size; /* dword 0*/
247 u8 pidx[13]; /* dword 1*/
248 u8 rsvd2[3]; /* dword 1*/
249 u8 pd[10]; /* dword 1*/
250 u8 count[3]; /* dword 1*/
251 u8 solevent; /* dword 1*/
252 u8 stalled; /* dword 1*/
253 u8 armed; /* dword 1*/
254 u8 rsvd3[4]; /* dword 2*/
255 u8 func[8]; /* dword 2*/
256 u8 rsvd4; /* dword 2*/
257 u8 delaymult[10]; /* dword 2*/
258 u8 rsvd5[2]; /* dword 2*/
259 u8 phase[2]; /* dword 2*/
260 u8 nodelay; /* dword 2*/
261 u8 rsvd6[4]; /* dword 2*/
262 u8 rsvd7[32]; /* dword 3*/
265 struct be_cmd_req_eq_create {
266 struct be_cmd_req_hdr hdr;
267 u16 num_pages; /* sword */
268 u16 rsvd0; /* sword */
269 u8 context[sizeof(struct amap_eq_context) / 8];
270 struct phys_addr pages[8];
273 struct be_cmd_resp_eq_create {
274 struct be_cmd_resp_hdr resp_hdr;
275 u16 eq_id; /* sword */
276 u16 rsvd0; /* sword */
279 /******************** Mac query ***************************/
281 MAC_ADDRESS_TYPE_STORAGE = 0x0,
282 MAC_ADDRESS_TYPE_NETWORK = 0x1,
283 MAC_ADDRESS_TYPE_PD = 0x2,
284 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
292 struct be_cmd_req_mac_query {
293 struct be_cmd_req_hdr hdr;
299 struct be_cmd_resp_mac_query {
300 struct be_cmd_resp_hdr hdr;
304 /******************** PMac Add ***************************/
305 struct be_cmd_req_pmac_add {
306 struct be_cmd_req_hdr hdr;
308 u8 mac_address[ETH_ALEN];
312 struct be_cmd_resp_pmac_add {
313 struct be_cmd_resp_hdr hdr;
317 /******************** PMac Del ***************************/
318 struct be_cmd_req_pmac_del {
319 struct be_cmd_req_hdr hdr;
324 /******************** Create CQ ***************************/
325 /* Pseudo amap definition in which each bit of the actual structure is defined
326 * as a byte: used to calculate offset/shift/mask of each field */
327 struct amap_cq_context_be {
328 u8 cidx[11]; /* dword 0*/
329 u8 rsvd0; /* dword 0*/
330 u8 coalescwm[2]; /* dword 0*/
331 u8 nodelay; /* dword 0*/
332 u8 epidx[11]; /* dword 0*/
333 u8 rsvd1; /* dword 0*/
334 u8 count[2]; /* dword 0*/
335 u8 valid; /* dword 0*/
336 u8 solevent; /* dword 0*/
337 u8 eventable; /* dword 0*/
338 u8 pidx[11]; /* dword 1*/
339 u8 rsvd2; /* dword 1*/
340 u8 pd[10]; /* dword 1*/
341 u8 eqid[8]; /* dword 1*/
342 u8 stalled; /* dword 1*/
343 u8 armed; /* dword 1*/
344 u8 rsvd3[4]; /* dword 2*/
345 u8 func[8]; /* dword 2*/
346 u8 rsvd4[20]; /* dword 2*/
347 u8 rsvd5[32]; /* dword 3*/
350 struct amap_cq_context_lancer {
351 u8 rsvd0[12]; /* dword 0*/
352 u8 coalescwm[2]; /* dword 0*/
353 u8 nodelay; /* dword 0*/
354 u8 rsvd1[12]; /* dword 0*/
355 u8 count[2]; /* dword 0*/
356 u8 valid; /* dword 0*/
357 u8 rsvd2; /* dword 0*/
358 u8 eventable; /* dword 0*/
359 u8 eqid[16]; /* dword 1*/
360 u8 rsvd3[15]; /* dword 1*/
361 u8 armed; /* dword 1*/
362 u8 rsvd4[32]; /* dword 2*/
363 u8 rsvd5[32]; /* dword 3*/
366 struct be_cmd_req_cq_create {
367 struct be_cmd_req_hdr hdr;
371 u8 context[sizeof(struct amap_cq_context_be) / 8];
372 struct phys_addr pages[8];
376 struct be_cmd_resp_cq_create {
377 struct be_cmd_resp_hdr hdr;
382 /******************** Create MCCQ ***************************/
383 /* Pseudo amap definition in which each bit of the actual structure is defined
384 * as a byte: used to calculate offset/shift/mask of each field */
385 struct amap_mcc_context_be {
400 struct amap_mcc_context_lancer {
406 u8 async_cq_valid[1];
411 struct be_cmd_req_mcc_create {
412 struct be_cmd_req_hdr hdr;
415 u32 async_event_bitmap[1];
416 u8 context[sizeof(struct amap_mcc_context_be) / 8];
417 struct phys_addr pages[8];
420 struct be_cmd_resp_mcc_create {
421 struct be_cmd_resp_hdr hdr;
426 /******************** Create TxQ ***************************/
427 #define BE_ETH_TX_RING_TYPE_STANDARD 2
428 #define BE_ULP1_NUM 1
430 /* Pseudo amap definition in which each bit of the actual structure is defined
431 * as a byte: used to calculate offset/shift/mask of each field */
432 struct amap_tx_context {
433 u8 if_id[16]; /* dword 0 */
434 u8 tx_ring_size[4]; /* dword 0 */
435 u8 rsvd1[26]; /* dword 0 */
436 u8 pci_func_id[8]; /* dword 1 */
437 u8 rsvd2[9]; /* dword 1 */
438 u8 ctx_valid; /* dword 1 */
439 u8 cq_id_send[16]; /* dword 2 */
440 u8 rsvd3[16]; /* dword 2 */
441 u8 rsvd4[32]; /* dword 3 */
442 u8 rsvd5[32]; /* dword 4 */
443 u8 rsvd6[32]; /* dword 5 */
444 u8 rsvd7[32]; /* dword 6 */
445 u8 rsvd8[32]; /* dword 7 */
446 u8 rsvd9[32]; /* dword 8 */
447 u8 rsvd10[32]; /* dword 9 */
448 u8 rsvd11[32]; /* dword 10 */
449 u8 rsvd12[32]; /* dword 11 */
450 u8 rsvd13[32]; /* dword 12 */
451 u8 rsvd14[32]; /* dword 13 */
452 u8 rsvd15[32]; /* dword 14 */
453 u8 rsvd16[32]; /* dword 15 */
456 struct be_cmd_req_eth_tx_create {
457 struct be_cmd_req_hdr hdr;
462 u8 context[sizeof(struct amap_tx_context) / 8];
463 struct phys_addr pages[8];
466 struct be_cmd_resp_eth_tx_create {
467 struct be_cmd_resp_hdr hdr;
472 /******************** Create RxQ ***************************/
473 struct be_cmd_req_eth_rx_create {
474 struct be_cmd_req_hdr hdr;
478 struct phys_addr pages[2];
485 struct be_cmd_resp_eth_rx_create {
486 struct be_cmd_resp_hdr hdr;
492 /******************** Q Destroy ***************************/
493 /* Type of Queue to be destroyed */
502 struct be_cmd_req_q_destroy {
503 struct be_cmd_req_hdr hdr;
505 u16 bypass_flush; /* valid only for rx q destroy */
508 /************ I/f Create (it's actually I/f Config Create)**********/
510 /* Capability flags for the i/f */
512 BE_IF_FLAGS_RSS = 0x4,
513 BE_IF_FLAGS_PROMISCUOUS = 0x8,
514 BE_IF_FLAGS_BROADCAST = 0x10,
515 BE_IF_FLAGS_UNTAGGED = 0x20,
516 BE_IF_FLAGS_ULP = 0x40,
517 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
518 BE_IF_FLAGS_VLAN = 0x100,
519 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
520 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
521 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
522 BE_IF_FLAGS_MULTICAST = 0x1000
525 /* An RX interface is an object with one or more MAC addresses and
526 * filtering capabilities. */
527 struct be_cmd_req_if_create {
528 struct be_cmd_req_hdr hdr;
529 u32 version; /* ignore currently */
530 u32 capability_flags;
532 u8 mac_addr[ETH_ALEN];
534 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
535 u32 vlan_tag; /* not used currently */
538 struct be_cmd_resp_if_create {
539 struct be_cmd_resp_hdr hdr;
544 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
545 struct be_cmd_req_if_destroy {
546 struct be_cmd_req_hdr hdr;
550 /*************** HW Stats Get **********************************/
551 struct be_port_rxf_stats {
552 u32 rx_bytes_lsd; /* dword 0*/
553 u32 rx_bytes_msd; /* dword 1*/
554 u32 rx_total_frames; /* dword 2*/
555 u32 rx_unicast_frames; /* dword 3*/
556 u32 rx_multicast_frames; /* dword 4*/
557 u32 rx_broadcast_frames; /* dword 5*/
558 u32 rx_crc_errors; /* dword 6*/
559 u32 rx_alignment_symbol_errors; /* dword 7*/
560 u32 rx_pause_frames; /* dword 8*/
561 u32 rx_control_frames; /* dword 9*/
562 u32 rx_in_range_errors; /* dword 10*/
563 u32 rx_out_range_errors; /* dword 11*/
564 u32 rx_frame_too_long; /* dword 12*/
565 u32 rx_address_match_errors; /* dword 13*/
566 u32 rx_vlan_mismatch; /* dword 14*/
567 u32 rx_dropped_too_small; /* dword 15*/
568 u32 rx_dropped_too_short; /* dword 16*/
569 u32 rx_dropped_header_too_small; /* dword 17*/
570 u32 rx_dropped_tcp_length; /* dword 18*/
571 u32 rx_dropped_runt; /* dword 19*/
572 u32 rx_64_byte_packets; /* dword 20*/
573 u32 rx_65_127_byte_packets; /* dword 21*/
574 u32 rx_128_256_byte_packets; /* dword 22*/
575 u32 rx_256_511_byte_packets; /* dword 23*/
576 u32 rx_512_1023_byte_packets; /* dword 24*/
577 u32 rx_1024_1518_byte_packets; /* dword 25*/
578 u32 rx_1519_2047_byte_packets; /* dword 26*/
579 u32 rx_2048_4095_byte_packets; /* dword 27*/
580 u32 rx_4096_8191_byte_packets; /* dword 28*/
581 u32 rx_8192_9216_byte_packets; /* dword 29*/
582 u32 rx_ip_checksum_errs; /* dword 30*/
583 u32 rx_tcp_checksum_errs; /* dword 31*/
584 u32 rx_udp_checksum_errs; /* dword 32*/
585 u32 rx_non_rss_packets; /* dword 33*/
586 u32 rx_ipv4_packets; /* dword 34*/
587 u32 rx_ipv6_packets; /* dword 35*/
588 u32 rx_ipv4_bytes_lsd; /* dword 36*/
589 u32 rx_ipv4_bytes_msd; /* dword 37*/
590 u32 rx_ipv6_bytes_lsd; /* dword 38*/
591 u32 rx_ipv6_bytes_msd; /* dword 39*/
592 u32 rx_chute1_packets; /* dword 40*/
593 u32 rx_chute2_packets; /* dword 41*/
594 u32 rx_chute3_packets; /* dword 42*/
595 u32 rx_management_packets; /* dword 43*/
596 u32 rx_switched_unicast_packets; /* dword 44*/
597 u32 rx_switched_multicast_packets; /* dword 45*/
598 u32 rx_switched_broadcast_packets; /* dword 46*/
599 u32 tx_bytes_lsd; /* dword 47*/
600 u32 tx_bytes_msd; /* dword 48*/
601 u32 tx_unicastframes; /* dword 49*/
602 u32 tx_multicastframes; /* dword 50*/
603 u32 tx_broadcastframes; /* dword 51*/
604 u32 tx_pauseframes; /* dword 52*/
605 u32 tx_controlframes; /* dword 53*/
606 u32 tx_64_byte_packets; /* dword 54*/
607 u32 tx_65_127_byte_packets; /* dword 55*/
608 u32 tx_128_256_byte_packets; /* dword 56*/
609 u32 tx_256_511_byte_packets; /* dword 57*/
610 u32 tx_512_1023_byte_packets; /* dword 58*/
611 u32 tx_1024_1518_byte_packets; /* dword 59*/
612 u32 tx_1519_2047_byte_packets; /* dword 60*/
613 u32 tx_2048_4095_byte_packets; /* dword 61*/
614 u32 tx_4096_8191_byte_packets; /* dword 62*/
615 u32 tx_8192_9216_byte_packets; /* dword 63*/
616 u32 rx_fifo_overflow; /* dword 64*/
617 u32 rx_input_fifo_overflow; /* dword 65*/
620 struct be_rxf_stats {
621 struct be_port_rxf_stats port[2];
622 u32 rx_drops_no_pbuf; /* dword 132*/
623 u32 rx_drops_no_txpb; /* dword 133*/
624 u32 rx_drops_no_erx_descr; /* dword 134*/
625 u32 rx_drops_no_tpre_descr; /* dword 135*/
626 u32 management_rx_port_packets; /* dword 136*/
627 u32 management_rx_port_bytes; /* dword 137*/
628 u32 management_rx_port_pause_frames; /* dword 138*/
629 u32 management_rx_port_errors; /* dword 139*/
630 u32 management_tx_port_packets; /* dword 140*/
631 u32 management_tx_port_bytes; /* dword 141*/
632 u32 management_tx_port_pause; /* dword 142*/
633 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
634 u32 rx_drops_too_many_frags; /* dword 144*/
635 u32 rx_drops_invalid_ring; /* dword 145*/
636 u32 forwarded_packets; /* dword 146*/
637 u32 rx_drops_mtu; /* dword 147*/
639 u32 port0_jabber_events;
640 u32 port1_jabber_events;
644 struct be_erx_stats {
645 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
646 u32 debug_wdma_sent_hold; /* dword 44*/
647 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
648 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
649 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
652 struct be_pmem_stats {
658 struct be_rxf_stats rxf;
660 struct be_erx_stats erx;
661 struct be_pmem_stats pmem;
664 struct be_cmd_req_get_stats {
665 struct be_cmd_req_hdr hdr;
666 u8 rsvd[sizeof(struct be_hw_stats)];
669 struct be_cmd_resp_get_stats {
670 struct be_cmd_resp_hdr hdr;
671 struct be_hw_stats hw_stats;
674 struct be_cmd_req_get_cntl_addnl_attribs {
675 struct be_cmd_req_hdr hdr;
679 struct be_cmd_resp_get_cntl_addnl_attribs {
680 struct be_cmd_resp_hdr hdr;
684 u8 on_die_temperature; /* in degrees centigrade*/
688 struct be_cmd_req_vlan_config {
689 struct be_cmd_req_hdr hdr;
697 struct be_cmd_req_promiscuous_config {
698 struct be_cmd_req_hdr hdr;
699 u8 port0_promiscuous;
700 u8 port1_promiscuous;
704 /******************** Multicast MAC Config *******************/
705 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
710 struct be_cmd_req_mcast_mac_config {
711 struct be_cmd_req_hdr hdr;
715 struct macaddr mac[BE_MAX_MC];
718 static inline struct be_hw_stats *
719 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
721 return &cmd->hw_stats;
724 /******************** Link Status Query *******************/
725 struct be_cmd_req_link_status {
726 struct be_cmd_req_hdr hdr;
731 PHY_LINK_DUPLEX_NONE = 0x0,
732 PHY_LINK_DUPLEX_HALF = 0x1,
733 PHY_LINK_DUPLEX_FULL = 0x2
737 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
738 PHY_LINK_SPEED_10MBPS = 0x1,
739 PHY_LINK_SPEED_100MBPS = 0x2,
740 PHY_LINK_SPEED_1GBPS = 0x3,
741 PHY_LINK_SPEED_10GBPS = 0x4
744 struct be_cmd_resp_link_status {
745 struct be_cmd_resp_hdr hdr;
756 /******************** Port Identification ***************************/
757 /* Identifies the type of port attached to NIC */
758 struct be_cmd_req_port_type {
759 struct be_cmd_req_hdr hdr;
769 struct be_cmd_resp_port_type {
770 struct be_cmd_resp_hdr hdr;
793 /******************** Get FW Version *******************/
794 struct be_cmd_req_get_fw_version {
795 struct be_cmd_req_hdr hdr;
796 u8 rsvd0[FW_VER_LEN];
797 u8 rsvd1[FW_VER_LEN];
800 struct be_cmd_resp_get_fw_version {
801 struct be_cmd_resp_hdr hdr;
802 u8 firmware_version_string[FW_VER_LEN];
803 u8 fw_on_flash_version_string[FW_VER_LEN];
806 /******************** Set Flow Contrl *******************/
807 struct be_cmd_req_set_flow_control {
808 struct be_cmd_req_hdr hdr;
813 /******************** Get Flow Contrl *******************/
814 struct be_cmd_req_get_flow_control {
815 struct be_cmd_req_hdr hdr;
819 struct be_cmd_resp_get_flow_control {
820 struct be_cmd_resp_hdr hdr;
825 /******************** Modify EQ Delay *******************/
826 struct be_cmd_req_modify_eq_delay {
827 struct be_cmd_req_hdr hdr;
832 u32 delay_multiplier;
836 struct be_cmd_resp_modify_eq_delay {
837 struct be_cmd_resp_hdr hdr;
841 /******************** Get FW Config *******************/
842 #define BE_FUNCTION_CAPS_RSS 0x2
843 struct be_cmd_req_query_fw_cfg {
844 struct be_cmd_req_hdr hdr;
848 struct be_cmd_resp_query_fw_cfg {
849 struct be_cmd_resp_hdr hdr;
850 u32 be_config_number;
858 /******************** RSS Config *******************/
860 #define RSS_ENABLE_NONE 0x0
861 #define RSS_ENABLE_IPV4 0x1
862 #define RSS_ENABLE_TCP_IPV4 0x2
863 #define RSS_ENABLE_IPV6 0x4
864 #define RSS_ENABLE_TCP_IPV6 0x8
866 struct be_cmd_req_rss_config {
867 struct be_cmd_req_hdr hdr;
870 u16 cpu_table_size_log2;
877 /******************** Port Beacon ***************************/
879 #define BEACON_STATE_ENABLED 0x1
880 #define BEACON_STATE_DISABLED 0x0
882 struct be_cmd_req_enable_disable_beacon {
883 struct be_cmd_req_hdr hdr;
890 struct be_cmd_resp_enable_disable_beacon {
891 struct be_cmd_resp_hdr resp_hdr;
895 struct be_cmd_req_get_beacon_state {
896 struct be_cmd_req_hdr hdr;
902 struct be_cmd_resp_get_beacon_state {
903 struct be_cmd_resp_hdr resp_hdr;
908 /****************** Firmware Flash ******************/
909 struct flashrom_params {
917 struct be_cmd_write_flashrom {
918 struct be_cmd_req_hdr hdr;
919 struct flashrom_params params;
922 /************************ WOL *******************************/
923 struct be_cmd_req_acpi_wol_magic_config{
924 struct be_cmd_req_hdr hdr;
930 /********************** LoopBack test *********************/
931 struct be_cmd_req_loopback_test {
932 struct be_cmd_req_hdr hdr;
941 struct be_cmd_resp_loopback_test {
942 struct be_cmd_resp_hdr resp_hdr;
950 struct be_cmd_req_set_lmode {
951 struct be_cmd_req_hdr hdr;
958 struct be_cmd_resp_set_lmode {
959 struct be_cmd_resp_hdr resp_hdr;
963 /********************** DDR DMA test *********************/
964 struct be_cmd_req_ddrdma_test {
965 struct be_cmd_req_hdr hdr;
973 struct be_cmd_resp_ddrdma_test {
974 struct be_cmd_resp_hdr hdr;
982 /*********************** SEEPROM Read ***********************/
984 #define BE_READ_SEEPROM_LEN 1024
985 struct be_cmd_req_seeprom_read {
986 struct be_cmd_req_hdr hdr;
987 u8 rsvd0[BE_READ_SEEPROM_LEN];
990 struct be_cmd_resp_seeprom_read {
991 struct be_cmd_req_hdr hdr;
992 u8 seeprom_data[BE_READ_SEEPROM_LEN];
996 PHY_TYPE_CX4_10GB = 0,
999 PHY_TYPE_SFP_PLUS_10GB,
1002 PHY_TYPE_BASET_10GB,
1004 PHY_TYPE_DISABLED = 255
1007 struct be_cmd_req_get_phy_info {
1008 struct be_cmd_req_hdr hdr;
1011 struct be_cmd_resp_get_phy_info {
1012 struct be_cmd_req_hdr hdr;
1019 /*********************** Set QOS ***********************/
1021 #define BE_QOS_BITS_NIC 1
1023 struct be_cmd_req_set_qos {
1024 struct be_cmd_req_hdr hdr;
1030 struct be_cmd_resp_set_qos {
1031 struct be_cmd_resp_hdr hdr;
1035 /*********************** Controller Attributes ***********************/
1036 struct be_cmd_req_cntl_attribs {
1037 struct be_cmd_req_hdr hdr;
1040 struct be_cmd_resp_cntl_attribs {
1041 struct be_cmd_resp_hdr hdr;
1042 struct mgmt_controller_attrib attribs;
1045 extern int be_pci_fnum_get(struct be_adapter *adapter);
1046 extern int be_cmd_POST(struct be_adapter *adapter);
1047 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1048 u8 type, bool permanent, u32 if_handle);
1049 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1050 u32 if_id, u32 *pmac_id, u32 domain);
1051 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1052 u32 pmac_id, u32 domain);
1053 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1054 u32 en_flags, u8 *mac, bool pmac_invalid,
1055 u32 *if_handle, u32 *pmac_id, u32 domain);
1056 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1058 extern int be_cmd_eq_create(struct be_adapter *adapter,
1059 struct be_queue_info *eq, int eq_delay);
1060 extern int be_cmd_cq_create(struct be_adapter *adapter,
1061 struct be_queue_info *cq, struct be_queue_info *eq,
1062 bool sol_evts, bool no_delay,
1063 int num_cqe_dma_coalesce);
1064 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1065 struct be_queue_info *mccq,
1066 struct be_queue_info *cq);
1067 extern int be_cmd_txq_create(struct be_adapter *adapter,
1068 struct be_queue_info *txq,
1069 struct be_queue_info *cq);
1070 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1071 struct be_queue_info *rxq, u16 cq_id,
1072 u16 frag_size, u16 max_frame_size, u32 if_id,
1073 u32 rss, u8 *rss_id);
1074 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1076 extern int be_cmd_link_status_query(struct be_adapter *adapter,
1077 bool *link_up, u8 *mac_speed, u16 *link_speed);
1078 extern int be_cmd_reset(struct be_adapter *adapter);
1079 extern int be_cmd_get_stats(struct be_adapter *adapter,
1080 struct be_dma_mem *nonemb_cmd);
1081 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1083 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1084 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1085 u16 *vtag_array, u32 num, bool untagged,
1087 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
1088 u8 port_num, bool en);
1089 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1090 struct net_device *netdev, struct be_dma_mem *mem);
1091 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1092 u32 tx_fc, u32 rx_fc);
1093 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1094 u32 *tx_fc, u32 *rx_fc);
1095 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1096 u32 *port_num, u32 *function_mode, u32 *function_caps);
1097 extern int be_cmd_reset_function(struct be_adapter *adapter);
1098 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1100 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1101 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1102 u8 port_num, u8 beacon, u8 status, u8 state);
1103 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1104 u8 port_num, u32 *state);
1105 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1106 struct be_dma_mem *cmd, u32 flash_oper,
1107 u32 flash_opcode, u32 buf_size);
1108 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1110 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1111 struct be_dma_mem *nonemb_cmd);
1112 extern int be_cmd_fw_init(struct be_adapter *adapter);
1113 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1114 extern void be_async_mcc_enable(struct be_adapter *adapter);
1115 extern void be_async_mcc_disable(struct be_adapter *adapter);
1116 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1117 u32 loopback_type, u32 pkt_size,
1118 u32 num_pkts, u64 pattern);
1119 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1120 u32 byte_cnt, struct be_dma_mem *cmd);
1121 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1122 struct be_dma_mem *nonemb_cmd);
1123 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1124 u8 loopback_type, u8 enable);
1125 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1126 struct be_dma_mem *cmd);
1127 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1128 extern void be_detect_dump_ue(struct be_adapter *adapter);
1129 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1130 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);