2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
52 /* Completion Status */
54 MCC_STATUS_SUCCESS = 0x0,
55 /* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57 /* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59 /* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61 /* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63 /* The command is completing with a DMA error */
64 MCC_STATUS_DMA_FAILED = 0x5,
65 MCC_STATUS_NOT_SUPPORTED = 66
68 #define CQE_STATUS_COMPL_MASK 0xFFFF
69 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70 #define CQE_STATUS_EXTD_MASK 0xFFFF
71 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
80 /* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
86 struct be_async_event_trailer {
91 ASYNC_EVENT_LINK_DOWN = 0x0,
92 ASYNC_EVENT_LINK_UP = 0x1
95 /* When the event code of an async trailer is link-state, the mcc_compl
96 * must be interpreted as follows
98 struct be_async_event_link_state {
105 struct be_async_event_trailer trailer;
108 struct be_mcc_mailbox {
109 struct be_mcc_wrb wrb;
110 struct be_mcc_compl compl;
113 #define CMD_SUBSYSTEM_COMMON 0x1
114 #define CMD_SUBSYSTEM_ETH 0x3
115 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
117 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
118 #define OPCODE_COMMON_NTWK_MAC_SET 2
119 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
120 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
121 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
122 #define OPCODE_COMMON_READ_FLASHROM 6
123 #define OPCODE_COMMON_WRITE_FLASHROM 7
124 #define OPCODE_COMMON_CQ_CREATE 12
125 #define OPCODE_COMMON_EQ_CREATE 13
126 #define OPCODE_COMMON_MCC_CREATE 21
127 #define OPCODE_COMMON_SEEPROM_READ 30
128 #define OPCODE_COMMON_NTWK_RX_FILTER 34
129 #define OPCODE_COMMON_GET_FW_VERSION 35
130 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
131 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
132 #define OPCODE_COMMON_SET_FRAME_SIZE 39
133 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
134 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
135 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
136 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
137 #define OPCODE_COMMON_MCC_DESTROY 53
138 #define OPCODE_COMMON_CQ_DESTROY 54
139 #define OPCODE_COMMON_EQ_DESTROY 55
140 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
141 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
142 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
143 #define OPCODE_COMMON_FUNCTION_RESET 61
144 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
145 #define OPCODE_COMMON_GET_BEACON_STATE 70
146 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
148 #define OPCODE_ETH_ACPI_CONFIG 2
149 #define OPCODE_ETH_PROMISCUOUS 3
150 #define OPCODE_ETH_GET_STATISTICS 4
151 #define OPCODE_ETH_TX_CREATE 7
152 #define OPCODE_ETH_RX_CREATE 8
153 #define OPCODE_ETH_TX_DESTROY 9
154 #define OPCODE_ETH_RX_DESTROY 10
155 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
157 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
158 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
159 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
161 struct be_cmd_req_hdr {
162 u8 opcode; /* dword 0 */
163 u8 subsystem; /* dword 0 */
164 u8 port_number; /* dword 0 */
165 u8 domain; /* dword 0 */
166 u32 timeout; /* dword 1 */
167 u32 request_length; /* dword 2 */
168 u32 rsvd; /* dword 3 */
171 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
172 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
173 struct be_cmd_resp_hdr {
174 u32 info; /* dword 0 */
175 u32 status; /* dword 1 */
176 u32 response_length; /* dword 2 */
177 u32 actual_resp_len; /* dword 3 */
185 /**************************
186 * BE Command definitions *
187 **************************/
189 /* Pseudo amap definition in which each bit of the actual structure is defined
190 * as a byte: used to calculate offset/shift/mask of each field */
191 struct amap_eq_context {
192 u8 cidx[13]; /* dword 0*/
193 u8 rsvd0[3]; /* dword 0*/
194 u8 epidx[13]; /* dword 0*/
195 u8 valid; /* dword 0*/
196 u8 rsvd1; /* dword 0*/
197 u8 size; /* dword 0*/
198 u8 pidx[13]; /* dword 1*/
199 u8 rsvd2[3]; /* dword 1*/
200 u8 pd[10]; /* dword 1*/
201 u8 count[3]; /* dword 1*/
202 u8 solevent; /* dword 1*/
203 u8 stalled; /* dword 1*/
204 u8 armed; /* dword 1*/
205 u8 rsvd3[4]; /* dword 2*/
206 u8 func[8]; /* dword 2*/
207 u8 rsvd4; /* dword 2*/
208 u8 delaymult[10]; /* dword 2*/
209 u8 rsvd5[2]; /* dword 2*/
210 u8 phase[2]; /* dword 2*/
211 u8 nodelay; /* dword 2*/
212 u8 rsvd6[4]; /* dword 2*/
213 u8 rsvd7[32]; /* dword 3*/
216 struct be_cmd_req_eq_create {
217 struct be_cmd_req_hdr hdr;
218 u16 num_pages; /* sword */
219 u16 rsvd0; /* sword */
220 u8 context[sizeof(struct amap_eq_context) / 8];
221 struct phys_addr pages[8];
224 struct be_cmd_resp_eq_create {
225 struct be_cmd_resp_hdr resp_hdr;
226 u16 eq_id; /* sword */
227 u16 rsvd0; /* sword */
230 /******************** Mac query ***************************/
232 MAC_ADDRESS_TYPE_STORAGE = 0x0,
233 MAC_ADDRESS_TYPE_NETWORK = 0x1,
234 MAC_ADDRESS_TYPE_PD = 0x2,
235 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
243 struct be_cmd_req_mac_query {
244 struct be_cmd_req_hdr hdr;
250 struct be_cmd_resp_mac_query {
251 struct be_cmd_resp_hdr hdr;
255 /******************** PMac Add ***************************/
256 struct be_cmd_req_pmac_add {
257 struct be_cmd_req_hdr hdr;
259 u8 mac_address[ETH_ALEN];
263 struct be_cmd_resp_pmac_add {
264 struct be_cmd_resp_hdr hdr;
268 /******************** PMac Del ***************************/
269 struct be_cmd_req_pmac_del {
270 struct be_cmd_req_hdr hdr;
275 /******************** Create CQ ***************************/
276 /* Pseudo amap definition in which each bit of the actual structure is defined
277 * as a byte: used to calculate offset/shift/mask of each field */
278 struct amap_cq_context {
279 u8 cidx[11]; /* dword 0*/
280 u8 rsvd0; /* dword 0*/
281 u8 coalescwm[2]; /* dword 0*/
282 u8 nodelay; /* dword 0*/
283 u8 epidx[11]; /* dword 0*/
284 u8 rsvd1; /* dword 0*/
285 u8 count[2]; /* dword 0*/
286 u8 valid; /* dword 0*/
287 u8 solevent; /* dword 0*/
288 u8 eventable; /* dword 0*/
289 u8 pidx[11]; /* dword 1*/
290 u8 rsvd2; /* dword 1*/
291 u8 pd[10]; /* dword 1*/
292 u8 eqid[8]; /* dword 1*/
293 u8 stalled; /* dword 1*/
294 u8 armed; /* dword 1*/
295 u8 rsvd3[4]; /* dword 2*/
296 u8 func[8]; /* dword 2*/
297 u8 rsvd4[20]; /* dword 2*/
298 u8 rsvd5[32]; /* dword 3*/
301 struct be_cmd_req_cq_create {
302 struct be_cmd_req_hdr hdr;
305 u8 context[sizeof(struct amap_cq_context) / 8];
306 struct phys_addr pages[8];
309 struct be_cmd_resp_cq_create {
310 struct be_cmd_resp_hdr hdr;
315 /******************** Create MCCQ ***************************/
316 /* Pseudo amap definition in which each bit of the actual structure is defined
317 * as a byte: used to calculate offset/shift/mask of each field */
318 struct amap_mcc_context {
333 struct be_cmd_req_mcc_create {
334 struct be_cmd_req_hdr hdr;
337 u8 context[sizeof(struct amap_mcc_context) / 8];
338 struct phys_addr pages[8];
341 struct be_cmd_resp_mcc_create {
342 struct be_cmd_resp_hdr hdr;
347 /******************** Create TxQ ***************************/
348 #define BE_ETH_TX_RING_TYPE_STANDARD 2
349 #define BE_ULP1_NUM 1
351 /* Pseudo amap definition in which each bit of the actual structure is defined
352 * as a byte: used to calculate offset/shift/mask of each field */
353 struct amap_tx_context {
354 u8 rsvd0[16]; /* dword 0 */
355 u8 tx_ring_size[4]; /* dword 0 */
356 u8 rsvd1[26]; /* dword 0 */
357 u8 pci_func_id[8]; /* dword 1 */
358 u8 rsvd2[9]; /* dword 1 */
359 u8 ctx_valid; /* dword 1 */
360 u8 cq_id_send[16]; /* dword 2 */
361 u8 rsvd3[16]; /* dword 2 */
362 u8 rsvd4[32]; /* dword 3 */
363 u8 rsvd5[32]; /* dword 4 */
364 u8 rsvd6[32]; /* dword 5 */
365 u8 rsvd7[32]; /* dword 6 */
366 u8 rsvd8[32]; /* dword 7 */
367 u8 rsvd9[32]; /* dword 8 */
368 u8 rsvd10[32]; /* dword 9 */
369 u8 rsvd11[32]; /* dword 10 */
370 u8 rsvd12[32]; /* dword 11 */
371 u8 rsvd13[32]; /* dword 12 */
372 u8 rsvd14[32]; /* dword 13 */
373 u8 rsvd15[32]; /* dword 14 */
374 u8 rsvd16[32]; /* dword 15 */
377 struct be_cmd_req_eth_tx_create {
378 struct be_cmd_req_hdr hdr;
383 u8 context[sizeof(struct amap_tx_context) / 8];
384 struct phys_addr pages[8];
387 struct be_cmd_resp_eth_tx_create {
388 struct be_cmd_resp_hdr hdr;
393 /******************** Create RxQ ***************************/
394 struct be_cmd_req_eth_rx_create {
395 struct be_cmd_req_hdr hdr;
399 struct phys_addr pages[2];
406 struct be_cmd_resp_eth_rx_create {
407 struct be_cmd_resp_hdr hdr;
413 /******************** Q Destroy ***************************/
414 /* Type of Queue to be destroyed */
423 struct be_cmd_req_q_destroy {
424 struct be_cmd_req_hdr hdr;
426 u16 bypass_flush; /* valid only for rx q destroy */
429 /************ I/f Create (it's actually I/f Config Create)**********/
431 /* Capability flags for the i/f */
433 BE_IF_FLAGS_RSS = 0x4,
434 BE_IF_FLAGS_PROMISCUOUS = 0x8,
435 BE_IF_FLAGS_BROADCAST = 0x10,
436 BE_IF_FLAGS_UNTAGGED = 0x20,
437 BE_IF_FLAGS_ULP = 0x40,
438 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
439 BE_IF_FLAGS_VLAN = 0x100,
440 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
441 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
442 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
445 /* An RX interface is an object with one or more MAC addresses and
446 * filtering capabilities. */
447 struct be_cmd_req_if_create {
448 struct be_cmd_req_hdr hdr;
449 u32 version; /* ignore currently */
450 u32 capability_flags;
452 u8 mac_addr[ETH_ALEN];
454 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
455 u32 vlan_tag; /* not used currently */
458 struct be_cmd_resp_if_create {
459 struct be_cmd_resp_hdr hdr;
464 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
465 struct be_cmd_req_if_destroy {
466 struct be_cmd_req_hdr hdr;
470 /*************** HW Stats Get **********************************/
471 struct be_port_rxf_stats {
472 u32 rx_bytes_lsd; /* dword 0*/
473 u32 rx_bytes_msd; /* dword 1*/
474 u32 rx_total_frames; /* dword 2*/
475 u32 rx_unicast_frames; /* dword 3*/
476 u32 rx_multicast_frames; /* dword 4*/
477 u32 rx_broadcast_frames; /* dword 5*/
478 u32 rx_crc_errors; /* dword 6*/
479 u32 rx_alignment_symbol_errors; /* dword 7*/
480 u32 rx_pause_frames; /* dword 8*/
481 u32 rx_control_frames; /* dword 9*/
482 u32 rx_in_range_errors; /* dword 10*/
483 u32 rx_out_range_errors; /* dword 11*/
484 u32 rx_frame_too_long; /* dword 12*/
485 u32 rx_address_match_errors; /* dword 13*/
486 u32 rx_vlan_mismatch; /* dword 14*/
487 u32 rx_dropped_too_small; /* dword 15*/
488 u32 rx_dropped_too_short; /* dword 16*/
489 u32 rx_dropped_header_too_small; /* dword 17*/
490 u32 rx_dropped_tcp_length; /* dword 18*/
491 u32 rx_dropped_runt; /* dword 19*/
492 u32 rx_64_byte_packets; /* dword 20*/
493 u32 rx_65_127_byte_packets; /* dword 21*/
494 u32 rx_128_256_byte_packets; /* dword 22*/
495 u32 rx_256_511_byte_packets; /* dword 23*/
496 u32 rx_512_1023_byte_packets; /* dword 24*/
497 u32 rx_1024_1518_byte_packets; /* dword 25*/
498 u32 rx_1519_2047_byte_packets; /* dword 26*/
499 u32 rx_2048_4095_byte_packets; /* dword 27*/
500 u32 rx_4096_8191_byte_packets; /* dword 28*/
501 u32 rx_8192_9216_byte_packets; /* dword 29*/
502 u32 rx_ip_checksum_errs; /* dword 30*/
503 u32 rx_tcp_checksum_errs; /* dword 31*/
504 u32 rx_udp_checksum_errs; /* dword 32*/
505 u32 rx_non_rss_packets; /* dword 33*/
506 u32 rx_ipv4_packets; /* dword 34*/
507 u32 rx_ipv6_packets; /* dword 35*/
508 u32 rx_ipv4_bytes_lsd; /* dword 36*/
509 u32 rx_ipv4_bytes_msd; /* dword 37*/
510 u32 rx_ipv6_bytes_lsd; /* dword 38*/
511 u32 rx_ipv6_bytes_msd; /* dword 39*/
512 u32 rx_chute1_packets; /* dword 40*/
513 u32 rx_chute2_packets; /* dword 41*/
514 u32 rx_chute3_packets; /* dword 42*/
515 u32 rx_management_packets; /* dword 43*/
516 u32 rx_switched_unicast_packets; /* dword 44*/
517 u32 rx_switched_multicast_packets; /* dword 45*/
518 u32 rx_switched_broadcast_packets; /* dword 46*/
519 u32 tx_bytes_lsd; /* dword 47*/
520 u32 tx_bytes_msd; /* dword 48*/
521 u32 tx_unicastframes; /* dword 49*/
522 u32 tx_multicastframes; /* dword 50*/
523 u32 tx_broadcastframes; /* dword 51*/
524 u32 tx_pauseframes; /* dword 52*/
525 u32 tx_controlframes; /* dword 53*/
526 u32 tx_64_byte_packets; /* dword 54*/
527 u32 tx_65_127_byte_packets; /* dword 55*/
528 u32 tx_128_256_byte_packets; /* dword 56*/
529 u32 tx_256_511_byte_packets; /* dword 57*/
530 u32 tx_512_1023_byte_packets; /* dword 58*/
531 u32 tx_1024_1518_byte_packets; /* dword 59*/
532 u32 tx_1519_2047_byte_packets; /* dword 60*/
533 u32 tx_2048_4095_byte_packets; /* dword 61*/
534 u32 tx_4096_8191_byte_packets; /* dword 62*/
535 u32 tx_8192_9216_byte_packets; /* dword 63*/
536 u32 rx_fifo_overflow; /* dword 64*/
537 u32 rx_input_fifo_overflow; /* dword 65*/
540 struct be_rxf_stats {
541 struct be_port_rxf_stats port[2];
542 u32 rx_drops_no_pbuf; /* dword 132*/
543 u32 rx_drops_no_txpb; /* dword 133*/
544 u32 rx_drops_no_erx_descr; /* dword 134*/
545 u32 rx_drops_no_tpre_descr; /* dword 135*/
546 u32 management_rx_port_packets; /* dword 136*/
547 u32 management_rx_port_bytes; /* dword 137*/
548 u32 management_rx_port_pause_frames; /* dword 138*/
549 u32 management_rx_port_errors; /* dword 139*/
550 u32 management_tx_port_packets; /* dword 140*/
551 u32 management_tx_port_bytes; /* dword 141*/
552 u32 management_tx_port_pause; /* dword 142*/
553 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
554 u32 rx_drops_too_many_frags; /* dword 144*/
555 u32 rx_drops_invalid_ring; /* dword 145*/
556 u32 forwarded_packets; /* dword 146*/
557 u32 rx_drops_mtu; /* dword 147*/
561 struct be_erx_stats {
562 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
563 u32 debug_wdma_sent_hold; /* dword 44*/
564 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
565 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
566 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
570 struct be_rxf_stats rxf;
572 struct be_erx_stats erx;
575 struct be_cmd_req_get_stats {
576 struct be_cmd_req_hdr hdr;
577 u8 rsvd[sizeof(struct be_hw_stats)];
580 struct be_cmd_resp_get_stats {
581 struct be_cmd_resp_hdr hdr;
582 struct be_hw_stats hw_stats;
585 struct be_cmd_req_vlan_config {
586 struct be_cmd_req_hdr hdr;
594 struct be_cmd_req_promiscuous_config {
595 struct be_cmd_req_hdr hdr;
596 u8 port0_promiscuous;
597 u8 port1_promiscuous;
601 /******************** Multicast MAC Config *******************/
602 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
607 struct be_cmd_req_mcast_mac_config {
608 struct be_cmd_req_hdr hdr;
612 struct macaddr mac[BE_MAX_MC];
615 static inline struct be_hw_stats *
616 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
618 return &cmd->hw_stats;
621 /******************** Link Status Query *******************/
622 struct be_cmd_req_link_status {
623 struct be_cmd_req_hdr hdr;
628 PHY_LINK_DUPLEX_NONE = 0x0,
629 PHY_LINK_DUPLEX_HALF = 0x1,
630 PHY_LINK_DUPLEX_FULL = 0x2
634 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
635 PHY_LINK_SPEED_10MBPS = 0x1,
636 PHY_LINK_SPEED_100MBPS = 0x2,
637 PHY_LINK_SPEED_1GBPS = 0x3,
638 PHY_LINK_SPEED_10GBPS = 0x4
641 struct be_cmd_resp_link_status {
642 struct be_cmd_resp_hdr hdr;
653 /******************** Port Identification ***************************/
654 /* Identifies the type of port attached to NIC */
655 struct be_cmd_req_port_type {
656 struct be_cmd_req_hdr hdr;
666 struct be_cmd_resp_port_type {
667 struct be_cmd_resp_hdr hdr;
690 /******************** Get FW Version *******************/
691 struct be_cmd_req_get_fw_version {
692 struct be_cmd_req_hdr hdr;
693 u8 rsvd0[FW_VER_LEN];
694 u8 rsvd1[FW_VER_LEN];
697 struct be_cmd_resp_get_fw_version {
698 struct be_cmd_resp_hdr hdr;
699 u8 firmware_version_string[FW_VER_LEN];
700 u8 fw_on_flash_version_string[FW_VER_LEN];
703 /******************** Set Flow Contrl *******************/
704 struct be_cmd_req_set_flow_control {
705 struct be_cmd_req_hdr hdr;
710 /******************** Get Flow Contrl *******************/
711 struct be_cmd_req_get_flow_control {
712 struct be_cmd_req_hdr hdr;
716 struct be_cmd_resp_get_flow_control {
717 struct be_cmd_resp_hdr hdr;
722 /******************** Modify EQ Delay *******************/
723 struct be_cmd_req_modify_eq_delay {
724 struct be_cmd_req_hdr hdr;
729 u32 delay_multiplier;
733 struct be_cmd_resp_modify_eq_delay {
734 struct be_cmd_resp_hdr hdr;
738 /******************** Get FW Config *******************/
739 struct be_cmd_req_query_fw_cfg {
740 struct be_cmd_req_hdr hdr;
744 struct be_cmd_resp_query_fw_cfg {
745 struct be_cmd_resp_hdr hdr;
746 u32 be_config_number;
753 /******************** Port Beacon ***************************/
755 #define BEACON_STATE_ENABLED 0x1
756 #define BEACON_STATE_DISABLED 0x0
758 struct be_cmd_req_enable_disable_beacon {
759 struct be_cmd_req_hdr hdr;
766 struct be_cmd_resp_enable_disable_beacon {
767 struct be_cmd_resp_hdr resp_hdr;
771 struct be_cmd_req_get_beacon_state {
772 struct be_cmd_req_hdr hdr;
778 struct be_cmd_resp_get_beacon_state {
779 struct be_cmd_resp_hdr resp_hdr;
784 /****************** Firmware Flash ******************/
785 struct flashrom_params {
793 struct be_cmd_write_flashrom {
794 struct be_cmd_req_hdr hdr;
795 struct flashrom_params params;
798 /************************ WOL *******************************/
799 struct be_cmd_req_acpi_wol_magic_config{
800 struct be_cmd_req_hdr hdr;
806 /********************** LoopBack test *********************/
807 struct be_cmd_req_loopback_test {
808 struct be_cmd_req_hdr hdr;
817 struct be_cmd_resp_loopback_test {
818 struct be_cmd_resp_hdr resp_hdr;
826 struct be_cmd_req_set_lmode {
827 struct be_cmd_req_hdr hdr;
834 struct be_cmd_resp_set_lmode {
835 struct be_cmd_resp_hdr resp_hdr;
839 /********************** DDR DMA test *********************/
840 struct be_cmd_req_ddrdma_test {
841 struct be_cmd_req_hdr hdr;
849 struct be_cmd_resp_ddrdma_test {
850 struct be_cmd_resp_hdr hdr;
858 /*********************** SEEPROM Read ***********************/
860 #define BE_READ_SEEPROM_LEN 1024
861 struct be_cmd_req_seeprom_read {
862 struct be_cmd_req_hdr hdr;
863 u8 rsvd0[BE_READ_SEEPROM_LEN];
866 struct be_cmd_resp_seeprom_read {
867 struct be_cmd_req_hdr hdr;
868 u8 seeprom_data[BE_READ_SEEPROM_LEN];
871 extern int be_pci_fnum_get(struct be_adapter *adapter);
872 extern int be_cmd_POST(struct be_adapter *adapter);
873 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
874 u8 type, bool permanent, u32 if_handle);
875 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
876 u32 if_id, u32 *pmac_id);
877 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
878 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
879 u32 en_flags, u8 *mac, bool pmac_invalid,
880 u32 *if_handle, u32 *pmac_id);
881 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
882 extern int be_cmd_eq_create(struct be_adapter *adapter,
883 struct be_queue_info *eq, int eq_delay);
884 extern int be_cmd_cq_create(struct be_adapter *adapter,
885 struct be_queue_info *cq, struct be_queue_info *eq,
886 bool sol_evts, bool no_delay,
887 int num_cqe_dma_coalesce);
888 extern int be_cmd_mccq_create(struct be_adapter *adapter,
889 struct be_queue_info *mccq,
890 struct be_queue_info *cq);
891 extern int be_cmd_txq_create(struct be_adapter *adapter,
892 struct be_queue_info *txq,
893 struct be_queue_info *cq);
894 extern int be_cmd_rxq_create(struct be_adapter *adapter,
895 struct be_queue_info *rxq, u16 cq_id,
896 u16 frag_size, u16 max_frame_size, u32 if_id,
898 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
900 extern int be_cmd_link_status_query(struct be_adapter *adapter,
901 bool *link_up, u8 *mac_speed, u16 *link_speed);
902 extern int be_cmd_reset(struct be_adapter *adapter);
903 extern int be_cmd_get_stats(struct be_adapter *adapter,
904 struct be_dma_mem *nonemb_cmd);
905 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
907 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
908 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
909 u16 *vtag_array, u32 num, bool untagged,
911 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
912 u8 port_num, bool en);
913 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
914 struct dev_mc_list *mc_list, u32 mc_count,
915 struct be_dma_mem *mem);
916 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
917 u32 tx_fc, u32 rx_fc);
918 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
919 u32 *tx_fc, u32 *rx_fc);
920 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
921 u32 *port_num, u32 *cap);
922 extern int be_cmd_reset_function(struct be_adapter *adapter);
923 extern int be_process_mcc(struct be_adapter *adapter);
924 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
925 u8 port_num, u8 beacon, u8 status, u8 state);
926 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
927 u8 port_num, u32 *state);
928 extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
930 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
931 struct be_dma_mem *cmd, u32 flash_oper,
932 u32 flash_opcode, u32 buf_size);
933 extern int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc);
934 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
935 struct be_dma_mem *nonemb_cmd);
936 extern int be_cmd_fw_init(struct be_adapter *adapter);
937 extern int be_cmd_fw_clean(struct be_adapter *adapter);
938 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
939 u32 loopback_type, u32 pkt_size,
940 u32 num_pkts, u64 pattern);
941 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
942 u32 byte_cnt, struct be_dma_mem *cmd);
943 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
944 struct be_dma_mem *nonemb_cmd);
945 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
946 u8 loopback_type, u8 enable);