drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5,
  65         MCC_STATUS_NOT_SUPPORTED = 66
  66 };
  67
  68 #define CQE_STATUS_COMPL_MASK           0xFFFF
  69 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  70 #define CQE_STATUS_EXTD_MASK            0xFFFF
  71 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  72
  73 struct be_mcc_compl {
  74         u32 status;             /* dword 0 */
  75         u32 tag0;               /* dword 1 */
  76         u32 tag1;               /* dword 2 */
  77         u32 flags;              /* dword 3 */
  78 };
  79
  80 /* When the async bit of mcc_compl is set, the last 4 bytes of
  81  * mcc_compl is interpreted as follows:
  82  */
  83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  84 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  85 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT  16
  86 #define ASYNC_TRAILER_EVENT_TYPE_MASK   0xFF
  87 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  88 #define ASYNC_EVENT_CODE_GRP_5          0x5
  89 #define ASYNC_EVENT_QOS_SPEED           0x1
  90 #define ASYNC_EVENT_COS_PRIORITY        0x2
  91 #define ASYNC_EVENT_PVID_STATE          0x3
  92 struct be_async_event_trailer {
  93         u32 code;
  94 };
  95
  96 enum {
  97         ASYNC_EVENT_LINK_DOWN   = 0x0,
  98         ASYNC_EVENT_LINK_UP     = 0x1
  99 };
 100
 101 /* When the event code of an async trailer is link-state, the mcc_compl
 102  * must be interpreted as follows
 103  */
 104 struct be_async_event_link_state {
 105         u8 physical_port;
 106         u8 port_link_status;
 107         u8 port_duplex;
 108         u8 port_speed;
 109         u8 port_fault;
 110         u8 rsvd0[7];
 111         struct be_async_event_trailer trailer;
 112 } __packed;
 113
 114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
 115  * the mcc_compl must be interpreted as follows
 116  */
 117 struct be_async_event_grp5_qos_link_speed {
 118         u8 physical_port;
 119         u8 rsvd[5];
 120         u16 qos_link_speed;
 121         u32 event_tag;
 122         struct be_async_event_trailer trailer;
 123 } __packed;
 124
 125 /* When the event code of an async trailer is GRP5 and event type is
 126  * CoS-Priority, the mcc_compl must be interpreted as follows
 127  */
 128 struct be_async_event_grp5_cos_priority {
 129         u8 physical_port;
 130         u8 available_priority_bmap;
 131         u8 reco_default_priority;
 132         u8 valid;
 133         u8 rsvd0;
 134         u8 event_tag;
 135         struct be_async_event_trailer trailer;
 136 } __packed;
 137
 138 /* When the event code of an async trailer is GRP5 and event type is
 139  * PVID state, the mcc_compl must be interpreted as follows
 140  */
 141 struct be_async_event_grp5_pvid_state {
 142         u8 enabled;
 143         u8 rsvd0;
 144         u16 tag;
 145         u32 event_tag;
 146         u32 rsvd1;
 147         struct be_async_event_trailer trailer;
 148 } __packed;
 149
 150 struct be_mcc_mailbox {
 151         struct be_mcc_wrb wrb;
 152         struct be_mcc_compl compl;
 153 };
 154
 155 #define CMD_SUBSYSTEM_COMMON    0x1
 156 #define CMD_SUBSYSTEM_ETH       0x3
 157 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
 158
 159 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 160 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 161 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 162 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 163 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 164 #define OPCODE_COMMON_READ_FLASHROM                     6
 165 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 166 #define OPCODE_COMMON_CQ_CREATE                         12
 167 #define OPCODE_COMMON_EQ_CREATE                         13
 168 #define OPCODE_COMMON_MCC_CREATE                        21
 169 #define OPCODE_COMMON_SET_QOS                           28
 170 #define OPCODE_COMMON_MCC_CREATE_EXT                    90
 171 #define OPCODE_COMMON_SEEPROM_READ                      30
 172 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES               32
 173 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 174 #define OPCODE_COMMON_GET_FW_VERSION                    35
 175 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 176 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 177 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 178 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 179 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 180 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 181 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 182 #define OPCODE_COMMON_MCC_DESTROY                       53
 183 #define OPCODE_COMMON_CQ_DESTROY                        54
 184 #define OPCODE_COMMON_EQ_DESTROY                        55
 185 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 186 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 187 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 188 #define OPCODE_COMMON_FUNCTION_RESET                    61
 189 #define OPCODE_COMMON_MANAGE_FAT                        68
 190 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
 191 #define OPCODE_COMMON_GET_BEACON_STATE                  70
 192 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
 193 #define OPCODE_COMMON_GET_PHY_DETAILS                   102
 194 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP           103
 195 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES    121
 196 #define OPCODE_COMMON_WRITE_OBJECT                      172
 197
 198 #define OPCODE_ETH_RSS_CONFIG                           1
 199 #define OPCODE_ETH_ACPI_CONFIG                          2
 200 #define OPCODE_ETH_PROMISCUOUS                          3
 201 #define OPCODE_ETH_GET_STATISTICS                       4
 202 #define OPCODE_ETH_TX_CREATE                            7
 203 #define OPCODE_ETH_RX_CREATE                            8
 204 #define OPCODE_ETH_TX_DESTROY                           9
 205 #define OPCODE_ETH_RX_DESTROY                           10
 206 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
 207 #define OPCODE_ETH_GET_PPORT_STATS                      18
 208
 209 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
 210 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
 211 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE               19
 212
 213 struct be_cmd_req_hdr {
 214         u8 opcode;              /* dword 0 */
 215         u8 subsystem;           /* dword 0 */
 216         u8 port_number;         /* dword 0 */
 217         u8 domain;              /* dword 0 */
 218         u32 timeout;            /* dword 1 */
 219         u32 request_length;     /* dword 2 */
 220         u8 version;             /* dword 3 */
 221         u8 rsvd[3];             /* dword 3 */
 222 };
 223
 224 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 225 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 226 struct be_cmd_resp_hdr {
 227         u32 info;               /* dword 0 */
 228         u32 status;             /* dword 1 */
 229         u32 response_length;    /* dword 2 */
 230         u32 actual_resp_len;    /* dword 3 */
 231 };
 232
 233 struct phys_addr {
 234         u32 lo;
 235         u32 hi;
 236 };
 237
 238 /**************************
 239  * BE Command definitions *
 240  **************************/
 241
 242 /* Pseudo amap definition in which each bit of the actual structure is defined
 243  * as a byte: used to calculate offset/shift/mask of each field */
 244 struct amap_eq_context {
 245         u8 cidx[13];            /* dword 0*/
 246         u8 rsvd0[3];            /* dword 0*/
 247         u8 epidx[13];           /* dword 0*/
 248         u8 valid;               /* dword 0*/
 249         u8 rsvd1;               /* dword 0*/
 250         u8 size;                /* dword 0*/
 251         u8 pidx[13];            /* dword 1*/
 252         u8 rsvd2[3];            /* dword 1*/
 253         u8 pd[10];              /* dword 1*/
 254         u8 count[3];            /* dword 1*/
 255         u8 solevent;            /* dword 1*/
 256         u8 stalled;             /* dword 1*/
 257         u8 armed;               /* dword 1*/
 258         u8 rsvd3[4];            /* dword 2*/
 259         u8 func[8];             /* dword 2*/
 260         u8 rsvd4;               /* dword 2*/
 261         u8 delaymult[10];       /* dword 2*/
 262         u8 rsvd5[2];            /* dword 2*/
 263         u8 phase[2];            /* dword 2*/
 264         u8 nodelay;             /* dword 2*/
 265         u8 rsvd6[4];            /* dword 2*/
 266         u8 rsvd7[32];           /* dword 3*/
 267 } __packed;
 268
 269 struct be_cmd_req_eq_create {
 270         struct be_cmd_req_hdr hdr;
 271         u16 num_pages;          /* sword */
 272         u16 rsvd0;              /* sword */
 273         u8 context[sizeof(struct amap_eq_context) / 8];
 274         struct phys_addr pages[8];
 275 } __packed;
 276
 277 struct be_cmd_resp_eq_create {
 278         struct be_cmd_resp_hdr resp_hdr;
 279         u16 eq_id;              /* sword */
 280         u16 rsvd0;              /* sword */
 281 } __packed;
 282
 283 /******************** Mac query ***************************/
 284 enum {
 285         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 286         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 287         MAC_ADDRESS_TYPE_PD = 0x2,
 288         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 289 };
 290
 291 struct mac_addr {
 292         u16 size_of_struct;
 293         u8 addr[ETH_ALEN];
 294 } __packed;
 295
 296 struct be_cmd_req_mac_query {
 297         struct be_cmd_req_hdr hdr;
 298         u8 type;
 299         u8 permanent;
 300         u16 if_id;
 301 } __packed;
 302
 303 struct be_cmd_resp_mac_query {
 304         struct be_cmd_resp_hdr hdr;
 305         struct mac_addr mac;
 306 };
 307
 308 /******************** PMac Add ***************************/
 309 struct be_cmd_req_pmac_add {
 310         struct be_cmd_req_hdr hdr;
 311         u32 if_id;
 312         u8 mac_address[ETH_ALEN];
 313         u8 rsvd0[2];
 314 } __packed;
 315
 316 struct be_cmd_resp_pmac_add {
 317         struct be_cmd_resp_hdr hdr;
 318         u32 pmac_id;
 319 };
 320
 321 /******************** PMac Del ***************************/
 322 struct be_cmd_req_pmac_del {
 323         struct be_cmd_req_hdr hdr;
 324         u32 if_id;
 325         u32 pmac_id;
 326 };
 327
 328 /******************** Create CQ ***************************/
 329 /* Pseudo amap definition in which each bit of the actual structure is defined
 330  * as a byte: used to calculate offset/shift/mask of each field */
 331 struct amap_cq_context_be {
 332         u8 cidx[11];            /* dword 0*/
 333         u8 rsvd0;               /* dword 0*/
 334         u8 coalescwm[2];        /* dword 0*/
 335         u8 nodelay;             /* dword 0*/
 336         u8 epidx[11];           /* dword 0*/
 337         u8 rsvd1;               /* dword 0*/
 338         u8 count[2];            /* dword 0*/
 339         u8 valid;               /* dword 0*/
 340         u8 solevent;            /* dword 0*/
 341         u8 eventable;           /* dword 0*/
 342         u8 pidx[11];            /* dword 1*/
 343         u8 rsvd2;               /* dword 1*/
 344         u8 pd[10];              /* dword 1*/
 345         u8 eqid[8];             /* dword 1*/
 346         u8 stalled;             /* dword 1*/
 347         u8 armed;               /* dword 1*/
 348         u8 rsvd3[4];            /* dword 2*/
 349         u8 func[8];             /* dword 2*/
 350         u8 rsvd4[20];           /* dword 2*/
 351         u8 rsvd5[32];           /* dword 3*/
 352 } __packed;
 353
 354 struct amap_cq_context_lancer {
 355         u8 rsvd0[12];           /* dword 0*/
 356         u8 coalescwm[2];        /* dword 0*/
 357         u8 nodelay;             /* dword 0*/
 358         u8 rsvd1[12];           /* dword 0*/
 359         u8 count[2];            /* dword 0*/
 360         u8 valid;               /* dword 0*/
 361         u8 rsvd2;               /* dword 0*/
 362         u8 eventable;           /* dword 0*/
 363         u8 eqid[16];            /* dword 1*/
 364         u8 rsvd3[15];           /* dword 1*/
 365         u8 armed;               /* dword 1*/
 366         u8 rsvd4[32];           /* dword 2*/
 367         u8 rsvd5[32];           /* dword 3*/
 368 } __packed;
 369
 370 struct be_cmd_req_cq_create {
 371         struct be_cmd_req_hdr hdr;
 372         u16 num_pages;
 373         u8 page_size;
 374         u8 rsvd0;
 375         u8 context[sizeof(struct amap_cq_context_be) / 8];
 376         struct phys_addr pages[8];
 377 } __packed;
 378
 379
 380 struct be_cmd_resp_cq_create {
 381         struct be_cmd_resp_hdr hdr;
 382         u16 cq_id;
 383         u16 rsvd0;
 384 } __packed;
 385
 386 struct be_cmd_req_get_fat {
 387         struct be_cmd_req_hdr hdr;
 388         u32 fat_operation;
 389         u32 read_log_offset;
 390         u32 read_log_length;
 391         u32 data_buffer_size;
 392         u32 data_buffer[1];
 393 } __packed;
 394
 395 struct be_cmd_resp_get_fat {
 396         struct be_cmd_resp_hdr hdr;
 397         u32 log_size;
 398         u32 read_log_length;
 399         u32 rsvd[2];
 400         u32 data_buffer[1];
 401 } __packed;
 402
 403
 404 /******************** Create MCCQ ***************************/
 405 /* Pseudo amap definition in which each bit of the actual structure is defined
 406  * as a byte: used to calculate offset/shift/mask of each field */
 407 struct amap_mcc_context_be {
 408         u8 con_index[14];
 409         u8 rsvd0[2];
 410         u8 ring_size[4];
 411         u8 fetch_wrb;
 412         u8 fetch_r2t;
 413         u8 cq_id[10];
 414         u8 prod_index[14];
 415         u8 fid[8];
 416         u8 pdid[9];
 417         u8 valid;
 418         u8 rsvd1[32];
 419         u8 rsvd2[32];
 420 } __packed;
 421
 422 struct amap_mcc_context_lancer {
 423         u8 async_cq_id[16];
 424         u8 ring_size[4];
 425         u8 rsvd0[12];
 426         u8 rsvd1[31];
 427         u8 valid;
 428         u8 async_cq_valid[1];
 429         u8 rsvd2[31];
 430         u8 rsvd3[32];
 431 } __packed;
 432
 433 struct be_cmd_req_mcc_create {
 434         struct be_cmd_req_hdr hdr;
 435         u16 num_pages;
 436         u16 cq_id;
 437         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 438         struct phys_addr pages[8];
 439 } __packed;
 440
 441 struct be_cmd_req_mcc_ext_create {
 442         struct be_cmd_req_hdr hdr;
 443         u16 num_pages;
 444         u16 cq_id;
 445         u32 async_event_bitmap[1];
 446         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 447         struct phys_addr pages[8];
 448 } __packed;
 449
 450 struct be_cmd_resp_mcc_create {
 451         struct be_cmd_resp_hdr hdr;
 452         u16 id;
 453         u16 rsvd0;
 454 } __packed;
 455
 456 /******************** Create TxQ ***************************/
 457 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 458 #define BE_ULP1_NUM                             1
 459
 460 /* Pseudo amap definition in which each bit of the actual structure is defined
 461  * as a byte: used to calculate offset/shift/mask of each field */
 462 struct amap_tx_context {
 463         u8 if_id[16];           /* dword 0 */
 464         u8 tx_ring_size[4];     /* dword 0 */
 465         u8 rsvd1[26];           /* dword 0 */
 466         u8 pci_func_id[8];      /* dword 1 */
 467         u8 rsvd2[9];            /* dword 1 */
 468         u8 ctx_valid;           /* dword 1 */
 469         u8 cq_id_send[16];      /* dword 2 */
 470         u8 rsvd3[16];           /* dword 2 */
 471         u8 rsvd4[32];           /* dword 3 */
 472         u8 rsvd5[32];           /* dword 4 */
 473         u8 rsvd6[32];           /* dword 5 */
 474         u8 rsvd7[32];           /* dword 6 */
 475         u8 rsvd8[32];           /* dword 7 */
 476         u8 rsvd9[32];           /* dword 8 */
 477         u8 rsvd10[32];          /* dword 9 */
 478         u8 rsvd11[32];          /* dword 10 */
 479         u8 rsvd12[32];          /* dword 11 */
 480         u8 rsvd13[32];          /* dword 12 */
 481         u8 rsvd14[32];          /* dword 13 */
 482         u8 rsvd15[32];          /* dword 14 */
 483         u8 rsvd16[32];          /* dword 15 */
 484 } __packed;
 485
 486 struct be_cmd_req_eth_tx_create {
 487         struct be_cmd_req_hdr hdr;
 488         u8 num_pages;
 489         u8 ulp_num;
 490         u8 type;
 491         u8 bound_port;
 492         u8 context[sizeof(struct amap_tx_context) / 8];
 493         struct phys_addr pages[8];
 494 } __packed;
 495
 496 struct be_cmd_resp_eth_tx_create {
 497         struct be_cmd_resp_hdr hdr;
 498         u16 cid;
 499         u16 rsvd0;
 500 } __packed;
 501
 502 /******************** Create RxQ ***************************/
 503 struct be_cmd_req_eth_rx_create {
 504         struct be_cmd_req_hdr hdr;
 505         u16 cq_id;
 506         u8 frag_size;
 507         u8 num_pages;
 508         struct phys_addr pages[2];
 509         u32 interface_id;
 510         u16 max_frame_size;
 511         u16 rsvd0;
 512         u32 rss_queue;
 513 } __packed;
 514
 515 struct be_cmd_resp_eth_rx_create {
 516         struct be_cmd_resp_hdr hdr;
 517         u16 id;
 518         u8 rss_id;
 519         u8 rsvd0;
 520 } __packed;
 521
 522 /******************** Q Destroy  ***************************/
 523 /* Type of Queue to be destroyed */
 524 enum {
 525         QTYPE_EQ = 1,
 526         QTYPE_CQ,
 527         QTYPE_TXQ,
 528         QTYPE_RXQ,
 529         QTYPE_MCCQ
 530 };
 531
 532 struct be_cmd_req_q_destroy {
 533         struct be_cmd_req_hdr hdr;
 534         u16 id;
 535         u16 bypass_flush;       /* valid only for rx q destroy */
 536 } __packed;
 537
 538 /************ I/f Create (it's actually I/f Config Create)**********/
 539
 540 /* Capability flags for the i/f */
 541 enum be_if_flags {
 542         BE_IF_FLAGS_RSS = 0x4,
 543         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 544         BE_IF_FLAGS_BROADCAST = 0x10,
 545         BE_IF_FLAGS_UNTAGGED = 0x20,
 546         BE_IF_FLAGS_ULP = 0x40,
 547         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 548         BE_IF_FLAGS_VLAN = 0x100,
 549         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 550         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 551         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
 552         BE_IF_FLAGS_MULTICAST = 0x1000
 553 };
 554
 555 /* An RX interface is an object with one or more MAC addresses and
 556  * filtering capabilities. */
 557 struct be_cmd_req_if_create {
 558         struct be_cmd_req_hdr hdr;
 559         u32 version;            /* ignore currently */
 560         u32 capability_flags;
 561         u32 enable_flags;
 562         u8 mac_addr[ETH_ALEN];
 563         u8 rsvd0;
 564         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 565         u32 vlan_tag;    /* not used currently */
 566 } __packed;
 567
 568 struct be_cmd_resp_if_create {
 569         struct be_cmd_resp_hdr hdr;
 570         u32 interface_id;
 571         u32 pmac_id;
 572 };
 573
 574 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 575 struct be_cmd_req_if_destroy {
 576         struct be_cmd_req_hdr hdr;
 577         u32 interface_id;
 578 };
 579
 580 /*************** HW Stats Get **********************************/
 581 struct be_port_rxf_stats_v0 {
 582         u32 rx_bytes_lsd;       /* dword 0*/
 583         u32 rx_bytes_msd;       /* dword 1*/
 584         u32 rx_total_frames;    /* dword 2*/
 585         u32 rx_unicast_frames;  /* dword 3*/
 586         u32 rx_multicast_frames;        /* dword 4*/
 587         u32 rx_broadcast_frames;        /* dword 5*/
 588         u32 rx_crc_errors;      /* dword 6*/
 589         u32 rx_alignment_symbol_errors; /* dword 7*/
 590         u32 rx_pause_frames;    /* dword 8*/
 591         u32 rx_control_frames;  /* dword 9*/
 592         u32 rx_in_range_errors; /* dword 10*/
 593         u32 rx_out_range_errors;        /* dword 11*/
 594         u32 rx_frame_too_long;  /* dword 12*/
 595         u32 rx_address_match_errors;    /* dword 13*/
 596         u32 rx_vlan_mismatch;   /* dword 14*/
 597         u32 rx_dropped_too_small;       /* dword 15*/
 598         u32 rx_dropped_too_short;       /* dword 16*/
 599         u32 rx_dropped_header_too_small;        /* dword 17*/
 600         u32 rx_dropped_tcp_length;      /* dword 18*/
 601         u32 rx_dropped_runt;    /* dword 19*/
 602         u32 rx_64_byte_packets; /* dword 20*/
 603         u32 rx_65_127_byte_packets;     /* dword 21*/
 604         u32 rx_128_256_byte_packets;    /* dword 22*/
 605         u32 rx_256_511_byte_packets;    /* dword 23*/
 606         u32 rx_512_1023_byte_packets;   /* dword 24*/
 607         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 608         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 609         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 610         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 611         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 612         u32 rx_ip_checksum_errs;        /* dword 30*/
 613         u32 rx_tcp_checksum_errs;       /* dword 31*/
 614         u32 rx_udp_checksum_errs;       /* dword 32*/
 615         u32 rx_non_rss_packets; /* dword 33*/
 616         u32 rx_ipv4_packets;    /* dword 34*/
 617         u32 rx_ipv6_packets;    /* dword 35*/
 618         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 619         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 620         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 621         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 622         u32 rx_chute1_packets;  /* dword 40*/
 623         u32 rx_chute2_packets;  /* dword 41*/
 624         u32 rx_chute3_packets;  /* dword 42*/
 625         u32 rx_management_packets;      /* dword 43*/
 626         u32 rx_switched_unicast_packets;        /* dword 44*/
 627         u32 rx_switched_multicast_packets;      /* dword 45*/
 628         u32 rx_switched_broadcast_packets;      /* dword 46*/
 629         u32 tx_bytes_lsd;       /* dword 47*/
 630         u32 tx_bytes_msd;       /* dword 48*/
 631         u32 tx_unicastframes;   /* dword 49*/
 632         u32 tx_multicastframes; /* dword 50*/
 633         u32 tx_broadcastframes; /* dword 51*/
 634         u32 tx_pauseframes;     /* dword 52*/
 635         u32 tx_controlframes;   /* dword 53*/
 636         u32 tx_64_byte_packets; /* dword 54*/
 637         u32 tx_65_127_byte_packets;     /* dword 55*/
 638         u32 tx_128_256_byte_packets;    /* dword 56*/
 639         u32 tx_256_511_byte_packets;    /* dword 57*/
 640         u32 tx_512_1023_byte_packets;   /* dword 58*/
 641         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 642         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 643         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 644         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 645         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 646         u32 rx_fifo_overflow;   /* dword 64*/
 647         u32 rx_input_fifo_overflow;     /* dword 65*/
 648 };
 649
 650 struct be_rxf_stats_v0 {
 651         struct be_port_rxf_stats_v0 port[2];
 652         u32 rx_drops_no_pbuf;   /* dword 132*/
 653         u32 rx_drops_no_txpb;   /* dword 133*/
 654         u32 rx_drops_no_erx_descr;      /* dword 134*/
 655         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 656         u32 management_rx_port_packets; /* dword 136*/
 657         u32 management_rx_port_bytes;   /* dword 137*/
 658         u32 management_rx_port_pause_frames;    /* dword 138*/
 659         u32 management_rx_port_errors;  /* dword 139*/
 660         u32 management_tx_port_packets; /* dword 140*/
 661         u32 management_tx_port_bytes;   /* dword 141*/
 662         u32 management_tx_port_pause;   /* dword 142*/
 663         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 664         u32 rx_drops_too_many_frags;    /* dword 144*/
 665         u32 rx_drops_invalid_ring;      /* dword 145*/
 666         u32 forwarded_packets;  /* dword 146*/
 667         u32 rx_drops_mtu;       /* dword 147*/
 668         u32 rsvd0[7];
 669         u32 port0_jabber_events;
 670         u32 port1_jabber_events;
 671         u32 rsvd1[6];
 672 };
 673
 674 struct be_erx_stats_v0 {
 675         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 676         u32 rsvd[4];
 677 };
 678
 679 struct be_pmem_stats {
 680         u32 eth_red_drops;
 681         u32 rsvd[5];
 682 };
 683
 684 struct be_hw_stats_v0 {
 685         struct be_rxf_stats_v0 rxf;
 686         u32 rsvd[48];
 687         struct be_erx_stats_v0 erx;
 688         struct be_pmem_stats pmem;
 689 };
 690
 691 struct be_cmd_req_get_stats_v0 {
 692         struct be_cmd_req_hdr hdr;
 693         u8 rsvd[sizeof(struct be_hw_stats_v0)];
 694 };
 695
 696 struct be_cmd_resp_get_stats_v0 {
 697         struct be_cmd_resp_hdr hdr;
 698         struct be_hw_stats_v0 hw_stats;
 699 };
 700
 701 #define make_64bit_val(hi_32, lo_32)    (((u64)hi_32<<32) | lo_32)
 702 struct lancer_cmd_pport_stats {
 703         u32 tx_packets_lo;
 704         u32 tx_packets_hi;
 705         u32 tx_unicast_packets_lo;
 706         u32 tx_unicast_packets_hi;
 707         u32 tx_multicast_packets_lo;
 708         u32 tx_multicast_packets_hi;
 709         u32 tx_broadcast_packets_lo;
 710         u32 tx_broadcast_packets_hi;
 711         u32 tx_bytes_lo;
 712         u32 tx_bytes_hi;
 713         u32 tx_unicast_bytes_lo;
 714         u32 tx_unicast_bytes_hi;
 715         u32 tx_multicast_bytes_lo;
 716         u32 tx_multicast_bytes_hi;
 717         u32 tx_broadcast_bytes_lo;
 718         u32 tx_broadcast_bytes_hi;
 719         u32 tx_discards_lo;
 720         u32 tx_discards_hi;
 721         u32 tx_errors_lo;
 722         u32 tx_errors_hi;
 723         u32 tx_pause_frames_lo;
 724         u32 tx_pause_frames_hi;
 725         u32 tx_pause_on_frames_lo;
 726         u32 tx_pause_on_frames_hi;
 727         u32 tx_pause_off_frames_lo;
 728         u32 tx_pause_off_frames_hi;
 729         u32 tx_internal_mac_errors_lo;
 730         u32 tx_internal_mac_errors_hi;
 731         u32 tx_control_frames_lo;
 732         u32 tx_control_frames_hi;
 733         u32 tx_packets_64_bytes_lo;
 734         u32 tx_packets_64_bytes_hi;
 735         u32 tx_packets_65_to_127_bytes_lo;
 736         u32 tx_packets_65_to_127_bytes_hi;
 737         u32 tx_packets_128_to_255_bytes_lo;
 738         u32 tx_packets_128_to_255_bytes_hi;
 739         u32 tx_packets_256_to_511_bytes_lo;
 740         u32 tx_packets_256_to_511_bytes_hi;
 741         u32 tx_packets_512_to_1023_bytes_lo;
 742         u32 tx_packets_512_to_1023_bytes_hi;
 743         u32 tx_packets_1024_to_1518_bytes_lo;
 744         u32 tx_packets_1024_to_1518_bytes_hi;
 745         u32 tx_packets_1519_to_2047_bytes_lo;
 746         u32 tx_packets_1519_to_2047_bytes_hi;
 747         u32 tx_packets_2048_to_4095_bytes_lo;
 748         u32 tx_packets_2048_to_4095_bytes_hi;
 749         u32 tx_packets_4096_to_8191_bytes_lo;
 750         u32 tx_packets_4096_to_8191_bytes_hi;
 751         u32 tx_packets_8192_to_9216_bytes_lo;
 752         u32 tx_packets_8192_to_9216_bytes_hi;
 753         u32 tx_lso_packets_lo;
 754         u32 tx_lso_packets_hi;
 755         u32 rx_packets_lo;
 756         u32 rx_packets_hi;
 757         u32 rx_unicast_packets_lo;
 758         u32 rx_unicast_packets_hi;
 759         u32 rx_multicast_packets_lo;
 760         u32 rx_multicast_packets_hi;
 761         u32 rx_broadcast_packets_lo;
 762         u32 rx_broadcast_packets_hi;
 763         u32 rx_bytes_lo;
 764         u32 rx_bytes_hi;
 765         u32 rx_unicast_bytes_lo;
 766         u32 rx_unicast_bytes_hi;
 767         u32 rx_multicast_bytes_lo;
 768         u32 rx_multicast_bytes_hi;
 769         u32 rx_broadcast_bytes_lo;
 770         u32 rx_broadcast_bytes_hi;
 771         u32 rx_unknown_protos;
 772         u32 rsvd_69; /* Word 69 is reserved */
 773         u32 rx_discards_lo;
 774         u32 rx_discards_hi;
 775         u32 rx_errors_lo;
 776         u32 rx_errors_hi;
 777         u32 rx_crc_errors_lo;
 778         u32 rx_crc_errors_hi;
 779         u32 rx_alignment_errors_lo;
 780         u32 rx_alignment_errors_hi;
 781         u32 rx_symbol_errors_lo;
 782         u32 rx_symbol_errors_hi;
 783         u32 rx_pause_frames_lo;
 784         u32 rx_pause_frames_hi;
 785         u32 rx_pause_on_frames_lo;
 786         u32 rx_pause_on_frames_hi;
 787         u32 rx_pause_off_frames_lo;
 788         u32 rx_pause_off_frames_hi;
 789         u32 rx_frames_too_long_lo;
 790         u32 rx_frames_too_long_hi;
 791         u32 rx_internal_mac_errors_lo;
 792         u32 rx_internal_mac_errors_hi;
 793         u32 rx_undersize_packets;
 794         u32 rx_oversize_packets;
 795         u32 rx_fragment_packets;
 796         u32 rx_jabbers;
 797         u32 rx_control_frames_lo;
 798         u32 rx_control_frames_hi;
 799         u32 rx_control_frames_unknown_opcode_lo;
 800         u32 rx_control_frames_unknown_opcode_hi;
 801         u32 rx_in_range_errors;
 802         u32 rx_out_of_range_errors;
 803         u32 rx_address_match_errors;
 804         u32 rx_vlan_mismatch_errors;
 805         u32 rx_dropped_too_small;
 806         u32 rx_dropped_too_short;
 807         u32 rx_dropped_header_too_small;
 808         u32 rx_dropped_invalid_tcp_length;
 809         u32 rx_dropped_runt;
 810         u32 rx_ip_checksum_errors;
 811         u32 rx_tcp_checksum_errors;
 812         u32 rx_udp_checksum_errors;
 813         u32 rx_non_rss_packets;
 814         u32 rsvd_111;
 815         u32 rx_ipv4_packets_lo;
 816         u32 rx_ipv4_packets_hi;
 817         u32 rx_ipv6_packets_lo;
 818         u32 rx_ipv6_packets_hi;
 819         u32 rx_ipv4_bytes_lo;
 820         u32 rx_ipv4_bytes_hi;
 821         u32 rx_ipv6_bytes_lo;
 822         u32 rx_ipv6_bytes_hi;
 823         u32 rx_nic_packets_lo;
 824         u32 rx_nic_packets_hi;
 825         u32 rx_tcp_packets_lo;
 826         u32 rx_tcp_packets_hi;
 827         u32 rx_iscsi_packets_lo;
 828         u32 rx_iscsi_packets_hi;
 829         u32 rx_management_packets_lo;
 830         u32 rx_management_packets_hi;
 831         u32 rx_switched_unicast_packets_lo;
 832         u32 rx_switched_unicast_packets_hi;
 833         u32 rx_switched_multicast_packets_lo;
 834         u32 rx_switched_multicast_packets_hi;
 835         u32 rx_switched_broadcast_packets_lo;
 836         u32 rx_switched_broadcast_packets_hi;
 837         u32 num_forwards_lo;
 838         u32 num_forwards_hi;
 839         u32 rx_fifo_overflow;
 840         u32 rx_input_fifo_overflow;
 841         u32 rx_drops_too_many_frags_lo;
 842         u32 rx_drops_too_many_frags_hi;
 843         u32 rx_drops_invalid_queue;
 844         u32 rsvd_141;
 845         u32 rx_drops_mtu_lo;
 846         u32 rx_drops_mtu_hi;
 847         u32 rx_packets_64_bytes_lo;
 848         u32 rx_packets_64_bytes_hi;
 849         u32 rx_packets_65_to_127_bytes_lo;
 850         u32 rx_packets_65_to_127_bytes_hi;
 851         u32 rx_packets_128_to_255_bytes_lo;
 852         u32 rx_packets_128_to_255_bytes_hi;
 853         u32 rx_packets_256_to_511_bytes_lo;
 854         u32 rx_packets_256_to_511_bytes_hi;
 855         u32 rx_packets_512_to_1023_bytes_lo;
 856         u32 rx_packets_512_to_1023_bytes_hi;
 857         u32 rx_packets_1024_to_1518_bytes_lo;
 858         u32 rx_packets_1024_to_1518_bytes_hi;
 859         u32 rx_packets_1519_to_2047_bytes_lo;
 860         u32 rx_packets_1519_to_2047_bytes_hi;
 861         u32 rx_packets_2048_to_4095_bytes_lo;
 862         u32 rx_packets_2048_to_4095_bytes_hi;
 863         u32 rx_packets_4096_to_8191_bytes_lo;
 864         u32 rx_packets_4096_to_8191_bytes_hi;
 865         u32 rx_packets_8192_to_9216_bytes_lo;
 866         u32 rx_packets_8192_to_9216_bytes_hi;
 867 };
 868
 869 struct pport_stats_params {
 870         u16 pport_num;
 871         u8 rsvd;
 872         u8 reset_stats;
 873 };
 874
 875 struct lancer_cmd_req_pport_stats {
 876         struct be_cmd_req_hdr hdr;
 877         union {
 878                 struct pport_stats_params params;
 879                 u8 rsvd[sizeof(struct lancer_cmd_pport_stats)];
 880         } cmd_params;
 881 };
 882
 883 struct lancer_cmd_resp_pport_stats {
 884         struct be_cmd_resp_hdr hdr;
 885         struct lancer_cmd_pport_stats pport_stats;
 886 };
 887
 888 static inline  struct lancer_cmd_pport_stats*
 889         pport_stats_from_cmd(struct be_adapter *adapter)
 890 {
 891         struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
 892         return &cmd->pport_stats;
 893 }
 894
 895 struct be_cmd_req_get_cntl_addnl_attribs {
 896         struct be_cmd_req_hdr hdr;
 897         u8 rsvd[8];
 898 };
 899
 900 struct be_cmd_resp_get_cntl_addnl_attribs {
 901         struct be_cmd_resp_hdr hdr;
 902         u16 ipl_file_number;
 903         u8 ipl_file_version;
 904         u8 rsvd0;
 905         u8 on_die_temperature; /* in degrees centigrade*/
 906         u8 rsvd1[3];
 907 };
 908
 909 struct be_cmd_req_vlan_config {
 910         struct be_cmd_req_hdr hdr;
 911         u8 interface_id;
 912         u8 promiscuous;
 913         u8 untagged;
 914         u8 num_vlan;
 915         u16 normal_vlan[64];
 916 } __packed;
 917
 918 /******************** Multicast MAC Config *******************/
 919 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
 920 struct macaddr {
 921         u8 byte[ETH_ALEN];
 922 };
 923
 924 struct be_cmd_req_mcast_mac_config {
 925         struct be_cmd_req_hdr hdr;
 926         u16 num_mac;
 927         u8 promiscuous;
 928         u8 interface_id;
 929         struct macaddr mac[BE_MAX_MC];
 930 } __packed;
 931
 932 /******************* RX FILTER ******************************/
 933 struct be_cmd_req_rx_filter {
 934         struct be_cmd_req_hdr hdr;
 935         u32 global_flags_mask;
 936         u32 global_flags;
 937         u32 if_flags_mask;
 938         u32 if_flags;
 939         u32 if_id;
 940         u32 multicast_num;
 941         struct macaddr mac[BE_MAX_MC];
 942 };
 943
 944
 945 /******************** Link Status Query *******************/
 946 struct be_cmd_req_link_status {
 947         struct be_cmd_req_hdr hdr;
 948         u32 rsvd;
 949 };
 950
 951 enum {
 952         PHY_LINK_DUPLEX_NONE = 0x0,
 953         PHY_LINK_DUPLEX_HALF = 0x1,
 954         PHY_LINK_DUPLEX_FULL = 0x2
 955 };
 956
 957 enum {
 958         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 959         PHY_LINK_SPEED_10MBPS = 0x1,
 960         PHY_LINK_SPEED_100MBPS = 0x2,
 961         PHY_LINK_SPEED_1GBPS = 0x3,
 962         PHY_LINK_SPEED_10GBPS = 0x4
 963 };
 964
 965 struct be_cmd_resp_link_status {
 966         struct be_cmd_resp_hdr hdr;
 967         u8 physical_port;
 968         u8 mac_duplex;
 969         u8 mac_speed;
 970         u8 mac_fault;
 971         u8 mgmt_mac_duplex;
 972         u8 mgmt_mac_speed;
 973         u16 link_speed;
 974         u32 rsvd0;
 975 } __packed;
 976
 977 /******************** Port Identification ***************************/
 978 /*    Identifies the type of port attached to NIC     */
 979 struct be_cmd_req_port_type {
 980         struct be_cmd_req_hdr hdr;
 981         u32 page_num;
 982         u32 port;
 983 };
 984
 985 enum {
 986         TR_PAGE_A0 = 0xa0,
 987         TR_PAGE_A2 = 0xa2
 988 };
 989
 990 struct be_cmd_resp_port_type {
 991         struct be_cmd_resp_hdr hdr;
 992         u32 page_num;
 993         u32 port;
 994         struct data {
 995                 u8 identifier;
 996                 u8 identifier_ext;
 997                 u8 connector;
 998                 u8 transceiver[8];
 999                 u8 rsvd0[3];
1000                 u8 length_km;
1001                 u8 length_hm;
1002                 u8 length_om1;
1003                 u8 length_om2;
1004                 u8 length_cu;
1005                 u8 length_cu_m;
1006                 u8 vendor_name[16];
1007                 u8 rsvd;
1008                 u8 vendor_oui[3];
1009                 u8 vendor_pn[16];
1010                 u8 vendor_rev[4];
1011         } data;
1012 };
1013
1014 /******************** Get FW Version *******************/
1015 struct be_cmd_req_get_fw_version {
1016         struct be_cmd_req_hdr hdr;
1017         u8 rsvd0[FW_VER_LEN];
1018         u8 rsvd1[FW_VER_LEN];
1019 } __packed;
1020
1021 struct be_cmd_resp_get_fw_version {
1022         struct be_cmd_resp_hdr hdr;
1023         u8 firmware_version_string[FW_VER_LEN];
1024         u8 fw_on_flash_version_string[FW_VER_LEN];
1025 } __packed;
1026
1027 /******************** Set Flow Contrl *******************/
1028 struct be_cmd_req_set_flow_control {
1029         struct be_cmd_req_hdr hdr;
1030         u16 tx_flow_control;
1031         u16 rx_flow_control;
1032 } __packed;
1033
1034 /******************** Get Flow Contrl *******************/
1035 struct be_cmd_req_get_flow_control {
1036         struct be_cmd_req_hdr hdr;
1037         u32 rsvd;
1038 };
1039
1040 struct be_cmd_resp_get_flow_control {
1041         struct be_cmd_resp_hdr hdr;
1042         u16 tx_flow_control;
1043         u16 rx_flow_control;
1044 } __packed;
1045
1046 /******************** Modify EQ Delay *******************/
1047 struct be_cmd_req_modify_eq_delay {
1048         struct be_cmd_req_hdr hdr;
1049         u32 num_eq;
1050         struct {
1051                 u32 eq_id;
1052                 u32 phase;
1053                 u32 delay_multiplier;
1054         } delay[8];
1055 } __packed;
1056
1057 struct be_cmd_resp_modify_eq_delay {
1058         struct be_cmd_resp_hdr hdr;
1059         u32 rsvd0;
1060 } __packed;
1061
1062 /******************** Get FW Config *******************/
1063 #define BE_FUNCTION_CAPS_RSS                    0x2
1064 struct be_cmd_req_query_fw_cfg {
1065         struct be_cmd_req_hdr hdr;
1066         u32 rsvd[31];
1067 };
1068
1069 struct be_cmd_resp_query_fw_cfg {
1070         struct be_cmd_resp_hdr hdr;
1071         u32 be_config_number;
1072         u32 asic_revision;
1073         u32 phys_port;
1074         u32 function_mode;
1075         u32 rsvd[26];
1076         u32 function_caps;
1077 };
1078
1079 /******************** RSS Config *******************/
1080 /* RSS types */
1081 #define RSS_ENABLE_NONE                         0x0
1082 #define RSS_ENABLE_IPV4                         0x1
1083 #define RSS_ENABLE_TCP_IPV4                     0x2
1084 #define RSS_ENABLE_IPV6                         0x4
1085 #define RSS_ENABLE_TCP_IPV6                     0x8
1086
1087 struct be_cmd_req_rss_config {
1088         struct be_cmd_req_hdr hdr;
1089         u32 if_id;
1090         u16 enable_rss;
1091         u16 cpu_table_size_log2;
1092         u32 hash[10];
1093         u8 cpu_table[128];
1094         u8 flush;
1095         u8 rsvd0[3];
1096 };
1097
1098 /******************** Port Beacon ***************************/
1099
1100 #define BEACON_STATE_ENABLED            0x1
1101 #define BEACON_STATE_DISABLED           0x0
1102
1103 struct be_cmd_req_enable_disable_beacon {
1104         struct be_cmd_req_hdr hdr;
1105         u8  port_num;
1106         u8  beacon_state;
1107         u8  beacon_duration;
1108         u8  status_duration;
1109 } __packed;
1110
1111 struct be_cmd_resp_enable_disable_beacon {
1112         struct be_cmd_resp_hdr resp_hdr;
1113         u32 rsvd0;
1114 } __packed;
1115
1116 struct be_cmd_req_get_beacon_state {
1117         struct be_cmd_req_hdr hdr;
1118         u8  port_num;
1119         u8  rsvd0;
1120         u16 rsvd1;
1121 } __packed;
1122
1123 struct be_cmd_resp_get_beacon_state {
1124         struct be_cmd_resp_hdr resp_hdr;
1125         u8 beacon_state;
1126         u8 rsvd0[3];
1127 } __packed;
1128
1129 /****************** Firmware Flash ******************/
1130 struct flashrom_params {
1131         u32 op_code;
1132         u32 op_type;
1133         u32 data_buf_size;
1134         u32 offset;
1135         u8 data_buf[4];
1136 };
1137
1138 struct be_cmd_write_flashrom {
1139         struct be_cmd_req_hdr hdr;
1140         struct flashrom_params params;
1141 };
1142
1143 /**************** Lancer Firmware Flash ************/
1144 struct amap_lancer_write_obj_context {
1145         u8 write_length[24];
1146         u8 reserved1[7];
1147         u8 eof;
1148 } __packed;
1149
1150 struct lancer_cmd_req_write_object {
1151         struct be_cmd_req_hdr hdr;
1152         u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1153         u32 write_offset;
1154         u8 object_name[104];
1155         u32 descriptor_count;
1156         u32 buf_len;
1157         u32 addr_low;
1158         u32 addr_high;
1159 };
1160
1161 struct lancer_cmd_resp_write_object {
1162         u8 opcode;
1163         u8 subsystem;
1164         u8 rsvd1[2];
1165         u8 status;
1166         u8 additional_status;
1167         u8 rsvd2[2];
1168         u32 resp_len;
1169         u32 actual_resp_len;
1170         u32 actual_write_len;
1171 };
1172
1173 /************************ WOL *******************************/
1174 struct be_cmd_req_acpi_wol_magic_config{
1175         struct be_cmd_req_hdr hdr;
1176         u32 rsvd0[145];
1177         u8 magic_mac[6];
1178         u8 rsvd2[2];
1179 } __packed;
1180
1181 /********************** LoopBack test *********************/
1182 struct be_cmd_req_loopback_test {
1183         struct be_cmd_req_hdr hdr;
1184         u32 loopback_type;
1185         u32 num_pkts;
1186         u64 pattern;
1187         u32 src_port;
1188         u32 dest_port;
1189         u32 pkt_size;
1190 };
1191
1192 struct be_cmd_resp_loopback_test {
1193         struct be_cmd_resp_hdr resp_hdr;
1194         u32    status;
1195         u32    num_txfer;
1196         u32    num_rx;
1197         u32    miscomp_off;
1198         u32    ticks_compl;
1199 };
1200
1201 struct be_cmd_req_set_lmode {
1202         struct be_cmd_req_hdr hdr;
1203         u8 src_port;
1204         u8 dest_port;
1205         u8 loopback_type;
1206         u8 loopback_state;
1207 };
1208
1209 struct be_cmd_resp_set_lmode {
1210         struct be_cmd_resp_hdr resp_hdr;
1211         u8 rsvd0[4];
1212 };
1213
1214 /********************** DDR DMA test *********************/
1215 struct be_cmd_req_ddrdma_test {
1216         struct be_cmd_req_hdr hdr;
1217         u64 pattern;
1218         u32 byte_count;
1219         u32 rsvd0;
1220         u8  snd_buff[4096];
1221         u8  rsvd1[4096];
1222 };
1223
1224 struct be_cmd_resp_ddrdma_test {
1225         struct be_cmd_resp_hdr hdr;
1226         u64 pattern;
1227         u32 byte_cnt;
1228         u32 snd_err;
1229         u8  rsvd0[4096];
1230         u8  rcv_buff[4096];
1231 };
1232
1233 /*********************** SEEPROM Read ***********************/
1234
1235 #define BE_READ_SEEPROM_LEN 1024
1236 struct be_cmd_req_seeprom_read {
1237         struct be_cmd_req_hdr hdr;
1238         u8 rsvd0[BE_READ_SEEPROM_LEN];
1239 };
1240
1241 struct be_cmd_resp_seeprom_read {
1242         struct be_cmd_req_hdr hdr;
1243         u8 seeprom_data[BE_READ_SEEPROM_LEN];
1244 };
1245
1246 enum {
1247         PHY_TYPE_CX4_10GB = 0,
1248         PHY_TYPE_XFP_10GB,
1249         PHY_TYPE_SFP_1GB,
1250         PHY_TYPE_SFP_PLUS_10GB,
1251         PHY_TYPE_KR_10GB,
1252         PHY_TYPE_KX4_10GB,
1253         PHY_TYPE_BASET_10GB,
1254         PHY_TYPE_BASET_1GB,
1255         PHY_TYPE_DISABLED = 255
1256 };
1257
1258 struct be_cmd_req_get_phy_info {
1259         struct be_cmd_req_hdr hdr;
1260         u8 rsvd0[24];
1261 };
1262 struct be_cmd_resp_get_phy_info {
1263         struct be_cmd_req_hdr hdr;
1264         u16 phy_type;
1265         u16 interface_type;
1266         u32 misc_params;
1267         u32 future_use[4];
1268 };
1269
1270 /*********************** Set QOS ***********************/
1271
1272 #define BE_QOS_BITS_NIC                         1
1273
1274 struct be_cmd_req_set_qos {
1275         struct be_cmd_req_hdr hdr;
1276         u32 valid_bits;
1277         u32 max_bps_nic;
1278         u32 rsvd[7];
1279 };
1280
1281 struct be_cmd_resp_set_qos {
1282         struct be_cmd_resp_hdr hdr;
1283         u32 rsvd;
1284 };
1285
1286 /*********************** Controller Attributes ***********************/
1287 struct be_cmd_req_cntl_attribs {
1288         struct be_cmd_req_hdr hdr;
1289 };
1290
1291 struct be_cmd_resp_cntl_attribs {
1292         struct be_cmd_resp_hdr hdr;
1293         struct mgmt_controller_attrib attribs;
1294 };
1295
1296 /*********************** Set driver function ***********************/
1297 #define CAPABILITY_SW_TIMESTAMPS        2
1298 #define CAPABILITY_BE3_NATIVE_ERX_API   4
1299
1300 struct be_cmd_req_set_func_cap {
1301         struct be_cmd_req_hdr hdr;
1302         u32 valid_cap_flags;
1303         u32 cap_flags;
1304         u8 rsvd[212];
1305 };
1306
1307 struct be_cmd_resp_set_func_cap {
1308         struct be_cmd_resp_hdr hdr;
1309         u32 valid_cap_flags;
1310         u32 cap_flags;
1311         u8 rsvd[212];
1312 };
1313
1314 /*************** HW Stats Get v1 **********************************/
1315 #define BE_TXP_SW_SZ                    48
1316 struct be_port_rxf_stats_v1 {
1317         u32 rsvd0[12];
1318         u32 rx_crc_errors;
1319         u32 rx_alignment_symbol_errors;
1320         u32 rx_pause_frames;
1321         u32 rx_priority_pause_frames;
1322         u32 rx_control_frames;
1323         u32 rx_in_range_errors;
1324         u32 rx_out_range_errors;
1325         u32 rx_frame_too_long;
1326         u32 rx_address_match_errors;
1327         u32 rx_dropped_too_small;
1328         u32 rx_dropped_too_short;
1329         u32 rx_dropped_header_too_small;
1330         u32 rx_dropped_tcp_length;
1331         u32 rx_dropped_runt;
1332         u32 rsvd1[10];
1333         u32 rx_ip_checksum_errs;
1334         u32 rx_tcp_checksum_errs;
1335         u32 rx_udp_checksum_errs;
1336         u32 rsvd2[7];
1337         u32 rx_switched_unicast_packets;
1338         u32 rx_switched_multicast_packets;
1339         u32 rx_switched_broadcast_packets;
1340         u32 rsvd3[3];
1341         u32 tx_pauseframes;
1342         u32 tx_priority_pauseframes;
1343         u32 tx_controlframes;
1344         u32 rsvd4[10];
1345         u32 rxpp_fifo_overflow_drop;
1346         u32 rx_input_fifo_overflow_drop;
1347         u32 pmem_fifo_overflow_drop;
1348         u32 jabber_events;
1349         u32 rsvd5[3];
1350 };
1351
1352
1353 struct be_rxf_stats_v1 {
1354         struct be_port_rxf_stats_v1 port[4];
1355         u32 rsvd0[2];
1356         u32 rx_drops_no_pbuf;
1357         u32 rx_drops_no_txpb;
1358         u32 rx_drops_no_erx_descr;
1359         u32 rx_drops_no_tpre_descr;
1360         u32 rsvd1[6];
1361         u32 rx_drops_too_many_frags;
1362         u32 rx_drops_invalid_ring;
1363         u32 forwarded_packets;
1364         u32 rx_drops_mtu;
1365         u32 rsvd2[14];
1366 };
1367
1368 struct be_erx_stats_v1 {
1369         u32 rx_drops_no_fragments[68];     /* dwordS 0 to 67*/
1370         u32 rsvd[4];
1371 };
1372
1373 struct be_hw_stats_v1 {
1374         struct be_rxf_stats_v1 rxf;
1375         u32 rsvd0[BE_TXP_SW_SZ];
1376         struct be_erx_stats_v1 erx;
1377         struct be_pmem_stats pmem;
1378         u32 rsvd1[3];
1379 };
1380
1381 struct be_cmd_req_get_stats_v1 {
1382         struct be_cmd_req_hdr hdr;
1383         u8 rsvd[sizeof(struct be_hw_stats_v1)];
1384 };
1385
1386 struct be_cmd_resp_get_stats_v1 {
1387         struct be_cmd_resp_hdr hdr;
1388         struct be_hw_stats_v1 hw_stats;
1389 };
1390
1391 static inline void *
1392 hw_stats_from_cmd(struct be_adapter *adapter)
1393 {
1394         if (adapter->generation == BE_GEN3) {
1395                 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va;
1396
1397                 return &cmd->hw_stats;
1398         } else {
1399                 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va;
1400
1401                 return &cmd->hw_stats;
1402         }
1403 }
1404
1405 static inline void *be_port_rxf_stats_from_cmd(struct be_adapter *adapter)
1406 {
1407         if (adapter->generation == BE_GEN3) {
1408                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1409                 struct be_rxf_stats_v1 *rxf_stats = &hw_stats->rxf;
1410
1411                 return &rxf_stats->port[adapter->port_num];
1412         } else {
1413                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1414                 struct be_rxf_stats_v0 *rxf_stats = &hw_stats->rxf;
1415
1416                 return &rxf_stats->port[adapter->port_num];
1417         }
1418 }
1419
1420 static inline void *be_rxf_stats_from_cmd(struct be_adapter *adapter)
1421 {
1422         if (adapter->generation == BE_GEN3) {
1423                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1424
1425                 return &hw_stats->rxf;
1426         } else {
1427                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1428
1429                 return &hw_stats->rxf;
1430         }
1431 }
1432
1433 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter)
1434 {
1435         if (adapter->generation == BE_GEN3) {
1436                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1437
1438                 return &hw_stats->erx;
1439         } else {
1440                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1441
1442                 return &hw_stats->erx;
1443         }
1444 }
1445
1446 static inline void *be_pmem_stats_from_cmd(struct be_adapter *adapter)
1447 {
1448         if (adapter->generation == BE_GEN3) {
1449                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1450
1451                 return &hw_stats->pmem;
1452         } else {
1453                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1454
1455                 return &hw_stats->pmem;
1456         }
1457 }
1458
1459 extern int be_pci_fnum_get(struct be_adapter *adapter);
1460 extern int be_cmd_POST(struct be_adapter *adapter);
1461 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1462                         u8 type, bool permanent, u32 if_handle);
1463 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1464                         u32 if_id, u32 *pmac_id, u32 domain);
1465 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1466                         u32 pmac_id, u32 domain);
1467 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1468                         u32 en_flags, u8 *mac, bool pmac_invalid,
1469                         u32 *if_handle, u32 *pmac_id, u32 domain);
1470 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1471                         u32 domain);
1472 extern int be_cmd_eq_create(struct be_adapter *adapter,
1473                         struct be_queue_info *eq, int eq_delay);
1474 extern int be_cmd_cq_create(struct be_adapter *adapter,
1475                         struct be_queue_info *cq, struct be_queue_info *eq,
1476                         bool sol_evts, bool no_delay,
1477                         int num_cqe_dma_coalesce);
1478 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1479                         struct be_queue_info *mccq,
1480                         struct be_queue_info *cq);
1481 extern int be_cmd_txq_create(struct be_adapter *adapter,
1482                         struct be_queue_info *txq,
1483                         struct be_queue_info *cq);
1484 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1485                         struct be_queue_info *rxq, u16 cq_id,
1486                         u16 frag_size, u16 max_frame_size, u32 if_id,
1487                         u32 rss, u8 *rss_id);
1488 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1489                         int type);
1490 extern int be_cmd_link_status_query(struct be_adapter *adapter,
1491                         bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom);
1492 extern int be_cmd_reset(struct be_adapter *adapter);
1493 extern int be_cmd_get_stats(struct be_adapter *adapter,
1494                         struct be_dma_mem *nonemb_cmd);
1495 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1496                         struct be_dma_mem *nonemb_cmd);
1497 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1498
1499 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1500 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1501                         u16 *vtag_array, u32 num, bool untagged,
1502                         bool promiscuous);
1503 extern int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en);
1504 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1505                         struct net_device *netdev, struct be_dma_mem *mem);
1506 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1507                         u32 tx_fc, u32 rx_fc);
1508 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1509                         u32 *tx_fc, u32 *rx_fc);
1510 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1511                         u32 *port_num, u32 *function_mode, u32 *function_caps);
1512 extern int be_cmd_reset_function(struct be_adapter *adapter);
1513 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1514                         u16 table_size);
1515 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1516 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1517                         u8 port_num, u8 beacon, u8 status, u8 state);
1518 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1519                         u8 port_num, u32 *state);
1520 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1521                         struct be_dma_mem *cmd, u32 flash_oper,
1522                         u32 flash_opcode, u32 buf_size);
1523 extern int lancer_cmd_write_object(struct be_adapter *adapter,
1524                                 struct be_dma_mem *cmd,
1525                                 u32 data_size, u32 data_offset,
1526                                 const char *obj_name,
1527                                 u32 *data_written, u8 *addn_status);
1528 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1529                                 int offset);
1530 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1531                                 struct be_dma_mem *nonemb_cmd);
1532 extern int be_cmd_fw_init(struct be_adapter *adapter);
1533 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1534 extern void be_async_mcc_enable(struct be_adapter *adapter);
1535 extern void be_async_mcc_disable(struct be_adapter *adapter);
1536 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1537                                 u32 loopback_type, u32 pkt_size,
1538                                 u32 num_pkts, u64 pattern);
1539 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1540                         u32 byte_cnt, struct be_dma_mem *cmd);
1541 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1542                                 struct be_dma_mem *nonemb_cmd);
1543 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1544                                 u8 loopback_type, u8 enable);
1545 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1546                 struct be_dma_mem *cmd);
1547 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1548 extern void be_detect_dump_ue(struct be_adapter *adapter);
1549 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1550 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1551 extern int be_cmd_check_native_mode(struct be_adapter *adapter);
1552 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1553 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1554