2 * Linux network driver for Brocade Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
26 #define BFA_IOC_TOV 3000 /* msecs */
27 #define BFA_IOC_HWSEM_TOV 500 /* msecs */
28 #define BFA_IOC_HB_TOV 500 /* msecs */
29 #define BFA_IOC_HWINIT_MAX 2
30 #define BFA_IOC_TOV_RECOVER BFA_IOC_HB_TOV
33 * Generic Scatter Gather Element used by driver
41 * PCI device information required by IOC
47 void __iomem *pci_bar_kva;
51 * Structure used to remember the DMA-able memory block's KVA and Physical
55 void *kva; /* ! Kernel virtual address */
56 u64 pa; /* ! Physical address */
59 #define BFA_DMA_ALIGN_SZ 256
62 * smem size for Crossbow and Catapult
64 #define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
65 #define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
68 * @brief BFA dma address assignment macro
70 #define bfa_dma_addr_set(dma_addr, pa) \
71 __bfa_dma_addr_set(&dma_addr, (u64)pa)
74 __bfa_dma_addr_set(union bfi_addr_u *dma_addr, u64 pa)
76 dma_addr->a32.addr_lo = (u32) pa;
77 dma_addr->a32.addr_hi = (u32) (upper_32_bits(pa));
81 * @brief BFA dma address assignment macro. (big endian format)
83 #define bfa_dma_be_addr_set(dma_addr, pa) \
84 __bfa_dma_be_addr_set(&dma_addr, (u64)pa)
86 __bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
88 dma_addr->a32.addr_lo = (u32) htonl(pa);
89 dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa));
93 void __iomem *hfn_mbox_cmd;
94 void __iomem *hfn_mbox;
95 void __iomem *lpu_mbox_cmd;
96 void __iomem *lpu_mbox;
97 void __iomem *pss_ctl_reg;
98 void __iomem *pss_err_status_reg;
99 void __iomem *app_pll_fast_ctl_reg;
100 void __iomem *app_pll_slow_ctl_reg;
101 void __iomem *ioc_sem_reg;
102 void __iomem *ioc_usage_sem_reg;
103 void __iomem *ioc_init_sem_reg;
104 void __iomem *ioc_usage_reg;
105 void __iomem *host_page_num_fn;
106 void __iomem *heartbeat;
107 void __iomem *ioc_fwstate;
108 void __iomem *ll_halt;
109 void __iomem *err_set;
110 void __iomem *shirq_isr_next;
111 void __iomem *shirq_msk_next;
112 void __iomem *smem_page_start;
117 * IOC Mailbox structures
119 struct bfa_mbox_cmd {
121 u32 msg[BFI_IOC_MSGSZ];
127 typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg *m);
128 struct bfa_ioc_mbox_mod {
129 struct list_head cmd_q; /*!< pending mbox queue */
130 int nmclass; /*!< number of handlers */
132 bfa_ioc_mbox_mcfunc_t cbfn; /*!< message handlers */
134 } mbhdlr[BFI_MC_MAX];
138 * IOC callback function interfaces
140 typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
141 typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
142 typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
143 typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
144 struct bfa_ioc_cbfn {
145 bfa_ioc_enable_cbfn_t enable_cbfn;
146 bfa_ioc_disable_cbfn_t disable_cbfn;
147 bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
148 bfa_ioc_reset_cbfn_t reset_cbfn;
152 * Heartbeat failure notification queue element.
154 struct bfa_ioc_hbfail_notify {
156 bfa_ioc_hbfail_cbfn_t cbfn;
161 * Initialize a heartbeat failure notification structure
163 #define bfa_ioc_hbfail_init(__notify, __cbfn, __cbarg) do { \
164 (__notify)->cbfn = (__cbfn); \
165 (__notify)->cbarg = (__cbarg); \
171 struct bfa_pcidev pcidev;
172 struct bfa_timer_mod *timer_mod;
173 struct timer_list ioc_timer;
174 struct timer_list sem_timer;
175 struct timer_list hb_timer;
178 struct list_head hb_notify_q;
181 bool dbg_fwsave_once;
182 enum bfi_mclass ioc_mc;
183 struct bfa_ioc_regs ioc_regs;
184 struct bfa_ioc_drv_stats stats;
190 bool stats_busy; /*!< outstanding stats */
193 struct bfa_dma attr_dma;
194 struct bfi_ioc_attr *attr;
195 struct bfa_ioc_cbfn *cbfn;
196 struct bfa_ioc_mbox_mod mbox_mod;
197 struct bfa_ioc_hwif *ioc_hwif;
200 struct bfa_ioc_hwif {
201 enum bfa_status (*ioc_pll_init) (void __iomem *rb, bool fcmode);
202 bool (*ioc_firmware_lock) (struct bfa_ioc *ioc);
203 void (*ioc_firmware_unlock) (struct bfa_ioc *ioc);
204 void (*ioc_reg_init) (struct bfa_ioc *ioc);
205 void (*ioc_map_port) (struct bfa_ioc *ioc);
206 void (*ioc_isr_mode_set) (struct bfa_ioc *ioc,
208 void (*ioc_notify_hbfail) (struct bfa_ioc *ioc);
209 void (*ioc_ownership_reset) (struct bfa_ioc *ioc);
212 #define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
213 #define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
214 #define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
215 #define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
216 #define bfa_ioc_fetch_stats(__ioc, __stats) \
217 (((__stats)->drv_stats) = (__ioc)->stats)
218 #define bfa_ioc_clr_stats(__ioc) \
219 memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
220 #define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
221 #define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
222 #define bfa_ioc_speed_sup(__ioc) \
223 BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
224 #define bfa_ioc_get_nports(__ioc) \
225 BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
227 #define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
228 #define BFA_IOC_FWIMG_MINSZ (16 * 1024)
229 #define BFA_IOC_FWIMG_TYPE(__ioc) \
230 (((__ioc)->ctdev) ? \
231 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \
233 #define BFA_IOC_FW_SMEM_SIZE(__ioc) \
234 (((__ioc)->ctdev) ? BFI_SMEM_CT_SIZE : BFI_SMEM_CB_SIZE)
235 #define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
236 #define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
237 #define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
240 * IOC mailbox interface
242 void bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd);
243 void bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc);
244 void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
245 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
251 #define bfa_ioc_pll_init_asic(__ioc) \
252 ((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
255 #define bfa_ioc_isr_mode_set(__ioc, __msix) \
256 ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
257 #define bfa_ioc_ownership_reset(__ioc) \
258 ((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
260 void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);
262 void bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa,
263 struct bfa_ioc_cbfn *cbfn);
264 void bfa_nw_ioc_auto_recover(bool auto_recover);
265 void bfa_nw_ioc_detach(struct bfa_ioc *ioc);
266 void bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
268 u32 bfa_nw_ioc_meminfo(void);
269 void bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa);
270 void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
271 void bfa_nw_ioc_disable(struct bfa_ioc *ioc);
273 void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
275 void bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
276 void bfa_nw_ioc_hbfail_register(struct bfa_ioc *ioc,
277 struct bfa_ioc_hbfail_notify *notify);
278 bool bfa_nw_ioc_sem_get(void __iomem *sem_reg);
279 void bfa_nw_ioc_sem_release(void __iomem *sem_reg);
280 void bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc);
281 void bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc,
282 struct bfi_ioc_image_hdr *fwhdr);
283 bool bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc,
284 struct bfi_ioc_image_hdr *fwhdr);
285 mac_t bfa_nw_ioc_get_mac(struct bfa_ioc *ioc);
290 void bfa_nw_ioc_timeout(void *ioc);
291 void bfa_nw_ioc_hb_check(void *ioc);
292 void bfa_nw_ioc_sem_timeout(void *ioc);
295 * F/W Image Size & Chunk
297 u32 *bfa_cb_image_get_chunk(int type, u32 off);
298 u32 bfa_cb_image_get_size(int type);
300 #endif /* __BFA_IOC_H__ */