2 * Linux network driver for Brocade Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
22 #include "bfi_ctreg.h"
25 #define bfa_ioc_ct_sync_pos(__ioc) \
26 ((u32) (1 << bfa_ioc_pcifn(__ioc)))
27 #define BFA_IOC_SYNC_REQD_SH 16
28 #define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
29 #define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
30 #define bfa_ioc_ct_get_sync_reqd(__val) (__val >> BFA_IOC_SYNC_REQD_SH)
31 #define bfa_ioc_ct_sync_reqd_pos(__ioc) \
32 (bfa_ioc_ct_sync_pos(__ioc) << BFA_IOC_SYNC_REQD_SH)
35 * forward declarations
37 static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);
38 static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
39 static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
40 static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
41 static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
42 static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);
43 static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
44 static void bfa_ioc_ct_sync_join(struct bfa_ioc *ioc);
45 static void bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc);
46 static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc);
47 static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);
48 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode);
50 static struct bfa_ioc_hwif nw_hwif_ct;
53 * Called from bfa_ioc_attach() to map asic specific calls.
56 bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc)
58 nw_hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
59 nw_hwif_ct.ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
60 nw_hwif_ct.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
61 nw_hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
62 nw_hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
63 nw_hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
64 nw_hwif_ct.ioc_notify_fail = bfa_ioc_ct_notify_fail;
65 nw_hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
66 nw_hwif_ct.ioc_sync_join = bfa_ioc_ct_sync_join;
67 nw_hwif_ct.ioc_sync_leave = bfa_ioc_ct_sync_leave;
68 nw_hwif_ct.ioc_sync_ack = bfa_ioc_ct_sync_ack;
69 nw_hwif_ct.ioc_sync_complete = bfa_ioc_ct_sync_complete;
71 ioc->ioc_hwif = &nw_hwif_ct;
75 * Return true if firmware of current driver matches the running firmware.
78 bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
80 enum bfi_ioc_state ioc_fwstate;
82 struct bfi_ioc_image_hdr fwhdr;
85 * Firmware match check is relevant only for CNA.
91 * If bios boot (flash based) -- do not increment usage count
93 if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
97 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
98 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
101 * If usage count is 0, always return TRUE.
104 writel(1, ioc->ioc_regs.ioc_usage_reg);
105 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
106 writel(0, ioc->ioc_regs.ioc_fail_sync);
110 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
113 * Use count cannot be non-zero and chip in uninitialized state.
115 BUG_ON(!(ioc_fwstate != BFI_IOC_UNINIT));
118 * Check if another driver with a different firmware is active
120 bfa_nw_ioc_fwver_get(ioc, &fwhdr);
121 if (!bfa_nw_ioc_fwver_cmp(ioc, &fwhdr)) {
122 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
127 * Same firmware version. Increment the reference count.
130 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
131 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
136 bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
141 * Firmware lock is relevant only for CNA.
147 * If bios boot (flash based) -- do not decrement usage count
149 if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
154 * decrement usage count
156 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
157 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
158 BUG_ON(!(usecnt > 0));
161 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
163 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
167 * Notify other functions on HB failure.
170 bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc)
173 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
174 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
175 /* Wait for halt to take effect */
176 readl(ioc->ioc_regs.ll_halt);
177 readl(ioc->ioc_regs.alt_ll_halt);
179 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
180 readl(ioc->ioc_regs.err_set);
185 * Host to LPU mailbox message addresses
187 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
188 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
189 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
190 { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
191 { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
195 * Host <-> LPU mailbox command/status registers - port 0
197 static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
198 { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT },
199 { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT },
200 { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT },
201 { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT }
205 * Host <-> LPU mailbox command/status registers - port 1
207 static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
208 { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT },
209 { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT },
210 { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT },
211 { HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT }
215 bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
218 int pcifn = bfa_ioc_pcifn(ioc);
220 rb = bfa_ioc_bar0(ioc);
222 ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
223 ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
224 ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
226 if (ioc->port_id == 0) {
227 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
228 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
229 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
230 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
231 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
232 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
233 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
235 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
236 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
237 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
238 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
239 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
240 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
241 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
245 * PSS control registers
247 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
248 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
249 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG);
250 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG);
253 * IOC semaphore registers and serialization
255 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
256 ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
257 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
258 ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
259 ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
264 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
265 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
268 * err set reg : for notification of hb failure in fcmode
270 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
274 * Initialize IOC to port mapping.
277 #define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
279 bfa_ioc_ct_map_port(struct bfa_ioc *ioc)
281 void __iomem *rb = ioc->pcidev.pci_bar_kva;
285 * For catapult, base port id on personality register and IOC type
287 r32 = readl(rb + FNC_PERS_REG);
288 r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
289 ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
294 * Set interrupt mode for a function: INTX or MSIX
297 bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix)
299 void __iomem *rb = ioc->pcidev.pci_bar_kva;
302 r32 = readl(rb + FNC_PERS_REG);
304 mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
308 * If already in desired mode, do not change anything
314 mode = __F0_INTX_STATUS_MSIX;
316 mode = __F0_INTX_STATUS_INTA;
318 r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
319 r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
321 writel(r32, rb + FNC_PERS_REG);
325 * Cleanup hw semaphore and usecnt registers
328 bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
331 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
332 writel(0, ioc->ioc_regs.ioc_usage_reg);
333 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
337 * Read the hw sem reg to make sure that it is locked
338 * before we clear it. If it is not locked, writing 1
339 * will lock it instead of clearing it.
341 readl(ioc->ioc_regs.ioc_sem_reg);
342 bfa_nw_ioc_hw_sem_release(ioc);
346 * Synchronized IOC failure processing routines
349 bfa_ioc_ct_sync_join(struct bfa_ioc *ioc)
351 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
352 u32 sync_pos = bfa_ioc_ct_sync_reqd_pos(ioc);
354 writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
358 bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc)
360 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
361 u32 sync_msk = bfa_ioc_ct_sync_reqd_pos(ioc) |
362 bfa_ioc_ct_sync_pos(ioc);
364 writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
368 bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc)
370 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
372 writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);
376 bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc)
378 u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
379 u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
380 u32 sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
387 * The check below is to see whether any other PCI fn
388 * has reinitialized the ASIC (reset sync_ackd bits)
389 * and failed again while this IOC was waiting for hw
390 * semaphore (in bfa_iocpf_sm_semwait()).
392 tmp_ackd = sync_ackd;
393 if ((sync_reqd & bfa_ioc_ct_sync_pos(ioc)) &&
394 !(sync_ackd & bfa_ioc_ct_sync_pos(ioc)))
395 sync_ackd |= bfa_ioc_ct_sync_pos(ioc);
397 if (sync_reqd == sync_ackd) {
398 writel(bfa_ioc_ct_clear_sync_ackd(r32),
399 ioc->ioc_regs.ioc_fail_sync);
400 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
401 writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
406 * If another PCI fn reinitialized and failed again while
407 * this IOC was waiting for hw sem, the sync_ackd bit for
408 * this IOC need to be set again to allow reinitialization.
410 if (tmp_ackd != sync_ackd)
411 writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
416 static enum bfa_status
417 bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode)
419 u32 pll_sclk, pll_fclk, r32;
421 pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
422 __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
423 __APP_PLL_312_JITLMT0_1(3U) |
424 __APP_PLL_312_CNTLMT0_1(1U);
425 pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
426 __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
427 __APP_PLL_425_JITLMT0_1(3U) |
428 __APP_PLL_425_CNTLMT0_1(1U);
430 writel(0, (rb + OP_MODE));
431 writel(__APP_EMS_CMLCKSEL |
432 __APP_EMS_REFCKBUFEN2 |
433 __APP_EMS_CHANNEL_SEL,
434 (rb + ETH_MAC_SER_REG));
436 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
437 writel(__APP_EMS_REFCKBUFEN1,
438 (rb + ETH_MAC_SER_REG));
440 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
441 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
442 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
443 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
444 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
445 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
446 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
447 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
449 __APP_PLL_312_LOGIC_SOFT_RESET,
450 rb + APP_PLL_312_CTL_REG);
452 __APP_PLL_425_LOGIC_SOFT_RESET,
453 rb + APP_PLL_425_CTL_REG);
455 __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE,
456 rb + APP_PLL_312_CTL_REG);
458 __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE,
459 rb + APP_PLL_425_CTL_REG);
460 readl(rb + HOSTFN0_INT_MSK);
462 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
463 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
465 __APP_PLL_312_ENABLE,
466 rb + APP_PLL_312_CTL_REG);
468 __APP_PLL_425_ENABLE,
469 rb + APP_PLL_425_CTL_REG);
471 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
472 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
474 r32 = readl((rb + PSS_CTL_REG));
475 r32 &= ~__PSS_LMEM_RESET;
476 writel(r32, (rb + PSS_CTL_REG));
479 writel(0, (rb + PMM_1T_RESET_REG_P0));
480 writel(0, (rb + PMM_1T_RESET_REG_P1));
483 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
485 r32 = readl((rb + MBIST_STAT_REG));
486 writel(0, (rb + MBIST_CTL_REG));
487 return BFA_STATUS_OK;