1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
33 #include <linux/delay.h>
34 #include <asm/byteorder.h>
36 #include <linux/time.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
39 #include <linux/if_vlan.h>
40 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
45 #include <net/checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/prefetch.h>
49 #include <linux/cache.h>
50 #include <linux/firmware.h>
51 #include <linux/log2.h>
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
60 #define DRV_MODULE_NAME "bnx2"
61 #define DRV_MODULE_VERSION "2.0.8"
62 #define DRV_MODULE_RELDATE "Feb 15, 2010"
63 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
64 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
65 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j9.fw"
66 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
67 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
69 #define RUN_AT(x) (jiffies + (x))
71 /* Time in jiffies before concluding the transmitter is hung. */
72 #define TX_TIMEOUT (5*HZ)
74 static char version[] __devinitdata =
75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
78 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
79 MODULE_LICENSE("GPL");
80 MODULE_VERSION(DRV_MODULE_VERSION);
81 MODULE_FIRMWARE(FW_MIPS_FILE_06);
82 MODULE_FIRMWARE(FW_RV2P_FILE_06);
83 MODULE_FIRMWARE(FW_MIPS_FILE_09);
84 MODULE_FIRMWARE(FW_RV2P_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
87 static int disable_msi = 0;
89 module_param(disable_msi, int, 0);
90 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
106 /* indexed by board_t, above */
109 } board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
123 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
149 static const struct flash_spec flash_table[] =
151 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
238 static const struct flash_spec flash_5709 = {
239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
247 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
249 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
255 /* The ring uses 256 indices for 255 entries, one of them
256 * needs to be skipped.
258 diff = txr->tx_prod - txr->tx_cons;
259 if (unlikely(diff >= TX_DESC_CNT)) {
261 if (diff == TX_DESC_CNT)
262 diff = MAX_TX_DESC_CNT;
264 return (bp->tx_ring_size - diff);
268 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272 spin_lock_bh(&bp->indirect_lock);
273 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
274 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
275 spin_unlock_bh(&bp->indirect_lock);
280 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
282 spin_lock_bh(&bp->indirect_lock);
283 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
284 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
285 spin_unlock_bh(&bp->indirect_lock);
289 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
291 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
297 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
301 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
304 spin_lock_bh(&bp->indirect_lock);
305 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
308 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
309 REG_WR(bp, BNX2_CTX_CTX_CTRL,
310 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
311 for (i = 0; i < 5; i++) {
312 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
313 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
318 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
319 REG_WR(bp, BNX2_CTX_DATA, val);
321 spin_unlock_bh(&bp->indirect_lock);
326 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
328 struct bnx2 *bp = netdev_priv(dev);
329 struct drv_ctl_io *io = &info->data.io;
332 case DRV_CTL_IO_WR_CMD:
333 bnx2_reg_wr_ind(bp, io->offset, io->data);
335 case DRV_CTL_IO_RD_CMD:
336 io->data = bnx2_reg_rd_ind(bp, io->offset);
338 case DRV_CTL_CTX_WR_CMD:
339 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
347 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
349 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
350 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
353 if (bp->flags & BNX2_FLAG_USING_MSIX) {
354 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
355 bnapi->cnic_present = 0;
356 sb_id = bp->irq_nvecs;
357 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
359 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
360 bnapi->cnic_tag = bnapi->last_status_idx;
361 bnapi->cnic_present = 1;
363 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
366 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
367 cp->irq_arr[0].status_blk = (void *)
368 ((unsigned long) bnapi->status_blk.msi +
369 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
370 cp->irq_arr[0].status_blk_num = sb_id;
374 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
377 struct bnx2 *bp = netdev_priv(dev);
378 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
383 if (cp->drv_state & CNIC_DRV_STATE_REGD)
386 bp->cnic_data = data;
387 rcu_assign_pointer(bp->cnic_ops, ops);
390 cp->drv_state = CNIC_DRV_STATE_REGD;
392 bnx2_setup_cnic_irq_info(bp);
397 static int bnx2_unregister_cnic(struct net_device *dev)
399 struct bnx2 *bp = netdev_priv(dev);
400 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
401 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
403 mutex_lock(&bp->cnic_lock);
405 bnapi->cnic_present = 0;
406 rcu_assign_pointer(bp->cnic_ops, NULL);
407 mutex_unlock(&bp->cnic_lock);
412 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
414 struct bnx2 *bp = netdev_priv(dev);
415 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
417 cp->drv_owner = THIS_MODULE;
418 cp->chip_id = bp->chip_id;
420 cp->io_base = bp->regview;
421 cp->drv_ctl = bnx2_drv_ctl;
422 cp->drv_register_cnic = bnx2_register_cnic;
423 cp->drv_unregister_cnic = bnx2_unregister_cnic;
427 EXPORT_SYMBOL(bnx2_cnic_probe);
430 bnx2_cnic_stop(struct bnx2 *bp)
432 struct cnic_ops *c_ops;
433 struct cnic_ctl_info info;
435 mutex_lock(&bp->cnic_lock);
436 c_ops = bp->cnic_ops;
438 info.cmd = CNIC_CTL_STOP_CMD;
439 c_ops->cnic_ctl(bp->cnic_data, &info);
441 mutex_unlock(&bp->cnic_lock);
445 bnx2_cnic_start(struct bnx2 *bp)
447 struct cnic_ops *c_ops;
448 struct cnic_ctl_info info;
450 mutex_lock(&bp->cnic_lock);
451 c_ops = bp->cnic_ops;
453 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
454 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
456 bnapi->cnic_tag = bnapi->last_status_idx;
458 info.cmd = CNIC_CTL_START_CMD;
459 c_ops->cnic_ctl(bp->cnic_data, &info);
461 mutex_unlock(&bp->cnic_lock);
467 bnx2_cnic_stop(struct bnx2 *bp)
472 bnx2_cnic_start(struct bnx2 *bp)
479 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
484 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
485 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
486 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
488 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
489 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
494 val1 = (bp->phy_addr << 21) | (reg << 16) |
495 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
496 BNX2_EMAC_MDIO_COMM_START_BUSY;
497 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
499 for (i = 0; i < 50; i++) {
502 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
503 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
506 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
507 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
513 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
522 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
523 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
524 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
526 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
527 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
536 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
541 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
542 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
543 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
545 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
546 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
551 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
552 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
553 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
554 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
556 for (i = 0; i < 50; i++) {
559 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
560 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
566 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
571 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
572 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
573 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
575 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
576 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
585 bnx2_disable_int(struct bnx2 *bp)
588 struct bnx2_napi *bnapi;
590 for (i = 0; i < bp->irq_nvecs; i++) {
591 bnapi = &bp->bnx2_napi[i];
592 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
593 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
595 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
599 bnx2_enable_int(struct bnx2 *bp)
602 struct bnx2_napi *bnapi;
604 for (i = 0; i < bp->irq_nvecs; i++) {
605 bnapi = &bp->bnx2_napi[i];
607 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
608 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
609 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
610 bnapi->last_status_idx);
612 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
613 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
614 bnapi->last_status_idx);
616 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
620 bnx2_disable_int_sync(struct bnx2 *bp)
624 atomic_inc(&bp->intr_sem);
625 if (!netif_running(bp->dev))
628 bnx2_disable_int(bp);
629 for (i = 0; i < bp->irq_nvecs; i++)
630 synchronize_irq(bp->irq_tbl[i].vector);
634 bnx2_napi_disable(struct bnx2 *bp)
638 for (i = 0; i < bp->irq_nvecs; i++)
639 napi_disable(&bp->bnx2_napi[i].napi);
643 bnx2_napi_enable(struct bnx2 *bp)
647 for (i = 0; i < bp->irq_nvecs; i++)
648 napi_enable(&bp->bnx2_napi[i].napi);
652 bnx2_netif_stop(struct bnx2 *bp)
655 if (netif_running(bp->dev)) {
658 bnx2_napi_disable(bp);
659 netif_tx_disable(bp->dev);
660 /* prevent tx timeout */
661 for (i = 0; i < bp->dev->num_tx_queues; i++) {
662 struct netdev_queue *txq;
664 txq = netdev_get_tx_queue(bp->dev, i);
665 txq->trans_start = jiffies;
668 bnx2_disable_int_sync(bp);
672 bnx2_netif_start(struct bnx2 *bp)
674 if (atomic_dec_and_test(&bp->intr_sem)) {
675 if (netif_running(bp->dev)) {
676 netif_tx_wake_all_queues(bp->dev);
677 bnx2_napi_enable(bp);
685 bnx2_free_tx_mem(struct bnx2 *bp)
689 for (i = 0; i < bp->num_tx_rings; i++) {
690 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
691 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
693 if (txr->tx_desc_ring) {
694 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
696 txr->tx_desc_mapping);
697 txr->tx_desc_ring = NULL;
699 kfree(txr->tx_buf_ring);
700 txr->tx_buf_ring = NULL;
705 bnx2_free_rx_mem(struct bnx2 *bp)
709 for (i = 0; i < bp->num_rx_rings; i++) {
710 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
711 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
714 for (j = 0; j < bp->rx_max_ring; j++) {
715 if (rxr->rx_desc_ring[j])
716 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
717 rxr->rx_desc_ring[j],
718 rxr->rx_desc_mapping[j]);
719 rxr->rx_desc_ring[j] = NULL;
721 vfree(rxr->rx_buf_ring);
722 rxr->rx_buf_ring = NULL;
724 for (j = 0; j < bp->rx_max_pg_ring; j++) {
725 if (rxr->rx_pg_desc_ring[j])
726 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
727 rxr->rx_pg_desc_ring[j],
728 rxr->rx_pg_desc_mapping[j]);
729 rxr->rx_pg_desc_ring[j] = NULL;
731 vfree(rxr->rx_pg_ring);
732 rxr->rx_pg_ring = NULL;
737 bnx2_alloc_tx_mem(struct bnx2 *bp)
741 for (i = 0; i < bp->num_tx_rings; i++) {
742 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
743 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
745 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
746 if (txr->tx_buf_ring == NULL)
750 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
751 &txr->tx_desc_mapping);
752 if (txr->tx_desc_ring == NULL)
759 bnx2_alloc_rx_mem(struct bnx2 *bp)
763 for (i = 0; i < bp->num_rx_rings; i++) {
764 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
765 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
769 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
770 if (rxr->rx_buf_ring == NULL)
773 memset(rxr->rx_buf_ring, 0,
774 SW_RXBD_RING_SIZE * bp->rx_max_ring);
776 for (j = 0; j < bp->rx_max_ring; j++) {
777 rxr->rx_desc_ring[j] =
778 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
779 &rxr->rx_desc_mapping[j]);
780 if (rxr->rx_desc_ring[j] == NULL)
785 if (bp->rx_pg_ring_size) {
786 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
788 if (rxr->rx_pg_ring == NULL)
791 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
795 for (j = 0; j < bp->rx_max_pg_ring; j++) {
796 rxr->rx_pg_desc_ring[j] =
797 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
798 &rxr->rx_pg_desc_mapping[j]);
799 if (rxr->rx_pg_desc_ring[j] == NULL)
808 bnx2_free_mem(struct bnx2 *bp)
811 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
813 bnx2_free_tx_mem(bp);
814 bnx2_free_rx_mem(bp);
816 for (i = 0; i < bp->ctx_pages; i++) {
817 if (bp->ctx_blk[i]) {
818 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
820 bp->ctx_blk_mapping[i]);
821 bp->ctx_blk[i] = NULL;
824 if (bnapi->status_blk.msi) {
825 pci_free_consistent(bp->pdev, bp->status_stats_size,
826 bnapi->status_blk.msi,
827 bp->status_blk_mapping);
828 bnapi->status_blk.msi = NULL;
829 bp->stats_blk = NULL;
834 bnx2_alloc_mem(struct bnx2 *bp)
836 int i, status_blk_size, err;
837 struct bnx2_napi *bnapi;
840 /* Combine status and statistics blocks into one allocation. */
841 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
842 if (bp->flags & BNX2_FLAG_MSIX_CAP)
843 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
844 BNX2_SBLK_MSIX_ALIGN_SIZE);
845 bp->status_stats_size = status_blk_size +
846 sizeof(struct statistics_block);
848 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
849 &bp->status_blk_mapping);
850 if (status_blk == NULL)
853 memset(status_blk, 0, bp->status_stats_size);
855 bnapi = &bp->bnx2_napi[0];
856 bnapi->status_blk.msi = status_blk;
857 bnapi->hw_tx_cons_ptr =
858 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
859 bnapi->hw_rx_cons_ptr =
860 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
861 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
862 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
863 struct status_block_msix *sblk;
865 bnapi = &bp->bnx2_napi[i];
867 sblk = (void *) (status_blk +
868 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
869 bnapi->status_blk.msix = sblk;
870 bnapi->hw_tx_cons_ptr =
871 &sblk->status_tx_quick_consumer_index;
872 bnapi->hw_rx_cons_ptr =
873 &sblk->status_rx_quick_consumer_index;
874 bnapi->int_num = i << 24;
878 bp->stats_blk = status_blk + status_blk_size;
880 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
882 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
883 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
884 if (bp->ctx_pages == 0)
886 for (i = 0; i < bp->ctx_pages; i++) {
887 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
889 &bp->ctx_blk_mapping[i]);
890 if (bp->ctx_blk[i] == NULL)
895 err = bnx2_alloc_rx_mem(bp);
899 err = bnx2_alloc_tx_mem(bp);
911 bnx2_report_fw_link(struct bnx2 *bp)
913 u32 fw_link_status = 0;
915 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
921 switch (bp->line_speed) {
923 if (bp->duplex == DUPLEX_HALF)
924 fw_link_status = BNX2_LINK_STATUS_10HALF;
926 fw_link_status = BNX2_LINK_STATUS_10FULL;
929 if (bp->duplex == DUPLEX_HALF)
930 fw_link_status = BNX2_LINK_STATUS_100HALF;
932 fw_link_status = BNX2_LINK_STATUS_100FULL;
935 if (bp->duplex == DUPLEX_HALF)
936 fw_link_status = BNX2_LINK_STATUS_1000HALF;
938 fw_link_status = BNX2_LINK_STATUS_1000FULL;
941 if (bp->duplex == DUPLEX_HALF)
942 fw_link_status = BNX2_LINK_STATUS_2500HALF;
944 fw_link_status = BNX2_LINK_STATUS_2500FULL;
948 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
951 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
953 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
954 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
956 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
957 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
958 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
960 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
964 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
966 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
970 bnx2_xceiver_str(struct bnx2 *bp)
972 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
973 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
978 bnx2_report_link(struct bnx2 *bp)
981 netif_carrier_on(bp->dev);
982 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
983 bnx2_xceiver_str(bp),
985 bp->duplex == DUPLEX_FULL ? "full" : "half");
988 if (bp->flow_ctrl & FLOW_CTRL_RX) {
989 pr_cont(", receive ");
990 if (bp->flow_ctrl & FLOW_CTRL_TX)
991 pr_cont("& transmit ");
994 pr_cont(", transmit ");
996 pr_cont("flow control ON");
1000 netif_carrier_off(bp->dev);
1001 netdev_err(bp->dev, "NIC %s Link is Down\n",
1002 bnx2_xceiver_str(bp));
1005 bnx2_report_fw_link(bp);
1009 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1011 u32 local_adv, remote_adv;
1014 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1015 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1017 if (bp->duplex == DUPLEX_FULL) {
1018 bp->flow_ctrl = bp->req_flow_ctrl;
1023 if (bp->duplex != DUPLEX_FULL) {
1027 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1028 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1031 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1032 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1033 bp->flow_ctrl |= FLOW_CTRL_TX;
1034 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1035 bp->flow_ctrl |= FLOW_CTRL_RX;
1039 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1040 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1042 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1043 u32 new_local_adv = 0;
1044 u32 new_remote_adv = 0;
1046 if (local_adv & ADVERTISE_1000XPAUSE)
1047 new_local_adv |= ADVERTISE_PAUSE_CAP;
1048 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1049 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1050 if (remote_adv & ADVERTISE_1000XPAUSE)
1051 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1052 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1053 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1055 local_adv = new_local_adv;
1056 remote_adv = new_remote_adv;
1059 /* See Table 28B-3 of 802.3ab-1999 spec. */
1060 if (local_adv & ADVERTISE_PAUSE_CAP) {
1061 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1062 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1063 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1065 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1066 bp->flow_ctrl = FLOW_CTRL_RX;
1070 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1071 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1075 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1076 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1077 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1079 bp->flow_ctrl = FLOW_CTRL_TX;
1085 bnx2_5709s_linkup(struct bnx2 *bp)
1091 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1092 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1093 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1095 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1096 bp->line_speed = bp->req_line_speed;
1097 bp->duplex = bp->req_duplex;
1100 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1102 case MII_BNX2_GP_TOP_AN_SPEED_10:
1103 bp->line_speed = SPEED_10;
1105 case MII_BNX2_GP_TOP_AN_SPEED_100:
1106 bp->line_speed = SPEED_100;
1108 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1109 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1110 bp->line_speed = SPEED_1000;
1112 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1113 bp->line_speed = SPEED_2500;
1116 if (val & MII_BNX2_GP_TOP_AN_FD)
1117 bp->duplex = DUPLEX_FULL;
1119 bp->duplex = DUPLEX_HALF;
1124 bnx2_5708s_linkup(struct bnx2 *bp)
1129 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1130 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1131 case BCM5708S_1000X_STAT1_SPEED_10:
1132 bp->line_speed = SPEED_10;
1134 case BCM5708S_1000X_STAT1_SPEED_100:
1135 bp->line_speed = SPEED_100;
1137 case BCM5708S_1000X_STAT1_SPEED_1G:
1138 bp->line_speed = SPEED_1000;
1140 case BCM5708S_1000X_STAT1_SPEED_2G5:
1141 bp->line_speed = SPEED_2500;
1144 if (val & BCM5708S_1000X_STAT1_FD)
1145 bp->duplex = DUPLEX_FULL;
1147 bp->duplex = DUPLEX_HALF;
1153 bnx2_5706s_linkup(struct bnx2 *bp)
1155 u32 bmcr, local_adv, remote_adv, common;
1158 bp->line_speed = SPEED_1000;
1160 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1161 if (bmcr & BMCR_FULLDPLX) {
1162 bp->duplex = DUPLEX_FULL;
1165 bp->duplex = DUPLEX_HALF;
1168 if (!(bmcr & BMCR_ANENABLE)) {
1172 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1173 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1175 common = local_adv & remote_adv;
1176 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1178 if (common & ADVERTISE_1000XFULL) {
1179 bp->duplex = DUPLEX_FULL;
1182 bp->duplex = DUPLEX_HALF;
1190 bnx2_copper_linkup(struct bnx2 *bp)
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195 if (bmcr & BMCR_ANENABLE) {
1196 u32 local_adv, remote_adv, common;
1198 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1199 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1201 common = local_adv & (remote_adv >> 2);
1202 if (common & ADVERTISE_1000FULL) {
1203 bp->line_speed = SPEED_1000;
1204 bp->duplex = DUPLEX_FULL;
1206 else if (common & ADVERTISE_1000HALF) {
1207 bp->line_speed = SPEED_1000;
1208 bp->duplex = DUPLEX_HALF;
1211 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1212 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1214 common = local_adv & remote_adv;
1215 if (common & ADVERTISE_100FULL) {
1216 bp->line_speed = SPEED_100;
1217 bp->duplex = DUPLEX_FULL;
1219 else if (common & ADVERTISE_100HALF) {
1220 bp->line_speed = SPEED_100;
1221 bp->duplex = DUPLEX_HALF;
1223 else if (common & ADVERTISE_10FULL) {
1224 bp->line_speed = SPEED_10;
1225 bp->duplex = DUPLEX_FULL;
1227 else if (common & ADVERTISE_10HALF) {
1228 bp->line_speed = SPEED_10;
1229 bp->duplex = DUPLEX_HALF;
1238 if (bmcr & BMCR_SPEED100) {
1239 bp->line_speed = SPEED_100;
1242 bp->line_speed = SPEED_10;
1244 if (bmcr & BMCR_FULLDPLX) {
1245 bp->duplex = DUPLEX_FULL;
1248 bp->duplex = DUPLEX_HALF;
1256 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1258 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1260 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1261 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1264 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1265 u32 lo_water, hi_water;
1267 if (bp->flow_ctrl & FLOW_CTRL_TX)
1268 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1270 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1271 if (lo_water >= bp->rx_ring_size)
1274 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
1276 if (hi_water <= lo_water)
1279 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1280 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1284 else if (hi_water == 0)
1286 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1288 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1292 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1297 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1300 bnx2_init_rx_context(bp, cid);
1305 bnx2_set_mac_link(struct bnx2 *bp)
1309 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1310 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1311 (bp->duplex == DUPLEX_HALF)) {
1312 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1315 /* Configure the EMAC mode register. */
1316 val = REG_RD(bp, BNX2_EMAC_MODE);
1318 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1319 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1320 BNX2_EMAC_MODE_25G_MODE);
1323 switch (bp->line_speed) {
1325 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1326 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1331 val |= BNX2_EMAC_MODE_PORT_MII;
1334 val |= BNX2_EMAC_MODE_25G_MODE;
1337 val |= BNX2_EMAC_MODE_PORT_GMII;
1342 val |= BNX2_EMAC_MODE_PORT_GMII;
1345 /* Set the MAC to operate in the appropriate duplex mode. */
1346 if (bp->duplex == DUPLEX_HALF)
1347 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1348 REG_WR(bp, BNX2_EMAC_MODE, val);
1350 /* Enable/disable rx PAUSE. */
1351 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1353 if (bp->flow_ctrl & FLOW_CTRL_RX)
1354 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1355 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1357 /* Enable/disable tx PAUSE. */
1358 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1359 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1361 if (bp->flow_ctrl & FLOW_CTRL_TX)
1362 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1363 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1365 /* Acknowledge the interrupt. */
1366 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1368 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1369 bnx2_init_all_rx_contexts(bp);
1373 bnx2_enable_bmsr1(struct bnx2 *bp)
1375 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1376 (CHIP_NUM(bp) == CHIP_NUM_5709))
1377 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1378 MII_BNX2_BLK_ADDR_GP_STATUS);
1382 bnx2_disable_bmsr1(struct bnx2 *bp)
1384 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1385 (CHIP_NUM(bp) == CHIP_NUM_5709))
1386 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1387 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1391 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1396 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1399 if (bp->autoneg & AUTONEG_SPEED)
1400 bp->advertising |= ADVERTISED_2500baseX_Full;
1402 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1403 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1405 bnx2_read_phy(bp, bp->mii_up1, &up1);
1406 if (!(up1 & BCM5708S_UP1_2G5)) {
1407 up1 |= BCM5708S_UP1_2G5;
1408 bnx2_write_phy(bp, bp->mii_up1, up1);
1412 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1413 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1414 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1420 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1425 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1428 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1429 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1431 bnx2_read_phy(bp, bp->mii_up1, &up1);
1432 if (up1 & BCM5708S_UP1_2G5) {
1433 up1 &= ~BCM5708S_UP1_2G5;
1434 bnx2_write_phy(bp, bp->mii_up1, up1);
1438 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1439 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1440 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1446 bnx2_enable_forced_2g5(struct bnx2 *bp)
1450 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1453 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1456 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1457 MII_BNX2_BLK_ADDR_SERDES_DIG);
1458 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1459 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1460 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1461 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1463 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1464 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1465 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1467 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1468 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1469 bmcr |= BCM5708S_BMCR_FORCE_2500;
1474 if (bp->autoneg & AUTONEG_SPEED) {
1475 bmcr &= ~BMCR_ANENABLE;
1476 if (bp->req_duplex == DUPLEX_FULL)
1477 bmcr |= BMCR_FULLDPLX;
1479 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1483 bnx2_disable_forced_2g5(struct bnx2 *bp)
1487 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1490 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1493 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1494 MII_BNX2_BLK_ADDR_SERDES_DIG);
1495 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1496 val &= ~MII_BNX2_SD_MISC1_FORCE;
1497 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1499 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1500 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1501 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1503 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1504 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1505 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1510 if (bp->autoneg & AUTONEG_SPEED)
1511 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1512 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1516 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1520 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1521 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1525 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1529 bnx2_set_link(struct bnx2 *bp)
1534 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1539 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1542 link_up = bp->link_up;
1544 bnx2_enable_bmsr1(bp);
1545 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1546 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547 bnx2_disable_bmsr1(bp);
1549 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1550 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1553 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1554 bnx2_5706s_force_link_dn(bp, 0);
1555 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1557 val = REG_RD(bp, BNX2_EMAC_STATUS);
1559 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1560 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1561 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1563 if ((val & BNX2_EMAC_STATUS_LINK) &&
1564 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1565 bmsr |= BMSR_LSTATUS;
1567 bmsr &= ~BMSR_LSTATUS;
1570 if (bmsr & BMSR_LSTATUS) {
1573 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1574 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1575 bnx2_5706s_linkup(bp);
1576 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1577 bnx2_5708s_linkup(bp);
1578 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1579 bnx2_5709s_linkup(bp);
1582 bnx2_copper_linkup(bp);
1584 bnx2_resolve_flow_ctrl(bp);
1587 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1588 (bp->autoneg & AUTONEG_SPEED))
1589 bnx2_disable_forced_2g5(bp);
1591 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1594 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1595 bmcr |= BMCR_ANENABLE;
1596 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1598 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1603 if (bp->link_up != link_up) {
1604 bnx2_report_link(bp);
1607 bnx2_set_mac_link(bp);
1613 bnx2_reset_phy(struct bnx2 *bp)
1618 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1620 #define PHY_RESET_MAX_WAIT 100
1621 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1624 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1625 if (!(reg & BMCR_RESET)) {
1630 if (i == PHY_RESET_MAX_WAIT) {
1637 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1641 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1642 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1644 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1645 adv = ADVERTISE_1000XPAUSE;
1648 adv = ADVERTISE_PAUSE_CAP;
1651 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1652 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1653 adv = ADVERTISE_1000XPSE_ASYM;
1656 adv = ADVERTISE_PAUSE_ASYM;
1659 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1660 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1661 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1664 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1670 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1673 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1674 __releases(&bp->phy_lock)
1675 __acquires(&bp->phy_lock)
1677 u32 speed_arg = 0, pause_adv;
1679 pause_adv = bnx2_phy_get_pause_adv(bp);
1681 if (bp->autoneg & AUTONEG_SPEED) {
1682 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1683 if (bp->advertising & ADVERTISED_10baseT_Half)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1685 if (bp->advertising & ADVERTISED_10baseT_Full)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1687 if (bp->advertising & ADVERTISED_100baseT_Half)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1689 if (bp->advertising & ADVERTISED_100baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691 if (bp->advertising & ADVERTISED_1000baseT_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1693 if (bp->advertising & ADVERTISED_2500baseX_Full)
1694 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1696 if (bp->req_line_speed == SPEED_2500)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1698 else if (bp->req_line_speed == SPEED_1000)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1700 else if (bp->req_line_speed == SPEED_100) {
1701 if (bp->req_duplex == DUPLEX_FULL)
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1705 } else if (bp->req_line_speed == SPEED_10) {
1706 if (bp->req_duplex == DUPLEX_FULL)
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1709 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1713 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1715 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1716 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1718 if (port == PORT_TP)
1719 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1720 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1722 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1724 spin_unlock_bh(&bp->phy_lock);
1725 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1726 spin_lock_bh(&bp->phy_lock);
1732 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1733 __releases(&bp->phy_lock)
1734 __acquires(&bp->phy_lock)
1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1740 return (bnx2_setup_remote_phy(bp, port));
1742 if (!(bp->autoneg & AUTONEG_SPEED)) {
1744 int force_link_down = 0;
1746 if (bp->req_line_speed == SPEED_2500) {
1747 if (!bnx2_test_and_enable_2g5(bp))
1748 force_link_down = 1;
1749 } else if (bp->req_line_speed == SPEED_1000) {
1750 if (bnx2_test_and_disable_2g5(bp))
1751 force_link_down = 1;
1753 bnx2_read_phy(bp, bp->mii_adv, &adv);
1754 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1756 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1757 new_bmcr = bmcr & ~BMCR_ANENABLE;
1758 new_bmcr |= BMCR_SPEED1000;
1760 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1761 if (bp->req_line_speed == SPEED_2500)
1762 bnx2_enable_forced_2g5(bp);
1763 else if (bp->req_line_speed == SPEED_1000) {
1764 bnx2_disable_forced_2g5(bp);
1765 new_bmcr &= ~0x2000;
1768 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1769 if (bp->req_line_speed == SPEED_2500)
1770 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1772 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1775 if (bp->req_duplex == DUPLEX_FULL) {
1776 adv |= ADVERTISE_1000XFULL;
1777 new_bmcr |= BMCR_FULLDPLX;
1780 adv |= ADVERTISE_1000XHALF;
1781 new_bmcr &= ~BMCR_FULLDPLX;
1783 if ((new_bmcr != bmcr) || (force_link_down)) {
1784 /* Force a link down visible on the other side */
1786 bnx2_write_phy(bp, bp->mii_adv, adv &
1787 ~(ADVERTISE_1000XFULL |
1788 ADVERTISE_1000XHALF));
1789 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1790 BMCR_ANRESTART | BMCR_ANENABLE);
1793 netif_carrier_off(bp->dev);
1794 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1795 bnx2_report_link(bp);
1797 bnx2_write_phy(bp, bp->mii_adv, adv);
1798 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1800 bnx2_resolve_flow_ctrl(bp);
1801 bnx2_set_mac_link(bp);
1806 bnx2_test_and_enable_2g5(bp);
1808 if (bp->advertising & ADVERTISED_1000baseT_Full)
1809 new_adv |= ADVERTISE_1000XFULL;
1811 new_adv |= bnx2_phy_get_pause_adv(bp);
1813 bnx2_read_phy(bp, bp->mii_adv, &adv);
1814 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1816 bp->serdes_an_pending = 0;
1817 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1818 /* Force a link down visible on the other side */
1820 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1821 spin_unlock_bh(&bp->phy_lock);
1823 spin_lock_bh(&bp->phy_lock);
1826 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1827 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1829 /* Speed up link-up time when the link partner
1830 * does not autonegotiate which is very common
1831 * in blade servers. Some blade servers use
1832 * IPMI for kerboard input and it's important
1833 * to minimize link disruptions. Autoneg. involves
1834 * exchanging base pages plus 3 next pages and
1835 * normally completes in about 120 msec.
1837 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1838 bp->serdes_an_pending = 1;
1839 mod_timer(&bp->timer, jiffies + bp->current_interval);
1841 bnx2_resolve_flow_ctrl(bp);
1842 bnx2_set_mac_link(bp);
1848 #define ETHTOOL_ALL_FIBRE_SPEED \
1849 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1850 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1851 (ADVERTISED_1000baseT_Full)
1853 #define ETHTOOL_ALL_COPPER_SPEED \
1854 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1855 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1856 ADVERTISED_1000baseT_Full)
1858 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1859 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1861 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1864 bnx2_set_default_remote_link(struct bnx2 *bp)
1868 if (bp->phy_port == PORT_TP)
1869 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1871 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1873 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1874 bp->req_line_speed = 0;
1875 bp->autoneg |= AUTONEG_SPEED;
1876 bp->advertising = ADVERTISED_Autoneg;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1878 bp->advertising |= ADVERTISED_10baseT_Half;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1880 bp->advertising |= ADVERTISED_10baseT_Full;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1882 bp->advertising |= ADVERTISED_100baseT_Half;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1884 bp->advertising |= ADVERTISED_100baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1886 bp->advertising |= ADVERTISED_1000baseT_Full;
1887 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1888 bp->advertising |= ADVERTISED_2500baseX_Full;
1891 bp->advertising = 0;
1892 bp->req_duplex = DUPLEX_FULL;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1894 bp->req_line_speed = SPEED_10;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1896 bp->req_duplex = DUPLEX_HALF;
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1899 bp->req_line_speed = SPEED_100;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->req_duplex = DUPLEX_HALF;
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1904 bp->req_line_speed = SPEED_1000;
1905 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1906 bp->req_line_speed = SPEED_2500;
1911 bnx2_set_default_link(struct bnx2 *bp)
1913 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1914 bnx2_set_default_remote_link(bp);
1918 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1919 bp->req_line_speed = 0;
1920 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1923 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1925 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1926 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1927 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1929 bp->req_line_speed = bp->line_speed = SPEED_1000;
1930 bp->req_duplex = DUPLEX_FULL;
1933 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1937 bnx2_send_heart_beat(struct bnx2 *bp)
1942 spin_lock(&bp->indirect_lock);
1943 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1944 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1945 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1946 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1947 spin_unlock(&bp->indirect_lock);
1951 bnx2_remote_phy_event(struct bnx2 *bp)
1954 u8 link_up = bp->link_up;
1957 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1959 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1960 bnx2_send_heart_beat(bp);
1962 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1964 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1970 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1971 bp->duplex = DUPLEX_FULL;
1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF;
1975 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10;
1978 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF;
1980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
1991 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500;
2000 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2001 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2002 if (bp->duplex == DUPLEX_FULL)
2003 bp->flow_ctrl = bp->req_flow_ctrl;
2005 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2006 bp->flow_ctrl |= FLOW_CTRL_TX;
2007 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_RX;
2011 old_port = bp->phy_port;
2012 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2013 bp->phy_port = PORT_FIBRE;
2015 bp->phy_port = PORT_TP;
2017 if (old_port != bp->phy_port)
2018 bnx2_set_default_link(bp);
2021 if (bp->link_up != link_up)
2022 bnx2_report_link(bp);
2024 bnx2_set_mac_link(bp);
2028 bnx2_set_remote_link(struct bnx2 *bp)
2032 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2034 case BNX2_FW_EVT_CODE_LINK_EVENT:
2035 bnx2_remote_phy_event(bp);
2037 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2039 bnx2_send_heart_beat(bp);
2046 bnx2_setup_copper_phy(struct bnx2 *bp)
2047 __releases(&bp->phy_lock)
2048 __acquires(&bp->phy_lock)
2053 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2055 if (bp->autoneg & AUTONEG_SPEED) {
2056 u32 adv_reg, adv1000_reg;
2057 u32 new_adv_reg = 0;
2058 u32 new_adv1000_reg = 0;
2060 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2061 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2062 ADVERTISE_PAUSE_ASYM);
2064 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2065 adv1000_reg &= PHY_ALL_1000_SPEED;
2067 if (bp->advertising & ADVERTISED_10baseT_Half)
2068 new_adv_reg |= ADVERTISE_10HALF;
2069 if (bp->advertising & ADVERTISED_10baseT_Full)
2070 new_adv_reg |= ADVERTISE_10FULL;
2071 if (bp->advertising & ADVERTISED_100baseT_Half)
2072 new_adv_reg |= ADVERTISE_100HALF;
2073 if (bp->advertising & ADVERTISED_100baseT_Full)
2074 new_adv_reg |= ADVERTISE_100FULL;
2075 if (bp->advertising & ADVERTISED_1000baseT_Full)
2076 new_adv1000_reg |= ADVERTISE_1000FULL;
2078 new_adv_reg |= ADVERTISE_CSMA;
2080 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2082 if ((adv1000_reg != new_adv1000_reg) ||
2083 (adv_reg != new_adv_reg) ||
2084 ((bmcr & BMCR_ANENABLE) == 0)) {
2086 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2087 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2088 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2091 else if (bp->link_up) {
2092 /* Flow ctrl may have changed from auto to forced */
2093 /* or vice-versa. */
2095 bnx2_resolve_flow_ctrl(bp);
2096 bnx2_set_mac_link(bp);
2102 if (bp->req_line_speed == SPEED_100) {
2103 new_bmcr |= BMCR_SPEED100;
2105 if (bp->req_duplex == DUPLEX_FULL) {
2106 new_bmcr |= BMCR_FULLDPLX;
2108 if (new_bmcr != bmcr) {
2111 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2112 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2114 if (bmsr & BMSR_LSTATUS) {
2115 /* Force link down */
2116 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2117 spin_unlock_bh(&bp->phy_lock);
2119 spin_lock_bh(&bp->phy_lock);
2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2122 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2125 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2127 /* Normally, the new speed is setup after the link has
2128 * gone down and up again. In some cases, link will not go
2129 * down so we need to set up the new speed here.
2131 if (bmsr & BMSR_LSTATUS) {
2132 bp->line_speed = bp->req_line_speed;
2133 bp->duplex = bp->req_duplex;
2134 bnx2_resolve_flow_ctrl(bp);
2135 bnx2_set_mac_link(bp);
2138 bnx2_resolve_flow_ctrl(bp);
2139 bnx2_set_mac_link(bp);
2145 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2146 __releases(&bp->phy_lock)
2147 __acquires(&bp->phy_lock)
2149 if (bp->loopback == MAC_LOOPBACK)
2152 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2153 return (bnx2_setup_serdes_phy(bp, port));
2156 return (bnx2_setup_copper_phy(bp));
2161 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2165 bp->mii_bmcr = MII_BMCR + 0x10;
2166 bp->mii_bmsr = MII_BMSR + 0x10;
2167 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2168 bp->mii_adv = MII_ADVERTISE + 0x10;
2169 bp->mii_lpa = MII_LPA + 0x10;
2170 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2172 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2173 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2175 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2179 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2181 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2182 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2183 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2184 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2187 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2188 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2189 val |= BCM5708S_UP1_2G5;
2191 val &= ~BCM5708S_UP1_2G5;
2192 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2195 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2196 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2197 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2199 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2201 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2202 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2203 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2211 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2218 bp->mii_up1 = BCM5708S_UP1;
2220 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2221 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2222 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2224 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2225 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2226 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2228 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2229 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2230 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2232 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2233 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2234 val |= BCM5708S_UP1_2G5;
2235 bnx2_write_phy(bp, BCM5708S_UP1, val);
2238 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2239 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2240 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2241 /* increase tx signal amplitude */
2242 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2243 BCM5708S_BLK_ADDR_TX_MISC);
2244 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2245 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2246 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2247 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2250 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2251 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2256 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2257 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2258 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2259 BCM5708S_BLK_ADDR_TX_MISC);
2260 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2262 BCM5708S_BLK_ADDR_DIG);
2269 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2274 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2276 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2277 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2279 if (bp->dev->mtu > 1500) {
2282 /* Set extended packet length bit */
2283 bnx2_write_phy(bp, 0x18, 0x7);
2284 bnx2_read_phy(bp, 0x18, &val);
2285 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2287 bnx2_write_phy(bp, 0x1c, 0x6c00);
2288 bnx2_read_phy(bp, 0x1c, &val);
2289 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2294 bnx2_write_phy(bp, 0x18, 0x7);
2295 bnx2_read_phy(bp, 0x18, &val);
2296 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2298 bnx2_write_phy(bp, 0x1c, 0x6c00);
2299 bnx2_read_phy(bp, 0x1c, &val);
2300 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2307 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2314 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2315 bnx2_write_phy(bp, 0x18, 0x0c00);
2316 bnx2_write_phy(bp, 0x17, 0x000a);
2317 bnx2_write_phy(bp, 0x15, 0x310b);
2318 bnx2_write_phy(bp, 0x17, 0x201f);
2319 bnx2_write_phy(bp, 0x15, 0x9506);
2320 bnx2_write_phy(bp, 0x17, 0x401f);
2321 bnx2_write_phy(bp, 0x15, 0x14e2);
2322 bnx2_write_phy(bp, 0x18, 0x0400);
2325 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2326 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2327 MII_BNX2_DSP_EXPAND_REG | 0x8);
2328 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2330 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2333 if (bp->dev->mtu > 1500) {
2334 /* Set extended packet length bit */
2335 bnx2_write_phy(bp, 0x18, 0x7);
2336 bnx2_read_phy(bp, 0x18, &val);
2337 bnx2_write_phy(bp, 0x18, val | 0x4000);
2339 bnx2_read_phy(bp, 0x10, &val);
2340 bnx2_write_phy(bp, 0x10, val | 0x1);
2343 bnx2_write_phy(bp, 0x18, 0x7);
2344 bnx2_read_phy(bp, 0x18, &val);
2345 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2347 bnx2_read_phy(bp, 0x10, &val);
2348 bnx2_write_phy(bp, 0x10, val & ~0x1);
2351 /* ethernet@wirespeed */
2352 bnx2_write_phy(bp, 0x18, 0x7007);
2353 bnx2_read_phy(bp, 0x18, &val);
2354 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2360 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2361 __releases(&bp->phy_lock)
2362 __acquires(&bp->phy_lock)
2367 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2368 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2370 bp->mii_bmcr = MII_BMCR;
2371 bp->mii_bmsr = MII_BMSR;
2372 bp->mii_bmsr1 = MII_BMSR;
2373 bp->mii_adv = MII_ADVERTISE;
2374 bp->mii_lpa = MII_LPA;
2376 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2378 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2381 bnx2_read_phy(bp, MII_PHYSID1, &val);
2382 bp->phy_id = val << 16;
2383 bnx2_read_phy(bp, MII_PHYSID2, &val);
2384 bp->phy_id |= val & 0xffff;
2386 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2387 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2388 rc = bnx2_init_5706s_phy(bp, reset_phy);
2389 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2390 rc = bnx2_init_5708s_phy(bp, reset_phy);
2391 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2392 rc = bnx2_init_5709s_phy(bp, reset_phy);
2395 rc = bnx2_init_copper_phy(bp, reset_phy);
2400 rc = bnx2_setup_phy(bp, bp->phy_port);
2406 bnx2_set_mac_loopback(struct bnx2 *bp)
2410 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2411 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2412 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2413 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2418 static int bnx2_test_link(struct bnx2 *);
2421 bnx2_set_phy_loopback(struct bnx2 *bp)
2426 spin_lock_bh(&bp->phy_lock);
2427 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2429 spin_unlock_bh(&bp->phy_lock);
2433 for (i = 0; i < 10; i++) {
2434 if (bnx2_test_link(bp) == 0)
2439 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2440 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2441 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2442 BNX2_EMAC_MODE_25G_MODE);
2444 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2445 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2451 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2457 msg_data |= bp->fw_wr_seq;
2459 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2464 /* wait for an acknowledgement. */
2465 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2468 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2470 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2473 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2476 /* If we timed out, inform the firmware that this is the case. */
2477 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2479 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2481 msg_data &= ~BNX2_DRV_MSG_CODE;
2482 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2484 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2489 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2496 bnx2_init_5709_context(struct bnx2 *bp)
2501 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2502 val |= (BCM_PAGE_BITS - 8) << 16;
2503 REG_WR(bp, BNX2_CTX_COMMAND, val);
2504 for (i = 0; i < 10; i++) {
2505 val = REG_RD(bp, BNX2_CTX_COMMAND);
2506 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2510 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2513 for (i = 0; i < bp->ctx_pages; i++) {
2517 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2521 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2522 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2523 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2524 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2525 (u64) bp->ctx_blk_mapping[i] >> 32);
2526 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2527 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2528 for (j = 0; j < 10; j++) {
2530 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2531 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2535 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2544 bnx2_init_context(struct bnx2 *bp)
2550 u32 vcid_addr, pcid_addr, offset;
2555 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2558 vcid_addr = GET_PCID_ADDR(vcid);
2560 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2565 pcid_addr = GET_PCID_ADDR(new_vcid);
2568 vcid_addr = GET_CID_ADDR(vcid);
2569 pcid_addr = vcid_addr;
2572 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2573 vcid_addr += (i << PHY_CTX_SHIFT);
2574 pcid_addr += (i << PHY_CTX_SHIFT);
2576 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2577 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2579 /* Zero out the context. */
2580 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2581 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2587 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2593 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2594 if (good_mbuf == NULL) {
2595 pr_err("Failed to allocate memory in %s\n", __func__);
2599 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2600 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2604 /* Allocate a bunch of mbufs and save the good ones in an array. */
2605 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2606 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2607 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2608 BNX2_RBUF_COMMAND_ALLOC_REQ);
2610 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2612 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2614 /* The addresses with Bit 9 set are bad memory blocks. */
2615 if (!(val & (1 << 9))) {
2616 good_mbuf[good_mbuf_cnt] = (u16) val;
2620 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2623 /* Free the good ones back to the mbuf pool thus discarding
2624 * all the bad ones. */
2625 while (good_mbuf_cnt) {
2628 val = good_mbuf[good_mbuf_cnt];
2629 val = (val << 9) | val | 1;
2631 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2638 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2642 val = (mac_addr[0] << 8) | mac_addr[1];
2644 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2646 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2647 (mac_addr[4] << 8) | mac_addr[5];
2649 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2653 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2656 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2657 struct rx_bd *rxbd =
2658 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2659 struct page *page = alloc_page(GFP_ATOMIC);
2663 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2664 PCI_DMA_FROMDEVICE);
2665 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2671 pci_unmap_addr_set(rx_pg, mapping, mapping);
2672 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2673 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2678 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2680 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2681 struct page *page = rx_pg->page;
2686 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2687 PCI_DMA_FROMDEVICE);
2694 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2696 struct sk_buff *skb;
2697 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2699 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2700 unsigned long align;
2702 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2707 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2708 skb_reserve(skb, BNX2_RX_ALIGN - align);
2710 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2711 PCI_DMA_FROMDEVICE);
2712 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2718 pci_unmap_addr_set(rx_buf, mapping, mapping);
2720 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2721 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2723 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2729 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2731 struct status_block *sblk = bnapi->status_blk.msi;
2732 u32 new_link_state, old_link_state;
2735 new_link_state = sblk->status_attn_bits & event;
2736 old_link_state = sblk->status_attn_bits_ack & event;
2737 if (new_link_state != old_link_state) {
2739 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2741 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2749 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2751 spin_lock(&bp->phy_lock);
2753 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2755 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2756 bnx2_set_remote_link(bp);
2758 spin_unlock(&bp->phy_lock);
2763 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2767 /* Tell compiler that status block fields can change. */
2769 cons = *bnapi->hw_tx_cons_ptr;
2771 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2777 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2779 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2780 u16 hw_cons, sw_cons, sw_ring_cons;
2781 int tx_pkt = 0, index;
2782 struct netdev_queue *txq;
2784 index = (bnapi - bp->bnx2_napi);
2785 txq = netdev_get_tx_queue(bp->dev, index);
2787 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2788 sw_cons = txr->tx_cons;
2790 while (sw_cons != hw_cons) {
2791 struct sw_tx_bd *tx_buf;
2792 struct sk_buff *skb;
2795 sw_ring_cons = TX_RING_IDX(sw_cons);
2797 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2800 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2801 prefetch(&skb->end);
2803 /* partial BD completions possible with TSO packets */
2804 if (tx_buf->is_gso) {
2805 u16 last_idx, last_ring_idx;
2807 last_idx = sw_cons + tx_buf->nr_frags + 1;
2808 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2809 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2812 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2817 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2818 skb_headlen(skb), PCI_DMA_TODEVICE);
2821 last = tx_buf->nr_frags;
2823 for (i = 0; i < last; i++) {
2824 sw_cons = NEXT_TX_BD(sw_cons);
2826 pci_unmap_page(bp->pdev,
2828 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2830 skb_shinfo(skb)->frags[i].size,
2834 sw_cons = NEXT_TX_BD(sw_cons);
2838 if (tx_pkt == budget)
2841 if (hw_cons == sw_cons)
2842 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2845 txr->hw_tx_cons = hw_cons;
2846 txr->tx_cons = sw_cons;
2848 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2849 * before checking for netif_tx_queue_stopped(). Without the
2850 * memory barrier, there is a small possibility that bnx2_start_xmit()
2851 * will miss it and cause the queue to be stopped forever.
2855 if (unlikely(netif_tx_queue_stopped(txq)) &&
2856 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2857 __netif_tx_lock(txq, smp_processor_id());
2858 if ((netif_tx_queue_stopped(txq)) &&
2859 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2860 netif_tx_wake_queue(txq);
2861 __netif_tx_unlock(txq);
2868 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2869 struct sk_buff *skb, int count)
2871 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2872 struct rx_bd *cons_bd, *prod_bd;
2875 u16 cons = rxr->rx_pg_cons;
2877 cons_rx_pg = &rxr->rx_pg_ring[cons];
2879 /* The caller was unable to allocate a new page to replace the
2880 * last one in the frags array, so we need to recycle that page
2881 * and then free the skb.
2885 struct skb_shared_info *shinfo;
2887 shinfo = skb_shinfo(skb);
2889 page = shinfo->frags[shinfo->nr_frags].page;
2890 shinfo->frags[shinfo->nr_frags].page = NULL;
2892 cons_rx_pg->page = page;
2896 hw_prod = rxr->rx_pg_prod;
2898 for (i = 0; i < count; i++) {
2899 prod = RX_PG_RING_IDX(hw_prod);
2901 prod_rx_pg = &rxr->rx_pg_ring[prod];
2902 cons_rx_pg = &rxr->rx_pg_ring[cons];
2903 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2904 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2907 prod_rx_pg->page = cons_rx_pg->page;
2908 cons_rx_pg->page = NULL;
2909 pci_unmap_addr_set(prod_rx_pg, mapping,
2910 pci_unmap_addr(cons_rx_pg, mapping));
2912 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2913 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2916 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2917 hw_prod = NEXT_RX_BD(hw_prod);
2919 rxr->rx_pg_prod = hw_prod;
2920 rxr->rx_pg_cons = cons;
2924 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2925 struct sk_buff *skb, u16 cons, u16 prod)
2927 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2928 struct rx_bd *cons_bd, *prod_bd;
2930 cons_rx_buf = &rxr->rx_buf_ring[cons];
2931 prod_rx_buf = &rxr->rx_buf_ring[prod];
2933 pci_dma_sync_single_for_device(bp->pdev,
2934 pci_unmap_addr(cons_rx_buf, mapping),
2935 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2937 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2939 prod_rx_buf->skb = skb;
2944 pci_unmap_addr_set(prod_rx_buf, mapping,
2945 pci_unmap_addr(cons_rx_buf, mapping));
2947 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2948 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2949 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2950 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2954 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2955 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2959 u16 prod = ring_idx & 0xffff;
2961 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2962 if (unlikely(err)) {
2963 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2965 unsigned int raw_len = len + 4;
2966 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2968 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2973 skb_reserve(skb, BNX2_RX_OFFSET);
2974 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2975 PCI_DMA_FROMDEVICE);
2981 unsigned int i, frag_len, frag_size, pages;
2982 struct sw_pg *rx_pg;
2983 u16 pg_cons = rxr->rx_pg_cons;
2984 u16 pg_prod = rxr->rx_pg_prod;
2986 frag_size = len + 4 - hdr_len;
2987 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2988 skb_put(skb, hdr_len);
2990 for (i = 0; i < pages; i++) {
2991 dma_addr_t mapping_old;
2993 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2994 if (unlikely(frag_len <= 4)) {
2995 unsigned int tail = 4 - frag_len;
2997 rxr->rx_pg_cons = pg_cons;
2998 rxr->rx_pg_prod = pg_prod;
2999 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3006 &skb_shinfo(skb)->frags[i - 1];
3008 skb->data_len -= tail;
3009 skb->truesize -= tail;
3013 rx_pg = &rxr->rx_pg_ring[pg_cons];
3015 /* Don't unmap yet. If we're unable to allocate a new
3016 * page, we need to recycle the page and the DMA addr.
3018 mapping_old = pci_unmap_addr(rx_pg, mapping);
3022 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3025 err = bnx2_alloc_rx_page(bp, rxr,
3026 RX_PG_RING_IDX(pg_prod));
3027 if (unlikely(err)) {
3028 rxr->rx_pg_cons = pg_cons;
3029 rxr->rx_pg_prod = pg_prod;
3030 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3035 pci_unmap_page(bp->pdev, mapping_old,
3036 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3038 frag_size -= frag_len;
3039 skb->data_len += frag_len;
3040 skb->truesize += frag_len;
3041 skb->len += frag_len;
3043 pg_prod = NEXT_RX_BD(pg_prod);
3044 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3046 rxr->rx_pg_prod = pg_prod;
3047 rxr->rx_pg_cons = pg_cons;
3053 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3057 /* Tell compiler that status block fields can change. */
3059 cons = *bnapi->hw_rx_cons_ptr;
3061 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3067 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3069 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3070 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3071 struct l2_fhdr *rx_hdr;
3072 int rx_pkt = 0, pg_ring_used = 0;
3074 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3075 sw_cons = rxr->rx_cons;
3076 sw_prod = rxr->rx_prod;
3078 /* Memory barrier necessary as speculative reads of the rx
3079 * buffer can be ahead of the index in the status block
3082 while (sw_cons != hw_cons) {
3083 unsigned int len, hdr_len;
3085 struct sw_bd *rx_buf;
3086 struct sk_buff *skb;
3087 dma_addr_t dma_addr;
3089 int hw_vlan __maybe_unused = 0;
3091 sw_ring_cons = RX_RING_IDX(sw_cons);
3092 sw_ring_prod = RX_RING_IDX(sw_prod);
3094 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3099 dma_addr = pci_unmap_addr(rx_buf, mapping);
3101 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3102 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3103 PCI_DMA_FROMDEVICE);
3105 rx_hdr = (struct l2_fhdr *) skb->data;
3106 len = rx_hdr->l2_fhdr_pkt_len;
3107 status = rx_hdr->l2_fhdr_status;
3110 if (status & L2_FHDR_STATUS_SPLIT) {
3111 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3113 } else if (len > bp->rx_jumbo_thresh) {
3114 hdr_len = bp->rx_jumbo_thresh;
3118 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3119 L2_FHDR_ERRORS_PHY_DECODE |
3120 L2_FHDR_ERRORS_ALIGNMENT |
3121 L2_FHDR_ERRORS_TOO_SHORT |
3122 L2_FHDR_ERRORS_GIANT_FRAME))) {
3124 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3129 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3131 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3138 if (len <= bp->rx_copy_thresh) {
3139 struct sk_buff *new_skb;
3141 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3142 if (new_skb == NULL) {
3143 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3149 skb_copy_from_linear_data_offset(skb,
3151 new_skb->data, len + 6);
3152 skb_reserve(new_skb, 6);
3153 skb_put(new_skb, len);
3155 bnx2_reuse_rx_skb(bp, rxr, skb,
3156 sw_ring_cons, sw_ring_prod);
3159 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3160 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3163 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3164 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3165 vtag = rx_hdr->l2_fhdr_vlan_tag;
3172 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3175 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3176 ve->h_vlan_proto = htons(ETH_P_8021Q);
3177 ve->h_vlan_TCI = htons(vtag);
3182 skb->protocol = eth_type_trans(skb, bp->dev);
3184 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3185 (ntohs(skb->protocol) != 0x8100)) {
3192 skb->ip_summed = CHECKSUM_NONE;
3194 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3195 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3197 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3198 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3199 skb->ip_summed = CHECKSUM_UNNECESSARY;
3202 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3206 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3209 netif_receive_skb(skb);
3214 sw_cons = NEXT_RX_BD(sw_cons);
3215 sw_prod = NEXT_RX_BD(sw_prod);
3217 if ((rx_pkt == budget))
3220 /* Refresh hw_cons to see if there is new work */
3221 if (sw_cons == hw_cons) {
3222 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3226 rxr->rx_cons = sw_cons;
3227 rxr->rx_prod = sw_prod;
3230 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3232 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3234 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3242 /* MSI ISR - The only difference between this and the INTx ISR
3243 * is that the MSI interrupt is always serviced.
3246 bnx2_msi(int irq, void *dev_instance)
3248 struct bnx2_napi *bnapi = dev_instance;
3249 struct bnx2 *bp = bnapi->bp;
3251 prefetch(bnapi->status_blk.msi);
3252 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3253 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3254 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3256 /* Return here if interrupt is disabled. */
3257 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3260 napi_schedule(&bnapi->napi);
3266 bnx2_msi_1shot(int irq, void *dev_instance)
3268 struct bnx2_napi *bnapi = dev_instance;
3269 struct bnx2 *bp = bnapi->bp;
3271 prefetch(bnapi->status_blk.msi);
3273 /* Return here if interrupt is disabled. */
3274 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3277 napi_schedule(&bnapi->napi);
3283 bnx2_interrupt(int irq, void *dev_instance)
3285 struct bnx2_napi *bnapi = dev_instance;
3286 struct bnx2 *bp = bnapi->bp;
3287 struct status_block *sblk = bnapi->status_blk.msi;
3289 /* When using INTx, it is possible for the interrupt to arrive
3290 * at the CPU before the status block posted prior to the
3291 * interrupt. Reading a register will flush the status block.
3292 * When using MSI, the MSI message will always complete after
3293 * the status block write.
3295 if ((sblk->status_idx == bnapi->last_status_idx) &&
3296 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3297 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3300 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3301 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3302 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3304 /* Read back to deassert IRQ immediately to avoid too many
3305 * spurious interrupts.
3307 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3309 /* Return here if interrupt is shared and is disabled. */
3310 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3313 if (napi_schedule_prep(&bnapi->napi)) {
3314 bnapi->last_status_idx = sblk->status_idx;
3315 __napi_schedule(&bnapi->napi);
3322 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3324 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3325 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3327 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3328 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3333 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3334 STATUS_ATTN_BITS_TIMER_ABORT)
3337 bnx2_has_work(struct bnx2_napi *bnapi)
3339 struct status_block *sblk = bnapi->status_blk.msi;
3341 if (bnx2_has_fast_work(bnapi))
3345 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3349 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3350 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3357 bnx2_chk_missed_msi(struct bnx2 *bp)
3359 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3362 if (bnx2_has_work(bnapi)) {
3363 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3364 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3367 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3368 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3369 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3370 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3371 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3375 bp->idle_chk_status_idx = bnapi->last_status_idx;
3379 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3381 struct cnic_ops *c_ops;
3383 if (!bnapi->cnic_present)
3387 c_ops = rcu_dereference(bp->cnic_ops);
3389 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3390 bnapi->status_blk.msi);
3395 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3397 struct status_block *sblk = bnapi->status_blk.msi;
3398 u32 status_attn_bits = sblk->status_attn_bits;
3399 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3401 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3402 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3404 bnx2_phy_int(bp, bnapi);
3406 /* This is needed to take care of transient status
3407 * during link changes.
3409 REG_WR(bp, BNX2_HC_COMMAND,
3410 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3411 REG_RD(bp, BNX2_HC_COMMAND);
3415 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3416 int work_done, int budget)
3418 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3419 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3421 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3422 bnx2_tx_int(bp, bnapi, 0);
3424 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3425 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3430 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3432 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3433 struct bnx2 *bp = bnapi->bp;
3435 struct status_block_msix *sblk = bnapi->status_blk.msix;
3438 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3439 if (unlikely(work_done >= budget))
3442 bnapi->last_status_idx = sblk->status_idx;
3443 /* status idx must be read before checking for more work. */
3445 if (likely(!bnx2_has_fast_work(bnapi))) {
3447 napi_complete(napi);
3448 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3449 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3450 bnapi->last_status_idx);
3457 static int bnx2_poll(struct napi_struct *napi, int budget)
3459 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3460 struct bnx2 *bp = bnapi->bp;
3462 struct status_block *sblk = bnapi->status_blk.msi;
3465 bnx2_poll_link(bp, bnapi);
3467 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3470 bnx2_poll_cnic(bp, bnapi);
3473 /* bnapi->last_status_idx is used below to tell the hw how
3474 * much work has been processed, so we must read it before
3475 * checking for more work.
3477 bnapi->last_status_idx = sblk->status_idx;
3479 if (unlikely(work_done >= budget))
3483 if (likely(!bnx2_has_work(bnapi))) {
3484 napi_complete(napi);
3485 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3486 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3487 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3488 bnapi->last_status_idx);
3491 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3492 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3493 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3494 bnapi->last_status_idx);
3496 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3497 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3498 bnapi->last_status_idx);
3506 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3507 * from set_multicast.
3510 bnx2_set_rx_mode(struct net_device *dev)
3512 struct bnx2 *bp = netdev_priv(dev);
3513 u32 rx_mode, sort_mode;
3514 struct netdev_hw_addr *ha;
3517 if (!netif_running(dev))
3520 spin_lock_bh(&bp->phy_lock);
3522 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3523 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3524 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3526 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3527 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3529 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3530 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3532 if (dev->flags & IFF_PROMISC) {
3533 /* Promiscuous mode. */
3534 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3535 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3536 BNX2_RPM_SORT_USER0_PROM_VLAN;
3538 else if (dev->flags & IFF_ALLMULTI) {
3539 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3540 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3543 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3546 /* Accept one or more multicast(s). */
3547 struct dev_mc_list *mclist;
3548 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3553 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3555 netdev_for_each_mc_addr(mclist, dev) {
3556 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3558 regidx = (bit & 0xe0) >> 5;
3560 mc_filter[regidx] |= (1 << bit);
3563 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3564 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3568 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3571 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3572 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3573 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3574 BNX2_RPM_SORT_USER0_PROM_VLAN;
3575 } else if (!(dev->flags & IFF_PROMISC)) {
3576 /* Add all entries into to the match filter list */
3578 netdev_for_each_uc_addr(ha, dev) {
3579 bnx2_set_mac_addr(bp, ha->addr,
3580 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3582 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3588 if (rx_mode != bp->rx_mode) {
3589 bp->rx_mode = rx_mode;
3590 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3593 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3594 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3595 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3597 spin_unlock_bh(&bp->phy_lock);
3600 static int __devinit
3601 check_fw_section(const struct firmware *fw,
3602 const struct bnx2_fw_file_section *section,
3603 u32 alignment, bool non_empty)
3605 u32 offset = be32_to_cpu(section->offset);
3606 u32 len = be32_to_cpu(section->len);
3608 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3610 if ((non_empty && len == 0) || len > fw->size - offset ||
3611 len & (alignment - 1))
3616 static int __devinit
3617 check_mips_fw_entry(const struct firmware *fw,
3618 const struct bnx2_mips_fw_file_entry *entry)
3620 if (check_fw_section(fw, &entry->text, 4, true) ||
3621 check_fw_section(fw, &entry->data, 4, false) ||
3622 check_fw_section(fw, &entry->rodata, 4, false))
3627 static int __devinit
3628 bnx2_request_firmware(struct bnx2 *bp)
3630 const char *mips_fw_file, *rv2p_fw_file;
3631 const struct bnx2_mips_fw_file *mips_fw;
3632 const struct bnx2_rv2p_fw_file *rv2p_fw;
3635 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3636 mips_fw_file = FW_MIPS_FILE_09;
3637 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3638 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3639 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3641 rv2p_fw_file = FW_RV2P_FILE_09;
3643 mips_fw_file = FW_MIPS_FILE_06;
3644 rv2p_fw_file = FW_RV2P_FILE_06;
3647 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3649 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3653 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3655 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3658 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3659 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3660 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3661 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3662 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3663 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3664 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3665 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3666 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3669 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3670 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3671 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3672 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3680 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3683 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3684 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3685 rv2p_code |= RV2P_BD_PAGE_SIZE;
3692 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3693 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3695 u32 rv2p_code_len, file_offset;
3700 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3701 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3703 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3705 if (rv2p_proc == RV2P_PROC1) {
3706 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3707 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3709 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3710 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3713 for (i = 0; i < rv2p_code_len; i += 8) {
3714 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3716 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3719 val = (i / 8) | cmd;
3720 REG_WR(bp, addr, val);
3723 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3724 for (i = 0; i < 8; i++) {
3727 loc = be32_to_cpu(fw_entry->fixup[i]);
3728 if (loc && ((loc * 4) < rv2p_code_len)) {
3729 code = be32_to_cpu(*(rv2p_code + loc - 1));
3730 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3731 code = be32_to_cpu(*(rv2p_code + loc));
3732 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3733 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3735 val = (loc / 2) | cmd;
3736 REG_WR(bp, addr, val);
3740 /* Reset the processor, un-stall is done later. */
3741 if (rv2p_proc == RV2P_PROC1) {
3742 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3745 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3752 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3753 const struct bnx2_mips_fw_file_entry *fw_entry)
3755 u32 addr, len, file_offset;
3761 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3762 val |= cpu_reg->mode_value_halt;
3763 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3764 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3766 /* Load the Text area. */
3767 addr = be32_to_cpu(fw_entry->text.addr);
3768 len = be32_to_cpu(fw_entry->text.len);
3769 file_offset = be32_to_cpu(fw_entry->text.offset);
3770 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3772 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3776 for (j = 0; j < (len / 4); j++, offset += 4)
3777 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3780 /* Load the Data area. */
3781 addr = be32_to_cpu(fw_entry->data.addr);
3782 len = be32_to_cpu(fw_entry->data.len);
3783 file_offset = be32_to_cpu(fw_entry->data.offset);
3784 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3786 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3790 for (j = 0; j < (len / 4); j++, offset += 4)
3791 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3794 /* Load the Read-Only area. */
3795 addr = be32_to_cpu(fw_entry->rodata.addr);
3796 len = be32_to_cpu(fw_entry->rodata.len);
3797 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3798 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3800 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3804 for (j = 0; j < (len / 4); j++, offset += 4)
3805 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3808 /* Clear the pre-fetch instruction. */
3809 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3811 val = be32_to_cpu(fw_entry->start_addr);
3812 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3814 /* Start the CPU. */
3815 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3816 val &= ~cpu_reg->mode_value_halt;
3817 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3818 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3824 bnx2_init_cpus(struct bnx2 *bp)
3826 const struct bnx2_mips_fw_file *mips_fw =
3827 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3828 const struct bnx2_rv2p_fw_file *rv2p_fw =
3829 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3832 /* Initialize the RV2P processor. */
3833 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3834 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3836 /* Initialize the RX Processor. */
3837 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3841 /* Initialize the TX Processor. */
3842 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3846 /* Initialize the TX Patch-up Processor. */
3847 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3851 /* Initialize the Completion Processor. */
3852 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3856 /* Initialize the Command Processor. */
3857 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3864 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3868 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3874 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3875 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3876 PCI_PM_CTRL_PME_STATUS);
3878 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3879 /* delay required during transition out of D3hot */
3882 val = REG_RD(bp, BNX2_EMAC_MODE);
3883 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3884 val &= ~BNX2_EMAC_MODE_MPKT;
3885 REG_WR(bp, BNX2_EMAC_MODE, val);
3887 val = REG_RD(bp, BNX2_RPM_CONFIG);
3888 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3889 REG_WR(bp, BNX2_RPM_CONFIG, val);
3900 autoneg = bp->autoneg;
3901 advertising = bp->advertising;
3903 if (bp->phy_port == PORT_TP) {
3904 bp->autoneg = AUTONEG_SPEED;
3905 bp->advertising = ADVERTISED_10baseT_Half |
3906 ADVERTISED_10baseT_Full |
3907 ADVERTISED_100baseT_Half |
3908 ADVERTISED_100baseT_Full |
3912 spin_lock_bh(&bp->phy_lock);
3913 bnx2_setup_phy(bp, bp->phy_port);
3914 spin_unlock_bh(&bp->phy_lock);
3916 bp->autoneg = autoneg;
3917 bp->advertising = advertising;
3919 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3921 val = REG_RD(bp, BNX2_EMAC_MODE);
3923 /* Enable port mode. */
3924 val &= ~BNX2_EMAC_MODE_PORT;
3925 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3926 BNX2_EMAC_MODE_ACPI_RCVD |
3927 BNX2_EMAC_MODE_MPKT;
3928 if (bp->phy_port == PORT_TP)
3929 val |= BNX2_EMAC_MODE_PORT_MII;
3931 val |= BNX2_EMAC_MODE_PORT_GMII;
3932 if (bp->line_speed == SPEED_2500)
3933 val |= BNX2_EMAC_MODE_25G_MODE;
3936 REG_WR(bp, BNX2_EMAC_MODE, val);
3938 /* receive all multicast */
3939 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3940 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3943 REG_WR(bp, BNX2_EMAC_RX_MODE,
3944 BNX2_EMAC_RX_MODE_SORT_MODE);
3946 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3947 BNX2_RPM_SORT_USER0_MC_EN;
3948 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3949 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3950 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3951 BNX2_RPM_SORT_USER0_ENA);
3953 /* Need to enable EMAC and RPM for WOL. */
3954 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3955 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3956 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3957 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3959 val = REG_RD(bp, BNX2_RPM_CONFIG);
3960 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3961 REG_WR(bp, BNX2_RPM_CONFIG, val);
3963 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3966 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3969 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3970 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3973 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3974 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3975 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3984 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3986 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3989 /* No more memory access after this point until
3990 * device is brought back to D0.
4002 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4007 /* Request access to the flash interface. */
4008 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4009 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4010 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4011 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4017 if (j >= NVRAM_TIMEOUT_COUNT)
4024 bnx2_release_nvram_lock(struct bnx2 *bp)
4029 /* Relinquish nvram interface. */
4030 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4032 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4033 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4034 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4040 if (j >= NVRAM_TIMEOUT_COUNT)
4048 bnx2_enable_nvram_write(struct bnx2 *bp)
4052 val = REG_RD(bp, BNX2_MISC_CFG);
4053 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4055 if (bp->flash_info->flags & BNX2_NV_WREN) {
4058 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4059 REG_WR(bp, BNX2_NVM_COMMAND,
4060 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4062 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4065 val = REG_RD(bp, BNX2_NVM_COMMAND);
4066 if (val & BNX2_NVM_COMMAND_DONE)
4070 if (j >= NVRAM_TIMEOUT_COUNT)
4077 bnx2_disable_nvram_write(struct bnx2 *bp)
4081 val = REG_RD(bp, BNX2_MISC_CFG);
4082 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4087 bnx2_enable_nvram_access(struct bnx2 *bp)
4091 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4092 /* Enable both bits, even on read. */
4093 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4094 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4098 bnx2_disable_nvram_access(struct bnx2 *bp)
4102 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4103 /* Disable both bits, even after read. */
4104 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4105 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4106 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4110 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4115 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4116 /* Buffered flash, no erase needed */
4119 /* Build an erase command */
4120 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4121 BNX2_NVM_COMMAND_DOIT;
4123 /* Need to clear DONE bit separately. */
4124 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4126 /* Address of the NVRAM to read from. */
4127 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4129 /* Issue an erase command. */
4130 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4132 /* Wait for completion. */
4133 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4138 val = REG_RD(bp, BNX2_NVM_COMMAND);
4139 if (val & BNX2_NVM_COMMAND_DONE)
4143 if (j >= NVRAM_TIMEOUT_COUNT)
4150 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4155 /* Build the command word. */
4156 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4158 /* Calculate an offset of a buffered flash, not needed for 5709. */
4159 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4160 offset = ((offset / bp->flash_info->page_size) <<
4161 bp->flash_info->page_bits) +
4162 (offset % bp->flash_info->page_size);
4165 /* Need to clear DONE bit separately. */
4166 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4168 /* Address of the NVRAM to read from. */
4169 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4171 /* Issue a read command. */
4172 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4174 /* Wait for completion. */
4175 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4180 val = REG_RD(bp, BNX2_NVM_COMMAND);
4181 if (val & BNX2_NVM_COMMAND_DONE) {
4182 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4183 memcpy(ret_val, &v, 4);
4187 if (j >= NVRAM_TIMEOUT_COUNT)
4195 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4201 /* Build the command word. */
4202 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4204 /* Calculate an offset of a buffered flash, not needed for 5709. */
4205 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4206 offset = ((offset / bp->flash_info->page_size) <<
4207 bp->flash_info->page_bits) +
4208 (offset % bp->flash_info->page_size);
4211 /* Need to clear DONE bit separately. */
4212 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4214 memcpy(&val32, val, 4);
4216 /* Write the data. */
4217 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4219 /* Address of the NVRAM to write to. */
4220 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4222 /* Issue the write command. */
4223 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4225 /* Wait for completion. */
4226 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4229 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4232 if (j >= NVRAM_TIMEOUT_COUNT)
4239 bnx2_init_nvram(struct bnx2 *bp)
4242 int j, entry_count, rc = 0;
4243 const struct flash_spec *flash;
4245 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4246 bp->flash_info = &flash_5709;
4247 goto get_flash_size;
4250 /* Determine the selected interface. */
4251 val = REG_RD(bp, BNX2_NVM_CFG1);
4253 entry_count = ARRAY_SIZE(flash_table);
4255 if (val & 0x40000000) {
4257 /* Flash interface has been reconfigured */
4258 for (j = 0, flash = &flash_table[0]; j < entry_count;
4260 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4261 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4262 bp->flash_info = flash;
4269 /* Not yet been reconfigured */
4271 if (val & (1 << 23))
4272 mask = FLASH_BACKUP_STRAP_MASK;
4274 mask = FLASH_STRAP_MASK;
4276 for (j = 0, flash = &flash_table[0]; j < entry_count;
4279 if ((val & mask) == (flash->strapping & mask)) {
4280 bp->flash_info = flash;
4282 /* Request access to the flash interface. */
4283 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4286 /* Enable access to flash interface */
4287 bnx2_enable_nvram_access(bp);
4289 /* Reconfigure the flash interface */
4290 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4291 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4292 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4293 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4295 /* Disable access to flash interface */
4296 bnx2_disable_nvram_access(bp);
4297 bnx2_release_nvram_lock(bp);
4302 } /* if (val & 0x40000000) */
4304 if (j == entry_count) {
4305 bp->flash_info = NULL;
4306 pr_alert("Unknown flash/EEPROM type\n");
4311 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4312 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4314 bp->flash_size = val;
4316 bp->flash_size = bp->flash_info->total_size;
4322 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4326 u32 cmd_flags, offset32, len32, extra;
4331 /* Request access to the flash interface. */
4332 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4335 /* Enable access to flash interface */
4336 bnx2_enable_nvram_access(bp);
4349 pre_len = 4 - (offset & 3);
4351 if (pre_len >= len32) {
4353 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4354 BNX2_NVM_COMMAND_LAST;
4357 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4360 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4365 memcpy(ret_buf, buf + (offset & 3), pre_len);
4372 extra = 4 - (len32 & 3);
4373 len32 = (len32 + 4) & ~3;
4380 cmd_flags = BNX2_NVM_COMMAND_LAST;
4382 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4383 BNX2_NVM_COMMAND_LAST;
4385 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4387 memcpy(ret_buf, buf, 4 - extra);
4389 else if (len32 > 0) {
4392 /* Read the first word. */
4396 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4398 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4400 /* Advance to the next dword. */
4405 while (len32 > 4 && rc == 0) {
4406 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4408 /* Advance to the next dword. */
4417 cmd_flags = BNX2_NVM_COMMAND_LAST;
4418 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4420 memcpy(ret_buf, buf, 4 - extra);
4423 /* Disable access to flash interface */
4424 bnx2_disable_nvram_access(bp);
4426 bnx2_release_nvram_lock(bp);
4432 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4435 u32 written, offset32, len32;
4436 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4438 int align_start, align_end;
4443 align_start = align_end = 0;
4445 if ((align_start = (offset32 & 3))) {
4447 len32 += align_start;
4450 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4455 align_end = 4 - (len32 & 3);
4457 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4461 if (align_start || align_end) {
4462 align_buf = kmalloc(len32, GFP_KERNEL);
4463 if (align_buf == NULL)
4466 memcpy(align_buf, start, 4);
4469 memcpy(align_buf + len32 - 4, end, 4);
4471 memcpy(align_buf + align_start, data_buf, buf_size);
4475 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4476 flash_buffer = kmalloc(264, GFP_KERNEL);
4477 if (flash_buffer == NULL) {
4479 goto nvram_write_end;
4484 while ((written < len32) && (rc == 0)) {
4485 u32 page_start, page_end, data_start, data_end;
4486 u32 addr, cmd_flags;
4489 /* Find the page_start addr */
4490 page_start = offset32 + written;
4491 page_start -= (page_start % bp->flash_info->page_size);
4492 /* Find the page_end addr */
4493 page_end = page_start + bp->flash_info->page_size;
4494 /* Find the data_start addr */
4495 data_start = (written == 0) ? offset32 : page_start;
4496 /* Find the data_end addr */
4497 data_end = (page_end > offset32 + len32) ?
4498 (offset32 + len32) : page_end;
4500 /* Request access to the flash interface. */
4501 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4502 goto nvram_write_end;
4504 /* Enable access to flash interface */
4505 bnx2_enable_nvram_access(bp);
4507 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4508 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4511 /* Read the whole page into the buffer
4512 * (non-buffer flash only) */
4513 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4514 if (j == (bp->flash_info->page_size - 4)) {
4515 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4517 rc = bnx2_nvram_read_dword(bp,
4523 goto nvram_write_end;
4529 /* Enable writes to flash interface (unlock write-protect) */
4530 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4531 goto nvram_write_end;
4533 /* Loop to write back the buffer data from page_start to
4536 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4537 /* Erase the page */
4538 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4539 goto nvram_write_end;
4541 /* Re-enable the write again for the actual write */
4542 bnx2_enable_nvram_write(bp);
4544 for (addr = page_start; addr < data_start;
4545 addr += 4, i += 4) {
4547 rc = bnx2_nvram_write_dword(bp, addr,
4548 &flash_buffer[i], cmd_flags);
4551 goto nvram_write_end;
4557 /* Loop to write the new data from data_start to data_end */
4558 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4559 if ((addr == page_end - 4) ||
4560 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4561 (addr == data_end - 4))) {
4563 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4565 rc = bnx2_nvram_write_dword(bp, addr, buf,
4569 goto nvram_write_end;
4575 /* Loop to write back the buffer data from data_end
4577 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4578 for (addr = data_end; addr < page_end;
4579 addr += 4, i += 4) {
4581 if (addr == page_end-4) {
4582 cmd_flags = BNX2_NVM_COMMAND_LAST;
4584 rc = bnx2_nvram_write_dword(bp, addr,
4585 &flash_buffer[i], cmd_flags);
4588 goto nvram_write_end;
4594 /* Disable writes to flash interface (lock write-protect) */
4595 bnx2_disable_nvram_write(bp);
4597 /* Disable access to flash interface */
4598 bnx2_disable_nvram_access(bp);
4599 bnx2_release_nvram_lock(bp);
4601 /* Increment written */
4602 written += data_end - data_start;
4606 kfree(flash_buffer);
4612 bnx2_init_fw_cap(struct bnx2 *bp)
4616 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4617 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4619 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4620 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4622 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4623 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4626 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4627 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4628 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4631 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4632 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4635 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4637 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4638 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4639 bp->phy_port = PORT_FIBRE;
4641 bp->phy_port = PORT_TP;
4643 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4644 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4647 if (netif_running(bp->dev) && sig)
4648 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4652 bnx2_setup_msix_tbl(struct bnx2 *bp)
4654 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4656 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4657 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4661 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4667 /* Wait for the current PCI transaction to complete before
4668 * issuing a reset. */
4669 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4670 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4671 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4672 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4673 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4674 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4677 /* Wait for the firmware to tell us it is ok to issue a reset. */
4678 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4680 /* Deposit a driver reset signature so the firmware knows that
4681 * this is a soft reset. */
4682 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4683 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4685 /* Do a dummy read to force the chip to complete all current transaction
4686 * before we issue a reset. */
4687 val = REG_RD(bp, BNX2_MISC_ID);
4689 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4690 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4691 REG_RD(bp, BNX2_MISC_COMMAND);
4694 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4695 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4697 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4700 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4701 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4702 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4705 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4707 /* Reading back any register after chip reset will hang the
4708 * bus on 5706 A0 and A1. The msleep below provides plenty
4709 * of margin for write posting.
4711 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4712 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4715 /* Reset takes approximate 30 usec */
4716 for (i = 0; i < 10; i++) {
4717 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4718 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4719 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4724 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4725 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4726 pr_err("Chip reset did not complete\n");
4731 /* Make sure byte swapping is properly configured. */
4732 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4733 if (val != 0x01020304) {
4734 pr_err("Chip not in correct endian mode\n");
4738 /* Wait for the firmware to finish its initialization. */
4739 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4743 spin_lock_bh(&bp->phy_lock);
4744 old_port = bp->phy_port;
4745 bnx2_init_fw_cap(bp);
4746 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4747 old_port != bp->phy_port)
4748 bnx2_set_default_remote_link(bp);
4749 spin_unlock_bh(&bp->phy_lock);
4751 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4752 /* Adjust the voltage regular to two steps lower. The default
4753 * of this register is 0x0000000e. */
4754 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4756 /* Remove bad rbuf memory from the free pool. */
4757 rc = bnx2_alloc_bad_rbuf(bp);
4760 if (bp->flags & BNX2_FLAG_USING_MSIX)
4761 bnx2_setup_msix_tbl(bp);
4767 bnx2_init_chip(struct bnx2 *bp)
4772 /* Make sure the interrupt is not active. */
4773 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4775 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4776 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4778 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4780 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4781 DMA_READ_CHANS << 12 |
4782 DMA_WRITE_CHANS << 16;
4784 val |= (0x2 << 20) | (1 << 11);
4786 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4789 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4790 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4791 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4793 REG_WR(bp, BNX2_DMA_CONFIG, val);
4795 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4796 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4797 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4798 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4801 if (bp->flags & BNX2_FLAG_PCIX) {
4804 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4806 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4807 val16 & ~PCI_X_CMD_ERO);
4810 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4811 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4812 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4813 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4815 /* Initialize context mapping and zero out the quick contexts. The
4816 * context block must have already been enabled. */
4817 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4818 rc = bnx2_init_5709_context(bp);
4822 bnx2_init_context(bp);
4824 if ((rc = bnx2_init_cpus(bp)) != 0)
4827 bnx2_init_nvram(bp);
4829 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4831 val = REG_RD(bp, BNX2_MQ_CONFIG);
4832 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4833 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4834 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4835 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4836 if (CHIP_REV(bp) == CHIP_REV_Ax)
4837 val |= BNX2_MQ_CONFIG_HALT_DIS;
4840 REG_WR(bp, BNX2_MQ_CONFIG, val);
4842 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4843 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4844 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4846 val = (BCM_PAGE_BITS - 8) << 24;
4847 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4849 /* Configure page size. */
4850 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4851 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4852 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4853 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4855 val = bp->mac_addr[0] +
4856 (bp->mac_addr[1] << 8) +
4857 (bp->mac_addr[2] << 16) +
4859 (bp->mac_addr[4] << 8) +
4860 (bp->mac_addr[5] << 16);
4861 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4863 /* Program the MTU. Also include 4 bytes for CRC32. */
4865 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4866 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4867 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4868 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4873 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4874 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4875 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4877 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4878 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4879 bp->bnx2_napi[i].last_status_idx = 0;
4881 bp->idle_chk_status_idx = 0xffff;
4883 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4885 /* Set up how to generate a link change interrupt. */
4886 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4888 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4889 (u64) bp->status_blk_mapping & 0xffffffff);
4890 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4892 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4893 (u64) bp->stats_blk_mapping & 0xffffffff);
4894 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4895 (u64) bp->stats_blk_mapping >> 32);
4897 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4898 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4900 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4901 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4903 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4904 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4906 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4908 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4910 REG_WR(bp, BNX2_HC_COM_TICKS,
4911 (bp->com_ticks_int << 16) | bp->com_ticks);
4913 REG_WR(bp, BNX2_HC_CMD_TICKS,
4914 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4916 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4917 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4919 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4920 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4922 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4923 val = BNX2_HC_CONFIG_COLLECT_STATS;
4925 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4926 BNX2_HC_CONFIG_COLLECT_STATS;
4929 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4930 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4931 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4933 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4936 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4937 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4939 REG_WR(bp, BNX2_HC_CONFIG, val);
4941 for (i = 1; i < bp->irq_nvecs; i++) {
4942 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4943 BNX2_HC_SB_CONFIG_1;
4946 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4947 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4948 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4950 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4951 (bp->tx_quick_cons_trip_int << 16) |
4952 bp->tx_quick_cons_trip);
4954 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4955 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4957 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4958 (bp->rx_quick_cons_trip_int << 16) |
4959 bp->rx_quick_cons_trip);
4961 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4962 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4965 /* Clear internal stats counters. */
4966 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4968 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4970 /* Initialize the receive filter. */
4971 bnx2_set_rx_mode(bp->dev);
4973 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4974 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4975 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4976 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4978 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4981 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4982 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4986 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4992 bnx2_clear_ring_states(struct bnx2 *bp)
4994 struct bnx2_napi *bnapi;
4995 struct bnx2_tx_ring_info *txr;
4996 struct bnx2_rx_ring_info *rxr;
4999 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5000 bnapi = &bp->bnx2_napi[i];
5001 txr = &bnapi->tx_ring;
5002 rxr = &bnapi->rx_ring;
5005 txr->hw_tx_cons = 0;
5006 rxr->rx_prod_bseq = 0;
5009 rxr->rx_pg_prod = 0;
5010 rxr->rx_pg_cons = 0;
5015 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5017 u32 val, offset0, offset1, offset2, offset3;
5018 u32 cid_addr = GET_CID_ADDR(cid);
5020 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5021 offset0 = BNX2_L2CTX_TYPE_XI;
5022 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5023 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5024 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5026 offset0 = BNX2_L2CTX_TYPE;
5027 offset1 = BNX2_L2CTX_CMD_TYPE;
5028 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5029 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5031 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5032 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5034 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5035 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5037 val = (u64) txr->tx_desc_mapping >> 32;
5038 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5040 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5041 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5045 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5049 struct bnx2_napi *bnapi;
5050 struct bnx2_tx_ring_info *txr;
5052 bnapi = &bp->bnx2_napi[ring_num];
5053 txr = &bnapi->tx_ring;
5058 cid = TX_TSS_CID + ring_num - 1;
5060 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5062 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5064 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5065 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5068 txr->tx_prod_bseq = 0;
5070 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5071 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5073 bnx2_init_tx_context(bp, cid, txr);
5077 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5083 for (i = 0; i < num_rings; i++) {
5086 rxbd = &rx_ring[i][0];
5087 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5088 rxbd->rx_bd_len = buf_size;
5089 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5091 if (i == (num_rings - 1))
5095 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5096 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5101 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5104 u16 prod, ring_prod;
5105 u32 cid, rx_cid_addr, val;
5106 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5107 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5112 cid = RX_RSS_CID + ring_num - 1;
5114 rx_cid_addr = GET_CID_ADDR(cid);
5116 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5117 bp->rx_buf_use_size, bp->rx_max_ring);
5119 bnx2_init_rx_context(bp, cid);
5121 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5122 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5123 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5126 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5127 if (bp->rx_pg_ring_size) {
5128 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5129 rxr->rx_pg_desc_mapping,
5130 PAGE_SIZE, bp->rx_max_pg_ring);
5131 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5132 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5133 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5134 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5136 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5137 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5139 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5140 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5142 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5143 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5146 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5147 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5149 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5150 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5152 ring_prod = prod = rxr->rx_pg_prod;
5153 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5154 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
5155 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5156 ring_num, i, bp->rx_pg_ring_size);
5159 prod = NEXT_RX_BD(prod);
5160 ring_prod = RX_PG_RING_IDX(prod);
5162 rxr->rx_pg_prod = prod;
5164 ring_prod = prod = rxr->rx_prod;
5165 for (i = 0; i < bp->rx_ring_size; i++) {
5166 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
5167 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5168 ring_num, i, bp->rx_ring_size);
5171 prod = NEXT_RX_BD(prod);
5172 ring_prod = RX_RING_IDX(prod);
5174 rxr->rx_prod = prod;
5176 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5177 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5178 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5180 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5181 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5183 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5187 bnx2_init_all_rings(struct bnx2 *bp)
5192 bnx2_clear_ring_states(bp);
5194 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5195 for (i = 0; i < bp->num_tx_rings; i++)
5196 bnx2_init_tx_ring(bp, i);
5198 if (bp->num_tx_rings > 1)
5199 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5202 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5203 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5205 for (i = 0; i < bp->num_rx_rings; i++)
5206 bnx2_init_rx_ring(bp, i);
5208 if (bp->num_rx_rings > 1) {
5210 u8 *tbl = (u8 *) &tbl_32;
5212 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5213 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5215 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5216 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5219 BNX2_RXP_SCRATCH_RSS_TBL + i,
5220 cpu_to_be32(tbl_32));
5223 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5224 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5226 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5231 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5233 u32 max, num_rings = 1;
5235 while (ring_size > MAX_RX_DESC_CNT) {
5236 ring_size -= MAX_RX_DESC_CNT;
5239 /* round to next power of 2 */
5241 while ((max & num_rings) == 0)
5244 if (num_rings != max)
5251 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5253 u32 rx_size, rx_space, jumbo_size;
5255 /* 8 for CRC and VLAN */
5256 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5258 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5259 sizeof(struct skb_shared_info);
5261 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5262 bp->rx_pg_ring_size = 0;
5263 bp->rx_max_pg_ring = 0;
5264 bp->rx_max_pg_ring_idx = 0;
5265 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5266 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5268 jumbo_size = size * pages;
5269 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5270 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5272 bp->rx_pg_ring_size = jumbo_size;
5273 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5275 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5276 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5277 bp->rx_copy_thresh = 0;
5280 bp->rx_buf_use_size = rx_size;
5282 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5283 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5284 bp->rx_ring_size = size;
5285 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5286 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5290 bnx2_free_tx_skbs(struct bnx2 *bp)
5294 for (i = 0; i < bp->num_tx_rings; i++) {
5295 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5296 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5299 if (txr->tx_buf_ring == NULL)
5302 for (j = 0; j < TX_DESC_CNT; ) {
5303 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5304 struct sk_buff *skb = tx_buf->skb;
5312 pci_unmap_single(bp->pdev,
5313 pci_unmap_addr(tx_buf, mapping),
5319 last = tx_buf->nr_frags;
5321 for (k = 0; k < last; k++, j++) {
5322 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5323 pci_unmap_page(bp->pdev,
5324 pci_unmap_addr(tx_buf, mapping),
5325 skb_shinfo(skb)->frags[k].size,
5334 bnx2_free_rx_skbs(struct bnx2 *bp)
5338 for (i = 0; i < bp->num_rx_rings; i++) {
5339 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5340 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5343 if (rxr->rx_buf_ring == NULL)
5346 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5347 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5348 struct sk_buff *skb = rx_buf->skb;
5353 pci_unmap_single(bp->pdev,
5354 pci_unmap_addr(rx_buf, mapping),
5355 bp->rx_buf_use_size,
5356 PCI_DMA_FROMDEVICE);
5362 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5363 bnx2_free_rx_page(bp, rxr, j);
5368 bnx2_free_skbs(struct bnx2 *bp)
5370 bnx2_free_tx_skbs(bp);
5371 bnx2_free_rx_skbs(bp);
5375 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5379 rc = bnx2_reset_chip(bp, reset_code);
5384 if ((rc = bnx2_init_chip(bp)) != 0)
5387 bnx2_init_all_rings(bp);
5392 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5396 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5399 spin_lock_bh(&bp->phy_lock);
5400 bnx2_init_phy(bp, reset_phy);
5402 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5403 bnx2_remote_phy_event(bp);
5404 spin_unlock_bh(&bp->phy_lock);
5409 bnx2_shutdown_chip(struct bnx2 *bp)
5413 if (bp->flags & BNX2_FLAG_NO_WOL)
5414 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5416 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5418 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5420 return bnx2_reset_chip(bp, reset_code);
5424 bnx2_test_registers(struct bnx2 *bp)
5428 static const struct {
5431 #define BNX2_FL_NOT_5709 1
5435 { 0x006c, 0, 0x00000000, 0x0000003f },
5436 { 0x0090, 0, 0xffffffff, 0x00000000 },
5437 { 0x0094, 0, 0x00000000, 0x00000000 },
5439 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5440 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5441 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5442 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5443 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5444 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5445 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5446 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5447 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5449 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5450 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5451 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5452 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5453 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5454 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5456 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5457 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5458 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5460 { 0x1000, 0, 0x00000000, 0x00000001 },
5461 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5463 { 0x1408, 0, 0x01c00800, 0x00000000 },
5464 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5465 { 0x14a8, 0, 0x00000000, 0x000001ff },
5466 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5467 { 0x14b0, 0, 0x00000002, 0x00000001 },
5468 { 0x14b8, 0, 0x00000000, 0x00000000 },
5469 { 0x14c0, 0, 0x00000000, 0x00000009 },
5470 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5471 { 0x14cc, 0, 0x00000000, 0x00000001 },
5472 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5474 { 0x1800, 0, 0x00000000, 0x00000001 },
5475 { 0x1804, 0, 0x00000000, 0x00000003 },
5477 { 0x2800, 0, 0x00000000, 0x00000001 },
5478 { 0x2804, 0, 0x00000000, 0x00003f01 },
5479 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5480 { 0x2810, 0, 0xffff0000, 0x00000000 },
5481 { 0x2814, 0, 0xffff0000, 0x00000000 },
5482 { 0x2818, 0, 0xffff0000, 0x00000000 },
5483 { 0x281c, 0, 0xffff0000, 0x00000000 },
5484 { 0x2834, 0, 0xffffffff, 0x00000000 },
5485 { 0x2840, 0, 0x00000000, 0xffffffff },
5486 { 0x2844, 0, 0x00000000, 0xffffffff },
5487 { 0x2848, 0, 0xffffffff, 0x00000000 },
5488 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5490 { 0x2c00, 0, 0x00000000, 0x00000011 },
5491 { 0x2c04, 0, 0x00000000, 0x00030007 },
5493 { 0x3c00, 0, 0x00000000, 0x00000001 },
5494 { 0x3c04, 0, 0x00000000, 0x00070000 },
5495 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5496 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5497 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5498 { 0x3c14, 0, 0x00000000, 0xffffffff },
5499 { 0x3c18, 0, 0x00000000, 0xffffffff },
5500 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5501 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5503 { 0x5004, 0, 0x00000000, 0x0000007f },
5504 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5506 { 0x5c00, 0, 0x00000000, 0x00000001 },
5507 { 0x5c04, 0, 0x00000000, 0x0003000f },
5508 { 0x5c08, 0, 0x00000003, 0x00000000 },
5509 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5510 { 0x5c10, 0, 0x00000000, 0xffffffff },
5511 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5512 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5513 { 0x5c88, 0, 0x00000000, 0x00077373 },
5514 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5516 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5517 { 0x680c, 0, 0xffffffff, 0x00000000 },
5518 { 0x6810, 0, 0xffffffff, 0x00000000 },
5519 { 0x6814, 0, 0xffffffff, 0x00000000 },
5520 { 0x6818, 0, 0xffffffff, 0x00000000 },
5521 { 0x681c, 0, 0xffffffff, 0x00000000 },
5522 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5523 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5524 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5525 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5526 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5527 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5528 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5529 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5530 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5531 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5532 { 0x684c, 0, 0xffffffff, 0x00000000 },
5533 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5534 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5535 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5536 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5537 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5538 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5540 { 0xffff, 0, 0x00000000, 0x00000000 },
5545 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5548 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5549 u32 offset, rw_mask, ro_mask, save_val, val;
5550 u16 flags = reg_tbl[i].flags;
5552 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5555 offset = (u32) reg_tbl[i].offset;
5556 rw_mask = reg_tbl[i].rw_mask;
5557 ro_mask = reg_tbl[i].ro_mask;
5559 save_val = readl(bp->regview + offset);
5561 writel(0, bp->regview + offset);
5563 val = readl(bp->regview + offset);
5564 if ((val & rw_mask) != 0) {
5568 if ((val & ro_mask) != (save_val & ro_mask)) {
5572 writel(0xffffffff, bp->regview + offset);
5574 val = readl(bp->regview + offset);
5575 if ((val & rw_mask) != rw_mask) {
5579 if ((val & ro_mask) != (save_val & ro_mask)) {
5583 writel(save_val, bp->regview + offset);
5587 writel(save_val, bp->regview + offset);
5595 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5597 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5598 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5601 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5604 for (offset = 0; offset < size; offset += 4) {
5606 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5608 if (bnx2_reg_rd_ind(bp, start + offset) !=
5618 bnx2_test_memory(struct bnx2 *bp)
5622 static struct mem_entry {
5625 } mem_tbl_5706[] = {
5626 { 0x60000, 0x4000 },
5627 { 0xa0000, 0x3000 },
5628 { 0xe0000, 0x4000 },
5629 { 0x120000, 0x4000 },
5630 { 0x1a0000, 0x4000 },
5631 { 0x160000, 0x4000 },
5635 { 0x60000, 0x4000 },
5636 { 0xa0000, 0x3000 },
5637 { 0xe0000, 0x4000 },
5638 { 0x120000, 0x4000 },
5639 { 0x1a0000, 0x4000 },
5642 struct mem_entry *mem_tbl;
5644 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5645 mem_tbl = mem_tbl_5709;
5647 mem_tbl = mem_tbl_5706;
5649 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5650 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5651 mem_tbl[i].len)) != 0) {
5659 #define BNX2_MAC_LOOPBACK 0
5660 #define BNX2_PHY_LOOPBACK 1
5663 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5665 unsigned int pkt_size, num_pkts, i;
5666 struct sk_buff *skb, *rx_skb;
5667 unsigned char *packet;
5668 u16 rx_start_idx, rx_idx;
5671 struct sw_bd *rx_buf;
5672 struct l2_fhdr *rx_hdr;
5674 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5675 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5676 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5680 txr = &tx_napi->tx_ring;
5681 rxr = &bnapi->rx_ring;
5682 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5683 bp->loopback = MAC_LOOPBACK;
5684 bnx2_set_mac_loopback(bp);
5686 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5687 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5690 bp->loopback = PHY_LOOPBACK;
5691 bnx2_set_phy_loopback(bp);
5696 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5697 skb = netdev_alloc_skb(bp->dev, pkt_size);
5700 packet = skb_put(skb, pkt_size);
5701 memcpy(packet, bp->dev->dev_addr, 6);
5702 memset(packet + 6, 0x0, 8);
5703 for (i = 14; i < pkt_size; i++)
5704 packet[i] = (unsigned char) (i & 0xff);
5706 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5708 if (pci_dma_mapping_error(bp->pdev, map)) {
5713 REG_WR(bp, BNX2_HC_COMMAND,
5714 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5716 REG_RD(bp, BNX2_HC_COMMAND);
5719 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5723 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5725 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5726 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5727 txbd->tx_bd_mss_nbytes = pkt_size;
5728 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5731 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5732 txr->tx_prod_bseq += pkt_size;
5734 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5735 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5739 REG_WR(bp, BNX2_HC_COMMAND,
5740 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5742 REG_RD(bp, BNX2_HC_COMMAND);
5746 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5749 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5750 goto loopback_test_done;
5752 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5753 if (rx_idx != rx_start_idx + num_pkts) {
5754 goto loopback_test_done;
5757 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5758 rx_skb = rx_buf->skb;
5760 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5761 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5763 pci_dma_sync_single_for_cpu(bp->pdev,
5764 pci_unmap_addr(rx_buf, mapping),
5765 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5767 if (rx_hdr->l2_fhdr_status &
5768 (L2_FHDR_ERRORS_BAD_CRC |
5769 L2_FHDR_ERRORS_PHY_DECODE |
5770 L2_FHDR_ERRORS_ALIGNMENT |
5771 L2_FHDR_ERRORS_TOO_SHORT |
5772 L2_FHDR_ERRORS_GIANT_FRAME)) {
5774 goto loopback_test_done;
5777 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5778 goto loopback_test_done;
5781 for (i = 14; i < pkt_size; i++) {
5782 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5783 goto loopback_test_done;
5794 #define BNX2_MAC_LOOPBACK_FAILED 1
5795 #define BNX2_PHY_LOOPBACK_FAILED 2
5796 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5797 BNX2_PHY_LOOPBACK_FAILED)
5800 bnx2_test_loopback(struct bnx2 *bp)
5804 if (!netif_running(bp->dev))
5805 return BNX2_LOOPBACK_FAILED;
5807 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5808 spin_lock_bh(&bp->phy_lock);
5809 bnx2_init_phy(bp, 1);
5810 spin_unlock_bh(&bp->phy_lock);
5811 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5812 rc |= BNX2_MAC_LOOPBACK_FAILED;
5813 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5814 rc |= BNX2_PHY_LOOPBACK_FAILED;
5818 #define NVRAM_SIZE 0x200
5819 #define CRC32_RESIDUAL 0xdebb20e3
5822 bnx2_test_nvram(struct bnx2 *bp)
5824 __be32 buf[NVRAM_SIZE / 4];
5825 u8 *data = (u8 *) buf;
5829 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5830 goto test_nvram_done;
5832 magic = be32_to_cpu(buf[0]);
5833 if (magic != 0x669955aa) {
5835 goto test_nvram_done;
5838 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5839 goto test_nvram_done;
5841 csum = ether_crc_le(0x100, data);
5842 if (csum != CRC32_RESIDUAL) {
5844 goto test_nvram_done;
5847 csum = ether_crc_le(0x100, data + 0x100);
5848 if (csum != CRC32_RESIDUAL) {
5857 bnx2_test_link(struct bnx2 *bp)
5861 if (!netif_running(bp->dev))
5864 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5869 spin_lock_bh(&bp->phy_lock);
5870 bnx2_enable_bmsr1(bp);
5871 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5872 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5873 bnx2_disable_bmsr1(bp);
5874 spin_unlock_bh(&bp->phy_lock);
5876 if (bmsr & BMSR_LSTATUS) {
5883 bnx2_test_intr(struct bnx2 *bp)
5888 if (!netif_running(bp->dev))
5891 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5893 /* This register is not touched during run-time. */
5894 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5895 REG_RD(bp, BNX2_HC_COMMAND);
5897 for (i = 0; i < 10; i++) {
5898 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5904 msleep_interruptible(10);
5912 /* Determining link for parallel detection. */
5914 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5916 u32 mode_ctl, an_dbg, exp;
5918 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5921 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5922 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5924 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5927 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5928 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5929 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5931 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5934 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5935 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5936 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5938 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5945 bnx2_5706_serdes_timer(struct bnx2 *bp)
5949 spin_lock(&bp->phy_lock);
5950 if (bp->serdes_an_pending) {
5951 bp->serdes_an_pending--;
5953 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5956 bp->current_interval = BNX2_TIMER_INTERVAL;
5958 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5960 if (bmcr & BMCR_ANENABLE) {
5961 if (bnx2_5706_serdes_has_link(bp)) {
5962 bmcr &= ~BMCR_ANENABLE;
5963 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5964 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5965 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5969 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5970 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5973 bnx2_write_phy(bp, 0x17, 0x0f01);
5974 bnx2_read_phy(bp, 0x15, &phy2);
5978 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5979 bmcr |= BMCR_ANENABLE;
5980 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5982 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5985 bp->current_interval = BNX2_TIMER_INTERVAL;
5990 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5991 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5992 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5994 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5995 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5996 bnx2_5706s_force_link_dn(bp, 1);
5997 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6000 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6003 spin_unlock(&bp->phy_lock);
6007 bnx2_5708_serdes_timer(struct bnx2 *bp)
6009 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6012 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6013 bp->serdes_an_pending = 0;
6017 spin_lock(&bp->phy_lock);
6018 if (bp->serdes_an_pending)
6019 bp->serdes_an_pending--;
6020 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6023 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6024 if (bmcr & BMCR_ANENABLE) {
6025 bnx2_enable_forced_2g5(bp);
6026 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6028 bnx2_disable_forced_2g5(bp);
6029 bp->serdes_an_pending = 2;
6030 bp->current_interval = BNX2_TIMER_INTERVAL;
6034 bp->current_interval = BNX2_TIMER_INTERVAL;
6036 spin_unlock(&bp->phy_lock);
6040 bnx2_timer(unsigned long data)
6042 struct bnx2 *bp = (struct bnx2 *) data;
6044 if (!netif_running(bp->dev))
6047 if (atomic_read(&bp->intr_sem) != 0)
6048 goto bnx2_restart_timer;
6050 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6051 BNX2_FLAG_USING_MSI)
6052 bnx2_chk_missed_msi(bp);
6054 bnx2_send_heart_beat(bp);
6056 bp->stats_blk->stat_FwRxDrop =
6057 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6059 /* workaround occasional corrupted counters */
6060 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6061 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6062 BNX2_HC_COMMAND_STATS_NOW);
6064 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6065 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6066 bnx2_5706_serdes_timer(bp);
6068 bnx2_5708_serdes_timer(bp);
6072 mod_timer(&bp->timer, jiffies + bp->current_interval);
6076 bnx2_request_irq(struct bnx2 *bp)
6078 unsigned long flags;
6079 struct bnx2_irq *irq;
6082 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6085 flags = IRQF_SHARED;
6087 for (i = 0; i < bp->irq_nvecs; i++) {
6088 irq = &bp->irq_tbl[i];
6089 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6099 bnx2_free_irq(struct bnx2 *bp)
6101 struct bnx2_irq *irq;
6104 for (i = 0; i < bp->irq_nvecs; i++) {
6105 irq = &bp->irq_tbl[i];
6107 free_irq(irq->vector, &bp->bnx2_napi[i]);
6110 if (bp->flags & BNX2_FLAG_USING_MSI)
6111 pci_disable_msi(bp->pdev);
6112 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6113 pci_disable_msix(bp->pdev);
6115 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6119 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6122 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6123 struct net_device *dev = bp->dev;
6124 const int len = sizeof(bp->irq_tbl[0].name);
6126 bnx2_setup_msix_tbl(bp);
6127 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6128 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6129 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6131 /* Need to flush the previous three writes to ensure MSI-X
6132 * is setup properly */
6133 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6135 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6136 msix_ent[i].entry = i;
6137 msix_ent[i].vector = 0;
6140 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6144 bp->irq_nvecs = msix_vecs;
6145 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6146 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6147 bp->irq_tbl[i].vector = msix_ent[i].vector;
6148 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6149 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6154 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6156 int cpus = num_online_cpus();
6157 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6159 bp->irq_tbl[0].handler = bnx2_interrupt;
6160 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6162 bp->irq_tbl[0].vector = bp->pdev->irq;
6164 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6165 bnx2_enable_msix(bp, msix_vecs);
6167 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6168 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6169 if (pci_enable_msi(bp->pdev) == 0) {
6170 bp->flags |= BNX2_FLAG_USING_MSI;
6171 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6172 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6173 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6175 bp->irq_tbl[0].handler = bnx2_msi;
6177 bp->irq_tbl[0].vector = bp->pdev->irq;
6181 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6182 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6184 bp->num_rx_rings = bp->irq_nvecs;
6187 /* Called with rtnl_lock */
6189 bnx2_open(struct net_device *dev)
6191 struct bnx2 *bp = netdev_priv(dev);
6194 netif_carrier_off(dev);
6196 bnx2_set_power_state(bp, PCI_D0);
6197 bnx2_disable_int(bp);
6199 bnx2_setup_int_mode(bp, disable_msi);
6200 bnx2_napi_enable(bp);
6201 rc = bnx2_alloc_mem(bp);
6205 rc = bnx2_request_irq(bp);
6209 rc = bnx2_init_nic(bp, 1);
6213 mod_timer(&bp->timer, jiffies + bp->current_interval);
6215 atomic_set(&bp->intr_sem, 0);
6217 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6219 bnx2_enable_int(bp);
6221 if (bp->flags & BNX2_FLAG_USING_MSI) {
6222 /* Test MSI to make sure it is working
6223 * If MSI test fails, go back to INTx mode
6225 if (bnx2_test_intr(bp) != 0) {
6226 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6228 bnx2_disable_int(bp);
6231 bnx2_setup_int_mode(bp, 1);
6233 rc = bnx2_init_nic(bp, 0);
6236 rc = bnx2_request_irq(bp);
6239 del_timer_sync(&bp->timer);
6242 bnx2_enable_int(bp);
6245 if (bp->flags & BNX2_FLAG_USING_MSI)
6246 netdev_info(dev, "using MSI\n");
6247 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6248 netdev_info(dev, "using MSIX\n");
6250 netif_tx_start_all_queues(dev);
6255 bnx2_napi_disable(bp);
6263 bnx2_reset_task(struct work_struct *work)
6265 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6268 if (!netif_running(bp->dev)) {
6273 bnx2_netif_stop(bp);
6275 bnx2_init_nic(bp, 1);
6277 atomic_set(&bp->intr_sem, 1);
6278 bnx2_netif_start(bp);
6283 bnx2_dump_state(struct bnx2 *bp)
6285 struct net_device *dev = bp->dev;
6287 netdev_err(dev, "DEBUG: intr_sem[%x]\n", atomic_read(&bp->intr_sem));
6288 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] RPM_MGMT_PKT_CTRL[%08x]\n",
6289 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6290 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6291 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6292 bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P0),
6293 bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P1));
6294 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6295 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6296 if (bp->flags & BNX2_FLAG_USING_MSIX)
6297 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6298 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6302 bnx2_tx_timeout(struct net_device *dev)
6304 struct bnx2 *bp = netdev_priv(dev);
6306 bnx2_dump_state(bp);
6308 /* This allows the netif to be shutdown gracefully before resetting */
6309 schedule_work(&bp->reset_task);
6313 /* Called with rtnl_lock */
6315 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6317 struct bnx2 *bp = netdev_priv(dev);
6319 if (netif_running(dev))
6320 bnx2_netif_stop(bp);
6324 if (!netif_running(dev))
6327 bnx2_set_rx_mode(dev);
6328 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6329 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6331 bnx2_netif_start(bp);
6335 /* Called with netif_tx_lock.
6336 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6337 * netif_wake_queue().
6340 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6342 struct bnx2 *bp = netdev_priv(dev);
6345 struct sw_tx_bd *tx_buf;
6346 u32 len, vlan_tag_flags, last_frag, mss;
6347 u16 prod, ring_prod;
6349 struct bnx2_napi *bnapi;
6350 struct bnx2_tx_ring_info *txr;
6351 struct netdev_queue *txq;
6353 /* Determine which tx ring we will be placed on */
6354 i = skb_get_queue_mapping(skb);
6355 bnapi = &bp->bnx2_napi[i];
6356 txr = &bnapi->tx_ring;
6357 txq = netdev_get_tx_queue(dev, i);
6359 if (unlikely(bnx2_tx_avail(bp, txr) <
6360 (skb_shinfo(skb)->nr_frags + 1))) {
6361 netif_tx_stop_queue(txq);
6362 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6364 return NETDEV_TX_BUSY;
6366 len = skb_headlen(skb);
6367 prod = txr->tx_prod;
6368 ring_prod = TX_RING_IDX(prod);
6371 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6372 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6376 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6378 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6381 if ((mss = skb_shinfo(skb)->gso_size)) {
6385 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6387 tcp_opt_len = tcp_optlen(skb);
6389 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6390 u32 tcp_off = skb_transport_offset(skb) -
6391 sizeof(struct ipv6hdr) - ETH_HLEN;
6393 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6394 TX_BD_FLAGS_SW_FLAGS;
6395 if (likely(tcp_off == 0))
6396 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6399 vlan_tag_flags |= ((tcp_off & 0x3) <<
6400 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6401 ((tcp_off & 0x10) <<
6402 TX_BD_FLAGS_TCP6_OFF4_SHL);
6403 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6407 if (tcp_opt_len || (iph->ihl > 5)) {
6408 vlan_tag_flags |= ((iph->ihl - 5) +
6409 (tcp_opt_len >> 2)) << 8;
6415 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6416 if (pci_dma_mapping_error(bp->pdev, mapping)) {
6418 return NETDEV_TX_OK;
6421 tx_buf = &txr->tx_buf_ring[ring_prod];
6423 pci_unmap_addr_set(tx_buf, mapping, mapping);
6425 txbd = &txr->tx_desc_ring[ring_prod];
6427 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6428 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6429 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6430 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6432 last_frag = skb_shinfo(skb)->nr_frags;
6433 tx_buf->nr_frags = last_frag;
6434 tx_buf->is_gso = skb_is_gso(skb);
6436 for (i = 0; i < last_frag; i++) {
6437 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6439 prod = NEXT_TX_BD(prod);
6440 ring_prod = TX_RING_IDX(prod);
6441 txbd = &txr->tx_desc_ring[ring_prod];
6444 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6445 len, PCI_DMA_TODEVICE);
6446 if (pci_dma_mapping_error(bp->pdev, mapping))
6448 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6451 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6452 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6453 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6454 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6457 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6459 prod = NEXT_TX_BD(prod);
6460 txr->tx_prod_bseq += skb->len;
6462 REG_WR16(bp, txr->tx_bidx_addr, prod);
6463 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6467 txr->tx_prod = prod;
6469 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6470 netif_tx_stop_queue(txq);
6471 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6472 netif_tx_wake_queue(txq);
6475 return NETDEV_TX_OK;
6477 /* save value of frag that failed */
6480 /* start back at beginning and unmap skb */
6481 prod = txr->tx_prod;
6482 ring_prod = TX_RING_IDX(prod);
6483 tx_buf = &txr->tx_buf_ring[ring_prod];
6485 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6486 skb_headlen(skb), PCI_DMA_TODEVICE);
6488 /* unmap remaining mapped pages */
6489 for (i = 0; i < last_frag; i++) {
6490 prod = NEXT_TX_BD(prod);
6491 ring_prod = TX_RING_IDX(prod);
6492 tx_buf = &txr->tx_buf_ring[ring_prod];
6493 pci_unmap_page(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6494 skb_shinfo(skb)->frags[i].size,
6499 return NETDEV_TX_OK;
6502 /* Called with rtnl_lock */
6504 bnx2_close(struct net_device *dev)
6506 struct bnx2 *bp = netdev_priv(dev);
6508 cancel_work_sync(&bp->reset_task);
6510 bnx2_disable_int_sync(bp);
6511 bnx2_napi_disable(bp);
6512 del_timer_sync(&bp->timer);
6513 bnx2_shutdown_chip(bp);
6518 netif_carrier_off(bp->dev);
6519 bnx2_set_power_state(bp, PCI_D3hot);
6524 bnx2_save_stats(struct bnx2 *bp)
6526 u32 *hw_stats = (u32 *) bp->stats_blk;
6527 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6530 /* The 1st 10 counters are 64-bit counters */
6531 for (i = 0; i < 20; i += 2) {
6535 hi = temp_stats[i] + hw_stats[i];
6536 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6537 if (lo > 0xffffffff)
6540 temp_stats[i + 1] = lo & 0xffffffff;
6543 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6544 temp_stats[i] += hw_stats[i];
6547 #define GET_64BIT_NET_STATS64(ctr) \
6548 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6549 (unsigned long) (ctr##_lo)
6551 #define GET_64BIT_NET_STATS32(ctr) \
6554 #if (BITS_PER_LONG == 64)
6555 #define GET_64BIT_NET_STATS(ctr) \
6556 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6557 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6559 #define GET_64BIT_NET_STATS(ctr) \
6560 GET_64BIT_NET_STATS32(bp->stats_blk->ctr) + \
6561 GET_64BIT_NET_STATS32(bp->temp_stats_blk->ctr)
6564 #define GET_32BIT_NET_STATS(ctr) \
6565 (unsigned long) (bp->stats_blk->ctr + \
6566 bp->temp_stats_blk->ctr)
6568 static struct net_device_stats *
6569 bnx2_get_stats(struct net_device *dev)
6571 struct bnx2 *bp = netdev_priv(dev);
6572 struct net_device_stats *net_stats = &dev->stats;
6574 if (bp->stats_blk == NULL) {
6577 net_stats->rx_packets =
6578 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6579 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6580 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6582 net_stats->tx_packets =
6583 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6584 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6585 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6587 net_stats->rx_bytes =
6588 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6590 net_stats->tx_bytes =
6591 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6593 net_stats->multicast =
6594 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts);
6596 net_stats->collisions =
6597 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6599 net_stats->rx_length_errors =
6600 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6601 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6603 net_stats->rx_over_errors =
6604 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6605 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6607 net_stats->rx_frame_errors =
6608 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6610 net_stats->rx_crc_errors =
6611 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6613 net_stats->rx_errors = net_stats->rx_length_errors +
6614 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6615 net_stats->rx_crc_errors;
6617 net_stats->tx_aborted_errors =
6618 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6619 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6621 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6622 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6623 net_stats->tx_carrier_errors = 0;
6625 net_stats->tx_carrier_errors =
6626 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6629 net_stats->tx_errors =
6630 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6631 net_stats->tx_aborted_errors +
6632 net_stats->tx_carrier_errors;
6634 net_stats->rx_missed_errors =
6635 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6636 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6637 GET_32BIT_NET_STATS(stat_FwRxDrop);
6642 /* All ethtool functions called with rtnl_lock */
6645 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6647 struct bnx2 *bp = netdev_priv(dev);
6648 int support_serdes = 0, support_copper = 0;
6650 cmd->supported = SUPPORTED_Autoneg;
6651 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6654 } else if (bp->phy_port == PORT_FIBRE)
6659 if (support_serdes) {
6660 cmd->supported |= SUPPORTED_1000baseT_Full |
6662 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6663 cmd->supported |= SUPPORTED_2500baseX_Full;
6666 if (support_copper) {
6667 cmd->supported |= SUPPORTED_10baseT_Half |
6668 SUPPORTED_10baseT_Full |
6669 SUPPORTED_100baseT_Half |
6670 SUPPORTED_100baseT_Full |
6671 SUPPORTED_1000baseT_Full |
6676 spin_lock_bh(&bp->phy_lock);
6677 cmd->port = bp->phy_port;
6678 cmd->advertising = bp->advertising;
6680 if (bp->autoneg & AUTONEG_SPEED) {
6681 cmd->autoneg = AUTONEG_ENABLE;
6684 cmd->autoneg = AUTONEG_DISABLE;
6687 if (netif_carrier_ok(dev)) {
6688 cmd->speed = bp->line_speed;
6689 cmd->duplex = bp->duplex;
6695 spin_unlock_bh(&bp->phy_lock);
6697 cmd->transceiver = XCVR_INTERNAL;
6698 cmd->phy_address = bp->phy_addr;
6704 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6706 struct bnx2 *bp = netdev_priv(dev);
6707 u8 autoneg = bp->autoneg;
6708 u8 req_duplex = bp->req_duplex;
6709 u16 req_line_speed = bp->req_line_speed;
6710 u32 advertising = bp->advertising;
6713 spin_lock_bh(&bp->phy_lock);
6715 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6716 goto err_out_unlock;
6718 if (cmd->port != bp->phy_port &&
6719 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6720 goto err_out_unlock;
6722 /* If device is down, we can store the settings only if the user
6723 * is setting the currently active port.
6725 if (!netif_running(dev) && cmd->port != bp->phy_port)
6726 goto err_out_unlock;
6728 if (cmd->autoneg == AUTONEG_ENABLE) {
6729 autoneg |= AUTONEG_SPEED;
6731 advertising = cmd->advertising;
6732 if (cmd->port == PORT_TP) {
6733 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6735 advertising = ETHTOOL_ALL_COPPER_SPEED;
6737 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6739 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6741 advertising |= ADVERTISED_Autoneg;
6744 if (cmd->port == PORT_FIBRE) {
6745 if ((cmd->speed != SPEED_1000 &&
6746 cmd->speed != SPEED_2500) ||
6747 (cmd->duplex != DUPLEX_FULL))
6748 goto err_out_unlock;
6750 if (cmd->speed == SPEED_2500 &&
6751 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6752 goto err_out_unlock;
6754 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6755 goto err_out_unlock;
6757 autoneg &= ~AUTONEG_SPEED;
6758 req_line_speed = cmd->speed;
6759 req_duplex = cmd->duplex;
6763 bp->autoneg = autoneg;
6764 bp->advertising = advertising;
6765 bp->req_line_speed = req_line_speed;
6766 bp->req_duplex = req_duplex;
6769 /* If device is down, the new settings will be picked up when it is
6772 if (netif_running(dev))
6773 err = bnx2_setup_phy(bp, cmd->port);
6776 spin_unlock_bh(&bp->phy_lock);
6782 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6784 struct bnx2 *bp = netdev_priv(dev);
6786 strcpy(info->driver, DRV_MODULE_NAME);
6787 strcpy(info->version, DRV_MODULE_VERSION);
6788 strcpy(info->bus_info, pci_name(bp->pdev));
6789 strcpy(info->fw_version, bp->fw_version);
6792 #define BNX2_REGDUMP_LEN (32 * 1024)
6795 bnx2_get_regs_len(struct net_device *dev)
6797 return BNX2_REGDUMP_LEN;
6801 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6803 u32 *p = _p, i, offset;
6805 struct bnx2 *bp = netdev_priv(dev);
6806 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6807 0x0800, 0x0880, 0x0c00, 0x0c10,
6808 0x0c30, 0x0d08, 0x1000, 0x101c,
6809 0x1040, 0x1048, 0x1080, 0x10a4,
6810 0x1400, 0x1490, 0x1498, 0x14f0,
6811 0x1500, 0x155c, 0x1580, 0x15dc,
6812 0x1600, 0x1658, 0x1680, 0x16d8,
6813 0x1800, 0x1820, 0x1840, 0x1854,
6814 0x1880, 0x1894, 0x1900, 0x1984,
6815 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6816 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6817 0x2000, 0x2030, 0x23c0, 0x2400,
6818 0x2800, 0x2820, 0x2830, 0x2850,
6819 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6820 0x3c00, 0x3c94, 0x4000, 0x4010,
6821 0x4080, 0x4090, 0x43c0, 0x4458,
6822 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6823 0x4fc0, 0x5010, 0x53c0, 0x5444,
6824 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6825 0x5fc0, 0x6000, 0x6400, 0x6428,
6826 0x6800, 0x6848, 0x684c, 0x6860,
6827 0x6888, 0x6910, 0x8000 };
6831 memset(p, 0, BNX2_REGDUMP_LEN);
6833 if (!netif_running(bp->dev))
6837 offset = reg_boundaries[0];
6839 while (offset < BNX2_REGDUMP_LEN) {
6840 *p++ = REG_RD(bp, offset);
6842 if (offset == reg_boundaries[i + 1]) {
6843 offset = reg_boundaries[i + 2];
6844 p = (u32 *) (orig_p + offset);
6851 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6853 struct bnx2 *bp = netdev_priv(dev);
6855 if (bp->flags & BNX2_FLAG_NO_WOL) {
6860 wol->supported = WAKE_MAGIC;
6862 wol->wolopts = WAKE_MAGIC;
6866 memset(&wol->sopass, 0, sizeof(wol->sopass));
6870 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6872 struct bnx2 *bp = netdev_priv(dev);
6874 if (wol->wolopts & ~WAKE_MAGIC)
6877 if (wol->wolopts & WAKE_MAGIC) {
6878 if (bp->flags & BNX2_FLAG_NO_WOL)
6890 bnx2_nway_reset(struct net_device *dev)
6892 struct bnx2 *bp = netdev_priv(dev);
6895 if (!netif_running(dev))
6898 if (!(bp->autoneg & AUTONEG_SPEED)) {
6902 spin_lock_bh(&bp->phy_lock);
6904 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6907 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6908 spin_unlock_bh(&bp->phy_lock);
6912 /* Force a link down visible on the other side */
6913 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6914 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6915 spin_unlock_bh(&bp->phy_lock);
6919 spin_lock_bh(&bp->phy_lock);
6921 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6922 bp->serdes_an_pending = 1;
6923 mod_timer(&bp->timer, jiffies + bp->current_interval);
6926 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6927 bmcr &= ~BMCR_LOOPBACK;
6928 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6930 spin_unlock_bh(&bp->phy_lock);
6936 bnx2_get_link(struct net_device *dev)
6938 struct bnx2 *bp = netdev_priv(dev);
6944 bnx2_get_eeprom_len(struct net_device *dev)
6946 struct bnx2 *bp = netdev_priv(dev);
6948 if (bp->flash_info == NULL)
6951 return (int) bp->flash_size;
6955 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6958 struct bnx2 *bp = netdev_priv(dev);
6961 if (!netif_running(dev))
6964 /* parameters already validated in ethtool_get_eeprom */
6966 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6972 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6975 struct bnx2 *bp = netdev_priv(dev);
6978 if (!netif_running(dev))
6981 /* parameters already validated in ethtool_set_eeprom */
6983 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6989 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6991 struct bnx2 *bp = netdev_priv(dev);
6993 memset(coal, 0, sizeof(struct ethtool_coalesce));
6995 coal->rx_coalesce_usecs = bp->rx_ticks;
6996 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6997 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6998 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7000 coal->tx_coalesce_usecs = bp->tx_ticks;
7001 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7002 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7003 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7005 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7011 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7013 struct bnx2 *bp = netdev_priv(dev);
7015 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7016 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7018 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7019 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7021 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7022 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7024 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7025 if (bp->rx_quick_cons_trip_int > 0xff)
7026 bp->rx_quick_cons_trip_int = 0xff;
7028 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7029 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7031 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7032 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7034 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7035 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7037 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7038 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7041 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7042 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7043 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7044 bp->stats_ticks = USEC_PER_SEC;
7046 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7047 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7048 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7050 if (netif_running(bp->dev)) {
7051 bnx2_netif_stop(bp);
7052 bnx2_init_nic(bp, 0);
7053 bnx2_netif_start(bp);
7060 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7062 struct bnx2 *bp = netdev_priv(dev);
7064 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7065 ering->rx_mini_max_pending = 0;
7066 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7068 ering->rx_pending = bp->rx_ring_size;
7069 ering->rx_mini_pending = 0;
7070 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7072 ering->tx_max_pending = MAX_TX_DESC_CNT;
7073 ering->tx_pending = bp->tx_ring_size;
7077 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7079 if (netif_running(bp->dev)) {
7080 /* Reset will erase chipset stats; save them */
7081 bnx2_save_stats(bp);
7083 bnx2_netif_stop(bp);
7084 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7089 bnx2_set_rx_ring_size(bp, rx);
7090 bp->tx_ring_size = tx;
7092 if (netif_running(bp->dev)) {
7095 rc = bnx2_alloc_mem(bp);
7097 rc = bnx2_init_nic(bp, 0);
7100 bnx2_napi_enable(bp);
7105 mutex_lock(&bp->cnic_lock);
7106 /* Let cnic know about the new status block. */
7107 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7108 bnx2_setup_cnic_irq_info(bp);
7109 mutex_unlock(&bp->cnic_lock);
7111 bnx2_netif_start(bp);
7117 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7119 struct bnx2 *bp = netdev_priv(dev);
7122 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7123 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7124 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7128 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7133 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7135 struct bnx2 *bp = netdev_priv(dev);
7137 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7138 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7139 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7143 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7145 struct bnx2 *bp = netdev_priv(dev);
7147 bp->req_flow_ctrl = 0;
7148 if (epause->rx_pause)
7149 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7150 if (epause->tx_pause)
7151 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7153 if (epause->autoneg) {
7154 bp->autoneg |= AUTONEG_FLOW_CTRL;
7157 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7160 if (netif_running(dev)) {
7161 spin_lock_bh(&bp->phy_lock);
7162 bnx2_setup_phy(bp, bp->phy_port);
7163 spin_unlock_bh(&bp->phy_lock);
7170 bnx2_get_rx_csum(struct net_device *dev)
7172 struct bnx2 *bp = netdev_priv(dev);
7178 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7180 struct bnx2 *bp = netdev_priv(dev);
7187 bnx2_set_tso(struct net_device *dev, u32 data)
7189 struct bnx2 *bp = netdev_priv(dev);
7192 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7193 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7194 dev->features |= NETIF_F_TSO6;
7196 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7202 char string[ETH_GSTRING_LEN];
7203 } bnx2_stats_str_arr[] = {
7205 { "rx_error_bytes" },
7207 { "tx_error_bytes" },
7208 { "rx_ucast_packets" },
7209 { "rx_mcast_packets" },
7210 { "rx_bcast_packets" },
7211 { "tx_ucast_packets" },
7212 { "tx_mcast_packets" },
7213 { "tx_bcast_packets" },
7214 { "tx_mac_errors" },
7215 { "tx_carrier_errors" },
7216 { "rx_crc_errors" },
7217 { "rx_align_errors" },
7218 { "tx_single_collisions" },
7219 { "tx_multi_collisions" },
7221 { "tx_excess_collisions" },
7222 { "tx_late_collisions" },
7223 { "tx_total_collisions" },
7226 { "rx_undersize_packets" },
7227 { "rx_oversize_packets" },
7228 { "rx_64_byte_packets" },
7229 { "rx_65_to_127_byte_packets" },
7230 { "rx_128_to_255_byte_packets" },
7231 { "rx_256_to_511_byte_packets" },
7232 { "rx_512_to_1023_byte_packets" },
7233 { "rx_1024_to_1522_byte_packets" },
7234 { "rx_1523_to_9022_byte_packets" },
7235 { "tx_64_byte_packets" },
7236 { "tx_65_to_127_byte_packets" },
7237 { "tx_128_to_255_byte_packets" },
7238 { "tx_256_to_511_byte_packets" },
7239 { "tx_512_to_1023_byte_packets" },
7240 { "tx_1024_to_1522_byte_packets" },
7241 { "tx_1523_to_9022_byte_packets" },
7242 { "rx_xon_frames" },
7243 { "rx_xoff_frames" },
7244 { "tx_xon_frames" },
7245 { "tx_xoff_frames" },
7246 { "rx_mac_ctrl_frames" },
7247 { "rx_filtered_packets" },
7248 { "rx_ftq_discards" },
7250 { "rx_fw_discards" },
7253 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7254 sizeof(bnx2_stats_str_arr[0]))
7256 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7258 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7259 STATS_OFFSET32(stat_IfHCInOctets_hi),
7260 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7261 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7262 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7263 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7264 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7265 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7266 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7267 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7268 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7269 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7270 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7271 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7272 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7273 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7274 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7275 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7276 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7277 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7278 STATS_OFFSET32(stat_EtherStatsCollisions),
7279 STATS_OFFSET32(stat_EtherStatsFragments),
7280 STATS_OFFSET32(stat_EtherStatsJabbers),
7281 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7282 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7283 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7284 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7285 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7286 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7287 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7288 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7289 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7290 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7291 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7292 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7293 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7294 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7295 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7296 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7297 STATS_OFFSET32(stat_XonPauseFramesReceived),
7298 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7299 STATS_OFFSET32(stat_OutXonSent),
7300 STATS_OFFSET32(stat_OutXoffSent),
7301 STATS_OFFSET32(stat_MacControlFramesReceived),
7302 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7303 STATS_OFFSET32(stat_IfInFTQDiscards),
7304 STATS_OFFSET32(stat_IfInMBUFDiscards),
7305 STATS_OFFSET32(stat_FwRxDrop),
7308 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7309 * skipped because of errata.
7311 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7312 8,0,8,8,8,8,8,8,8,8,
7313 4,0,4,4,4,4,4,4,4,4,
7314 4,4,4,4,4,4,4,4,4,4,
7315 4,4,4,4,4,4,4,4,4,4,
7319 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7320 8,0,8,8,8,8,8,8,8,8,
7321 4,4,4,4,4,4,4,4,4,4,
7322 4,4,4,4,4,4,4,4,4,4,
7323 4,4,4,4,4,4,4,4,4,4,
7327 #define BNX2_NUM_TESTS 6
7330 char string[ETH_GSTRING_LEN];
7331 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7332 { "register_test (offline)" },
7333 { "memory_test (offline)" },
7334 { "loopback_test (offline)" },
7335 { "nvram_test (online)" },
7336 { "interrupt_test (online)" },
7337 { "link_test (online)" },
7341 bnx2_get_sset_count(struct net_device *dev, int sset)
7345 return BNX2_NUM_TESTS;
7347 return BNX2_NUM_STATS;
7354 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7356 struct bnx2 *bp = netdev_priv(dev);
7358 bnx2_set_power_state(bp, PCI_D0);
7360 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7361 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7364 bnx2_netif_stop(bp);
7365 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7368 if (bnx2_test_registers(bp) != 0) {
7370 etest->flags |= ETH_TEST_FL_FAILED;
7372 if (bnx2_test_memory(bp) != 0) {
7374 etest->flags |= ETH_TEST_FL_FAILED;
7376 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7377 etest->flags |= ETH_TEST_FL_FAILED;
7379 if (!netif_running(bp->dev))
7380 bnx2_shutdown_chip(bp);
7382 bnx2_init_nic(bp, 1);
7383 bnx2_netif_start(bp);
7386 /* wait for link up */
7387 for (i = 0; i < 7; i++) {
7390 msleep_interruptible(1000);
7394 if (bnx2_test_nvram(bp) != 0) {
7396 etest->flags |= ETH_TEST_FL_FAILED;
7398 if (bnx2_test_intr(bp) != 0) {
7400 etest->flags |= ETH_TEST_FL_FAILED;
7403 if (bnx2_test_link(bp) != 0) {
7405 etest->flags |= ETH_TEST_FL_FAILED;
7408 if (!netif_running(bp->dev))
7409 bnx2_set_power_state(bp, PCI_D3hot);
7413 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7415 switch (stringset) {
7417 memcpy(buf, bnx2_stats_str_arr,
7418 sizeof(bnx2_stats_str_arr));
7421 memcpy(buf, bnx2_tests_str_arr,
7422 sizeof(bnx2_tests_str_arr));
7428 bnx2_get_ethtool_stats(struct net_device *dev,
7429 struct ethtool_stats *stats, u64 *buf)
7431 struct bnx2 *bp = netdev_priv(dev);
7433 u32 *hw_stats = (u32 *) bp->stats_blk;
7434 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7435 u8 *stats_len_arr = NULL;
7437 if (hw_stats == NULL) {
7438 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7442 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7443 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7444 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7445 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7446 stats_len_arr = bnx2_5706_stats_len_arr;
7448 stats_len_arr = bnx2_5708_stats_len_arr;
7450 for (i = 0; i < BNX2_NUM_STATS; i++) {
7451 unsigned long offset;
7453 if (stats_len_arr[i] == 0) {
7454 /* skip this counter */
7459 offset = bnx2_stats_offset_arr[i];
7460 if (stats_len_arr[i] == 4) {
7461 /* 4-byte counter */
7462 buf[i] = (u64) *(hw_stats + offset) +
7463 *(temp_stats + offset);
7466 /* 8-byte counter */
7467 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7468 *(hw_stats + offset + 1) +
7469 (((u64) *(temp_stats + offset)) << 32) +
7470 *(temp_stats + offset + 1);
7475 bnx2_phys_id(struct net_device *dev, u32 data)
7477 struct bnx2 *bp = netdev_priv(dev);
7481 bnx2_set_power_state(bp, PCI_D0);
7486 save = REG_RD(bp, BNX2_MISC_CFG);
7487 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7489 for (i = 0; i < (data * 2); i++) {
7491 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7494 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7495 BNX2_EMAC_LED_1000MB_OVERRIDE |
7496 BNX2_EMAC_LED_100MB_OVERRIDE |
7497 BNX2_EMAC_LED_10MB_OVERRIDE |
7498 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7499 BNX2_EMAC_LED_TRAFFIC);
7501 msleep_interruptible(500);
7502 if (signal_pending(current))
7505 REG_WR(bp, BNX2_EMAC_LED, 0);
7506 REG_WR(bp, BNX2_MISC_CFG, save);
7508 if (!netif_running(dev))
7509 bnx2_set_power_state(bp, PCI_D3hot);
7515 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7517 struct bnx2 *bp = netdev_priv(dev);
7519 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7520 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7522 return (ethtool_op_set_tx_csum(dev, data));
7525 static const struct ethtool_ops bnx2_ethtool_ops = {
7526 .get_settings = bnx2_get_settings,
7527 .set_settings = bnx2_set_settings,
7528 .get_drvinfo = bnx2_get_drvinfo,
7529 .get_regs_len = bnx2_get_regs_len,
7530 .get_regs = bnx2_get_regs,
7531 .get_wol = bnx2_get_wol,
7532 .set_wol = bnx2_set_wol,
7533 .nway_reset = bnx2_nway_reset,
7534 .get_link = bnx2_get_link,
7535 .get_eeprom_len = bnx2_get_eeprom_len,
7536 .get_eeprom = bnx2_get_eeprom,
7537 .set_eeprom = bnx2_set_eeprom,
7538 .get_coalesce = bnx2_get_coalesce,
7539 .set_coalesce = bnx2_set_coalesce,
7540 .get_ringparam = bnx2_get_ringparam,
7541 .set_ringparam = bnx2_set_ringparam,
7542 .get_pauseparam = bnx2_get_pauseparam,
7543 .set_pauseparam = bnx2_set_pauseparam,
7544 .get_rx_csum = bnx2_get_rx_csum,
7545 .set_rx_csum = bnx2_set_rx_csum,
7546 .set_tx_csum = bnx2_set_tx_csum,
7547 .set_sg = ethtool_op_set_sg,
7548 .set_tso = bnx2_set_tso,
7549 .self_test = bnx2_self_test,
7550 .get_strings = bnx2_get_strings,
7551 .phys_id = bnx2_phys_id,
7552 .get_ethtool_stats = bnx2_get_ethtool_stats,
7553 .get_sset_count = bnx2_get_sset_count,
7556 /* Called with rtnl_lock */
7558 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7560 struct mii_ioctl_data *data = if_mii(ifr);
7561 struct bnx2 *bp = netdev_priv(dev);
7566 data->phy_id = bp->phy_addr;
7572 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7575 if (!netif_running(dev))
7578 spin_lock_bh(&bp->phy_lock);
7579 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7580 spin_unlock_bh(&bp->phy_lock);
7582 data->val_out = mii_regval;
7588 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7591 if (!netif_running(dev))
7594 spin_lock_bh(&bp->phy_lock);
7595 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7596 spin_unlock_bh(&bp->phy_lock);
7607 /* Called with rtnl_lock */
7609 bnx2_change_mac_addr(struct net_device *dev, void *p)
7611 struct sockaddr *addr = p;
7612 struct bnx2 *bp = netdev_priv(dev);
7614 if (!is_valid_ether_addr(addr->sa_data))
7617 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7618 if (netif_running(dev))
7619 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7624 /* Called with rtnl_lock */
7626 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7628 struct bnx2 *bp = netdev_priv(dev);
7630 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7631 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7635 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7638 #ifdef CONFIG_NET_POLL_CONTROLLER
7640 poll_bnx2(struct net_device *dev)
7642 struct bnx2 *bp = netdev_priv(dev);
7645 for (i = 0; i < bp->irq_nvecs; i++) {
7646 disable_irq(bp->irq_tbl[i].vector);
7647 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7648 enable_irq(bp->irq_tbl[i].vector);
7653 static void __devinit
7654 bnx2_get_5709_media(struct bnx2 *bp)
7656 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7657 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7660 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7662 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7663 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7667 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7668 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7670 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7672 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7677 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7685 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7691 static void __devinit
7692 bnx2_get_pci_speed(struct bnx2 *bp)
7696 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7697 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7700 bp->flags |= BNX2_FLAG_PCIX;
7702 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7704 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7706 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7707 bp->bus_speed_mhz = 133;
7710 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7711 bp->bus_speed_mhz = 100;
7714 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7715 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7716 bp->bus_speed_mhz = 66;
7719 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7720 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7721 bp->bus_speed_mhz = 50;
7724 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7725 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7726 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7727 bp->bus_speed_mhz = 33;
7732 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7733 bp->bus_speed_mhz = 66;
7735 bp->bus_speed_mhz = 33;
7738 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7739 bp->flags |= BNX2_FLAG_PCI_32BIT;
7743 static void __devinit
7744 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7748 unsigned int block_end, rosize, len;
7750 #define BNX2_VPD_NVRAM_OFFSET 0x300
7751 #define BNX2_VPD_LEN 128
7752 #define BNX2_MAX_VER_SLEN 30
7754 data = kmalloc(256, GFP_KERNEL);
7758 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7763 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7764 data[i] = data[i + BNX2_VPD_LEN + 3];
7765 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7766 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7767 data[i + 3] = data[i + BNX2_VPD_LEN];
7770 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7774 rosize = pci_vpd_lrdt_size(&data[i]);
7775 i += PCI_VPD_LRDT_TAG_SIZE;
7776 block_end = i + rosize;
7778 if (block_end > BNX2_VPD_LEN)
7781 j = pci_vpd_find_info_keyword(data, i, rosize,
7782 PCI_VPD_RO_KEYWORD_MFR_ID);
7786 len = pci_vpd_info_field_size(&data[j]);
7788 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7789 if (j + len > block_end || len != 4 ||
7790 memcmp(&data[j], "1028", 4))
7793 j = pci_vpd_find_info_keyword(data, i, rosize,
7794 PCI_VPD_RO_KEYWORD_VENDOR0);
7798 len = pci_vpd_info_field_size(&data[j]);
7800 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7801 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7804 memcpy(bp->fw_version, &data[j], len);
7805 bp->fw_version[len] = ' ';
7811 static int __devinit
7812 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7815 unsigned long mem_len;
7818 u64 dma_mask, persist_dma_mask;
7820 SET_NETDEV_DEV(dev, &pdev->dev);
7821 bp = netdev_priv(dev);
7826 bp->temp_stats_blk =
7827 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7829 if (bp->temp_stats_blk == NULL) {
7834 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7835 rc = pci_enable_device(pdev);
7837 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7841 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7843 "Cannot find PCI device base address, aborting\n");
7845 goto err_out_disable;
7848 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7850 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7851 goto err_out_disable;
7854 pci_set_master(pdev);
7855 pci_save_state(pdev);
7857 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7858 if (bp->pm_cap == 0) {
7860 "Cannot find power management capability, aborting\n");
7862 goto err_out_release;
7868 spin_lock_init(&bp->phy_lock);
7869 spin_lock_init(&bp->indirect_lock);
7871 mutex_init(&bp->cnic_lock);
7873 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7875 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7876 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7877 dev->mem_end = dev->mem_start + mem_len;
7878 dev->irq = pdev->irq;
7880 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7883 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7885 goto err_out_release;
7888 /* Configure byte swap and enable write to the reg_window registers.
7889 * Rely on CPU to do target byte swapping on big endian systems
7890 * The chip's target access swapping will not swap all accesses
7892 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7893 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7894 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7896 bnx2_set_power_state(bp, PCI_D0);
7898 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7900 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7901 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7903 "Cannot find PCIE capability, aborting\n");
7907 bp->flags |= BNX2_FLAG_PCIE;
7908 if (CHIP_REV(bp) == CHIP_REV_Ax)
7909 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7911 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7912 if (bp->pcix_cap == 0) {
7914 "Cannot find PCIX capability, aborting\n");
7918 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7921 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7922 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7923 bp->flags |= BNX2_FLAG_MSIX_CAP;
7926 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7927 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7928 bp->flags |= BNX2_FLAG_MSI_CAP;
7931 /* 5708 cannot support DMA addresses > 40-bit. */
7932 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7933 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7935 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7937 /* Configure DMA attributes. */
7938 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7939 dev->features |= NETIF_F_HIGHDMA;
7940 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7943 "pci_set_consistent_dma_mask failed, aborting\n");
7946 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7947 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7951 if (!(bp->flags & BNX2_FLAG_PCIE))
7952 bnx2_get_pci_speed(bp);
7954 /* 5706A0 may falsely detect SERR and PERR. */
7955 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7956 reg = REG_RD(bp, PCI_COMMAND);
7957 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7958 REG_WR(bp, PCI_COMMAND, reg);
7960 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7961 !(bp->flags & BNX2_FLAG_PCIX)) {
7964 "5706 A1 can only be used in a PCIX bus, aborting\n");
7968 bnx2_init_nvram(bp);
7970 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7972 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7973 BNX2_SHM_HDR_SIGNATURE_SIG) {
7974 u32 off = PCI_FUNC(pdev->devfn) << 2;
7976 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7978 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7980 /* Get the permanent MAC address. First we need to make sure the
7981 * firmware is actually running.
7983 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7985 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7986 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7987 dev_err(&pdev->dev, "Firmware not running, aborting\n");
7992 bnx2_read_vpd_fw_ver(bp);
7994 j = strlen(bp->fw_version);
7995 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7996 for (i = 0; i < 3 && j < 24; i++) {
8000 bp->fw_version[j++] = 'b';
8001 bp->fw_version[j++] = 'c';
8002 bp->fw_version[j++] = ' ';
8004 num = (u8) (reg >> (24 - (i * 8)));
8005 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8006 if (num >= k || !skip0 || k == 1) {
8007 bp->fw_version[j++] = (num / k) + '0';
8012 bp->fw_version[j++] = '.';
8014 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8015 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8018 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8019 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8021 for (i = 0; i < 30; i++) {
8022 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8023 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8028 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8029 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8030 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8031 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8032 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8035 bp->fw_version[j++] = ' ';
8036 for (i = 0; i < 3 && j < 28; i++) {
8037 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8039 memcpy(&bp->fw_version[j], ®, 4);
8044 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8045 bp->mac_addr[0] = (u8) (reg >> 8);
8046 bp->mac_addr[1] = (u8) reg;
8048 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8049 bp->mac_addr[2] = (u8) (reg >> 24);
8050 bp->mac_addr[3] = (u8) (reg >> 16);
8051 bp->mac_addr[4] = (u8) (reg >> 8);
8052 bp->mac_addr[5] = (u8) reg;
8054 bp->tx_ring_size = MAX_TX_DESC_CNT;
8055 bnx2_set_rx_ring_size(bp, 255);
8059 bp->tx_quick_cons_trip_int = 2;
8060 bp->tx_quick_cons_trip = 20;
8061 bp->tx_ticks_int = 18;
8064 bp->rx_quick_cons_trip_int = 2;
8065 bp->rx_quick_cons_trip = 12;
8066 bp->rx_ticks_int = 18;
8069 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8071 bp->current_interval = BNX2_TIMER_INTERVAL;
8075 /* Disable WOL support if we are running on a SERDES chip. */
8076 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8077 bnx2_get_5709_media(bp);
8078 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8079 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8081 bp->phy_port = PORT_TP;
8082 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8083 bp->phy_port = PORT_FIBRE;
8084 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8085 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8086 bp->flags |= BNX2_FLAG_NO_WOL;
8089 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8090 /* Don't do parallel detect on this board because of
8091 * some board problems. The link will not go down
8092 * if we do parallel detect.
8094 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8095 pdev->subsystem_device == 0x310c)
8096 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8099 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8100 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8102 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8103 CHIP_NUM(bp) == CHIP_NUM_5708)
8104 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8105 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8106 (CHIP_REV(bp) == CHIP_REV_Ax ||
8107 CHIP_REV(bp) == CHIP_REV_Bx))
8108 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8110 bnx2_init_fw_cap(bp);
8112 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8113 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8114 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8115 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8116 bp->flags |= BNX2_FLAG_NO_WOL;
8120 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8121 bp->tx_quick_cons_trip_int =
8122 bp->tx_quick_cons_trip;
8123 bp->tx_ticks_int = bp->tx_ticks;
8124 bp->rx_quick_cons_trip_int =
8125 bp->rx_quick_cons_trip;
8126 bp->rx_ticks_int = bp->rx_ticks;
8127 bp->comp_prod_trip_int = bp->comp_prod_trip;
8128 bp->com_ticks_int = bp->com_ticks;
8129 bp->cmd_ticks_int = bp->cmd_ticks;
8132 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8134 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8135 * with byte enables disabled on the unused 32-bit word. This is legal
8136 * but causes problems on the AMD 8132 which will eventually stop
8137 * responding after a while.
8139 * AMD believes this incompatibility is unique to the 5706, and
8140 * prefers to locally disable MSI rather than globally disabling it.
8142 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8143 struct pci_dev *amd_8132 = NULL;
8145 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8146 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8149 if (amd_8132->revision >= 0x10 &&
8150 amd_8132->revision <= 0x13) {
8152 pci_dev_put(amd_8132);
8158 bnx2_set_default_link(bp);
8159 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8161 init_timer(&bp->timer);
8162 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8163 bp->timer.data = (unsigned long) bp;
8164 bp->timer.function = bnx2_timer;
8170 iounmap(bp->regview);
8175 pci_release_regions(pdev);
8178 pci_disable_device(pdev);
8179 pci_set_drvdata(pdev, NULL);
8185 static char * __devinit
8186 bnx2_bus_string(struct bnx2 *bp, char *str)
8190 if (bp->flags & BNX2_FLAG_PCIE) {
8191 s += sprintf(s, "PCI Express");
8193 s += sprintf(s, "PCI");
8194 if (bp->flags & BNX2_FLAG_PCIX)
8195 s += sprintf(s, "-X");
8196 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8197 s += sprintf(s, " 32-bit");
8199 s += sprintf(s, " 64-bit");
8200 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8205 static void __devinit
8206 bnx2_init_napi(struct bnx2 *bp)
8210 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
8211 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8212 int (*poll)(struct napi_struct *, int);
8217 poll = bnx2_poll_msix;
8219 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8224 static const struct net_device_ops bnx2_netdev_ops = {
8225 .ndo_open = bnx2_open,
8226 .ndo_start_xmit = bnx2_start_xmit,
8227 .ndo_stop = bnx2_close,
8228 .ndo_get_stats = bnx2_get_stats,
8229 .ndo_set_rx_mode = bnx2_set_rx_mode,
8230 .ndo_do_ioctl = bnx2_ioctl,
8231 .ndo_validate_addr = eth_validate_addr,
8232 .ndo_set_mac_address = bnx2_change_mac_addr,
8233 .ndo_change_mtu = bnx2_change_mtu,
8234 .ndo_tx_timeout = bnx2_tx_timeout,
8236 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8238 #ifdef CONFIG_NET_POLL_CONTROLLER
8239 .ndo_poll_controller = poll_bnx2,
8243 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8246 dev->vlan_features |= flags;
8250 static int __devinit
8251 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8253 static int version_printed = 0;
8254 struct net_device *dev = NULL;
8259 if (version_printed++ == 0)
8260 pr_info("%s", version);
8262 /* dev zeroed in init_etherdev */
8263 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8268 rc = bnx2_init_board(pdev, dev);
8274 dev->netdev_ops = &bnx2_netdev_ops;
8275 dev->watchdog_timeo = TX_TIMEOUT;
8276 dev->ethtool_ops = &bnx2_ethtool_ops;
8278 bp = netdev_priv(dev);
8281 pci_set_drvdata(pdev, dev);
8283 rc = bnx2_request_firmware(bp);
8287 memcpy(dev->dev_addr, bp->mac_addr, 6);
8288 memcpy(dev->perm_addr, bp->mac_addr, 6);
8290 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
8291 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8292 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8293 dev->features |= NETIF_F_IPV6_CSUM;
8294 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8297 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8299 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8300 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8301 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8302 dev->features |= NETIF_F_TSO6;
8303 vlan_features_add(dev, NETIF_F_TSO6);
8305 if ((rc = register_netdev(dev))) {
8306 dev_err(&pdev->dev, "Cannot register net device\n");
8310 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8311 board_info[ent->driver_data].name,
8312 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8313 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8314 bnx2_bus_string(bp, str),
8316 bp->pdev->irq, dev->dev_addr);
8321 if (bp->mips_firmware)
8322 release_firmware(bp->mips_firmware);
8323 if (bp->rv2p_firmware)
8324 release_firmware(bp->rv2p_firmware);
8327 iounmap(bp->regview);
8328 pci_release_regions(pdev);
8329 pci_disable_device(pdev);
8330 pci_set_drvdata(pdev, NULL);
8335 static void __devexit
8336 bnx2_remove_one(struct pci_dev *pdev)
8338 struct net_device *dev = pci_get_drvdata(pdev);
8339 struct bnx2 *bp = netdev_priv(dev);
8341 flush_scheduled_work();
8343 unregister_netdev(dev);
8345 if (bp->mips_firmware)
8346 release_firmware(bp->mips_firmware);
8347 if (bp->rv2p_firmware)
8348 release_firmware(bp->rv2p_firmware);
8351 iounmap(bp->regview);
8353 kfree(bp->temp_stats_blk);
8356 pci_release_regions(pdev);
8357 pci_disable_device(pdev);
8358 pci_set_drvdata(pdev, NULL);
8362 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8364 struct net_device *dev = pci_get_drvdata(pdev);
8365 struct bnx2 *bp = netdev_priv(dev);
8367 /* PCI register 4 needs to be saved whether netif_running() or not.
8368 * MSI address and data need to be saved if using MSI and
8371 pci_save_state(pdev);
8372 if (!netif_running(dev))
8375 flush_scheduled_work();
8376 bnx2_netif_stop(bp);
8377 netif_device_detach(dev);
8378 del_timer_sync(&bp->timer);
8379 bnx2_shutdown_chip(bp);
8381 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8386 bnx2_resume(struct pci_dev *pdev)
8388 struct net_device *dev = pci_get_drvdata(pdev);
8389 struct bnx2 *bp = netdev_priv(dev);
8391 pci_restore_state(pdev);
8392 if (!netif_running(dev))
8395 bnx2_set_power_state(bp, PCI_D0);
8396 netif_device_attach(dev);
8397 bnx2_init_nic(bp, 1);
8398 bnx2_netif_start(bp);
8403 * bnx2_io_error_detected - called when PCI error is detected
8404 * @pdev: Pointer to PCI device
8405 * @state: The current pci connection state
8407 * This function is called after a PCI bus error affecting
8408 * this device has been detected.
8410 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8411 pci_channel_state_t state)
8413 struct net_device *dev = pci_get_drvdata(pdev);
8414 struct bnx2 *bp = netdev_priv(dev);
8417 netif_device_detach(dev);
8419 if (state == pci_channel_io_perm_failure) {
8421 return PCI_ERS_RESULT_DISCONNECT;
8424 if (netif_running(dev)) {
8425 bnx2_netif_stop(bp);
8426 del_timer_sync(&bp->timer);
8427 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8430 pci_disable_device(pdev);
8433 /* Request a slot slot reset. */
8434 return PCI_ERS_RESULT_NEED_RESET;
8438 * bnx2_io_slot_reset - called after the pci bus has been reset.
8439 * @pdev: Pointer to PCI device
8441 * Restart the card from scratch, as if from a cold-boot.
8443 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8445 struct net_device *dev = pci_get_drvdata(pdev);
8446 struct bnx2 *bp = netdev_priv(dev);
8449 if (pci_enable_device(pdev)) {
8451 "Cannot re-enable PCI device after reset\n");
8453 return PCI_ERS_RESULT_DISCONNECT;
8455 pci_set_master(pdev);
8456 pci_restore_state(pdev);
8457 pci_save_state(pdev);
8459 if (netif_running(dev)) {
8460 bnx2_set_power_state(bp, PCI_D0);
8461 bnx2_init_nic(bp, 1);
8465 return PCI_ERS_RESULT_RECOVERED;
8469 * bnx2_io_resume - called when traffic can start flowing again.
8470 * @pdev: Pointer to PCI device
8472 * This callback is called when the error recovery driver tells us that
8473 * its OK to resume normal operation.
8475 static void bnx2_io_resume(struct pci_dev *pdev)
8477 struct net_device *dev = pci_get_drvdata(pdev);
8478 struct bnx2 *bp = netdev_priv(dev);
8481 if (netif_running(dev))
8482 bnx2_netif_start(bp);
8484 netif_device_attach(dev);
8488 static struct pci_error_handlers bnx2_err_handler = {
8489 .error_detected = bnx2_io_error_detected,
8490 .slot_reset = bnx2_io_slot_reset,
8491 .resume = bnx2_io_resume,
8494 static struct pci_driver bnx2_pci_driver = {
8495 .name = DRV_MODULE_NAME,
8496 .id_table = bnx2_pci_tbl,
8497 .probe = bnx2_init_one,
8498 .remove = __devexit_p(bnx2_remove_one),
8499 .suspend = bnx2_suspend,
8500 .resume = bnx2_resume,
8501 .err_handler = &bnx2_err_handler,
8504 static int __init bnx2_init(void)
8506 return pci_register_driver(&bnx2_pci_driver);
8509 static void __exit bnx2_cleanup(void)
8511 pci_unregister_driver(&bnx2_pci_driver);
8514 module_init(bnx2_init);
8515 module_exit(bnx2_cleanup);