1 /* bnx2x_init.h: Broadcom Everest network driver.
2 * Structures and macroes needed during the initialization.
4 * Copyright (c) 2007-2009 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
10 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
11 * Written by: Eliezer Tamir
12 * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
18 /* RAM0 size in bytes */
19 #define STORM_INTMEM_SIZE_E1 0x5800
20 #define STORM_INTMEM_SIZE_E1H 0x10000
21 #define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
22 STORM_INTMEM_SIZE_E1H) / 4)
25 /* Init operation types and structures */
26 /* Common for both E1 and E1H */
27 #define OP_RD 0x1 /* read single register */
28 #define OP_WR 0x2 /* write single register */
29 #define OP_IW 0x3 /* write single register using mailbox */
30 #define OP_SW 0x4 /* copy a string to the device */
31 #define OP_SI 0x5 /* copy a string using mailbox */
32 #define OP_ZR 0x6 /* clear memory */
33 #define OP_ZP 0x7 /* unzip then copy with DMAE */
34 #define OP_WR_64 0x8 /* write 64 bit pattern */
35 #define OP_WB 0x9 /* copy a string using DMAE */
37 /* FPGA and EMUL specific operations */
38 #define OP_WR_EMUL 0xa /* write single register on Emulation */
39 #define OP_WR_FPGA 0xb /* write single register on FPGA */
40 #define OP_WR_ASIC 0xc /* write single register on ASIC */
43 /* Never reorder stages !!! */
44 #define COMMON_STAGE 0
54 #define FUNC7_STAGE 10
55 #define STAGE_IDX_MAX 11
61 /* Indices of blocks */
85 #define TIMERS_BLOCK 23
97 #define MISC_AEU_BLOCK 35
98 #define PGLUE_B_BLOCK 36
101 #define QM_4PORT_BLOCK 39
102 #define XSEM_4PORT_BLOCK 40
105 /* Returns the index of start or end of a specific block stage in ops array*/
106 #define BLOCK_OPS_IDX(block, stage, end) \
107 (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
128 struct op_string_write {
131 #ifdef __LITTLE_ENDIAN
134 #else /* __BIG_ENDIAN */
148 struct op_write write;
149 struct op_string_write str_wr;
154 #define INITOP_SET 0 /* set the HW directly */
155 #define INITOP_CLEAR 1 /* clear the HW directly */
156 #define INITOP_INIT 2 /* set the init-value array */
158 /****************************************************************************
160 ****************************************************************************/
162 dma_addr_t page_mapping;
167 struct ilt_client_info {
173 #define ILT_CLIENT_SKIP_INIT 0x1
174 #define ILT_CLIENT_SKIP_MEM 0x2
179 struct ilt_line *lines;
180 struct ilt_client_info clients[4];
181 #define ILT_CLIENT_CDU 0
182 #define ILT_CLIENT_QM 1
183 #define ILT_CLIENT_SRC 2
184 #define ILT_CLIENT_TM 3
187 /****************************************************************************
189 ****************************************************************************/
195 #endif /* BNX2X_INIT_H */