1 /* Copyright 2008-2009 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
29 /********************************************************/
31 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */
32 #define ETH_MIN_PACKET_SIZE 60
33 #define ETH_MAX_PACKET_SIZE 1500
34 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
35 #define MDIO_ACCESS_TIMEOUT 1000
36 #define BMAC_CONTROL_RX_ENABLE 2
38 /***********************************************************/
39 /* Shortcut definitions */
40 /***********************************************************/
42 #define NIG_LATCH_BC_ENABLE_MI_INT 0
44 #define NIG_STATUS_EMAC0_MI_INT \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
46 #define NIG_STATUS_XGXS0_LINK10G \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
48 #define NIG_STATUS_XGXS0_LINK_STATUS \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
50 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
52 #define NIG_STATUS_SERDES0_LINK_STATUS \
53 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
54 #define NIG_MASK_MI_INT \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
56 #define NIG_MASK_XGXS0_LINK10G \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
58 #define NIG_MASK_XGXS0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
60 #define NIG_MASK_SERDES0_LINK_STATUS \
61 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
63 #define MDIO_AN_CL73_OR_37_COMPLETE \
64 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
65 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
67 #define XGXS_RESET_BITS \
68 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
74 #define SERDES_RESET_BITS \
75 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
80 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
82 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83 #define AUTONEG_PARALLEL \
84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
85 #define AUTONEG_SGMII_FIBER_AUTODET \
86 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
87 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
89 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
91 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
93 #define GP_STATUS_SPEED_MASK \
94 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
95 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
96 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
97 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
98 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
99 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
100 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
101 #define GP_STATUS_10G_HIG \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
103 #define GP_STATUS_10G_CX4 \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
105 #define GP_STATUS_12G_HIG \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
107 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
108 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
109 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
110 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
111 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
112 #define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
115 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
122 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
123 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
139 #define PHY_XGXS_FLAG 0x1
140 #define PHY_SGMII_FLAG 0x2
141 #define PHY_SERDES_FLAG 0x4
144 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
145 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
146 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
149 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
150 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
151 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
152 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
154 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
155 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
158 #define SFP_EEPROM_OPTIONS_ADDR 0x40
159 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
160 #define SFP_EEPROM_OPTIONS_SIZE 2
162 #define EDC_MODE_LINEAR 0x0022
163 #define EDC_MODE_LIMITING 0x0044
164 #define EDC_MODE_PASSIVE_DAC 0x0055
168 /**********************************************************/
170 /**********************************************************/
172 #define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
173 bnx2x_cl45_write(_bp, _phy, \
174 (_phy)->def_md_devad, \
175 (_bank + (_addr & 0xf)), \
178 #define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
179 bnx2x_cl45_read(_bp, _phy, \
180 (_phy)->def_md_devad, \
181 (_bank + (_addr & 0xf)), \
184 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
186 u32 val = REG_RD(bp, reg);
189 REG_WR(bp, reg, val);
193 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
195 u32 val = REG_RD(bp, reg);
198 REG_WR(bp, reg, val);
202 static void bnx2x_emac_init(struct link_params *params,
203 struct link_vars *vars)
205 /* reset and unreset the emac core */
206 struct bnx2x *bp = params->bp;
207 u8 port = params->port;
208 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
212 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
213 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
215 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
216 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
218 /* init emac - use read-modify-write */
219 /* self clear reset */
220 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
221 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
225 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
226 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
228 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
232 } while (val & EMAC_MODE_RESET);
234 /* Set mac address */
235 val = ((params->mac_addr[0] << 8) |
236 params->mac_addr[1]);
237 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
239 val = ((params->mac_addr[2] << 24) |
240 (params->mac_addr[3] << 16) |
241 (params->mac_addr[4] << 8) |
242 params->mac_addr[5]);
243 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
246 static u8 bnx2x_emac_enable(struct link_params *params,
247 struct link_vars *vars, u8 lb)
249 struct bnx2x *bp = params->bp;
250 u8 port = params->port;
251 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
254 DP(NETIF_MSG_LINK, "enabling EMAC\n");
256 /* enable emac and not bmac */
257 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
260 if (CHIP_REV_IS_EMUL(bp)) {
261 /* Use lane 1 (of lanes 0-3) */
262 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
263 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
269 if (CHIP_REV_IS_FPGA(bp)) {
270 /* Use lane 1 (of lanes 0-3) */
271 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
273 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
274 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
278 if (vars->phy_flags & PHY_XGXS_FLAG) {
279 u32 ser_lane = ((params->lane_config &
280 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
281 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
283 DP(NETIF_MSG_LINK, "XGXS\n");
284 /* select the master lanes (out of 0-3) */
285 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
288 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
291 } else { /* SerDes */
292 DP(NETIF_MSG_LINK, "SerDes\n");
294 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
298 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
300 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
303 if (CHIP_REV_IS_SLOW(bp)) {
304 /* config GMII mode */
305 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
306 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
307 (val | EMAC_MODE_PORT_GMII));
309 /* pause enable/disable */
310 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
311 EMAC_RX_MODE_FLOW_EN);
312 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
313 bnx2x_bits_en(bp, emac_base +
314 EMAC_REG_EMAC_RX_MODE,
315 EMAC_RX_MODE_FLOW_EN);
317 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
318 (EMAC_TX_MODE_EXT_PAUSE_EN |
319 EMAC_TX_MODE_FLOW_EN));
320 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
321 bnx2x_bits_en(bp, emac_base +
322 EMAC_REG_EMAC_TX_MODE,
323 (EMAC_TX_MODE_EXT_PAUSE_EN |
324 EMAC_TX_MODE_FLOW_EN));
327 /* KEEP_VLAN_TAG, promiscuous */
328 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
329 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
330 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
333 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
338 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
341 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
343 /* enable emac for jumbo packets */
344 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
345 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
346 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
349 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
351 /* disable the NIG in/out to the bmac */
352 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
353 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
354 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
356 /* enable the NIG in/out to the emac */
357 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
359 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
362 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
363 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
365 if (CHIP_REV_IS_EMUL(bp)) {
366 /* take the BigMac out of reset */
368 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
369 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
371 /* enable access for bmac registers */
372 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
374 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
376 vars->mac_type = MAC_TYPE_EMAC;
380 static void bnx2x_update_bmac2(struct link_params *params,
381 struct link_vars *vars,
385 * Set rx control: Strip CRC and enable BigMAC to relay
386 * control packets to the system as well
389 struct bnx2x *bp = params->bp;
390 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
391 NIG_REG_INGRESS_BMAC0_MEM;
394 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
395 /* Enable BigMAC to react on received Pause packets */
399 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL,
405 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
409 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL,
415 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
419 val = 0x3; /* Enable RX and TX */
421 val |= 0x4; /* Local loopback */
422 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
427 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
432 static u8 bnx2x_bmac1_enable(struct link_params *params,
433 struct link_vars *vars,
436 struct bnx2x *bp = params->bp;
437 u8 port = params->port;
438 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
439 NIG_REG_INGRESS_BMAC0_MEM;
443 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
448 REG_WR_DMAE(bp, bmac_addr +
449 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
453 wb_data[0] = ((params->mac_addr[2] << 24) |
454 (params->mac_addr[3] << 16) |
455 (params->mac_addr[4] << 8) |
456 params->mac_addr[5]);
457 wb_data[1] = ((params->mac_addr[0] << 8) |
458 params->mac_addr[1]);
459 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
464 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
468 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
475 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
479 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
483 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
485 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
488 /* rx control set to don't strip crc */
490 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
494 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
498 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
500 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
503 /* set cnt max size */
504 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
506 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
510 wb_data[0] = 0x1000200;
512 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
514 /* fix for emulation */
515 if (CHIP_REV_IS_EMUL(bp)) {
519 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
527 static u8 bnx2x_bmac2_enable(struct link_params *params,
528 struct link_vars *vars,
531 struct bnx2x *bp = params->bp;
532 u8 port = params->port;
533 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
534 NIG_REG_INGRESS_BMAC0_MEM;
537 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
541 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
545 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
548 REG_WR_DMAE(bp, bmac_addr +
549 BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
555 wb_data[0] = ((params->mac_addr[2] << 24) |
556 (params->mac_addr[3] << 16) |
557 (params->mac_addr[4] << 8) |
558 params->mac_addr[5]);
559 wb_data[1] = ((params->mac_addr[0] << 8) |
560 params->mac_addr[1]);
561 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
567 wb_data[0] = 0x1000200;
569 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
574 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
576 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE,
581 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
583 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE,
586 /* set cnt max size */
587 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
589 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE,
592 bnx2x_update_bmac2(params, vars, is_lb);
597 u8 bnx2x_bmac_enable(struct link_params *params,
598 struct link_vars *vars,
601 u8 rc, port = params->port;
602 struct bnx2x *bp = params->bp;
604 /* reset and unreset the BigMac */
605 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
606 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
609 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
610 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
612 /* enable access for bmac registers */
613 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
615 /* Enable BMAC according to BMAC type*/
617 rc = bnx2x_bmac2_enable(params, vars, is_lb);
619 rc = bnx2x_bmac1_enable(params, vars, is_lb);
620 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
621 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
622 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
624 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
626 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
627 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
628 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
629 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
630 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
631 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
633 vars->mac_type = MAC_TYPE_BMAC;
638 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
640 struct bnx2x *bp = params->bp;
642 REG_WR(bp, params->shmem_base +
643 offsetof(struct shmem_region,
644 port_mb[params->port].link_status),
648 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
650 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
651 NIG_REG_INGRESS_BMAC0_MEM;
653 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
655 /* Only if the bmac is out of reset */
656 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
657 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
660 if (CHIP_IS_E2(bp)) {
661 /* Clear Rx Enable bit in BMAC_CONTROL register */
662 REG_RD_DMAE(bp, bmac_addr +
663 BIGMAC2_REGISTER_BMAC_CONTROL,
665 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
666 REG_WR_DMAE(bp, bmac_addr +
667 BIGMAC2_REGISTER_BMAC_CONTROL,
670 /* Clear Rx Enable bit in BMAC_CONTROL register */
671 REG_RD_DMAE(bp, bmac_addr +
672 BIGMAC_REGISTER_BMAC_CONTROL,
674 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
675 REG_WR_DMAE(bp, bmac_addr +
676 BIGMAC_REGISTER_BMAC_CONTROL,
683 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
686 struct bnx2x *bp = params->bp;
687 u8 port = params->port;
692 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
694 /* wait for init credit */
695 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
696 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
697 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
699 while ((init_crd != crd) && count) {
702 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
705 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
706 if (init_crd != crd) {
707 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
712 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
713 line_speed == SPEED_10 ||
714 line_speed == SPEED_100 ||
715 line_speed == SPEED_1000 ||
716 line_speed == SPEED_2500) {
717 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
718 /* update threshold */
719 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
720 /* update init credit */
721 init_crd = 778; /* (800-18-4) */
724 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
726 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
727 /* update threshold */
728 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
729 /* update init credit */
730 switch (line_speed) {
732 init_crd = thresh + 553 - 22;
736 init_crd = thresh + 664 - 22;
740 init_crd = thresh + 742 - 22;
744 init_crd = thresh + 778 - 22;
747 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
752 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
753 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
754 line_speed, init_crd);
756 /* probe the credit changes */
757 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
759 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
762 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
766 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
767 u32 mdc_mdio_access, u8 port)
770 switch (mdc_mdio_access) {
771 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
773 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
774 if (REG_RD(bp, NIG_REG_PORT_SWAP))
775 emac_base = GRCBASE_EMAC1;
777 emac_base = GRCBASE_EMAC0;
779 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
780 if (REG_RD(bp, NIG_REG_PORT_SWAP))
781 emac_base = GRCBASE_EMAC0;
783 emac_base = GRCBASE_EMAC1;
785 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
786 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
788 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
789 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
798 u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
799 u8 devad, u16 reg, u16 val)
804 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
805 * (a value of 49==0x31) and make sure that the AUTO poll is off
808 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
809 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
810 EMAC_MDIO_MODE_CLOCK_CNT);
811 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
812 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
813 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
814 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
819 tmp = ((phy->addr << 21) | (devad << 16) | reg |
820 EMAC_MDIO_COMM_COMMAND_ADDRESS |
821 EMAC_MDIO_COMM_START_BUSY);
822 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
824 for (i = 0; i < 50; i++) {
827 tmp = REG_RD(bp, phy->mdio_ctrl +
828 EMAC_REG_EMAC_MDIO_COMM);
829 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
834 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
835 DP(NETIF_MSG_LINK, "write phy register failed\n");
839 tmp = ((phy->addr << 21) | (devad << 16) | val |
840 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
841 EMAC_MDIO_COMM_START_BUSY);
842 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
844 for (i = 0; i < 50; i++) {
847 tmp = REG_RD(bp, phy->mdio_ctrl +
848 EMAC_REG_EMAC_MDIO_COMM);
849 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
854 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
855 DP(NETIF_MSG_LINK, "write phy register failed\n");
860 /* Restore the saved mode */
861 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
866 u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
867 u8 devad, u16 reg, u16 *ret_val)
873 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
874 * (a value of 49==0x31) and make sure that the AUTO poll is off
877 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
878 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
879 EMAC_MDIO_MODE_CLOCK_CNT));
880 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
881 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
882 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
883 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
887 val = ((phy->addr << 21) | (devad << 16) | reg |
888 EMAC_MDIO_COMM_COMMAND_ADDRESS |
889 EMAC_MDIO_COMM_START_BUSY);
890 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
892 for (i = 0; i < 50; i++) {
895 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
896 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
901 if (val & EMAC_MDIO_COMM_START_BUSY) {
902 DP(NETIF_MSG_LINK, "read phy register failed\n");
909 val = ((phy->addr << 21) | (devad << 16) |
910 EMAC_MDIO_COMM_COMMAND_READ_45 |
911 EMAC_MDIO_COMM_START_BUSY);
912 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
914 for (i = 0; i < 50; i++) {
917 val = REG_RD(bp, phy->mdio_ctrl +
918 EMAC_REG_EMAC_MDIO_COMM);
919 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
920 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
924 if (val & EMAC_MDIO_COMM_START_BUSY) {
925 DP(NETIF_MSG_LINK, "read phy register failed\n");
932 /* Restore the saved mode */
933 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
938 u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
939 u8 devad, u16 reg, u16 *ret_val)
943 * Probe for the phy according to the given phy_addr, and execute
944 * the read request on it
946 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
947 if (params->phy[phy_index].addr == phy_addr) {
948 return bnx2x_cl45_read(params->bp,
949 ¶ms->phy[phy_index], devad,
956 u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
957 u8 devad, u16 reg, u16 val)
961 * Probe for the phy according to the given phy_addr, and execute
962 * the write request on it
964 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
965 if (params->phy[phy_index].addr == phy_addr) {
966 return bnx2x_cl45_write(params->bp,
967 ¶ms->phy[phy_index], devad,
974 static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
975 struct bnx2x_phy *phy)
979 struct bnx2x *bp = params->bp;
980 ser_lane = ((params->lane_config &
981 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
982 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
984 offset = phy->addr + ser_lane;
986 aer_val = 0x2800 + offset - 1;
988 aer_val = 0x3800 + offset;
989 CL45_WR_OVER_CL22(bp, phy,
990 MDIO_REG_BANK_AER_BLOCK,
991 MDIO_AER_BLOCK_AER_REG, aer_val);
993 static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
994 struct bnx2x_phy *phy)
996 CL45_WR_OVER_CL22(bp, phy,
997 MDIO_REG_BANK_AER_BLOCK,
998 MDIO_AER_BLOCK_AER_REG, 0x3800);
1001 /******************************************************************/
1002 /* Internal phy section */
1003 /******************************************************************/
1005 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1007 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1010 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1011 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1013 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1016 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1019 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1023 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1025 val = SERDES_RESET_BITS << (port*16);
1027 /* reset and unreset the SerDes/XGXS */
1028 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1030 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1032 bnx2x_set_serdes_access(bp, port);
1034 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
1036 DEFAULT_PHY_DEV_ADDR);
1039 static void bnx2x_xgxs_deassert(struct link_params *params)
1041 struct bnx2x *bp = params->bp;
1044 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1045 port = params->port;
1047 val = XGXS_RESET_BITS << (port*16);
1049 /* reset and unreset the SerDes/XGXS */
1050 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1052 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1054 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
1056 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1057 params->phy[INT_PHY].def_md_devad);
1061 void bnx2x_link_status_update(struct link_params *params,
1062 struct link_vars *vars)
1064 struct bnx2x *bp = params->bp;
1066 u8 port = params->port;
1068 vars->link_status = REG_RD(bp, params->shmem_base +
1069 offsetof(struct shmem_region,
1070 port_mb[port].link_status));
1072 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1074 if (vars->link_up) {
1075 DP(NETIF_MSG_LINK, "phy link up\n");
1077 vars->phy_link_up = 1;
1078 vars->duplex = DUPLEX_FULL;
1079 switch (vars->link_status &
1080 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1082 vars->duplex = DUPLEX_HALF;
1085 vars->line_speed = SPEED_10;
1089 vars->duplex = DUPLEX_HALF;
1093 vars->line_speed = SPEED_100;
1097 vars->duplex = DUPLEX_HALF;
1100 vars->line_speed = SPEED_1000;
1104 vars->duplex = DUPLEX_HALF;
1107 vars->line_speed = SPEED_2500;
1111 vars->line_speed = SPEED_10000;
1115 vars->line_speed = SPEED_12000;
1119 vars->line_speed = SPEED_12500;
1123 vars->line_speed = SPEED_13000;
1127 vars->line_speed = SPEED_15000;
1131 vars->line_speed = SPEED_16000;
1137 vars->flow_ctrl = 0;
1138 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1139 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1141 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1142 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1144 if (!vars->flow_ctrl)
1145 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1147 if (vars->line_speed &&
1148 ((vars->line_speed == SPEED_10) ||
1149 (vars->line_speed == SPEED_100))) {
1150 vars->phy_flags |= PHY_SGMII_FLAG;
1152 vars->phy_flags &= ~PHY_SGMII_FLAG;
1155 /* anything 10 and over uses the bmac */
1156 link_10g = ((vars->line_speed == SPEED_10000) ||
1157 (vars->line_speed == SPEED_12000) ||
1158 (vars->line_speed == SPEED_12500) ||
1159 (vars->line_speed == SPEED_13000) ||
1160 (vars->line_speed == SPEED_15000) ||
1161 (vars->line_speed == SPEED_16000));
1163 vars->mac_type = MAC_TYPE_BMAC;
1165 vars->mac_type = MAC_TYPE_EMAC;
1167 } else { /* link down */
1168 DP(NETIF_MSG_LINK, "phy link down\n");
1170 vars->phy_link_up = 0;
1172 vars->line_speed = 0;
1173 vars->duplex = DUPLEX_FULL;
1174 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1176 /* indicate no mac active */
1177 vars->mac_type = MAC_TYPE_NONE;
1180 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
1181 vars->link_status, vars->phy_link_up);
1182 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
1183 vars->line_speed, vars->duplex, vars->flow_ctrl);
1187 static void bnx2x_set_master_ln(struct link_params *params,
1188 struct bnx2x_phy *phy)
1190 struct bnx2x *bp = params->bp;
1191 u16 new_master_ln, ser_lane;
1192 ser_lane = ((params->lane_config &
1193 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1194 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1196 /* set the master_ln for AN */
1197 CL45_RD_OVER_CL22(bp, phy,
1198 MDIO_REG_BANK_XGXS_BLOCK2,
1199 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1202 CL45_WR_OVER_CL22(bp, phy,
1203 MDIO_REG_BANK_XGXS_BLOCK2 ,
1204 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1205 (new_master_ln | ser_lane));
1208 static u8 bnx2x_reset_unicore(struct link_params *params,
1209 struct bnx2x_phy *phy,
1212 struct bnx2x *bp = params->bp;
1216 CL45_RD_OVER_CL22(bp, phy,
1217 MDIO_REG_BANK_COMBO_IEEE0,
1218 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1220 /* reset the unicore */
1221 CL45_WR_OVER_CL22(bp, phy,
1222 MDIO_REG_BANK_COMBO_IEEE0,
1223 MDIO_COMBO_IEEE0_MII_CONTROL,
1225 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1227 bnx2x_set_serdes_access(bp, params->port);
1229 /* wait for the reset to self clear */
1230 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1233 /* the reset erased the previous bank value */
1234 CL45_RD_OVER_CL22(bp, phy,
1235 MDIO_REG_BANK_COMBO_IEEE0,
1236 MDIO_COMBO_IEEE0_MII_CONTROL,
1239 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1245 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1250 static void bnx2x_set_swap_lanes(struct link_params *params,
1251 struct bnx2x_phy *phy)
1253 struct bnx2x *bp = params->bp;
1254 /* Each two bits represents a lane number:
1255 No swap is 0123 => 0x1b no need to enable the swap */
1256 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1258 ser_lane = ((params->lane_config &
1259 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1260 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1261 rx_lane_swap = ((params->lane_config &
1262 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1263 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1264 tx_lane_swap = ((params->lane_config &
1265 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1266 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1268 if (rx_lane_swap != 0x1b) {
1269 CL45_WR_OVER_CL22(bp, phy,
1270 MDIO_REG_BANK_XGXS_BLOCK2,
1271 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1273 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1274 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1276 CL45_WR_OVER_CL22(bp, phy,
1277 MDIO_REG_BANK_XGXS_BLOCK2,
1278 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1281 if (tx_lane_swap != 0x1b) {
1282 CL45_WR_OVER_CL22(bp, phy,
1283 MDIO_REG_BANK_XGXS_BLOCK2,
1284 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1286 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1288 CL45_WR_OVER_CL22(bp, phy,
1289 MDIO_REG_BANK_XGXS_BLOCK2,
1290 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1294 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1295 struct link_params *params)
1297 struct bnx2x *bp = params->bp;
1299 CL45_RD_OVER_CL22(bp, phy,
1300 MDIO_REG_BANK_SERDES_DIGITAL,
1301 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1303 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1304 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1306 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1307 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1308 phy->speed_cap_mask, control2);
1309 CL45_WR_OVER_CL22(bp, phy,
1310 MDIO_REG_BANK_SERDES_DIGITAL,
1311 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1314 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1315 (phy->speed_cap_mask &
1316 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1317 DP(NETIF_MSG_LINK, "XGXS\n");
1319 CL45_WR_OVER_CL22(bp, phy,
1320 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1321 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1322 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1324 CL45_RD_OVER_CL22(bp, phy,
1325 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1326 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1331 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1333 CL45_WR_OVER_CL22(bp, phy,
1334 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1335 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1338 /* Disable parallel detection of HiG */
1339 CL45_WR_OVER_CL22(bp, phy,
1340 MDIO_REG_BANK_XGXS_BLOCK2,
1341 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1342 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1343 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1347 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1348 struct link_params *params,
1349 struct link_vars *vars,
1352 struct bnx2x *bp = params->bp;
1356 CL45_RD_OVER_CL22(bp, phy,
1357 MDIO_REG_BANK_COMBO_IEEE0,
1358 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1360 /* CL37 Autoneg Enabled */
1361 if (vars->line_speed == SPEED_AUTO_NEG)
1362 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1363 else /* CL37 Autoneg Disabled */
1364 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1365 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1367 CL45_WR_OVER_CL22(bp, phy,
1368 MDIO_REG_BANK_COMBO_IEEE0,
1369 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1371 /* Enable/Disable Autodetection */
1373 CL45_RD_OVER_CL22(bp, phy,
1374 MDIO_REG_BANK_SERDES_DIGITAL,
1375 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
1376 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1377 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1378 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1379 if (vars->line_speed == SPEED_AUTO_NEG)
1380 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1382 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1384 CL45_WR_OVER_CL22(bp, phy,
1385 MDIO_REG_BANK_SERDES_DIGITAL,
1386 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1388 /* Enable TetonII and BAM autoneg */
1389 CL45_RD_OVER_CL22(bp, phy,
1390 MDIO_REG_BANK_BAM_NEXT_PAGE,
1391 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1393 if (vars->line_speed == SPEED_AUTO_NEG) {
1394 /* Enable BAM aneg Mode and TetonII aneg Mode */
1395 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1396 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1398 /* TetonII and BAM Autoneg Disabled */
1399 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1400 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1402 CL45_WR_OVER_CL22(bp, phy,
1403 MDIO_REG_BANK_BAM_NEXT_PAGE,
1404 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1408 /* Enable Cl73 FSM status bits */
1409 CL45_WR_OVER_CL22(bp, phy,
1410 MDIO_REG_BANK_CL73_USERB0,
1411 MDIO_CL73_USERB0_CL73_UCTRL,
1414 /* Enable BAM Station Manager*/
1415 CL45_WR_OVER_CL22(bp, phy,
1416 MDIO_REG_BANK_CL73_USERB0,
1417 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1418 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1419 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1420 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1422 /* Advertise CL73 link speeds */
1423 CL45_RD_OVER_CL22(bp, phy,
1424 MDIO_REG_BANK_CL73_IEEEB1,
1425 MDIO_CL73_IEEEB1_AN_ADV2,
1427 if (phy->speed_cap_mask &
1428 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1429 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1430 if (phy->speed_cap_mask &
1431 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1432 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1434 CL45_WR_OVER_CL22(bp, phy,
1435 MDIO_REG_BANK_CL73_IEEEB1,
1436 MDIO_CL73_IEEEB1_AN_ADV2,
1439 /* CL73 Autoneg Enabled */
1440 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1442 } else /* CL73 Autoneg Disabled */
1445 CL45_WR_OVER_CL22(bp, phy,
1446 MDIO_REG_BANK_CL73_IEEEB0,
1447 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1450 /* program SerDes, forced speed */
1451 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
1452 struct link_params *params,
1453 struct link_vars *vars)
1455 struct bnx2x *bp = params->bp;
1458 /* program duplex, disable autoneg and sgmii*/
1459 CL45_RD_OVER_CL22(bp, phy,
1460 MDIO_REG_BANK_COMBO_IEEE0,
1461 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1462 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
1463 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1464 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
1465 if (phy->req_duplex == DUPLEX_FULL)
1466 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1467 CL45_WR_OVER_CL22(bp, phy,
1468 MDIO_REG_BANK_COMBO_IEEE0,
1469 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1472 - needed only if the speed is greater than 1G (2.5G or 10G) */
1473 CL45_RD_OVER_CL22(bp, phy,
1474 MDIO_REG_BANK_SERDES_DIGITAL,
1475 MDIO_SERDES_DIGITAL_MISC1, ®_val);
1476 /* clearing the speed value before setting the right speed */
1477 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1479 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1480 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1482 if (!((vars->line_speed == SPEED_1000) ||
1483 (vars->line_speed == SPEED_100) ||
1484 (vars->line_speed == SPEED_10))) {
1486 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1487 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1488 if (vars->line_speed == SPEED_10000)
1490 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1491 if (vars->line_speed == SPEED_13000)
1493 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1496 CL45_WR_OVER_CL22(bp, phy,
1497 MDIO_REG_BANK_SERDES_DIGITAL,
1498 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1502 static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
1503 struct link_params *params)
1505 struct bnx2x *bp = params->bp;
1508 /* configure the 48 bits for BAM AN */
1510 /* set extended capabilities */
1511 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1512 val |= MDIO_OVER_1G_UP1_2_5G;
1513 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1514 val |= MDIO_OVER_1G_UP1_10G;
1515 CL45_WR_OVER_CL22(bp, phy,
1516 MDIO_REG_BANK_OVER_1G,
1517 MDIO_OVER_1G_UP1, val);
1519 CL45_WR_OVER_CL22(bp, phy,
1520 MDIO_REG_BANK_OVER_1G,
1521 MDIO_OVER_1G_UP3, 0x400);
1524 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
1525 struct link_params *params, u16 *ieee_fc)
1527 struct bnx2x *bp = params->bp;
1528 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1529 /* resolve pause mode and advertisement
1530 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1532 switch (phy->req_flow_ctrl) {
1533 case BNX2X_FLOW_CTRL_AUTO:
1534 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
1536 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1539 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1542 case BNX2X_FLOW_CTRL_TX:
1544 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1547 case BNX2X_FLOW_CTRL_RX:
1548 case BNX2X_FLOW_CTRL_BOTH:
1549 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1552 case BNX2X_FLOW_CTRL_NONE:
1554 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1557 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
1560 static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
1561 struct link_params *params,
1564 struct bnx2x *bp = params->bp;
1566 /* for AN, we are always publishing full duplex */
1568 CL45_WR_OVER_CL22(bp, phy,
1569 MDIO_REG_BANK_COMBO_IEEE0,
1570 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
1571 CL45_RD_OVER_CL22(bp, phy,
1572 MDIO_REG_BANK_CL73_IEEEB1,
1573 MDIO_CL73_IEEEB1_AN_ADV1, &val);
1574 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
1575 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
1576 CL45_WR_OVER_CL22(bp, phy,
1577 MDIO_REG_BANK_CL73_IEEEB1,
1578 MDIO_CL73_IEEEB1_AN_ADV1, val);
1581 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
1582 struct link_params *params,
1585 struct bnx2x *bp = params->bp;
1588 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
1589 /* Enable and restart BAM/CL37 aneg */
1592 CL45_RD_OVER_CL22(bp, phy,
1593 MDIO_REG_BANK_CL73_IEEEB0,
1594 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1597 CL45_WR_OVER_CL22(bp, phy,
1598 MDIO_REG_BANK_CL73_IEEEB0,
1599 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1601 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1602 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1605 CL45_RD_OVER_CL22(bp, phy,
1606 MDIO_REG_BANK_COMBO_IEEE0,
1607 MDIO_COMBO_IEEE0_MII_CONTROL,
1610 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1612 CL45_WR_OVER_CL22(bp, phy,
1613 MDIO_REG_BANK_COMBO_IEEE0,
1614 MDIO_COMBO_IEEE0_MII_CONTROL,
1616 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1617 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1621 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
1622 struct link_params *params,
1623 struct link_vars *vars)
1625 struct bnx2x *bp = params->bp;
1628 /* in SGMII mode, the unicore is always slave */
1630 CL45_RD_OVER_CL22(bp, phy,
1631 MDIO_REG_BANK_SERDES_DIGITAL,
1632 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1634 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1635 /* set sgmii mode (and not fiber) */
1636 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1637 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1638 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1639 CL45_WR_OVER_CL22(bp, phy,
1640 MDIO_REG_BANK_SERDES_DIGITAL,
1641 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1644 /* if forced speed */
1645 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
1646 /* set speed, disable autoneg */
1649 CL45_RD_OVER_CL22(bp, phy,
1650 MDIO_REG_BANK_COMBO_IEEE0,
1651 MDIO_COMBO_IEEE0_MII_CONTROL,
1653 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1654 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1655 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1657 switch (vars->line_speed) {
1660 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1664 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1667 /* there is nothing to set for 10M */
1670 /* invalid speed for SGMII */
1671 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1676 /* setting the full duplex */
1677 if (phy->req_duplex == DUPLEX_FULL)
1679 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1680 CL45_WR_OVER_CL22(bp, phy,
1681 MDIO_REG_BANK_COMBO_IEEE0,
1682 MDIO_COMBO_IEEE0_MII_CONTROL,
1685 } else { /* AN mode */
1686 /* enable and restart AN */
1687 bnx2x_restart_autoneg(phy, params, 0);
1696 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1698 switch (pause_result) { /* ASYM P ASYM P */
1699 case 0xb: /* 1 0 1 1 */
1700 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
1703 case 0xe: /* 1 1 1 0 */
1704 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
1707 case 0x5: /* 0 1 0 1 */
1708 case 0x7: /* 0 1 1 1 */
1709 case 0xd: /* 1 1 0 1 */
1710 case 0xf: /* 1 1 1 1 */
1711 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
1717 if (pause_result & (1<<0))
1718 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
1719 if (pause_result & (1<<1))
1720 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
1723 static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
1724 struct link_params *params)
1726 struct bnx2x *bp = params->bp;
1727 u16 pd_10g, status2_1000x;
1728 if (phy->req_line_speed != SPEED_AUTO_NEG)
1730 CL45_RD_OVER_CL22(bp, phy,
1731 MDIO_REG_BANK_SERDES_DIGITAL,
1732 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1734 CL45_RD_OVER_CL22(bp, phy,
1735 MDIO_REG_BANK_SERDES_DIGITAL,
1736 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
1738 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
1739 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
1744 CL45_RD_OVER_CL22(bp, phy,
1745 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1746 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
1749 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
1750 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
1757 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
1758 struct link_params *params,
1759 struct link_vars *vars,
1762 struct bnx2x *bp = params->bp;
1763 u16 ld_pause; /* local driver */
1764 u16 lp_pause; /* link partner */
1767 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1769 /* resolve from gp_status in case of AN complete and not sgmii */
1770 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
1771 vars->flow_ctrl = phy->req_flow_ctrl;
1772 else if (phy->req_line_speed != SPEED_AUTO_NEG)
1773 vars->flow_ctrl = params->req_fc_auto_adv;
1774 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1775 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
1776 if (bnx2x_direct_parallel_detect_used(phy, params)) {
1777 vars->flow_ctrl = params->req_fc_auto_adv;
1781 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1782 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
1783 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
1784 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
1786 CL45_RD_OVER_CL22(bp, phy,
1787 MDIO_REG_BANK_CL73_IEEEB1,
1788 MDIO_CL73_IEEEB1_AN_ADV1,
1790 CL45_RD_OVER_CL22(bp, phy,
1791 MDIO_REG_BANK_CL73_IEEEB1,
1792 MDIO_CL73_IEEEB1_AN_LP_ADV1,
1794 pause_result = (ld_pause &
1795 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
1797 pause_result |= (lp_pause &
1798 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
1800 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
1803 CL45_RD_OVER_CL22(bp, phy,
1804 MDIO_REG_BANK_COMBO_IEEE0,
1805 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1807 CL45_RD_OVER_CL22(bp, phy,
1808 MDIO_REG_BANK_COMBO_IEEE0,
1809 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1811 pause_result = (ld_pause &
1812 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1813 pause_result |= (lp_pause &
1814 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1815 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
1818 bnx2x_pause_resolve(vars, pause_result);
1820 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1823 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
1824 struct link_params *params)
1826 struct bnx2x *bp = params->bp;
1827 u16 rx_status, ustat_val, cl37_fsm_recieved;
1828 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1829 /* Step 1: Make sure signal is detected */
1830 CL45_RD_OVER_CL22(bp, phy,
1834 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
1835 (MDIO_RX0_RX_STATUS_SIGDET)) {
1836 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1837 "rx_status(0x80b0) = 0x%x\n", rx_status);
1838 CL45_WR_OVER_CL22(bp, phy,
1839 MDIO_REG_BANK_CL73_IEEEB0,
1840 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1841 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1844 /* Step 2: Check CL73 state machine */
1845 CL45_RD_OVER_CL22(bp, phy,
1846 MDIO_REG_BANK_CL73_USERB0,
1847 MDIO_CL73_USERB0_CL73_USTAT1,
1850 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1851 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
1852 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1853 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
1854 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
1855 "ustat_val(0x8371) = 0x%x\n", ustat_val);
1858 /* Step 3: Check CL37 Message Pages received to indicate LP
1859 supports only CL37 */
1860 CL45_RD_OVER_CL22(bp, phy,
1861 MDIO_REG_BANK_REMOTE_PHY,
1862 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1863 &cl37_fsm_recieved);
1864 if ((cl37_fsm_recieved &
1865 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1866 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
1867 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1868 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
1869 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
1870 "misc_rx_status(0x8330) = 0x%x\n",
1874 /* The combined cl37/cl73 fsm state information indicating that we are
1875 connected to a device which does not support cl73, but does support
1876 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1878 CL45_WR_OVER_CL22(bp, phy,
1879 MDIO_REG_BANK_CL73_IEEEB0,
1880 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1882 /* Restart CL37 autoneg */
1883 bnx2x_restart_autoneg(phy, params, 0);
1884 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1887 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
1888 struct link_params *params,
1889 struct link_vars *vars,
1892 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1893 vars->link_status |=
1894 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1896 if (bnx2x_direct_parallel_detect_used(phy, params))
1897 vars->link_status |=
1898 LINK_STATUS_PARALLEL_DETECTION_USED;
1901 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
1902 struct link_params *params,
1903 struct link_vars *vars)
1905 struct bnx2x *bp = params->bp;
1906 u16 new_line_speed , gp_status;
1909 /* Read gp_status */
1910 CL45_RD_OVER_CL22(bp, phy,
1911 MDIO_REG_BANK_GP_STATUS,
1912 MDIO_GP_STATUS_TOP_AN_STATUS1,
1915 if (phy->req_line_speed == SPEED_AUTO_NEG)
1916 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1917 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1918 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1921 vars->phy_link_up = 1;
1922 vars->link_status |= LINK_STATUS_LINK_UP;
1924 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1925 vars->duplex = DUPLEX_FULL;
1927 vars->duplex = DUPLEX_HALF;
1929 if (SINGLE_MEDIA_DIRECT(params)) {
1930 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
1931 if (phy->req_line_speed == SPEED_AUTO_NEG)
1932 bnx2x_xgxs_an_resolve(phy, params, vars,
1936 switch (gp_status & GP_STATUS_SPEED_MASK) {
1938 new_line_speed = SPEED_10;
1939 if (vars->duplex == DUPLEX_FULL)
1940 vars->link_status |= LINK_10TFD;
1942 vars->link_status |= LINK_10THD;
1945 case GP_STATUS_100M:
1946 new_line_speed = SPEED_100;
1947 if (vars->duplex == DUPLEX_FULL)
1948 vars->link_status |= LINK_100TXFD;
1950 vars->link_status |= LINK_100TXHD;
1954 case GP_STATUS_1G_KX:
1955 new_line_speed = SPEED_1000;
1956 if (vars->duplex == DUPLEX_FULL)
1957 vars->link_status |= LINK_1000TFD;
1959 vars->link_status |= LINK_1000THD;
1962 case GP_STATUS_2_5G:
1963 new_line_speed = SPEED_2500;
1964 if (vars->duplex == DUPLEX_FULL)
1965 vars->link_status |= LINK_2500TFD;
1967 vars->link_status |= LINK_2500THD;
1973 "link speed unsupported gp_status 0x%x\n",
1977 case GP_STATUS_10G_KX4:
1978 case GP_STATUS_10G_HIG:
1979 case GP_STATUS_10G_CX4:
1980 new_line_speed = SPEED_10000;
1981 vars->link_status |= LINK_10GTFD;
1984 case GP_STATUS_12G_HIG:
1985 new_line_speed = SPEED_12000;
1986 vars->link_status |= LINK_12GTFD;
1989 case GP_STATUS_12_5G:
1990 new_line_speed = SPEED_12500;
1991 vars->link_status |= LINK_12_5GTFD;
1995 new_line_speed = SPEED_13000;
1996 vars->link_status |= LINK_13GTFD;
2000 new_line_speed = SPEED_15000;
2001 vars->link_status |= LINK_15GTFD;
2005 new_line_speed = SPEED_16000;
2006 vars->link_status |= LINK_16GTFD;
2011 "link speed unsupported gp_status 0x%x\n",
2016 vars->line_speed = new_line_speed;
2018 } else { /* link_down */
2019 DP(NETIF_MSG_LINK, "phy link down\n");
2021 vars->phy_link_up = 0;
2023 vars->duplex = DUPLEX_FULL;
2024 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2025 vars->mac_type = MAC_TYPE_NONE;
2027 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2028 SINGLE_MEDIA_DIRECT(params)) {
2029 /* Check signal is detected */
2030 bnx2x_check_fallback_to_cl37(phy, params);
2034 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
2035 gp_status, vars->phy_link_up, vars->line_speed);
2036 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
2037 vars->duplex, vars->flow_ctrl, vars->link_status);
2041 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2043 struct bnx2x *bp = params->bp;
2044 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
2050 CL45_RD_OVER_CL22(bp, phy,
2051 MDIO_REG_BANK_OVER_1G,
2052 MDIO_OVER_1G_LP_UP2, &lp_up2);
2054 /* bits [10:7] at lp_up2, positioned at [15:12] */
2055 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2056 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2057 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2062 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2063 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2064 CL45_RD_OVER_CL22(bp, phy,
2066 MDIO_TX0_TX_DRIVER, &tx_driver);
2068 /* replace tx_driver bits [15:12] */
2070 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2071 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2072 tx_driver |= lp_up2;
2073 CL45_WR_OVER_CL22(bp, phy,
2075 MDIO_TX0_TX_DRIVER, tx_driver);
2080 static u8 bnx2x_emac_program(struct link_params *params,
2081 struct link_vars *vars)
2083 struct bnx2x *bp = params->bp;
2084 u8 port = params->port;
2087 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2088 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2090 (EMAC_MODE_25G_MODE |
2091 EMAC_MODE_PORT_MII_10M |
2092 EMAC_MODE_HALF_DUPLEX));
2093 switch (vars->line_speed) {
2095 mode |= EMAC_MODE_PORT_MII_10M;
2099 mode |= EMAC_MODE_PORT_MII;
2103 mode |= EMAC_MODE_PORT_GMII;
2107 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2111 /* 10G not valid for EMAC */
2112 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2117 if (vars->duplex == DUPLEX_HALF)
2118 mode |= EMAC_MODE_HALF_DUPLEX;
2120 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2123 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2127 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2128 struct link_params *params)
2132 struct bnx2x *bp = params->bp;
2134 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2135 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2136 CL45_WR_OVER_CL22(bp, phy,
2138 MDIO_RX0_RX_EQ_BOOST,
2139 phy->rx_preemphasis[i]);
2142 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2143 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2144 CL45_WR_OVER_CL22(bp, phy,
2147 phy->tx_preemphasis[i]);
2151 static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2152 struct link_params *params,
2153 struct link_vars *vars)
2155 struct bnx2x *bp = params->bp;
2156 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2157 (params->loopback_mode == LOOPBACK_XGXS));
2158 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2159 if (SINGLE_MEDIA_DIRECT(params) &&
2160 (params->feature_config_flags &
2161 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2162 bnx2x_set_preemphasis(phy, params);
2164 /* forced speed requested? */
2165 if (vars->line_speed != SPEED_AUTO_NEG ||
2166 (SINGLE_MEDIA_DIRECT(params) &&
2167 params->loopback_mode == LOOPBACK_EXT)) {
2168 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2170 /* disable autoneg */
2171 bnx2x_set_autoneg(phy, params, vars, 0);
2173 /* program speed and duplex */
2174 bnx2x_program_serdes(phy, params, vars);
2176 } else { /* AN_mode */
2177 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2180 bnx2x_set_brcm_cl37_advertisment(phy, params);
2182 /* program duplex & pause advertisement (for aneg) */
2183 bnx2x_set_ieee_aneg_advertisment(phy, params,
2186 /* enable autoneg */
2187 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2189 /* enable and restart AN */
2190 bnx2x_restart_autoneg(phy, params, enable_cl73);
2193 } else { /* SGMII mode */
2194 DP(NETIF_MSG_LINK, "SGMII\n");
2196 bnx2x_initialize_sgmii_process(phy, params, vars);
2200 static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2201 struct link_params *params,
2202 struct link_vars *vars)
2205 vars->phy_flags |= PHY_SGMII_FLAG;
2206 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2207 bnx2x_set_aer_mmd_serdes(params->bp, phy);
2208 rc = bnx2x_reset_unicore(params, phy, 1);
2209 /* reset the SerDes and wait for reset bit return low */
2212 bnx2x_set_aer_mmd_serdes(params->bp, phy);
2217 static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2218 struct link_params *params,
2219 struct link_vars *vars)
2222 vars->phy_flags = PHY_XGXS_FLAG;
2223 if ((phy->req_line_speed &&
2224 ((phy->req_line_speed == SPEED_100) ||
2225 (phy->req_line_speed == SPEED_10))) ||
2226 (!phy->req_line_speed &&
2227 (phy->speed_cap_mask >=
2228 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2229 (phy->speed_cap_mask <
2230 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2232 vars->phy_flags |= PHY_SGMII_FLAG;
2234 vars->phy_flags &= ~PHY_SGMII_FLAG;
2236 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2237 bnx2x_set_aer_mmd_xgxs(params, phy);
2238 bnx2x_set_master_ln(params, phy);
2240 rc = bnx2x_reset_unicore(params, phy, 0);
2241 /* reset the SerDes and wait for reset bit return low */
2245 bnx2x_set_aer_mmd_xgxs(params, phy);
2247 /* setting the masterLn_def again after the reset */
2248 bnx2x_set_master_ln(params, phy);
2249 bnx2x_set_swap_lanes(params, phy);
2254 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2255 struct bnx2x_phy *phy)
2258 /* Wait for soft reset to get cleared upto 1 sec */
2259 for (cnt = 0; cnt < 1000; cnt++) {
2260 bnx2x_cl45_read(bp, phy,
2261 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2262 if (!(ctrl & (1<<15)))
2266 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2270 static void bnx2x_link_int_enable(struct link_params *params)
2272 u8 port = params->port;
2274 struct bnx2x *bp = params->bp;
2276 /* setting the status to report on link up
2277 for either XGXS or SerDes */
2279 if (params->switch_cfg == SWITCH_CFG_10G) {
2280 mask = (NIG_MASK_XGXS0_LINK10G |
2281 NIG_MASK_XGXS0_LINK_STATUS);
2282 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2283 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2284 params->phy[INT_PHY].type !=
2285 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2286 mask |= NIG_MASK_MI_INT;
2287 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2290 } else { /* SerDes */
2291 mask = NIG_MASK_SERDES0_LINK_STATUS;
2292 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2293 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2294 params->phy[INT_PHY].type !=
2295 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2296 mask |= NIG_MASK_MI_INT;
2297 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2301 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2304 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2305 (params->switch_cfg == SWITCH_CFG_10G),
2306 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2307 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2308 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2309 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2310 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2311 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2312 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2313 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2316 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2319 u32 latch_status = 0;
2322 * Disable the MI INT ( external phy int ) by writing 1 to the
2323 * status register. Link down indication is high-active-signal,
2324 * so in this case we need to write the status to clear the XOR
2326 /* Read Latched signals */
2327 latch_status = REG_RD(bp,
2328 NIG_REG_LATCH_STATUS_0 + port*8);
2329 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
2330 /* Handle only those with latched-signal=up.*/
2333 NIG_REG_STATUS_INTERRUPT_PORT0
2335 NIG_STATUS_EMAC0_MI_INT);
2338 NIG_REG_STATUS_INTERRUPT_PORT0
2340 NIG_STATUS_EMAC0_MI_INT);
2342 if (latch_status & 1) {
2344 /* For all latched-signal=up : Re-Arm Latch signals */
2345 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2346 (latch_status & 0xfffe) | (latch_status & 1));
2348 /* For all latched-signal=up,Write original_signal to status */
2351 static void bnx2x_link_int_ack(struct link_params *params,
2352 struct link_vars *vars, u8 is_10g)
2354 struct bnx2x *bp = params->bp;
2355 u8 port = params->port;
2357 /* first reset all status
2358 * we assume only one line will be change at a time */
2359 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2360 (NIG_STATUS_XGXS0_LINK10G |
2361 NIG_STATUS_XGXS0_LINK_STATUS |
2362 NIG_STATUS_SERDES0_LINK_STATUS));
2363 if (vars->phy_link_up) {
2365 /* Disable the 10G link interrupt
2366 * by writing 1 to the status register
2368 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2370 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2371 NIG_STATUS_XGXS0_LINK10G);
2373 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2374 /* Disable the link interrupt
2375 * by writing 1 to the relevant lane
2376 * in the status register
2378 u32 ser_lane = ((params->lane_config &
2379 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2380 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2382 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2385 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2387 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
2389 } else { /* SerDes */
2390 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2391 /* Disable the link interrupt
2392 * by writing 1 to the status register
2395 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2396 NIG_STATUS_SERDES0_LINK_STATUS);
2402 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2405 u32 mask = 0xf0000000;
2408 u8 remove_leading_zeros = 1;
2410 /* Need more than 10chars for this format */
2418 digit = ((num & mask) >> shift);
2419 if (digit == 0 && remove_leading_zeros) {
2422 } else if (digit < 0xa)
2423 *str_ptr = digit + '0';
2425 *str_ptr = digit - 0xa + 'a';
2426 remove_leading_zeros = 0;
2434 remove_leading_zeros = 1;
2441 static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
2448 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
2449 u8 *version, u16 len)
2454 u8 *ver_p = version;
2455 u16 remain_len = len;
2456 if (version == NULL || params == NULL)
2460 /* Extract first external phy*/
2462 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
2464 if (params->phy[EXT_PHY1].format_fw_ver) {
2465 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
2468 ver_p += (len - remain_len);
2470 if ((params->num_phys == MAX_PHYS) &&
2471 (params->phy[EXT_PHY2].ver_addr != 0)) {
2472 spirom_ver = REG_RD(bp,
2473 params->phy[EXT_PHY2].ver_addr);
2474 if (params->phy[EXT_PHY2].format_fw_ver) {
2478 status |= params->phy[EXT_PHY2].format_fw_ver(
2482 ver_p = version + (len - remain_len);
2489 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
2490 struct link_params *params)
2492 u8 port = params->port;
2493 struct bnx2x *bp = params->bp;
2495 if (phy->req_line_speed != SPEED_1000) {
2498 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
2500 /* change the uni_phy_addr in the nig */
2501 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
2504 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
2506 bnx2x_cl45_write(bp, phy,
2508 (MDIO_REG_BANK_AER_BLOCK +
2509 (MDIO_AER_BLOCK_AER_REG & 0xf)),
2512 bnx2x_cl45_write(bp, phy,
2514 (MDIO_REG_BANK_CL73_IEEEB0 +
2515 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
2518 /* set aer mmd back */
2519 bnx2x_set_aer_mmd_xgxs(params, phy);
2522 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
2527 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
2528 bnx2x_cl45_read(bp, phy, 5,
2529 (MDIO_REG_BANK_COMBO_IEEE0 +
2530 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
2532 bnx2x_cl45_write(bp, phy, 5,
2533 (MDIO_REG_BANK_COMBO_IEEE0 +
2534 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
2536 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
2541 *------------------------------------------------------------------------
2542 * bnx2x_override_led_value -
2544 * Override the led value of the requested led
2546 *------------------------------------------------------------------------
2548 u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
2549 u32 led_idx, u32 value)
2553 /* If port 0 then use EMAC0, else use EMAC1*/
2554 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2557 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
2558 port, led_idx, value);
2561 case 0: /* 10MB led */
2562 /* Read the current value of the LED register in
2564 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2565 /* Set the OVERRIDE bit to 1 */
2566 reg_val |= EMAC_LED_OVERRIDE;
2567 /* If value is 1, set the 10M_OVERRIDE bit,
2568 otherwise reset it.*/
2569 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
2570 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
2571 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2573 case 1: /*100MB led */
2574 /*Read the current value of the LED register in
2576 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2577 /* Set the OVERRIDE bit to 1 */
2578 reg_val |= EMAC_LED_OVERRIDE;
2579 /* If value is 1, set the 100M_OVERRIDE bit,
2580 otherwise reset it.*/
2581 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
2582 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
2583 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2585 case 2: /* 1000MB led */
2586 /* Read the current value of the LED register in the
2588 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2589 /* Set the OVERRIDE bit to 1 */
2590 reg_val |= EMAC_LED_OVERRIDE;
2591 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
2593 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
2594 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
2595 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2597 case 3: /* 2500MB led */
2598 /* Read the current value of the LED register in the
2600 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
2601 /* Set the OVERRIDE bit to 1 */
2602 reg_val |= EMAC_LED_OVERRIDE;
2603 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
2605 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
2606 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
2607 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2609 case 4: /*10G led */
2611 REG_WR(bp, NIG_REG_LED_10G_P0,
2614 REG_WR(bp, NIG_REG_LED_10G_P1,
2618 case 5: /* TRAFFIC led */
2619 /* Find if the traffic control is via BMAC or EMAC */
2621 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
2623 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
2625 /* Override the traffic led in the EMAC:*/
2627 /* Read the current value of the LED register in
2629 reg_val = REG_RD(bp, emac_base +
2631 /* Set the TRAFFIC_OVERRIDE bit to 1 */
2632 reg_val |= EMAC_LED_OVERRIDE;
2633 /* If value is 1, set the TRAFFIC bit, otherwise
2635 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
2636 (reg_val & ~EMAC_LED_TRAFFIC);
2637 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
2638 } else { /* Override the traffic led in the BMAC: */
2639 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
2641 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
2647 "bnx2x_override_led_value() unknown led index %d "
2648 "(should be 0-5)\n", led_idx);
2656 u8 bnx2x_set_led(struct link_params *params,
2657 struct link_vars *vars, u8 mode, u32 speed)
2659 u8 port = params->port;
2660 u16 hw_led_mode = params->hw_led_mode;
2663 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2664 struct bnx2x *bp = params->bp;
2665 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
2666 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
2667 speed, hw_led_mode);
2669 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
2670 if (params->phy[phy_idx].set_link_led) {
2671 params->phy[phy_idx].set_link_led(
2672 ¶ms->phy[phy_idx], params, mode);
2677 case LED_MODE_FRONT_PANEL_OFF:
2679 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
2680 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
2681 SHARED_HW_CFG_LED_MAC1);
2683 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
2684 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
2689 * For all other phys, OPER mode is same as ON, so in case
2690 * link is down, do nothing
2695 if (SINGLE_MEDIA_DIRECT(params)) {
2697 * This is a work-around for HW issue found when link
2700 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
2701 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
2703 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
2707 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
2709 /* Set blinking rate to ~15.9Hz */
2710 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
2711 LED_BLINK_RATE_VAL);
2712 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
2714 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
2715 EMAC_WR(bp, EMAC_REG_EMAC_LED,
2716 (tmp & (~EMAC_LED_OVERRIDE)));
2718 if (CHIP_IS_E1(bp) &&
2719 ((speed == SPEED_2500) ||
2720 (speed == SPEED_1000) ||
2721 (speed == SPEED_100) ||
2722 (speed == SPEED_10))) {
2723 /* On Everest 1 Ax chip versions for speeds less than
2724 10G LED scheme is different */
2725 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
2727 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
2729 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
2736 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
2745 * This function comes to reflect the actual link state read DIRECTLY from the
2748 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
2751 struct bnx2x *bp = params->bp;
2752 u16 gp_status = 0, phy_index = 0;
2753 u8 ext_phy_link_up = 0, serdes_phy_type;
2754 struct link_vars temp_vars;
2756 CL45_RD_OVER_CL22(bp, ¶ms->phy[INT_PHY],
2757 MDIO_REG_BANK_GP_STATUS,
2758 MDIO_GP_STATUS_TOP_AN_STATUS1,
2760 /* link is up only if both local phy and external phy are up */
2761 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
2764 switch (params->num_phys) {
2766 /* No external PHY */
2769 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
2770 ¶ms->phy[EXT_PHY1],
2771 params, &temp_vars);
2773 case 3: /* Dual Media */
2774 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
2776 serdes_phy_type = ((params->phy[phy_index].media_type ==
2777 ETH_PHY_SFP_FIBER) ||
2778 (params->phy[phy_index].media_type ==
2779 ETH_PHY_XFP_FIBER));
2781 if (is_serdes != serdes_phy_type)
2783 if (params->phy[phy_index].read_status) {
2785 params->phy[phy_index].read_status(
2786 ¶ms->phy[phy_index],
2787 params, &temp_vars);
2792 if (ext_phy_link_up)
2797 static u8 bnx2x_link_initialize(struct link_params *params,
2798 struct link_vars *vars)
2801 u8 phy_index, non_ext_phy;
2802 struct bnx2x *bp = params->bp;
2804 * In case of external phy existence, the line speed would be the
2805 * line speed linked up by the external phy. In case it is direct
2806 * only, then the line_speed during initialization will be
2807 * equal to the req_line_speed
2809 vars->line_speed = params->phy[INT_PHY].req_line_speed;
2812 * Initialize the internal phy in case this is a direct board
2813 * (no external phys), or this board has external phy which requires
2817 if (params->phy[INT_PHY].config_init)
2818 params->phy[INT_PHY].config_init(
2819 ¶ms->phy[INT_PHY],
2822 /* init ext phy and enable link state int */
2823 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
2824 (params->loopback_mode == LOOPBACK_XGXS));
2827 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
2828 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
2829 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
2830 if (vars->line_speed == SPEED_AUTO_NEG)
2831 bnx2x_set_parallel_detection(phy, params);
2832 bnx2x_init_internal_phy(phy, params, vars);
2835 /* Init external phy*/
2837 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
2840 * No need to initialize second phy in case of first
2841 * phy only selection. In case of second phy, we do
2842 * need to initialize the first phy, since they are
2845 if (phy_index == EXT_PHY2 &&
2846 (bnx2x_phy_selection(params) ==
2847 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
2848 DP(NETIF_MSG_LINK, "Not initializing"
2852 params->phy[phy_index].config_init(
2853 ¶ms->phy[phy_index],
2857 /* Reset the interrupt indication after phy was initialized */
2858 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
2860 (NIG_STATUS_XGXS0_LINK10G |
2861 NIG_STATUS_XGXS0_LINK_STATUS |
2862 NIG_STATUS_SERDES0_LINK_STATUS |
2867 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
2868 struct link_params *params)
2870 /* reset the SerDes/XGXS */
2871 REG_WR(params->bp, GRCBASE_MISC +
2872 MISC_REGISTERS_RESET_REG_3_CLEAR,
2873 (0x1ff << (params->port*16)));
2876 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
2877 struct link_params *params)
2879 struct bnx2x *bp = params->bp;
2883 gpio_port = BP_PATH(bp);
2885 gpio_port = params->port;
2886 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2887 MISC_REGISTERS_GPIO_OUTPUT_LOW,
2889 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2890 MISC_REGISTERS_GPIO_OUTPUT_LOW,
2892 DP(NETIF_MSG_LINK, "reset external PHY\n");
2895 static u8 bnx2x_update_link_down(struct link_params *params,
2896 struct link_vars *vars)
2898 struct bnx2x *bp = params->bp;
2899 u8 port = params->port;
2901 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
2902 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
2904 /* indicate no mac active */
2905 vars->mac_type = MAC_TYPE_NONE;
2907 /* update shared memory */
2908 vars->link_status = 0;
2909 vars->line_speed = 0;
2910 bnx2x_update_mng(params, vars->link_status);
2912 /* activate nig drain */
2913 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
2916 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
2921 bnx2x_bmac_rx_disable(bp, params->port);
2922 REG_WR(bp, GRCBASE_MISC +
2923 MISC_REGISTERS_RESET_REG_2_CLEAR,
2924 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2928 static u8 bnx2x_update_link_up(struct link_params *params,
2929 struct link_vars *vars,
2932 struct bnx2x *bp = params->bp;
2933 u8 port = params->port;
2936 vars->link_status |= LINK_STATUS_LINK_UP;
2938 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
2939 vars->link_status |=
2940 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
2942 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
2943 vars->link_status |=
2944 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
2947 bnx2x_bmac_enable(params, vars, 0);
2948 bnx2x_set_led(params, vars,
2949 LED_MODE_OPER, SPEED_10000);
2951 rc = bnx2x_emac_program(params, vars);
2953 bnx2x_emac_enable(params, vars, 0);
2956 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
2957 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
2958 SINGLE_MEDIA_DIRECT(params))
2959 bnx2x_set_gmii_tx_driver(params);
2963 if (!(CHIP_IS_E2(bp)))
2964 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
2968 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
2970 /* update shared memory */
2971 bnx2x_update_mng(params, vars->link_status);
2976 * The bnx2x_link_update function should be called upon link
2978 * Link is considered up as follows:
2979 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
2981 * - SINGLE_MEDIA - The link between the 577xx and the external
2982 * phy (XGXS) need to up as well as the external link of the
2984 * - DUAL_MEDIA - The link between the 577xx and the first
2985 * external phy needs to be up, and at least one of the 2
2986 * external phy link must be up.
2988 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
2990 struct bnx2x *bp = params->bp;
2991 struct link_vars phy_vars[MAX_PHYS];
2992 u8 port = params->port;
2993 u8 link_10g, phy_index;
2994 u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
2996 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
2997 u8 active_external_phy = INT_PHY;
2998 vars->link_status = 0;
2999 for (phy_index = INT_PHY; phy_index < params->num_phys;
3001 phy_vars[phy_index].flow_ctrl = 0;
3002 phy_vars[phy_index].link_status = 0;
3003 phy_vars[phy_index].line_speed = 0;
3004 phy_vars[phy_index].duplex = DUPLEX_FULL;
3005 phy_vars[phy_index].phy_link_up = 0;
3006 phy_vars[phy_index].link_up = 0;
3009 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3010 port, (vars->phy_flags & PHY_XGXS_FLAG),
3011 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3013 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3015 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3016 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3019 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3021 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3022 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3023 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3026 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3030 * Check external link change only for external phys, and apply
3031 * priority selection between them in case the link on both phys
3032 * is up. Note that the instead of the common vars, a temporary
3033 * vars argument is used since each phy may have different link/
3034 * speed/duplex result
3036 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3038 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
3039 if (!phy->read_status)
3041 /* Read link status and params of this ext phy */
3042 cur_link_up = phy->read_status(phy, params,
3043 &phy_vars[phy_index]);
3045 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3048 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3053 if (!ext_phy_link_up) {
3054 ext_phy_link_up = 1;
3055 active_external_phy = phy_index;
3057 switch (bnx2x_phy_selection(params)) {
3058 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3059 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3061 * In this option, the first PHY makes sure to pass the
3062 * traffic through itself only.
3063 * Its not clear how to reset the link on the second phy
3065 active_external_phy = EXT_PHY1;
3067 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3069 * In this option, the first PHY makes sure to pass the
3070 * traffic through the second PHY.
3072 active_external_phy = EXT_PHY2;
3076 * Link indication on both PHYs with the following cases
3078 * - FIRST_PHY means that second phy wasn't initialized,
3079 * hence its link is expected to be down
3080 * - SECOND_PHY means that first phy should not be able
3081 * to link up by itself (using configuration)
3082 * - DEFAULT should be overriden during initialiazation
3084 DP(NETIF_MSG_LINK, "Invalid link indication"
3085 "mpc=0x%x. DISABLING LINK !!!\n",
3086 params->multi_phy_config);
3087 ext_phy_link_up = 0;
3092 prev_line_speed = vars->line_speed;
3095 * Read the status of the internal phy. In case of
3096 * DIRECT_SINGLE_MEDIA board, this link is the external link,
3097 * otherwise this is the link between the 577xx and the first
3100 if (params->phy[INT_PHY].read_status)
3101 params->phy[INT_PHY].read_status(
3102 ¶ms->phy[INT_PHY],
3105 * The INT_PHY flow control reside in the vars. This include the
3106 * case where the speed or flow control are not set to AUTO.
3107 * Otherwise, the active external phy flow control result is set
3108 * to the vars. The ext_phy_line_speed is needed to check if the
3109 * speed is different between the internal phy and external phy.
3110 * This case may be result of intermediate link speed change.
3112 if (active_external_phy > INT_PHY) {
3113 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3115 * Link speed is taken from the XGXS. AN and FC result from
3118 vars->link_status |= phy_vars[active_external_phy].link_status;
3121 * if active_external_phy is first PHY and link is up - disable
3122 * disable TX on second external PHY
3124 if (active_external_phy == EXT_PHY1) {
3125 if (params->phy[EXT_PHY2].phy_specific_func) {
3126 DP(NETIF_MSG_LINK, "Disabling TX on"
3128 params->phy[EXT_PHY2].phy_specific_func(
3129 ¶ms->phy[EXT_PHY2],
3130 params, DISABLE_TX);
3134 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3135 vars->duplex = phy_vars[active_external_phy].duplex;
3136 if (params->phy[active_external_phy].supported &
3138 vars->link_status |= LINK_STATUS_SERDES_LINK;
3139 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3140 active_external_phy);
3143 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3145 if (params->phy[phy_index].flags &
3146 FLAGS_REARM_LATCH_SIGNAL) {
3147 bnx2x_rearm_latch_signal(bp, port,
3149 active_external_phy);
3153 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3154 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3155 vars->link_status, ext_phy_line_speed);
3157 * Upon link speed change set the NIG into drain mode. Comes to
3158 * deals with possible FIFO glitch due to clk change when speed
3159 * is decreased without link down indicator
3162 if (vars->phy_link_up) {
3163 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3164 (ext_phy_line_speed != vars->line_speed)) {
3165 DP(NETIF_MSG_LINK, "Internal link speed %d is"
3166 " different than the external"
3167 " link speed %d\n", vars->line_speed,
3168 ext_phy_line_speed);
3169 vars->phy_link_up = 0;
3170 } else if (prev_line_speed != vars->line_speed) {
3171 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3172 + params->port*4, 0);
3177 /* anything 10 and over uses the bmac */
3178 link_10g = ((vars->line_speed == SPEED_10000) ||
3179 (vars->line_speed == SPEED_12000) ||
3180 (vars->line_speed == SPEED_12500) ||
3181 (vars->line_speed == SPEED_13000) ||
3182 (vars->line_speed == SPEED_15000) ||
3183 (vars->line_speed == SPEED_16000));
3185 bnx2x_link_int_ack(params, vars, link_10g);
3188 * In case external phy link is up, and internal link is down
3189 * (not initialized yet probably after link initialization, it
3190 * needs to be initialized.
3191 * Note that after link down-up as result of cable plug, the xgxs
3192 * link would probably become up again without the need
3195 if (!(SINGLE_MEDIA_DIRECT(params))) {
3196 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3197 " init_preceding = %d\n", ext_phy_link_up,
3199 params->phy[EXT_PHY1].flags &
3200 FLAGS_INIT_XGXS_FIRST);
3201 if (!(params->phy[EXT_PHY1].flags &
3202 FLAGS_INIT_XGXS_FIRST)
3203 && ext_phy_link_up && !vars->phy_link_up) {
3204 vars->line_speed = ext_phy_line_speed;
3205 if (vars->line_speed < SPEED_1000)
3206 vars->phy_flags |= PHY_SGMII_FLAG;
3208 vars->phy_flags &= ~PHY_SGMII_FLAG;
3209 bnx2x_init_internal_phy(¶ms->phy[INT_PHY],
3215 * Link is up only if both local phy and external phy (in case of
3216 * non-direct board) are up
3218 vars->link_up = (vars->phy_link_up &&
3220 SINGLE_MEDIA_DIRECT(params)));
3223 rc = bnx2x_update_link_up(params, vars, link_10g);
3225 rc = bnx2x_update_link_down(params, vars);
3231 /*****************************************************************************/
3232 /* External Phy section */
3233 /*****************************************************************************/
3234 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3236 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3237 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3239 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3240 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3243 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3244 u32 spirom_ver, u32 ver_addr)
3246 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3247 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3250 REG_WR(bp, ver_addr, spirom_ver);
3253 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3254 struct bnx2x_phy *phy,
3257 u16 fw_ver1, fw_ver2;
3259 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3260 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3261 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3262 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3263 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3267 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3268 struct bnx2x_phy *phy,
3269 struct link_vars *vars)
3272 struct bnx2x *bp = params->bp;
3273 /* read modify write pause advertizing */
3274 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3276 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3278 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3279 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3280 if ((vars->ieee_fc &
3281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3282 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3283 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3285 if ((vars->ieee_fc &
3286 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3287 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3288 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3290 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3291 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3294 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3295 struct link_params *params,
3296 struct link_vars *vars)
3298 struct bnx2x *bp = params->bp;
3299 u16 ld_pause; /* local */
3300 u16 lp_pause; /* link partner */
3305 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3307 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3308 vars->flow_ctrl = phy->req_flow_ctrl;
3309 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3310 vars->flow_ctrl = params->req_fc_auto_adv;
3311 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3313 bnx2x_cl45_read(bp, phy,
3315 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3316 bnx2x_cl45_read(bp, phy,
3318 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3319 pause_result = (ld_pause &
3320 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3321 pause_result |= (lp_pause &
3322 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3323 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3325 bnx2x_pause_resolve(vars, pause_result);
3330 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3331 struct bnx2x_phy *phy,
3332 struct link_vars *vars)
3335 bnx2x_cl45_read(bp, phy,
3337 MDIO_AN_REG_STATUS, &val);
3338 bnx2x_cl45_read(bp, phy,
3340 MDIO_AN_REG_STATUS, &val);
3342 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3343 if ((val & (1<<0)) == 0)
3344 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3347 /******************************************************************/
3348 /* common BCM8073/BCM8727 PHY SECTION */
3349 /******************************************************************/
3350 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3351 struct link_params *params,
3352 struct link_vars *vars)
3354 struct bnx2x *bp = params->bp;
3355 if (phy->req_line_speed == SPEED_10 ||
3356 phy->req_line_speed == SPEED_100) {
3357 vars->flow_ctrl = phy->req_flow_ctrl;
3361 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3362 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3364 u16 ld_pause; /* local */
3365 u16 lp_pause; /* link partner */
3366 bnx2x_cl45_read(bp, phy,
3368 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3370 bnx2x_cl45_read(bp, phy,
3372 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3373 pause_result = (ld_pause &
3374 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3375 pause_result |= (lp_pause &
3376 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3378 bnx2x_pause_resolve(vars, pause_result);
3379 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3384 static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3385 struct bnx2x_phy *phy,
3388 /* Boot port from external ROM */
3390 bnx2x_cl45_write(bp, phy,
3392 MDIO_PMA_REG_GEN_CTRL,
3395 /* ucode reboot and rst */
3396 bnx2x_cl45_write(bp, phy,
3398 MDIO_PMA_REG_GEN_CTRL,
3401 bnx2x_cl45_write(bp, phy,
3403 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3405 /* Reset internal microprocessor */
3406 bnx2x_cl45_write(bp, phy,
3408 MDIO_PMA_REG_GEN_CTRL,
3409 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3411 /* Release srst bit */
3412 bnx2x_cl45_write(bp, phy,
3414 MDIO_PMA_REG_GEN_CTRL,
3415 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3417 /* wait for 120ms for code download via SPI port */
3420 /* Clear ser_boot_ctl bit */
3421 bnx2x_cl45_write(bp, phy,
3423 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3424 bnx2x_save_bcm_spirom_ver(bp, phy, port);
3427 static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3428 struct bnx2x_phy *phy)
3431 bnx2x_cl45_read(bp, phy,
3432 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
3435 /* Mustn't set low power mode in 8073 A0 */
3439 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3440 bnx2x_cl45_read(bp, phy,
3441 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3443 bnx2x_cl45_write(bp, phy,
3444 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3447 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
3448 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
3449 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
3450 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
3451 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
3454 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3455 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
3456 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
3459 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3460 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
3461 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
3463 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3464 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3466 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3469 /******************************************************************/
3470 /* BCM8073 PHY SECTION */
3471 /******************************************************************/
3472 static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3474 /* This is only required for 8073A1, version 102 only */
3477 /* Read 8073 HW revision*/
3478 bnx2x_cl45_read(bp, phy,
3480 MDIO_PMA_REG_8073_CHIP_REV, &val);
3483 /* No need to workaround in 8073 A1 */
3487 bnx2x_cl45_read(bp, phy,
3489 MDIO_PMA_REG_ROM_VER2, &val);
3491 /* SNR should be applied only for version 0x102 */
3498 static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3500 u16 val, cnt, cnt1 ;
3502 bnx2x_cl45_read(bp, phy,
3504 MDIO_PMA_REG_8073_CHIP_REV, &val);
3507 /* No need to workaround in 8073 A1 */
3510 /* XAUI workaround in 8073 A0: */
3512 /* After loading the boot ROM and restarting Autoneg,
3513 poll Dev1, Reg $C820: */
3515 for (cnt = 0; cnt < 1000; cnt++) {
3516 bnx2x_cl45_read(bp, phy,
3518 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3520 /* If bit [14] = 0 or bit [13] = 0, continue on with
3521 system initialization (XAUI work-around not required,
3522 as these bits indicate 2.5G or 1G link up). */
3523 if (!(val & (1<<14)) || !(val & (1<<13))) {
3524 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
3526 } else if (!(val & (1<<15))) {
3527 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
3528 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
3529 it's MSB (bit 15) goes to 1 (indicating that the
3530 XAUI workaround has completed),
3531 then continue on with system initialization.*/
3532 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
3533 bnx2x_cl45_read(bp, phy,
3535 MDIO_PMA_REG_8073_XAUI_WA, &val);
3536 if (val & (1<<15)) {
3538 "XAUI workaround has completed\n");
3547 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
3551 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
3553 /* Force KR or KX */
3554 bnx2x_cl45_write(bp, phy,
3555 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
3556 bnx2x_cl45_write(bp, phy,
3557 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
3558 bnx2x_cl45_write(bp, phy,
3559 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
3560 bnx2x_cl45_write(bp, phy,
3561 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
3564 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3565 struct bnx2x_phy *phy,
3566 struct link_vars *vars)
3569 struct bnx2x *bp = params->bp;
3570 bnx2x_cl45_read(bp, phy,
3571 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3573 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3574 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3575 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3576 if ((vars->ieee_fc &
3577 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3578 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3579 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3581 if ((vars->ieee_fc &
3582 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3583 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3584 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3586 if ((vars->ieee_fc &
3587 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3588 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3589 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3592 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3594 bnx2x_cl45_write(bp, phy,
3595 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
3599 static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
3600 struct link_params *params,
3601 struct link_vars *vars)
3603 struct bnx2x *bp = params->bp;
3606 DP(NETIF_MSG_LINK, "Init 8073\n");
3609 gpio_port = BP_PATH(bp);
3611 gpio_port = params->port;
3612 /* Restore normal power mode*/
3613 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3614 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
3616 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3617 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
3620 bnx2x_cl45_write(bp, phy,
3621 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
3622 bnx2x_cl45_write(bp, phy,
3623 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
3625 bnx2x_8073_set_pause_cl37(params, phy, vars);
3627 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
3629 bnx2x_cl45_read(bp, phy,
3630 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
3632 bnx2x_cl45_read(bp, phy,
3633 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
3635 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
3637 /* Enable CL37 BAM */
3638 bnx2x_cl45_read(bp, phy,
3640 MDIO_AN_REG_8073_BAM, &val);
3641 bnx2x_cl45_write(bp, phy,
3643 MDIO_AN_REG_8073_BAM, val | 1);
3645 if (params->loopback_mode == LOOPBACK_EXT) {
3646 bnx2x_807x_force_10G(bp, phy);
3647 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
3650 bnx2x_cl45_write(bp, phy,
3651 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
3653 if (phy->req_line_speed != SPEED_AUTO_NEG) {
3654 if (phy->req_line_speed == SPEED_10000) {
3656 } else if (phy->req_line_speed == SPEED_2500) {
3658 /* Note that 2.5G works only
3659 when used with 1G advertisment */
3664 if (phy->speed_cap_mask &
3665 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3668 /* Note that 2.5G works only when
3669 used with 1G advertisment */
3670 if (phy->speed_cap_mask &
3671 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3672 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
3674 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
3677 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
3678 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
3680 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
3681 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
3682 (phy->req_line_speed == SPEED_2500)) {
3684 /* Allow 2.5G for A1 and above */
3685 bnx2x_cl45_read(bp, phy,
3686 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
3688 DP(NETIF_MSG_LINK, "Add 2.5G\n");
3694 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
3698 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
3699 /* Add support for CL37 (passive mode) II */
3701 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
3702 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
3703 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
3706 /* Add support for CL37 (passive mode) III */
3707 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
3709 /* The SNR will improve about 2db by changing
3710 BW and FEE main tap. Rest commands are executed
3712 if (bnx2x_8073_is_snr_needed(bp, phy))
3713 bnx2x_cl45_write(bp, phy,
3714 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
3717 /* Enable FEC (Forware Error Correction) Request in the AN */
3718 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
3720 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
3722 bnx2x_ext_phy_set_pause(params, phy, vars);
3724 /* Restart autoneg */
3726 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3727 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
3728 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
3732 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
3733 struct link_params *params,
3734 struct link_vars *vars)
3736 struct bnx2x *bp = params->bp;
3739 u16 link_status = 0;
3740 u16 an1000_status = 0;
3742 bnx2x_cl45_read(bp, phy,
3743 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
3745 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
3747 /* clear the interrupt LASI status register */
3748 bnx2x_cl45_read(bp, phy,
3749 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
3750 bnx2x_cl45_read(bp, phy,
3751 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
3752 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
3754 bnx2x_cl45_read(bp, phy,
3755 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
3757 /* Check the LASI */
3758 bnx2x_cl45_read(bp, phy,
3759 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
3761 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
3763 /* Check the link status */
3764 bnx2x_cl45_read(bp, phy,
3765 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
3766 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
3768 bnx2x_cl45_read(bp, phy,
3769 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
3770 bnx2x_cl45_read(bp, phy,
3771 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
3772 link_up = ((val1 & 4) == 4);
3773 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
3776 ((phy->req_line_speed != SPEED_10000))) {
3777 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
3780 bnx2x_cl45_read(bp, phy,
3781 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
3782 bnx2x_cl45_read(bp, phy,
3783 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
3785 /* Check the link status on 1.1.2 */
3786 bnx2x_cl45_read(bp, phy,
3787 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
3788 bnx2x_cl45_read(bp, phy,
3789 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
3790 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
3791 "an_link_status=0x%x\n", val2, val1, an1000_status);
3793 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
3794 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
3795 /* The SNR will improve about 2dbby
3796 changing the BW and FEE main tap.*/
3797 /* The 1st write to change FFE main
3798 tap is set before restart AN */
3799 /* Change PLL Bandwidth in EDC
3801 bnx2x_cl45_write(bp, phy,
3802 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
3805 /* Change CDR Bandwidth in EDC register */
3806 bnx2x_cl45_write(bp, phy,
3807 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
3810 bnx2x_cl45_read(bp, phy,
3811 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3814 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
3815 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
3817 vars->line_speed = SPEED_10000;
3818 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
3820 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
3822 vars->line_speed = SPEED_2500;
3823 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
3825 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
3827 vars->line_speed = SPEED_1000;
3828 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
3832 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
3837 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
3838 bnx2x_8073_resolve_fc(phy, params, vars);
3843 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
3844 struct link_params *params)
3846 struct bnx2x *bp = params->bp;
3849 gpio_port = BP_PATH(bp);
3851 gpio_port = params->port;
3852 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
3854 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3855 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3859 /******************************************************************/
3860 /* BCM8705 PHY SECTION */
3861 /******************************************************************/
3862 static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
3863 struct link_params *params,
3864 struct link_vars *vars)
3866 struct bnx2x *bp = params->bp;
3867 DP(NETIF_MSG_LINK, "init 8705\n");
3868 /* Restore normal power mode*/
3869 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3870 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3872 bnx2x_ext_phy_hw_reset(bp, params->port);
3873 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
3874 bnx2x_wait_reset_complete(bp, phy);
3876 bnx2x_cl45_write(bp, phy,
3877 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
3878 bnx2x_cl45_write(bp, phy,
3879 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
3880 bnx2x_cl45_write(bp, phy,
3881 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
3882 bnx2x_cl45_write(bp, phy,
3883 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
3884 /* BCM8705 doesn't have microcode, hence the 0 */
3885 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
3889 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
3890 struct link_params *params,
3891 struct link_vars *vars)
3895 struct bnx2x *bp = params->bp;
3896 DP(NETIF_MSG_LINK, "read status 8705\n");
3897 bnx2x_cl45_read(bp, phy,
3898 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
3899 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
3901 bnx2x_cl45_read(bp, phy,
3902 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
3903 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
3905 bnx2x_cl45_read(bp, phy,
3906 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
3908 bnx2x_cl45_read(bp, phy,
3909 MDIO_PMA_DEVAD, 0xc809, &val1);
3910 bnx2x_cl45_read(bp, phy,
3911 MDIO_PMA_DEVAD, 0xc809, &val1);
3913 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
3914 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
3916 vars->line_speed = SPEED_10000;
3917 bnx2x_ext_phy_resolve_fc(phy, params, vars);
3922 /******************************************************************/
3923 /* SFP+ module Section */
3924 /******************************************************************/
3925 static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
3926 struct bnx2x_phy *phy,
3932 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
3934 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
3935 bnx2x_cl45_read(bp, phy,
3937 MDIO_PMA_REG_PHY_IDENTIFIER,
3945 bnx2x_cl45_write(bp, phy,
3947 MDIO_PMA_REG_PHY_IDENTIFIER,
3951 static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
3952 struct link_params *params,
3953 u16 addr, u8 byte_cnt, u8 *o_buf)
3955 struct bnx2x *bp = params->bp;
3958 if (byte_cnt > 16) {
3959 DP(NETIF_MSG_LINK, "Reading from eeprom is"
3960 " is limited to 0xf\n");
3963 /* Set the read command byte count */
3964 bnx2x_cl45_write(bp, phy,
3965 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
3966 (byte_cnt | 0xa000));
3968 /* Set the read command address */
3969 bnx2x_cl45_write(bp, phy,
3970 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
3973 /* Activate read command */
3974 bnx2x_cl45_write(bp, phy,
3975 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
3978 /* Wait up to 500us for command complete status */
3979 for (i = 0; i < 100; i++) {
3980 bnx2x_cl45_read(bp, phy,
3982 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
3983 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
3984 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
3989 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
3990 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
3992 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
3993 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
3997 /* Read the buffer */
3998 for (i = 0; i < byte_cnt; i++) {
3999 bnx2x_cl45_read(bp, phy,
4001 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4002 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4005 for (i = 0; i < 100; i++) {
4006 bnx2x_cl45_read(bp, phy,
4008 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4009 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4010 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4017 static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4018 struct link_params *params,
4019 u16 addr, u8 byte_cnt, u8 *o_buf)
4021 struct bnx2x *bp = params->bp;
4024 if (byte_cnt > 16) {
4025 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4026 " is limited to 0xf\n");
4030 /* Need to read from 1.8000 to clear it */
4031 bnx2x_cl45_read(bp, phy,
4033 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4036 /* Set the read command byte count */
4037 bnx2x_cl45_write(bp, phy,
4039 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4040 ((byte_cnt < 2) ? 2 : byte_cnt));
4042 /* Set the read command address */
4043 bnx2x_cl45_write(bp, phy,
4045 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4047 /* Set the destination address */
4048 bnx2x_cl45_write(bp, phy,
4051 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4053 /* Activate read command */
4054 bnx2x_cl45_write(bp, phy,
4056 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4058 /* Wait appropriate time for two-wire command to finish before
4059 polling the status register */
4062 /* Wait up to 500us for command complete status */
4063 for (i = 0; i < 100; i++) {
4064 bnx2x_cl45_read(bp, phy,
4066 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4067 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4068 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4073 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4074 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4076 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4077 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4081 /* Read the buffer */
4082 for (i = 0; i < byte_cnt; i++) {
4083 bnx2x_cl45_read(bp, phy,
4085 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4086 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4089 for (i = 0; i < 100; i++) {
4090 bnx2x_cl45_read(bp, phy,
4092 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4093 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4094 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4102 u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4103 struct link_params *params, u16 addr,
4104 u8 byte_cnt, u8 *o_buf)
4106 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4107 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4109 else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4110 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4115 static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4116 struct link_params *params,
4119 struct bnx2x *bp = params->bp;
4120 u8 val, check_limiting_mode = 0;
4121 *edc_mode = EDC_MODE_LIMITING;
4123 /* First check for copper cable */
4124 if (bnx2x_read_sfp_module_eeprom(phy,
4126 SFP_EEPROM_CON_TYPE_ADDR,
4129 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4134 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4136 u8 copper_module_type;
4138 /* Check if its active cable( includes SFP+ module)
4140 if (bnx2x_read_sfp_module_eeprom(phy,
4142 SFP_EEPROM_FC_TX_TECH_ADDR,
4144 &copper_module_type) !=
4147 "Failed to read copper-cable-type"
4148 " from SFP+ EEPROM\n");
4152 if (copper_module_type &
4153 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4154 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4155 check_limiting_mode = 1;
4156 } else if (copper_module_type &
4157 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4158 DP(NETIF_MSG_LINK, "Passive Copper"
4159 " cable detected\n");
4161 EDC_MODE_PASSIVE_DAC;
4163 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4164 "type 0x%x !!!\n", copper_module_type);
4169 case SFP_EEPROM_CON_TYPE_VAL_LC:
4170 DP(NETIF_MSG_LINK, "Optic module detected\n");
4171 check_limiting_mode = 1;
4174 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4179 if (check_limiting_mode) {
4180 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4181 if (bnx2x_read_sfp_module_eeprom(phy,
4183 SFP_EEPROM_OPTIONS_ADDR,
4184 SFP_EEPROM_OPTIONS_SIZE,
4186 DP(NETIF_MSG_LINK, "Failed to read Option"
4187 " field from module EEPROM\n");
4190 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4191 *edc_mode = EDC_MODE_LINEAR;
4193 *edc_mode = EDC_MODE_LIMITING;
4195 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4198 /* This function read the relevant field from the module ( SFP+ ),
4199 and verify it is compliant with this board */
4200 static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4201 struct link_params *params)
4203 struct bnx2x *bp = params->bp;
4205 u32 fw_resp, fw_cmd_param;
4206 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4207 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4208 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4209 val = REG_RD(bp, params->shmem_base +
4210 offsetof(struct shmem_region, dev_info.
4211 port_feature_config[params->port].config));
4212 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4213 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4214 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4218 if (params->feature_config_flags &
4219 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4220 /* Use specific phy request */
4221 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4222 } else if (params->feature_config_flags &
4223 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4224 /* Use first phy request only in case of non-dual media*/
4225 if (DUAL_MEDIA(params)) {
4226 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4230 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4232 /* No support in OPT MDL detection */
4233 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4238 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4239 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4240 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4241 DP(NETIF_MSG_LINK, "Approved module\n");
4245 /* format the warning message */
4246 if (bnx2x_read_sfp_module_eeprom(phy,
4248 SFP_EEPROM_VENDOR_NAME_ADDR,
4249 SFP_EEPROM_VENDOR_NAME_SIZE,
4251 vendor_name[0] = '\0';
4253 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4254 if (bnx2x_read_sfp_module_eeprom(phy,
4256 SFP_EEPROM_PART_NO_ADDR,
4257 SFP_EEPROM_PART_NO_SIZE,
4259 vendor_pn[0] = '\0';
4261 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4263 netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
4264 " Port %d from %s part number %s\n",
4265 params->port, vendor_name, vendor_pn);
4266 phy->flags |= FLAGS_SFP_NOT_APPROVED;
4270 static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4271 struct link_params *params)
4275 struct bnx2x *bp = params->bp;
4277 /* Initialization time after hot-plug may take up to 300ms for some
4278 phys type ( e.g. JDSU ) */
4279 for (timeout = 0; timeout < 60; timeout++) {
4280 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4282 DP(NETIF_MSG_LINK, "SFP+ module initialization "
4283 "took %d ms\n", timeout * 5);
4291 static void bnx2x_8727_power_module(struct bnx2x *bp,
4292 struct bnx2x_phy *phy,
4294 /* Make sure GPIOs are not using for LED mode */
4297 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
4298 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4300 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4301 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4302 * where the 1st bit is the over-current(only input), and 2nd bit is
4303 * for power( only output )
4307 * In case of NOC feature is disabled and power is up, set GPIO control
4308 * as input to enable listening of over-current indication
4310 if (phy->flags & FLAGS_NOC)
4313 FLAGS_NOC) && is_power_up)
4317 * Set GPIO control to OUTPUT, and set the power bit
4318 * to according to the is_power_up
4320 val = ((!(is_power_up)) << 1);
4322 bnx2x_cl45_write(bp, phy,
4324 MDIO_PMA_REG_8727_GPIO_CTRL,
4328 static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4329 struct bnx2x_phy *phy,
4332 u16 cur_limiting_mode;
4334 bnx2x_cl45_read(bp, phy,
4336 MDIO_PMA_REG_ROM_VER2,
4337 &cur_limiting_mode);
4338 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4341 if (edc_mode == EDC_MODE_LIMITING) {
4343 "Setting LIMITING MODE\n");
4344 bnx2x_cl45_write(bp, phy,
4346 MDIO_PMA_REG_ROM_VER2,
4348 } else { /* LRM mode ( default )*/
4350 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4352 /* Changing to LRM mode takes quite few seconds.
4353 So do it only if current mode is limiting
4354 ( default is LRM )*/
4355 if (cur_limiting_mode != EDC_MODE_LIMITING)
4358 bnx2x_cl45_write(bp, phy,
4360 MDIO_PMA_REG_LRM_MODE,
4362 bnx2x_cl45_write(bp, phy,
4364 MDIO_PMA_REG_ROM_VER2,
4366 bnx2x_cl45_write(bp, phy,
4368 MDIO_PMA_REG_MISC_CTRL0,
4370 bnx2x_cl45_write(bp, phy,
4372 MDIO_PMA_REG_LRM_MODE,
4378 static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4379 struct bnx2x_phy *phy,
4384 bnx2x_cl45_read(bp, phy,
4386 MDIO_PMA_REG_PHY_IDENTIFIER,
4389 bnx2x_cl45_write(bp, phy,
4391 MDIO_PMA_REG_PHY_IDENTIFIER,
4392 (phy_identifier & ~(1<<9)));
4394 bnx2x_cl45_read(bp, phy,
4396 MDIO_PMA_REG_ROM_VER2,
4398 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4399 bnx2x_cl45_write(bp, phy,
4401 MDIO_PMA_REG_ROM_VER2,
4402 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4404 bnx2x_cl45_write(bp, phy,
4406 MDIO_PMA_REG_PHY_IDENTIFIER,
4407 (phy_identifier | (1<<9)));
4412 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4413 struct link_params *params,
4416 struct bnx2x *bp = params->bp;
4420 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4423 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
4424 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4427 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
4433 static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
4434 struct link_params *params)
4436 struct bnx2x *bp = params->bp;
4440 u32 val = REG_RD(bp, params->shmem_base +
4441 offsetof(struct shmem_region, dev_info.
4442 port_feature_config[params->port].config));
4444 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
4447 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
4448 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4450 } else if (bnx2x_verify_sfp_module(phy, params) !=
4452 /* check SFP+ module compatibility */
4453 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4455 /* Turn on fault module-detected led */
4456 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4457 MISC_REGISTERS_GPIO_HIGH,
4459 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
4460 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4461 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
4462 /* Shutdown SFP+ module */
4463 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
4464 bnx2x_8727_power_module(bp, phy, 0);
4468 /* Turn off fault module-detected led */
4469 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
4470 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4471 MISC_REGISTERS_GPIO_LOW,
4475 /* power up the SFP module */
4476 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4477 bnx2x_8727_power_module(bp, phy, 1);
4479 /* Check and set limiting mode / LRM mode on 8726.
4480 On 8727 it is done automatically */
4481 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4482 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
4484 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
4486 * Enable transmit for this module if the module is approved, or
4487 * if unapproved modules should also enable the Tx laser
4490 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
4491 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4492 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4494 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4499 void bnx2x_handle_module_detect_int(struct link_params *params)
4501 struct bnx2x *bp = params->bp;
4502 struct bnx2x_phy *phy = ¶ms->phy[EXT_PHY1];
4504 u8 port = params->port;
4506 /* Set valid module led off */
4507 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4508 MISC_REGISTERS_GPIO_HIGH,
4511 /* Get current gpio val refelecting module plugged in / out*/
4512 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
4514 /* Call the handling function in case module is detected */
4515 if (gpio_val == 0) {
4517 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
4518 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
4521 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
4522 bnx2x_sfp_module_detection(phy, params);
4524 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4526 u32 val = REG_RD(bp, params->shmem_base +
4527 offsetof(struct shmem_region, dev_info.
4528 port_feature_config[params->port].
4531 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
4532 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
4534 /* Module was plugged out. */
4535 /* Disable transmit for this module */
4536 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4537 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4538 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4542 /******************************************************************/
4543 /* common BCM8706/BCM8726 PHY SECTION */
4544 /******************************************************************/
4545 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
4546 struct link_params *params,
4547 struct link_vars *vars)
4550 u16 val1, val2, rx_sd, pcs_status;
4551 struct bnx2x *bp = params->bp;
4552 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4554 bnx2x_cl45_read(bp, phy,
4555 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4556 /* clear LASI indication*/
4557 bnx2x_cl45_read(bp, phy,
4558 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4559 bnx2x_cl45_read(bp, phy,
4560 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
4561 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
4563 bnx2x_cl45_read(bp, phy,
4564 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4565 bnx2x_cl45_read(bp, phy,
4566 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
4567 bnx2x_cl45_read(bp, phy,
4568 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
4569 bnx2x_cl45_read(bp, phy,
4570 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
4572 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
4573 " link_status 0x%x\n", rx_sd, pcs_status, val2);
4574 /* link is up if both bit 0 of pmd_rx_sd and
4575 * bit 0 of pcs_status are set, or if the autoneg bit
4578 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
4581 vars->line_speed = SPEED_1000;
4583 vars->line_speed = SPEED_10000;
4584 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4589 /******************************************************************/
4590 /* BCM8706 PHY SECTION */
4591 /******************************************************************/
4592 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
4593 struct link_params *params,
4594 struct link_vars *vars)
4597 struct bnx2x *bp = params->bp;
4598 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4599 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4601 bnx2x_ext_phy_hw_reset(bp, params->port);
4602 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4603 bnx2x_wait_reset_complete(bp, phy);
4605 /* Wait until fw is loaded */
4606 for (cnt = 0; cnt < 100; cnt++) {
4607 bnx2x_cl45_read(bp, phy,
4608 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
4613 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
4614 if ((params->feature_config_flags &
4615 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4618 for (i = 0; i < 4; i++) {
4619 reg = MDIO_XS_8706_REG_BANK_RX0 +
4620 i*(MDIO_XS_8706_REG_BANK_RX1 -
4621 MDIO_XS_8706_REG_BANK_RX0);
4622 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
4623 /* Clear first 3 bits of the control */
4625 /* Set control bits according to configuration */
4626 val |= (phy->rx_preemphasis[i] & 0x7);
4627 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
4628 " reg 0x%x <-- val 0x%x\n", reg, val);
4629 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
4633 if (phy->req_line_speed == SPEED_10000) {
4634 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
4636 bnx2x_cl45_write(bp, phy,
4638 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
4639 bnx2x_cl45_write(bp, phy,
4640 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
4642 /* Force 1Gbps using autoneg with 1G advertisment */
4644 /* Allow CL37 through CL73 */
4645 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
4646 bnx2x_cl45_write(bp, phy,
4647 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
4649 /* Enable Full-Duplex advertisment on CL37 */
4650 bnx2x_cl45_write(bp, phy,
4651 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
4652 /* Enable CL37 AN */
4653 bnx2x_cl45_write(bp, phy,
4654 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4656 bnx2x_cl45_write(bp, phy,
4657 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
4659 /* Enable clause 73 AN */
4660 bnx2x_cl45_write(bp, phy,
4661 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4662 bnx2x_cl45_write(bp, phy,
4663 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4665 bnx2x_cl45_write(bp, phy,
4666 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
4669 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
4673 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
4674 struct link_params *params,
4675 struct link_vars *vars)
4677 return bnx2x_8706_8726_read_status(phy, params, vars);
4680 /******************************************************************/
4681 /* BCM8726 PHY SECTION */
4682 /******************************************************************/
4683 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
4684 struct link_params *params)
4686 struct bnx2x *bp = params->bp;
4687 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
4688 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
4691 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
4692 struct link_params *params)
4694 struct bnx2x *bp = params->bp;
4695 /* Need to wait 100ms after reset */
4698 /* Micro controller re-boot */
4699 bnx2x_cl45_write(bp, phy,
4700 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
4702 /* Set soft reset */
4703 bnx2x_cl45_write(bp, phy,
4705 MDIO_PMA_REG_GEN_CTRL,
4706 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
4708 bnx2x_cl45_write(bp, phy,
4710 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
4712 bnx2x_cl45_write(bp, phy,
4714 MDIO_PMA_REG_GEN_CTRL,
4715 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
4717 /* wait for 150ms for microcode load */
4720 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
4721 bnx2x_cl45_write(bp, phy,
4723 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
4726 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
4729 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
4730 struct link_params *params,
4731 struct link_vars *vars)
4733 struct bnx2x *bp = params->bp;
4735 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
4737 bnx2x_cl45_read(bp, phy,
4738 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
4740 if (val1 & (1<<15)) {
4741 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4743 vars->line_speed = 0;
4750 static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
4751 struct link_params *params,
4752 struct link_vars *vars)
4754 struct bnx2x *bp = params->bp;
4756 u32 swap_val, swap_override, aeu_gpio_mask, offset;
4757 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
4758 /* Restore normal power mode*/
4759 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4760 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4762 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4763 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4765 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
4766 bnx2x_wait_reset_complete(bp, phy);
4768 bnx2x_8726_external_rom_boot(phy, params);
4770 /* Need to call module detected on initialization since
4771 the module detection triggered by actual module
4772 insertion might occur before driver is loaded, and when
4773 driver is loaded, it reset all registers, including the
4775 bnx2x_sfp_module_detection(phy, params);
4777 if (phy->req_line_speed == SPEED_1000) {
4778 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4779 bnx2x_cl45_write(bp, phy,
4780 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
4781 bnx2x_cl45_write(bp, phy,
4782 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
4783 bnx2x_cl45_write(bp, phy,
4784 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
4785 bnx2x_cl45_write(bp, phy,
4786 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4788 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
4789 (phy->speed_cap_mask &
4790 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
4791 ((phy->speed_cap_mask &
4792 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
4793 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4794 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
4795 /* Set Flow control */
4796 bnx2x_ext_phy_set_pause(params, phy, vars);
4797 bnx2x_cl45_write(bp, phy,
4798 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
4799 bnx2x_cl45_write(bp, phy,
4800 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
4801 bnx2x_cl45_write(bp, phy,
4802 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
4803 bnx2x_cl45_write(bp, phy,
4804 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4805 bnx2x_cl45_write(bp, phy,
4806 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4807 /* Enable RX-ALARM control to receive
4808 interrupt for 1G speed change */
4809 bnx2x_cl45_write(bp, phy,
4810 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
4811 bnx2x_cl45_write(bp, phy,
4812 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4815 } else { /* Default 10G. Set only LASI control */
4816 bnx2x_cl45_write(bp, phy,
4817 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
4820 /* Set TX PreEmphasis if needed */
4821 if ((params->feature_config_flags &
4822 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4823 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4825 phy->tx_preemphasis[0],
4826 phy->tx_preemphasis[1]);
4827 bnx2x_cl45_write(bp, phy,
4829 MDIO_PMA_REG_8726_TX_CTRL1,
4830 phy->tx_preemphasis[0]);
4832 bnx2x_cl45_write(bp, phy,
4834 MDIO_PMA_REG_8726_TX_CTRL2,
4835 phy->tx_preemphasis[1]);
4838 /* Set GPIO3 to trigger SFP+ module insertion/removal */
4839 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
4840 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
4842 /* The GPIO should be swapped if the swap register is set and active */
4843 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4844 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4846 /* Select function upon port-swap configuration */
4847 if (params->port == 0) {
4848 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4849 aeu_gpio_mask = (swap_val && swap_override) ?
4850 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
4851 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
4853 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
4854 aeu_gpio_mask = (swap_val && swap_override) ?
4855 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
4856 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
4858 val = REG_RD(bp, offset);
4859 /* add GPIO3 to group */
4860 val |= aeu_gpio_mask;
4861 REG_WR(bp, offset, val);
4866 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
4867 struct link_params *params)
4869 struct bnx2x *bp = params->bp;
4870 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
4871 /* Set serial boot control for external load */
4872 bnx2x_cl45_write(bp, phy,
4874 MDIO_PMA_REG_GEN_CTRL, 0x0001);
4877 /******************************************************************/
4878 /* BCM8727 PHY SECTION */
4879 /******************************************************************/
4881 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
4882 struct link_params *params, u8 mode)
4884 struct bnx2x *bp = params->bp;
4885 u16 led_mode_bitmask = 0;
4886 u16 gpio_pins_bitmask = 0;
4888 /* Only NOC flavor requires to set the LED specifically */
4889 if (!(phy->flags & FLAGS_NOC))
4892 case LED_MODE_FRONT_PANEL_OFF:
4894 led_mode_bitmask = 0;
4895 gpio_pins_bitmask = 0x03;
4898 led_mode_bitmask = 0;
4899 gpio_pins_bitmask = 0x02;
4902 led_mode_bitmask = 0x60;
4903 gpio_pins_bitmask = 0x11;
4906 bnx2x_cl45_read(bp, phy,
4908 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4911 val |= led_mode_bitmask;
4912 bnx2x_cl45_write(bp, phy,
4914 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4916 bnx2x_cl45_read(bp, phy,
4918 MDIO_PMA_REG_8727_GPIO_CTRL,
4921 val |= gpio_pins_bitmask;
4922 bnx2x_cl45_write(bp, phy,
4924 MDIO_PMA_REG_8727_GPIO_CTRL,
4927 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
4928 struct link_params *params) {
4929 u32 swap_val, swap_override;
4932 * The PHY reset is controlled by GPIO 1. Fake the port number
4933 * to cancel the swap done in set_gpio()
4935 struct bnx2x *bp = params->bp;
4936 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4937 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4938 port = (swap_val && swap_override) ^ 1;
4939 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4940 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
4943 static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
4944 struct link_params *params,
4945 struct link_vars *vars)
4947 u16 tmp1, val, mod_abs;
4948 u16 rx_alarm_ctrl_val;
4950 struct bnx2x *bp = params->bp;
4951 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
4953 bnx2x_wait_reset_complete(bp, phy);
4954 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
4955 lasi_ctrl_val = 0x0004;
4957 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
4959 bnx2x_cl45_write(bp, phy,
4960 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4963 bnx2x_cl45_write(bp, phy,
4964 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
4966 /* Initially configure MOD_ABS to interrupt when
4967 module is presence( bit 8) */
4968 bnx2x_cl45_read(bp, phy,
4969 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4970 /* Set EDC off by setting OPTXLOS signal input to low
4972 When the EDC is off it locks onto a reference clock and
4973 avoids becoming 'lost'.*/
4975 if (!(phy->flags & FLAGS_NOC))
4977 bnx2x_cl45_write(bp, phy,
4978 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4981 /* Make MOD_ABS give interrupt on change */
4982 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4985 if (phy->flags & FLAGS_NOC)
4989 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
4990 * status which reflect SFP+ module over-current
4992 if (!(phy->flags & FLAGS_NOC))
4993 val &= 0xff8f; /* Reset bits 4-6 */
4994 bnx2x_cl45_write(bp, phy,
4995 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
4997 bnx2x_8727_power_module(bp, phy, 1);
4999 bnx2x_cl45_read(bp, phy,
5000 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5002 bnx2x_cl45_read(bp, phy,
5003 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5005 /* Set option 1G speed */
5006 if (phy->req_line_speed == SPEED_1000) {
5007 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5008 bnx2x_cl45_write(bp, phy,
5009 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5010 bnx2x_cl45_write(bp, phy,
5011 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5012 bnx2x_cl45_read(bp, phy,
5013 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5014 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
5016 * Power down the XAUI until link is up in case of dual-media
5019 if (DUAL_MEDIA(params)) {
5020 bnx2x_cl45_read(bp, phy,
5022 MDIO_PMA_REG_8727_PCS_GP, &val);
5024 bnx2x_cl45_write(bp, phy,
5026 MDIO_PMA_REG_8727_PCS_GP, val);
5028 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5029 ((phy->speed_cap_mask &
5030 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5031 ((phy->speed_cap_mask &
5032 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5033 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5035 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5036 bnx2x_cl45_write(bp, phy,
5037 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5038 bnx2x_cl45_write(bp, phy,
5039 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5042 * Since the 8727 has only single reset pin, need to set the 10G
5043 * registers although it is default
5045 bnx2x_cl45_write(bp, phy,
5046 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5048 bnx2x_cl45_write(bp, phy,
5049 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5050 bnx2x_cl45_write(bp, phy,
5051 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5052 bnx2x_cl45_write(bp, phy,
5053 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5057 /* Set 2-wire transfer rate of SFP+ module EEPROM
5058 * to 100Khz since some DACs(direct attached cables) do
5059 * not work at 400Khz.
5061 bnx2x_cl45_write(bp, phy,
5062 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5065 /* Set TX PreEmphasis if needed */
5066 if ((params->feature_config_flags &
5067 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5068 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5069 phy->tx_preemphasis[0],
5070 phy->tx_preemphasis[1]);
5071 bnx2x_cl45_write(bp, phy,
5072 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5073 phy->tx_preemphasis[0]);
5075 bnx2x_cl45_write(bp, phy,
5076 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5077 phy->tx_preemphasis[1]);
5083 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5084 struct link_params *params)
5086 struct bnx2x *bp = params->bp;
5087 u16 mod_abs, rx_alarm_status;
5088 u32 val = REG_RD(bp, params->shmem_base +
5089 offsetof(struct shmem_region, dev_info.
5090 port_feature_config[params->port].
5092 bnx2x_cl45_read(bp, phy,
5094 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5095 if (mod_abs & (1<<8)) {
5097 /* Module is absent */
5098 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5099 "show module is absent\n");
5101 /* 1. Set mod_abs to detect next module
5103 2. Set EDC off by setting OPTXLOS signal input to low
5105 When the EDC is off it locks onto a reference clock and
5106 avoids becoming 'lost'.*/
5108 if (!(phy->flags & FLAGS_NOC))
5110 bnx2x_cl45_write(bp, phy,
5112 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5114 /* Clear RX alarm since it stays up as long as
5115 the mod_abs wasn't changed */
5116 bnx2x_cl45_read(bp, phy,
5118 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5121 /* Module is present */
5122 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5123 "show module is present\n");
5124 /* First thing, disable transmitter,
5125 and if the module is ok, the
5126 module_detection will enable it*/
5128 /* 1. Set mod_abs to detect next module
5129 absent event ( bit 8)
5130 2. Restore the default polarity of the OPRXLOS signal and
5131 this signal will then correctly indicate the presence or
5132 absence of the Rx signal. (bit 9) */
5134 if (!(phy->flags & FLAGS_NOC))
5136 bnx2x_cl45_write(bp, phy,
5138 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5140 /* Clear RX alarm since it stays up as long as
5141 the mod_abs wasn't changed. This is need to be done
5142 before calling the module detection, otherwise it will clear
5143 the link update alarm */
5144 bnx2x_cl45_read(bp, phy,
5146 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5149 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5150 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5151 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5153 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5154 bnx2x_sfp_module_detection(phy, params);
5156 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5159 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5161 /* No need to check link status in case of
5162 module plugged in/out */
5165 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5166 struct link_params *params,
5167 struct link_vars *vars)
5170 struct bnx2x *bp = params->bp;
5172 u16 link_status = 0;
5173 u16 rx_alarm_status, lasi_ctrl, val1;
5175 /* If PHY is not initialized, do not check link status */
5176 bnx2x_cl45_read(bp, phy,
5177 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5182 /* Check the LASI */
5183 bnx2x_cl45_read(bp, phy,
5184 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5186 vars->line_speed = 0;
5187 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
5189 bnx2x_cl45_read(bp, phy,
5190 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5192 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5195 bnx2x_cl45_read(bp, phy,
5196 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5199 * If a module is present and there is need to check
5202 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5203 /* Check over-current using 8727 GPIO0 input*/
5204 bnx2x_cl45_read(bp, phy,
5205 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5208 if ((val1 & (1<<8)) == 0) {
5209 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5210 " on port %d\n", params->port);
5211 netdev_err(bp->dev, "Error: Power fault on Port %d has"
5212 " been detected and the power to "
5213 "that SFP+ module has been removed"
5214 " to prevent failure of the card."
5215 " Please remove the SFP+ module and"
5216 " restart the system to clear this"
5221 * Disable all RX_ALARMs except for
5224 bnx2x_cl45_write(bp, phy,
5226 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5228 bnx2x_cl45_read(bp, phy,
5230 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5231 /* Wait for module_absent_event */
5233 bnx2x_cl45_write(bp, phy,
5235 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5236 /* Clear RX alarm */
5237 bnx2x_cl45_read(bp, phy,
5239 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5242 } /* Over current check */
5244 /* When module absent bit is set, check module */
5245 if (rx_alarm_status & (1<<5)) {
5246 bnx2x_8727_handle_mod_abs(phy, params);
5247 /* Enable all mod_abs and link detection bits */
5248 bnx2x_cl45_write(bp, phy,
5249 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5252 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5253 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
5254 /* If transmitter is disabled, ignore false link up indication */
5255 bnx2x_cl45_read(bp, phy,
5256 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5257 if (val1 & (1<<15)) {
5258 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5262 bnx2x_cl45_read(bp, phy,
5264 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5266 /* Bits 0..2 --> speed detected,
5267 bits 13..15--> link is down */
5268 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5270 vars->line_speed = SPEED_10000;
5271 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5273 vars->line_speed = SPEED_1000;
5274 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5278 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5282 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5284 if ((DUAL_MEDIA(params)) &&
5285 (phy->req_line_speed == SPEED_1000)) {
5286 bnx2x_cl45_read(bp, phy,
5288 MDIO_PMA_REG_8727_PCS_GP, &val1);
5290 * In case of dual-media board and 1G, power up the XAUI side,
5291 * otherwise power it down. For 10G it is done automatically
5297 bnx2x_cl45_write(bp, phy,
5299 MDIO_PMA_REG_8727_PCS_GP, val1);
5304 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5305 struct link_params *params)
5307 struct bnx2x *bp = params->bp;
5308 /* Disable Transmitter */
5309 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5311 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5315 /******************************************************************/
5316 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
5317 /******************************************************************/
5318 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5319 struct link_params *params)
5321 u16 val, fw_ver1, fw_ver2, cnt;
5322 struct bnx2x *bp = params->bp;
5324 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
5325 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
5326 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
5327 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5328 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
5329 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
5330 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
5332 for (cnt = 0; cnt < 100; cnt++) {
5333 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5339 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
5340 bnx2x_save_spirom_version(bp, params->port, 0,
5346 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
5347 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
5348 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5349 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
5350 for (cnt = 0; cnt < 100; cnt++) {
5351 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5357 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
5358 bnx2x_save_spirom_version(bp, params->port, 0,
5363 /* lower 16 bits of the register SPI_FW_STATUS */
5364 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
5365 /* upper 16 bits of register SPI_FW_STATUS */
5366 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
5368 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
5372 static void bnx2x_848xx_set_led(struct bnx2x *bp,
5373 struct bnx2x_phy *phy)
5377 /* PHYC_CTL_LED_CTL */
5378 bnx2x_cl45_read(bp, phy,
5380 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
5384 bnx2x_cl45_write(bp, phy,
5386 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
5388 bnx2x_cl45_write(bp, phy,
5390 MDIO_PMA_REG_8481_LED1_MASK,
5393 bnx2x_cl45_write(bp, phy,
5395 MDIO_PMA_REG_8481_LED2_MASK,
5398 bnx2x_cl45_write(bp, phy,
5400 MDIO_PMA_REG_8481_LED3_MASK,
5403 /* 'Interrupt Mask' */
5404 bnx2x_cl45_write(bp, phy,
5409 static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
5410 struct link_params *params,
5411 struct link_vars *vars)
5413 struct bnx2x *bp = params->bp;
5414 u16 autoneg_val, an_1000_val, an_10_100_val;
5415 bnx2x_wait_reset_complete(bp, phy);
5416 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
5417 1 << NIG_LATCH_BC_ENABLE_MI_INT);
5419 bnx2x_cl45_write(bp, phy,
5420 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
5422 bnx2x_848xx_set_led(bp, phy);
5424 /* set 1000 speed advertisement */
5425 bnx2x_cl45_read(bp, phy,
5426 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5429 bnx2x_ext_phy_set_pause(params, phy, vars);
5430 bnx2x_cl45_read(bp, phy,
5432 MDIO_AN_REG_8481_LEGACY_AN_ADV,
5434 bnx2x_cl45_read(bp, phy,
5435 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
5437 /* Disable forced speed */
5438 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
5439 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
5441 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5442 (phy->speed_cap_mask &
5443 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5444 (phy->req_line_speed == SPEED_1000)) {
5445 an_1000_val |= (1<<8);
5446 autoneg_val |= (1<<9 | 1<<12);
5447 if (phy->req_duplex == DUPLEX_FULL)
5448 an_1000_val |= (1<<9);
5449 DP(NETIF_MSG_LINK, "Advertising 1G\n");
5451 an_1000_val &= ~((1<<8) | (1<<9));
5453 bnx2x_cl45_write(bp, phy,
5454 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5457 /* set 10 speed advertisement */
5458 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5459 (phy->speed_cap_mask &
5460 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
5461 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
5462 an_10_100_val |= (1<<7);
5463 /* Enable autoneg and restart autoneg for legacy speeds */
5464 autoneg_val |= (1<<9 | 1<<12);
5466 if (phy->req_duplex == DUPLEX_FULL)
5467 an_10_100_val |= (1<<8);
5468 DP(NETIF_MSG_LINK, "Advertising 100M\n");
5470 /* set 10 speed advertisement */
5471 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5472 (phy->speed_cap_mask &
5473 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
5474 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
5475 an_10_100_val |= (1<<5);
5476 autoneg_val |= (1<<9 | 1<<12);
5477 if (phy->req_duplex == DUPLEX_FULL)
5478 an_10_100_val |= (1<<6);
5479 DP(NETIF_MSG_LINK, "Advertising 10M\n");
5482 /* Only 10/100 are allowed to work in FORCE mode */
5483 if (phy->req_line_speed == SPEED_100) {
5484 autoneg_val |= (1<<13);
5485 /* Enabled AUTO-MDIX when autoneg is disabled */
5486 bnx2x_cl45_write(bp, phy,
5487 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
5488 (1<<15 | 1<<9 | 7<<0));
5489 DP(NETIF_MSG_LINK, "Setting 100M force\n");
5491 if (phy->req_line_speed == SPEED_10) {
5492 /* Enabled AUTO-MDIX when autoneg is disabled */
5493 bnx2x_cl45_write(bp, phy,
5494 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
5495 (1<<15 | 1<<9 | 7<<0));
5496 DP(NETIF_MSG_LINK, "Setting 10M force\n");
5499 bnx2x_cl45_write(bp, phy,
5500 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
5503 if (phy->req_duplex == DUPLEX_FULL)
5504 autoneg_val |= (1<<8);
5506 bnx2x_cl45_write(bp, phy,
5508 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
5510 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5511 (phy->speed_cap_mask &
5512 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
5513 (phy->req_line_speed == SPEED_10000)) {
5514 DP(NETIF_MSG_LINK, "Advertising 10G\n");
5515 /* Restart autoneg for 10G*/
5517 bnx2x_cl45_write(bp, phy,
5518 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
5520 } else if (phy->req_line_speed != SPEED_10 &&
5521 phy->req_line_speed != SPEED_100) {
5522 bnx2x_cl45_write(bp, phy,
5524 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
5527 /* Save spirom version */
5528 bnx2x_save_848xx_spirom_version(phy, params);
5533 static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
5534 struct link_params *params,
5535 struct link_vars *vars)
5537 struct bnx2x *bp = params->bp;
5538 /* Restore normal power mode*/
5539 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5540 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5543 bnx2x_ext_phy_hw_reset(bp, params->port);
5545 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5546 return bnx2x_848xx_cmn_config_init(phy, params, vars);
5549 static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
5550 struct link_params *params,
5551 struct link_vars *vars)
5553 struct bnx2x *bp = params->bp;
5554 u8 port = params->port, initialize = 1;
5557 u32 actual_phy_selection;
5560 /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
5563 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5564 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
5566 msleep(200); /* 100 is not enough */
5568 /* BCM84823 requires that XGXS links up first @ 10G for normal
5570 temp = vars->line_speed;
5571 vars->line_speed = SPEED_10000;
5572 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
5573 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
5574 vars->line_speed = temp;
5576 /* Set dual-media configuration according to configuration */
5578 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
5579 MDIO_CTL_REG_84823_MEDIA, &val);
5580 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
5581 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
5582 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
5583 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
5584 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
5585 val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
5586 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
5588 actual_phy_selection = bnx2x_phy_selection(params);
5590 switch (actual_phy_selection) {
5591 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
5592 /* Do nothing. Essentialy this is like the priority copper */
5594 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
5595 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
5597 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
5598 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
5600 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
5601 /* Do nothing here. The first PHY won't be initialized at all */
5603 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
5604 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
5608 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
5609 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
5611 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
5612 MDIO_CTL_REG_84823_MEDIA, val);
5613 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
5614 params->multi_phy_config, val);
5617 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
5619 bnx2x_save_848xx_spirom_version(phy, params);
5623 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
5624 struct link_params *params,
5625 struct link_vars *vars)
5627 struct bnx2x *bp = params->bp;
5628 u16 val, val1, val2;
5631 /* Check 10G-BaseT link status */
5632 /* Check PMD signal ok */
5633 bnx2x_cl45_read(bp, phy,
5634 MDIO_AN_DEVAD, 0xFFFA, &val1);
5635 bnx2x_cl45_read(bp, phy,
5636 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
5638 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
5640 /* Check link 10G */
5641 if (val2 & (1<<11)) {
5642 vars->line_speed = SPEED_10000;
5644 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
5645 } else { /* Check Legacy speed link */
5646 u16 legacy_status, legacy_speed;
5648 /* Enable expansion register 0x42 (Operation mode status) */
5649 bnx2x_cl45_write(bp, phy,
5651 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
5653 /* Get legacy speed operation status */
5654 bnx2x_cl45_read(bp, phy,
5656 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5659 DP(NETIF_MSG_LINK, "Legacy speed status"
5660 " = 0x%x\n", legacy_status);
5661 link_up = ((legacy_status & (1<<11)) == (1<<11));
5663 legacy_speed = (legacy_status & (3<<9));
5664 if (legacy_speed == (0<<9))
5665 vars->line_speed = SPEED_10;
5666 else if (legacy_speed == (1<<9))
5667 vars->line_speed = SPEED_100;
5668 else if (legacy_speed == (2<<9))
5669 vars->line_speed = SPEED_1000;
5670 else /* Should not happen */
5671 vars->line_speed = 0;
5673 if (legacy_status & (1<<8))
5674 vars->duplex = DUPLEX_FULL;
5676 vars->duplex = DUPLEX_HALF;
5678 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
5679 " is_duplex_full= %d\n", vars->line_speed,
5680 (vars->duplex == DUPLEX_FULL));
5681 /* Check legacy speed AN resolution */
5682 bnx2x_cl45_read(bp, phy,
5684 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
5687 vars->link_status |=
5688 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5689 bnx2x_cl45_read(bp, phy,
5691 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
5693 if ((val & (1<<0)) == 0)
5694 vars->link_status |=
5695 LINK_STATUS_PARALLEL_DETECTION_USED;
5699 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
5701 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5707 static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
5711 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
5712 status = bnx2x_format_ver(spirom_ver, str, len);
5716 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
5717 struct link_params *params)
5719 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5720 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
5721 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
5722 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
5725 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
5726 struct link_params *params)
5728 bnx2x_cl45_write(params->bp, phy,
5729 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
5730 bnx2x_cl45_write(params->bp, phy,
5731 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
5734 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
5735 struct link_params *params)
5737 struct bnx2x *bp = params->bp;
5738 u8 port = params->port;
5739 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5740 MISC_REGISTERS_GPIO_OUTPUT_LOW,
5744 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
5745 struct link_params *params, u8 mode)
5747 struct bnx2x *bp = params->bp;
5753 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
5755 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5756 SHARED_HW_CFG_LED_EXTPHY1) {
5759 bnx2x_cl45_write(bp, phy,
5761 MDIO_PMA_REG_8481_LED1_MASK,
5764 bnx2x_cl45_write(bp, phy,
5766 MDIO_PMA_REG_8481_LED2_MASK,
5769 bnx2x_cl45_write(bp, phy,
5771 MDIO_PMA_REG_8481_LED3_MASK,
5774 bnx2x_cl45_write(bp, phy,
5776 MDIO_PMA_REG_8481_LED5_MASK,
5780 bnx2x_cl45_write(bp, phy,
5782 MDIO_PMA_REG_8481_LED1_MASK,
5786 case LED_MODE_FRONT_PANEL_OFF:
5788 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
5791 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5792 SHARED_HW_CFG_LED_EXTPHY1) {
5795 bnx2x_cl45_write(bp, phy,
5797 MDIO_PMA_REG_8481_LED1_MASK,
5800 bnx2x_cl45_write(bp, phy,
5802 MDIO_PMA_REG_8481_LED2_MASK,
5805 bnx2x_cl45_write(bp, phy,
5807 MDIO_PMA_REG_8481_LED3_MASK,
5810 bnx2x_cl45_write(bp, phy,
5812 MDIO_PMA_REG_8481_LED5_MASK,
5816 bnx2x_cl45_write(bp, phy,
5818 MDIO_PMA_REG_8481_LED1_MASK,
5824 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
5826 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5827 SHARED_HW_CFG_LED_EXTPHY1) {
5828 /* Set control reg */
5829 bnx2x_cl45_read(bp, phy,
5831 MDIO_PMA_REG_8481_LINK_SIGNAL,
5836 bnx2x_cl45_write(bp, phy,
5838 MDIO_PMA_REG_8481_LINK_SIGNAL,
5842 bnx2x_cl45_write(bp, phy,
5844 MDIO_PMA_REG_8481_LED1_MASK,
5847 bnx2x_cl45_write(bp, phy,
5849 MDIO_PMA_REG_8481_LED2_MASK,
5852 bnx2x_cl45_write(bp, phy,
5854 MDIO_PMA_REG_8481_LED3_MASK,
5857 bnx2x_cl45_write(bp, phy,
5859 MDIO_PMA_REG_8481_LED5_MASK,
5862 bnx2x_cl45_write(bp, phy,
5864 MDIO_PMA_REG_8481_LED1_MASK,
5871 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
5873 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
5874 SHARED_HW_CFG_LED_EXTPHY1) {
5876 /* Set control reg */
5877 bnx2x_cl45_read(bp, phy,
5879 MDIO_PMA_REG_8481_LINK_SIGNAL,
5883 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
5884 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){
5885 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n");
5886 bnx2x_cl45_write(bp, phy,
5888 MDIO_PMA_REG_8481_LINK_SIGNAL,
5893 bnx2x_cl45_write(bp, phy,
5895 MDIO_PMA_REG_8481_LED1_MASK,
5898 bnx2x_cl45_write(bp, phy,
5900 MDIO_PMA_REG_8481_LED2_MASK,
5903 bnx2x_cl45_write(bp, phy,
5905 MDIO_PMA_REG_8481_LED3_MASK,
5908 bnx2x_cl45_write(bp, phy,
5910 MDIO_PMA_REG_8481_LED5_MASK,
5914 bnx2x_cl45_write(bp, phy,
5916 MDIO_PMA_REG_8481_LED1_MASK,
5922 /******************************************************************/
5923 /* SFX7101 PHY SECTION */
5924 /******************************************************************/
5925 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
5926 struct link_params *params)
5928 struct bnx2x *bp = params->bp;
5929 /* SFX7101_XGXS_TEST1 */
5930 bnx2x_cl45_write(bp, phy,
5931 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
5934 static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
5935 struct link_params *params,
5936 struct link_vars *vars)
5938 u16 fw_ver1, fw_ver2, val;
5939 struct bnx2x *bp = params->bp;
5940 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
5942 /* Restore normal power mode*/
5943 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5944 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5946 bnx2x_ext_phy_hw_reset(bp, params->port);
5947 bnx2x_wait_reset_complete(bp, phy);
5949 bnx2x_cl45_write(bp, phy,
5950 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
5951 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
5952 bnx2x_cl45_write(bp, phy,
5953 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
5955 bnx2x_ext_phy_set_pause(params, phy, vars);
5956 /* Restart autoneg */
5957 bnx2x_cl45_read(bp, phy,
5958 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
5960 bnx2x_cl45_write(bp, phy,
5961 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
5963 /* Save spirom version */
5964 bnx2x_cl45_read(bp, phy,
5965 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
5967 bnx2x_cl45_read(bp, phy,
5968 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
5969 bnx2x_save_spirom_version(bp, params->port,
5970 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
5974 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
5975 struct link_params *params,
5976 struct link_vars *vars)
5978 struct bnx2x *bp = params->bp;
5981 bnx2x_cl45_read(bp, phy,
5982 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5983 bnx2x_cl45_read(bp, phy,
5984 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5985 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
5987 bnx2x_cl45_read(bp, phy,
5988 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
5989 bnx2x_cl45_read(bp, phy,
5990 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
5991 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
5993 link_up = ((val1 & 4) == 4);
5995 * print the AN outcome of the SFX7101 PHY
5998 bnx2x_cl45_read(bp, phy,
5999 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6001 vars->line_speed = SPEED_10000;
6002 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6003 val2, (val2 & (1<<14)));
6004 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6005 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6011 static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6015 str[0] = (spirom_ver & 0xFF);
6016 str[1] = (spirom_ver & 0xFF00) >> 8;
6017 str[2] = (spirom_ver & 0xFF0000) >> 16;
6018 str[3] = (spirom_ver & 0xFF000000) >> 24;
6024 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6028 bnx2x_cl45_read(bp, phy,
6030 MDIO_PMA_REG_7101_RESET, &val);
6032 for (cnt = 0; cnt < 10; cnt++) {
6034 /* Writes a self-clearing reset */
6035 bnx2x_cl45_write(bp, phy,
6037 MDIO_PMA_REG_7101_RESET,
6039 /* Wait for clear */
6040 bnx2x_cl45_read(bp, phy,
6042 MDIO_PMA_REG_7101_RESET, &val);
6044 if ((val & (1<<15)) == 0)
6049 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6050 struct link_params *params) {
6051 /* Low power mode is controlled by GPIO 2 */
6052 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6053 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6054 /* The PHY reset is controlled by GPIO 1 */
6055 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6056 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6059 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6060 struct link_params *params, u8 mode)
6063 struct bnx2x *bp = params->bp;
6065 case LED_MODE_FRONT_PANEL_OFF:
6076 bnx2x_cl45_write(bp, phy,
6078 MDIO_PMA_REG_7107_LINK_LED_CNTL,
6082 /******************************************************************/
6083 /* STATIC PHY DECLARATION */
6084 /******************************************************************/
6086 static struct bnx2x_phy phy_null = {
6087 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6089 .flags = FLAGS_INIT_XGXS_FIRST,
6092 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6093 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6096 .media_type = ETH_PHY_NOT_PRESENT,
6099 .req_line_speed = 0,
6100 .speed_cap_mask = 0,
6103 .config_init = (config_init_t)NULL,
6104 .read_status = (read_status_t)NULL,
6105 .link_reset = (link_reset_t)NULL,
6106 .config_loopback = (config_loopback_t)NULL,
6107 .format_fw_ver = (format_fw_ver_t)NULL,
6108 .hw_reset = (hw_reset_t)NULL,
6109 .set_link_led = (set_link_led_t)NULL,
6110 .phy_specific_func = (phy_specific_func_t)NULL
6113 static struct bnx2x_phy phy_serdes = {
6114 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6119 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6120 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6122 .supported = (SUPPORTED_10baseT_Half |
6123 SUPPORTED_10baseT_Full |
6124 SUPPORTED_100baseT_Half |
6125 SUPPORTED_100baseT_Full |
6126 SUPPORTED_1000baseT_Full |
6127 SUPPORTED_2500baseX_Full |
6131 SUPPORTED_Asym_Pause),
6132 .media_type = ETH_PHY_UNSPECIFIED,
6135 .req_line_speed = 0,
6136 .speed_cap_mask = 0,
6139 .config_init = (config_init_t)bnx2x_init_serdes,
6140 .read_status = (read_status_t)bnx2x_link_settings_status,
6141 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6142 .config_loopback = (config_loopback_t)NULL,
6143 .format_fw_ver = (format_fw_ver_t)NULL,
6144 .hw_reset = (hw_reset_t)NULL,
6145 .set_link_led = (set_link_led_t)NULL,
6146 .phy_specific_func = (phy_specific_func_t)NULL
6149 static struct bnx2x_phy phy_xgxs = {
6150 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6155 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6156 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6158 .supported = (SUPPORTED_10baseT_Half |
6159 SUPPORTED_10baseT_Full |
6160 SUPPORTED_100baseT_Half |
6161 SUPPORTED_100baseT_Full |
6162 SUPPORTED_1000baseT_Full |
6163 SUPPORTED_2500baseX_Full |
6164 SUPPORTED_10000baseT_Full |
6168 SUPPORTED_Asym_Pause),
6169 .media_type = ETH_PHY_UNSPECIFIED,
6172 .req_line_speed = 0,
6173 .speed_cap_mask = 0,
6176 .config_init = (config_init_t)bnx2x_init_xgxs,
6177 .read_status = (read_status_t)bnx2x_link_settings_status,
6178 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6179 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6180 .format_fw_ver = (format_fw_ver_t)NULL,
6181 .hw_reset = (hw_reset_t)NULL,
6182 .set_link_led = (set_link_led_t)NULL,
6183 .phy_specific_func = (phy_specific_func_t)NULL
6186 static struct bnx2x_phy phy_7101 = {
6187 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6189 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6192 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6193 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6195 .supported = (SUPPORTED_10000baseT_Full |
6199 SUPPORTED_Asym_Pause),
6200 .media_type = ETH_PHY_BASE_T,
6203 .req_line_speed = 0,
6204 .speed_cap_mask = 0,
6207 .config_init = (config_init_t)bnx2x_7101_config_init,
6208 .read_status = (read_status_t)bnx2x_7101_read_status,
6209 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6210 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6211 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
6212 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
6213 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
6214 .phy_specific_func = (phy_specific_func_t)NULL
6216 static struct bnx2x_phy phy_8073 = {
6217 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6219 .flags = FLAGS_HW_LOCK_REQUIRED,
6222 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6223 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6225 .supported = (SUPPORTED_10000baseT_Full |
6226 SUPPORTED_2500baseX_Full |
6227 SUPPORTED_1000baseT_Full |
6231 SUPPORTED_Asym_Pause),
6232 .media_type = ETH_PHY_UNSPECIFIED,
6235 .req_line_speed = 0,
6236 .speed_cap_mask = 0,
6239 .config_init = (config_init_t)bnx2x_8073_config_init,
6240 .read_status = (read_status_t)bnx2x_8073_read_status,
6241 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
6242 .config_loopback = (config_loopback_t)NULL,
6243 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6244 .hw_reset = (hw_reset_t)NULL,
6245 .set_link_led = (set_link_led_t)NULL,
6246 .phy_specific_func = (phy_specific_func_t)NULL
6248 static struct bnx2x_phy phy_8705 = {
6249 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
6251 .flags = FLAGS_INIT_XGXS_FIRST,
6254 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6255 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6257 .supported = (SUPPORTED_10000baseT_Full |
6260 SUPPORTED_Asym_Pause),
6261 .media_type = ETH_PHY_XFP_FIBER,
6264 .req_line_speed = 0,
6265 .speed_cap_mask = 0,
6268 .config_init = (config_init_t)bnx2x_8705_config_init,
6269 .read_status = (read_status_t)bnx2x_8705_read_status,
6270 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6271 .config_loopback = (config_loopback_t)NULL,
6272 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
6273 .hw_reset = (hw_reset_t)NULL,
6274 .set_link_led = (set_link_led_t)NULL,
6275 .phy_specific_func = (phy_specific_func_t)NULL
6277 static struct bnx2x_phy phy_8706 = {
6278 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
6280 .flags = FLAGS_INIT_XGXS_FIRST,
6283 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6284 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6286 .supported = (SUPPORTED_10000baseT_Full |
6287 SUPPORTED_1000baseT_Full |
6290 SUPPORTED_Asym_Pause),
6291 .media_type = ETH_PHY_SFP_FIBER,
6294 .req_line_speed = 0,
6295 .speed_cap_mask = 0,
6298 .config_init = (config_init_t)bnx2x_8706_config_init,
6299 .read_status = (read_status_t)bnx2x_8706_read_status,
6300 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6301 .config_loopback = (config_loopback_t)NULL,
6302 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6303 .hw_reset = (hw_reset_t)NULL,
6304 .set_link_led = (set_link_led_t)NULL,
6305 .phy_specific_func = (phy_specific_func_t)NULL
6308 static struct bnx2x_phy phy_8726 = {
6309 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
6311 .flags = (FLAGS_HW_LOCK_REQUIRED |
6312 FLAGS_INIT_XGXS_FIRST),
6315 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6316 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6318 .supported = (SUPPORTED_10000baseT_Full |
6319 SUPPORTED_1000baseT_Full |
6323 SUPPORTED_Asym_Pause),
6324 .media_type = ETH_PHY_SFP_FIBER,
6327 .req_line_speed = 0,
6328 .speed_cap_mask = 0,
6331 .config_init = (config_init_t)bnx2x_8726_config_init,
6332 .read_status = (read_status_t)bnx2x_8726_read_status,
6333 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
6334 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
6335 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6336 .hw_reset = (hw_reset_t)NULL,
6337 .set_link_led = (set_link_led_t)NULL,
6338 .phy_specific_func = (phy_specific_func_t)NULL
6341 static struct bnx2x_phy phy_8727 = {
6342 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6344 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6347 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6348 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6350 .supported = (SUPPORTED_10000baseT_Full |
6351 SUPPORTED_1000baseT_Full |
6354 SUPPORTED_Asym_Pause),
6355 .media_type = ETH_PHY_SFP_FIBER,
6358 .req_line_speed = 0,
6359 .speed_cap_mask = 0,
6362 .config_init = (config_init_t)bnx2x_8727_config_init,
6363 .read_status = (read_status_t)bnx2x_8727_read_status,
6364 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
6365 .config_loopback = (config_loopback_t)NULL,
6366 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6367 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
6368 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
6369 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
6371 static struct bnx2x_phy phy_8481 = {
6372 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6374 .flags = FLAGS_FAN_FAILURE_DET_REQ |
6375 FLAGS_REARM_LATCH_SIGNAL,
6378 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6379 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6381 .supported = (SUPPORTED_10baseT_Half |
6382 SUPPORTED_10baseT_Full |
6383 SUPPORTED_100baseT_Half |
6384 SUPPORTED_100baseT_Full |
6385 SUPPORTED_1000baseT_Full |
6386 SUPPORTED_10000baseT_Full |
6390 SUPPORTED_Asym_Pause),
6391 .media_type = ETH_PHY_BASE_T,
6394 .req_line_speed = 0,
6395 .speed_cap_mask = 0,
6398 .config_init = (config_init_t)bnx2x_8481_config_init,
6399 .read_status = (read_status_t)bnx2x_848xx_read_status,
6400 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
6401 .config_loopback = (config_loopback_t)NULL,
6402 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
6403 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
6404 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
6405 .phy_specific_func = (phy_specific_func_t)NULL
6408 static struct bnx2x_phy phy_84823 = {
6409 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
6411 .flags = FLAGS_FAN_FAILURE_DET_REQ |
6412 FLAGS_REARM_LATCH_SIGNAL,
6415 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6416 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6418 .supported = (SUPPORTED_10baseT_Half |
6419 SUPPORTED_10baseT_Full |
6420 SUPPORTED_100baseT_Half |
6421 SUPPORTED_100baseT_Full |
6422 SUPPORTED_1000baseT_Full |
6423 SUPPORTED_10000baseT_Full |
6427 SUPPORTED_Asym_Pause),
6428 .media_type = ETH_PHY_BASE_T,
6431 .req_line_speed = 0,
6432 .speed_cap_mask = 0,
6435 .config_init = (config_init_t)bnx2x_848x3_config_init,
6436 .read_status = (read_status_t)bnx2x_848xx_read_status,
6437 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
6438 .config_loopback = (config_loopback_t)NULL,
6439 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
6440 .hw_reset = (hw_reset_t)NULL,
6441 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
6442 .phy_specific_func = (phy_specific_func_t)NULL
6445 /*****************************************************************/
6447 /* Populate the phy according. Main function: bnx2x_populate_phy */
6449 /*****************************************************************/
6451 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
6452 struct bnx2x_phy *phy, u8 port,
6455 /* Get the 4 lanes xgxs config rx and tx */
6456 u32 rx = 0, tx = 0, i;
6457 for (i = 0; i < 2; i++) {
6459 * INT_PHY and EXT_PHY1 share the same value location in the
6460 * shmem. When num_phys is greater than 1, than this value
6461 * applies only to EXT_PHY1
6463 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
6464 rx = REG_RD(bp, shmem_base +
6465 offsetof(struct shmem_region,
6466 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
6468 tx = REG_RD(bp, shmem_base +
6469 offsetof(struct shmem_region,
6470 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
6472 rx = REG_RD(bp, shmem_base +
6473 offsetof(struct shmem_region,
6474 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
6476 tx = REG_RD(bp, shmem_base +
6477 offsetof(struct shmem_region,
6478 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
6481 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
6482 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
6484 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
6485 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
6489 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
6490 u8 phy_index, u8 port)
6492 u32 ext_phy_config = 0;
6493 switch (phy_index) {
6495 ext_phy_config = REG_RD(bp, shmem_base +
6496 offsetof(struct shmem_region,
6497 dev_info.port_hw_config[port].external_phy_config));
6500 ext_phy_config = REG_RD(bp, shmem_base +
6501 offsetof(struct shmem_region,
6502 dev_info.port_hw_config[port].external_phy_config2));
6505 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
6509 return ext_phy_config;
6511 static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
6512 struct bnx2x_phy *phy)
6516 u32 switch_cfg = (REG_RD(bp, shmem_base +
6517 offsetof(struct shmem_region,
6518 dev_info.port_feature_config[port].link_config)) &
6519 PORT_FEATURE_CONNECTED_SWITCH_MASK);
6520 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
6521 switch (switch_cfg) {
6523 phy_addr = REG_RD(bp,
6524 NIG_REG_SERDES0_CTRL_PHY_ADDR +
6528 case SWITCH_CFG_10G:
6529 phy_addr = REG_RD(bp,
6530 NIG_REG_XGXS0_CTRL_PHY_ADDR +
6535 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6538 phy->addr = (u8)phy_addr;
6539 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
6540 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
6543 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
6545 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
6547 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
6548 port, phy->addr, phy->mdio_ctrl);
6550 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
6554 static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
6559 struct bnx2x_phy *phy)
6561 u32 ext_phy_config, phy_type, config2;
6562 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
6563 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
6565 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6566 /* Select the phy type */
6568 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6569 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
6572 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6575 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6578 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6579 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
6582 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6583 /* BCM8727_NOC => BCM8727 no over current */
6584 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
6586 phy->flags |= FLAGS_NOC;
6588 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6589 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
6592 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
6595 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
6598 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6601 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6609 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
6610 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
6613 * The shmem address of the phy version is located on different
6614 * structures. In case this structure is too old, do not set
6617 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
6618 dev_info.shared_hw_config.config2));
6619 if (phy_index == EXT_PHY1) {
6620 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
6621 port_mb[port].ext_phy_fw_version);
6623 /* Check specific mdc mdio settings */
6624 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
6625 mdc_mdio_access = config2 &
6626 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
6628 u32 size = REG_RD(bp, shmem2_base);
6631 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
6632 phy->ver_addr = shmem2_base +
6633 offsetof(struct shmem2_region,
6634 ext_phy_fw_version2[port]);
6636 /* Check specific mdc mdio settings */
6637 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
6638 mdc_mdio_access = (config2 &
6639 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
6640 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
6641 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
6643 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
6646 * In case mdc/mdio_access of the external phy is different than the
6647 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
6648 * to prevent one port interfere with another port's CL45 operations.
6650 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
6651 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
6652 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
6653 phy_type, port, phy_index);
6654 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
6655 phy->addr, phy->mdio_ctrl);
6659 static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
6660 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
6663 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
6664 if (phy_index == INT_PHY)
6665 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
6666 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
6671 static void bnx2x_phy_def_cfg(struct link_params *params,
6672 struct bnx2x_phy *phy,
6675 struct bnx2x *bp = params->bp;
6677 /* Populate the default phy configuration for MF mode */
6678 if (phy_index == EXT_PHY2) {
6679 link_config = REG_RD(bp, params->shmem_base +
6680 offsetof(struct shmem_region, dev_info.
6681 port_feature_config[params->port].link_config2));
6682 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
6683 offsetof(struct shmem_region, dev_info.
6684 port_hw_config[params->port].speed_capability_mask2));
6686 link_config = REG_RD(bp, params->shmem_base +
6687 offsetof(struct shmem_region, dev_info.
6688 port_feature_config[params->port].link_config));
6689 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
6690 offsetof(struct shmem_region, dev_info.
6691 port_hw_config[params->port].speed_capability_mask));
6693 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
6694 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
6696 phy->req_duplex = DUPLEX_FULL;
6697 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
6698 case PORT_FEATURE_LINK_SPEED_10M_HALF:
6699 phy->req_duplex = DUPLEX_HALF;
6700 case PORT_FEATURE_LINK_SPEED_10M_FULL:
6701 phy->req_line_speed = SPEED_10;
6703 case PORT_FEATURE_LINK_SPEED_100M_HALF:
6704 phy->req_duplex = DUPLEX_HALF;
6705 case PORT_FEATURE_LINK_SPEED_100M_FULL:
6706 phy->req_line_speed = SPEED_100;
6708 case PORT_FEATURE_LINK_SPEED_1G:
6709 phy->req_line_speed = SPEED_1000;
6711 case PORT_FEATURE_LINK_SPEED_2_5G:
6712 phy->req_line_speed = SPEED_2500;
6714 case PORT_FEATURE_LINK_SPEED_10G_CX4:
6715 phy->req_line_speed = SPEED_10000;
6718 phy->req_line_speed = SPEED_AUTO_NEG;
6722 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
6723 case PORT_FEATURE_FLOW_CONTROL_AUTO:
6724 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
6726 case PORT_FEATURE_FLOW_CONTROL_TX:
6727 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
6729 case PORT_FEATURE_FLOW_CONTROL_RX:
6730 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
6732 case PORT_FEATURE_FLOW_CONTROL_BOTH:
6733 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
6736 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6741 u32 bnx2x_phy_selection(struct link_params *params)
6743 u32 phy_config_swapped, prio_cfg;
6744 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
6746 phy_config_swapped = params->multi_phy_config &
6747 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
6749 prio_cfg = params->multi_phy_config &
6750 PORT_HW_CFG_PHY_SELECTION_MASK;
6752 if (phy_config_swapped) {
6754 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6755 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
6757 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6758 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
6760 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6761 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
6763 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6764 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
6768 return_cfg = prio_cfg;
6774 u8 bnx2x_phy_probe(struct link_params *params)
6776 u8 phy_index, actual_phy_idx, link_cfg_idx;
6777 u32 phy_config_swapped;
6778 struct bnx2x *bp = params->bp;
6779 struct bnx2x_phy *phy;
6780 params->num_phys = 0;
6781 DP(NETIF_MSG_LINK, "Begin phy probe\n");
6782 phy_config_swapped = params->multi_phy_config &
6783 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
6785 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
6787 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
6788 actual_phy_idx = phy_index;
6789 if (phy_config_swapped) {
6790 if (phy_index == EXT_PHY1)
6791 actual_phy_idx = EXT_PHY2;
6792 else if (phy_index == EXT_PHY2)
6793 actual_phy_idx = EXT_PHY1;
6795 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
6796 " actual_phy_idx %x\n", phy_config_swapped,
6797 phy_index, actual_phy_idx);
6798 phy = ¶ms->phy[actual_phy_idx];
6799 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
6800 params->shmem2_base, params->port,
6802 params->num_phys = 0;
6803 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
6805 for (phy_index = INT_PHY;
6806 phy_index < MAX_PHYS;
6811 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
6814 bnx2x_phy_def_cfg(params, phy, phy_index);
6818 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
6822 u32 bnx2x_supported_attr(struct link_params *params, u8 phy_idx)
6824 if (phy_idx < params->num_phys)
6825 return params->phy[phy_idx].supported;
6829 static void set_phy_vars(struct link_params *params)
6831 struct bnx2x *bp = params->bp;
6832 u8 actual_phy_idx, phy_index, link_cfg_idx;
6833 u8 phy_config_swapped = params->multi_phy_config &
6834 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
6835 for (phy_index = INT_PHY; phy_index < params->num_phys;
6837 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
6838 actual_phy_idx = phy_index;
6839 if (phy_config_swapped) {
6840 if (phy_index == EXT_PHY1)
6841 actual_phy_idx = EXT_PHY2;
6842 else if (phy_index == EXT_PHY2)
6843 actual_phy_idx = EXT_PHY1;
6845 params->phy[actual_phy_idx].req_flow_ctrl =
6846 params->req_flow_ctrl[link_cfg_idx];
6848 params->phy[actual_phy_idx].req_line_speed =
6849 params->req_line_speed[link_cfg_idx];
6851 params->phy[actual_phy_idx].speed_cap_mask =
6852 params->speed_cap_mask[link_cfg_idx];
6854 params->phy[actual_phy_idx].req_duplex =
6855 params->req_duplex[link_cfg_idx];
6857 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
6858 " speed_cap_mask %x\n",
6859 params->phy[actual_phy_idx].req_flow_ctrl,
6860 params->phy[actual_phy_idx].req_line_speed,
6861 params->phy[actual_phy_idx].speed_cap_mask);
6865 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
6867 struct bnx2x *bp = params->bp;
6868 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
6869 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
6870 params->req_line_speed[0], params->req_flow_ctrl[0]);
6871 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
6872 params->req_line_speed[1], params->req_flow_ctrl[1]);
6873 vars->link_status = 0;
6874 vars->phy_link_up = 0;
6876 vars->line_speed = 0;
6877 vars->duplex = DUPLEX_FULL;
6878 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6879 vars->mac_type = MAC_TYPE_NONE;
6880 vars->phy_flags = 0;
6882 /* disable attentions */
6883 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
6884 (NIG_MASK_XGXS0_LINK_STATUS |
6885 NIG_MASK_XGXS0_LINK10G |
6886 NIG_MASK_SERDES0_LINK_STATUS |
6889 bnx2x_emac_init(params, vars);
6891 if (params->num_phys == 0) {
6892 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
6895 set_phy_vars(params);
6897 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
6898 if (CHIP_REV_IS_FPGA(bp)) {
6901 vars->line_speed = SPEED_10000;
6902 vars->duplex = DUPLEX_FULL;
6903 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6904 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
6905 /* enable on E1.5 FPGA */
6906 if (CHIP_IS_E1H(bp)) {
6908 (BNX2X_FLOW_CTRL_TX |
6909 BNX2X_FLOW_CTRL_RX);
6910 vars->link_status |=
6911 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
6912 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
6915 bnx2x_emac_enable(params, vars, 0);
6916 if (!(CHIP_IS_E2(bp)))
6917 bnx2x_pbf_update(params, vars->flow_ctrl,
6920 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
6922 /* update shared memory */
6923 bnx2x_update_mng(params, vars->link_status);
6928 if (CHIP_REV_IS_EMUL(bp)) {
6931 vars->line_speed = SPEED_10000;
6932 vars->duplex = DUPLEX_FULL;
6933 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6934 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
6936 bnx2x_bmac_enable(params, vars, 0);
6938 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
6940 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
6941 + params->port*4, 0);
6943 /* update shared memory */
6944 bnx2x_update_mng(params, vars->link_status);
6949 if (params->loopback_mode == LOOPBACK_BMAC) {
6952 vars->line_speed = SPEED_10000;
6953 vars->duplex = DUPLEX_FULL;
6954 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6955 vars->mac_type = MAC_TYPE_BMAC;
6957 vars->phy_flags = PHY_XGXS_FLAG;
6959 bnx2x_xgxs_deassert(params);
6961 /* set bmac loopback */
6962 bnx2x_bmac_enable(params, vars, 1);
6964 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6967 } else if (params->loopback_mode == LOOPBACK_EMAC) {
6970 vars->line_speed = SPEED_1000;
6971 vars->duplex = DUPLEX_FULL;
6972 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6973 vars->mac_type = MAC_TYPE_EMAC;
6975 vars->phy_flags = PHY_XGXS_FLAG;
6977 bnx2x_xgxs_deassert(params);
6978 /* set bmac loopback */
6979 bnx2x_emac_enable(params, vars, 1);
6980 bnx2x_emac_program(params, vars);
6981 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6984 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
6985 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6988 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6989 vars->duplex = DUPLEX_FULL;
6990 if (params->req_line_speed[0] == SPEED_1000) {
6991 vars->line_speed = SPEED_1000;
6992 vars->mac_type = MAC_TYPE_EMAC;
6994 vars->line_speed = SPEED_10000;
6995 vars->mac_type = MAC_TYPE_BMAC;
6998 bnx2x_xgxs_deassert(params);
6999 bnx2x_link_initialize(params, vars);
7001 if (params->req_line_speed[0] == SPEED_1000) {
7002 bnx2x_emac_program(params, vars);
7003 bnx2x_emac_enable(params, vars, 0);
7005 bnx2x_bmac_enable(params, vars, 0);
7007 if (params->loopback_mode == LOOPBACK_XGXS) {
7008 /* set 10G XGXS loopback */
7009 params->phy[INT_PHY].config_loopback(
7010 ¶ms->phy[INT_PHY],
7014 /* set external phy loopback */
7016 for (phy_index = EXT_PHY1;
7017 phy_index < params->num_phys; phy_index++) {
7018 if (params->phy[phy_index].config_loopback)
7019 params->phy[phy_index].config_loopback(
7020 ¶ms->phy[phy_index],
7025 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7028 bnx2x_set_led(params, vars,
7029 LED_MODE_OPER, vars->line_speed);
7033 if (params->switch_cfg == SWITCH_CFG_10G)
7034 bnx2x_xgxs_deassert(params);
7036 bnx2x_serdes_deassert(bp, params->port);
7038 bnx2x_link_initialize(params, vars);
7040 bnx2x_link_int_enable(params);
7044 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7047 struct bnx2x *bp = params->bp;
7048 u8 phy_index, port = params->port;
7049 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7050 /* disable attentions */
7051 vars->link_status = 0;
7052 bnx2x_update_mng(params, vars->link_status);
7053 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7054 (NIG_MASK_XGXS0_LINK_STATUS |
7055 NIG_MASK_XGXS0_LINK10G |
7056 NIG_MASK_SERDES0_LINK_STATUS |
7059 /* activate nig drain */
7060 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7062 /* disable nig egress interface */
7063 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7064 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7066 /* Stop BigMac rx */
7067 bnx2x_bmac_rx_disable(bp, port);
7070 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7073 /* The PHY reset is controled by GPIO 1
7074 * Hold it as vars low
7076 /* clear link led */
7077 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7079 if (reset_ext_phy) {
7080 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7082 if (params->phy[phy_index].link_reset)
7083 params->phy[phy_index].link_reset(
7084 ¶ms->phy[phy_index],
7089 if (params->phy[INT_PHY].link_reset)
7090 params->phy[INT_PHY].link_reset(
7091 ¶ms->phy[INT_PHY], params);
7093 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7094 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
7096 /* disable nig ingress interface */
7097 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7098 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7099 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7100 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7105 /****************************************************************************/
7106 /* Common function */
7107 /****************************************************************************/
7108 static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7109 u32 shmem_base_path[],
7110 u32 shmem2_base_path[], u8 phy_index,
7113 struct bnx2x_phy phy[PORT_MAX];
7114 struct bnx2x_phy *phy_blk[PORT_MAX];
7117 s8 port_of_path = 0;
7119 /* PART1 - Reset both phys */
7120 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7121 u32 shmem_base, shmem2_base;
7122 /* In E2, same phy is using for port0 of the two paths */
7123 if (CHIP_IS_E2(bp)) {
7124 shmem_base = shmem_base_path[port];
7125 shmem2_base = shmem2_base_path[port];
7128 shmem_base = shmem_base_path[0];
7129 shmem2_base = shmem2_base_path[0];
7130 port_of_path = port;
7133 /* Extract the ext phy address for the port */
7134 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7135 port_of_path, &phy[port]) !=
7137 DP(NETIF_MSG_LINK, "populate_phy failed\n");
7140 /* disable attentions */
7141 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7142 (NIG_MASK_XGXS0_LINK_STATUS |
7143 NIG_MASK_XGXS0_LINK10G |
7144 NIG_MASK_SERDES0_LINK_STATUS |
7147 /* Need to take the phy out of low power mode in order
7148 to write to access its registers */
7149 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7150 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7153 bnx2x_cl45_write(bp, &phy[port],
7159 /* Add delay of 150ms after reset */
7162 if (phy[PORT_0].addr & 0x1) {
7163 phy_blk[PORT_0] = &(phy[PORT_1]);
7164 phy_blk[PORT_1] = &(phy[PORT_0]);
7166 phy_blk[PORT_0] = &(phy[PORT_0]);
7167 phy_blk[PORT_1] = &(phy[PORT_1]);
7170 /* PART2 - Download firmware to both phys */
7171 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7176 port_of_path = port;
7178 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7179 phy_blk[port]->addr);
7180 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7183 bnx2x_cl45_read(bp, phy_blk[port],
7185 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7186 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7188 "bnx2x_8073_common_init_phy port %x:"
7189 "Download failed. fw version = 0x%x\n",
7194 /* Only set bit 10 = 1 (Tx power down) */
7195 bnx2x_cl45_read(bp, phy_blk[port],
7197 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7199 /* Phase1 of TX_POWER_DOWN reset */
7200 bnx2x_cl45_write(bp, phy_blk[port],
7202 MDIO_PMA_REG_TX_POWER_DOWN,
7206 /* Toggle Transmitter: Power down and then up with 600ms
7210 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
7211 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7212 /* Phase2 of POWER_DOWN_RESET */
7213 /* Release bit 10 (Release Tx power down) */
7214 bnx2x_cl45_read(bp, phy_blk[port],
7216 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7218 bnx2x_cl45_write(bp, phy_blk[port],
7220 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
7223 /* Read modify write the SPI-ROM version select register */
7224 bnx2x_cl45_read(bp, phy_blk[port],
7226 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
7227 bnx2x_cl45_write(bp, phy_blk[port],
7229 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
7231 /* set GPIO2 back to LOW */
7232 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7233 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7237 static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7238 u32 shmem_base_path[],
7239 u32 shmem2_base_path[], u8 phy_index,
7244 struct bnx2x_phy phy;
7245 /* Use port1 because of the static port-swap */
7246 /* Enable the module detection interrupt */
7247 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
7248 val |= ((1<<MISC_REGISTERS_GPIO_3)|
7249 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
7250 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
7252 bnx2x_ext_phy_hw_reset(bp, 1);
7254 for (port = 0; port < PORT_MAX; port++) {
7255 u32 shmem_base, shmem2_base;
7257 /* In E2, same phy is using for port0 of the two paths */
7258 if (CHIP_IS_E2(bp)) {
7259 shmem_base = shmem_base_path[port];
7260 shmem2_base = shmem2_base_path[port];
7262 shmem_base = shmem_base_path[0];
7263 shmem2_base = shmem2_base_path[0];
7265 /* Extract the ext phy address for the port */
7266 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7269 DP(NETIF_MSG_LINK, "populate phy failed\n");
7274 bnx2x_cl45_write(bp, &phy,
7275 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
7278 /* Set fault module detected LED on */
7279 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
7280 MISC_REGISTERS_GPIO_HIGH,
7286 static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7287 u32 shmem_base_path[],
7288 u32 shmem2_base_path[], u8 phy_index,
7292 u32 swap_val, swap_override;
7293 struct bnx2x_phy phy[PORT_MAX];
7294 struct bnx2x_phy *phy_blk[PORT_MAX];
7296 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7297 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7301 bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override));
7303 /* Calculate the port based on port swap */
7304 port ^= (swap_val && swap_override);
7308 /* PART1 - Reset both phys */
7309 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7310 u32 shmem_base, shmem2_base;
7312 /* In E2, same phy is using for port0 of the two paths */
7313 if (CHIP_IS_E2(bp)) {
7314 shmem_base = shmem_base_path[port];
7315 shmem2_base = shmem2_base_path[port];
7318 shmem_base = shmem_base_path[0];
7319 shmem2_base = shmem2_base_path[0];
7320 port_of_path = port;
7323 /* Extract the ext phy address for the port */
7324 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7325 port_of_path, &phy[port]) !=
7327 DP(NETIF_MSG_LINK, "populate phy failed\n");
7330 /* disable attentions */
7331 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7333 (NIG_MASK_XGXS0_LINK_STATUS |
7334 NIG_MASK_XGXS0_LINK10G |
7335 NIG_MASK_SERDES0_LINK_STATUS |
7340 bnx2x_cl45_write(bp, &phy[port],
7346 /* Add delay of 150ms after reset */
7348 if (phy[PORT_0].addr & 0x1) {
7349 phy_blk[PORT_0] = &(phy[PORT_1]);
7350 phy_blk[PORT_1] = &(phy[PORT_0]);
7352 phy_blk[PORT_0] = &(phy[PORT_0]);
7353 phy_blk[PORT_1] = &(phy[PORT_1]);
7355 /* PART2 - Download firmware to both phys */
7356 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7361 port_of_path = port;
7362 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7363 phy_blk[port]->addr);
7364 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7366 bnx2x_cl45_read(bp, phy_blk[port],
7368 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7369 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7371 "bnx2x_8727_common_init_phy port %x:"
7372 "Download failed. fw version = 0x%x\n",
7381 static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
7382 u32 shmem2_base_path[], u8 phy_index,
7383 u32 ext_phy_type, u32 chip_id)
7387 switch (ext_phy_type) {
7388 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7389 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
7391 phy_index, chip_id);
7394 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7395 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7396 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
7398 phy_index, chip_id);
7401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7402 /* GPIO1 affects both ports, so there's need to pull
7403 it for single port alone */
7404 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
7406 phy_index, chip_id);
7408 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7413 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
7421 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
7422 u32 shmem2_base_path[], u32 chip_id)
7426 u32 ext_phy_type, ext_phy_config;
7427 DP(NETIF_MSG_LINK, "Begin common phy init\n");
7429 if (CHIP_REV_IS_EMUL(bp))
7432 /* Read the ext_phy_type for arbitrary port(0) */
7433 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
7435 ext_phy_config = bnx2x_get_ext_phy_config(bp,
7438 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7439 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
7441 phy_index, ext_phy_type,
7447 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
7450 struct bnx2x_phy phy;
7451 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7453 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7455 DP(NETIF_MSG_LINK, "populate phy failed\n");
7459 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
7465 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
7470 u8 phy_index, fan_failure_det_req = 0;
7471 struct bnx2x_phy phy;
7472 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
7474 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7477 DP(NETIF_MSG_LINK, "populate phy failed\n");
7480 fan_failure_det_req |= (phy.flags &
7481 FLAGS_FAN_FAILURE_DET_REQ);
7483 return fan_failure_det_req;
7486 void bnx2x_hw_reset_phy(struct link_params *params)
7489 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
7491 if (params->phy[phy_index].hw_reset) {
7492 params->phy[phy_index].hw_reset(
7493 ¶ms->phy[phy_index],
7495 params->phy[phy_index] = phy_null;