1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
52 #include <linux/stringify.h>
53 #include <linux/vmalloc.h>
56 #include "bnx2x_init.h"
57 #include "bnx2x_init_ops.h"
58 #include "bnx2x_cmn.h"
59 #include "bnx2x_dcb.h"
62 #include <linux/firmware.h>
63 #include "bnx2x_fw_file_hdr.h"
65 #define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
70 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
72 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
74 /* Time in jiffies before concluding the transmitter is hung */
75 #define TX_TIMEOUT (5*HZ)
77 static char version[] __devinitdata =
78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
81 MODULE_AUTHOR("Eliezer Tamir");
82 MODULE_DESCRIPTION("Broadcom NetXtreme II "
83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
86 MODULE_LICENSE("GPL");
87 MODULE_VERSION(DRV_MODULE_VERSION);
88 MODULE_FIRMWARE(FW_FILE_NAME_E1);
89 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
90 MODULE_FIRMWARE(FW_FILE_NAME_E2);
92 static int multi_mode = 1;
93 module_param(multi_mode, int, 0);
94 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
98 module_param(num_queues, int, 0);
99 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
102 static int disable_tpa;
103 module_param(disable_tpa, int, 0);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 #define INT_MODE_INTx 1
107 #define INT_MODE_MSI 2
109 module_param(int_mode, int, 0);
110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
113 static int dropless_fc;
114 module_param(dropless_fc, int, 0);
115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118 module_param(poll, int, 0);
119 MODULE_PARM_DESC(poll, " Use polling (for debug)");
121 static int mrrs = -1;
122 module_param(mrrs, int, 0);
123 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
126 module_param(debug, int, 0);
127 MODULE_PARM_DESC(debug, " Default debug msglevel");
131 struct workqueue_struct *bnx2x_wq;
133 enum bnx2x_board_type {
147 /* indexed by board_type, above */
150 } board_info[] __devinitdata = {
151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
165 #ifndef PCI_DEVICE_ID_NX2_57710
166 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
168 #ifndef PCI_DEVICE_ID_NX2_57711
169 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
171 #ifndef PCI_DEVICE_ID_NX2_57711E
172 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
174 #ifndef PCI_DEVICE_ID_NX2_57712
175 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
177 #ifndef PCI_DEVICE_ID_NX2_57712_MF
178 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
180 #ifndef PCI_DEVICE_ID_NX2_57800
181 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
183 #ifndef PCI_DEVICE_ID_NX2_57800_MF
184 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
186 #ifndef PCI_DEVICE_ID_NX2_57810
187 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
189 #ifndef PCI_DEVICE_ID_NX2_57810_MF
190 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
192 #ifndef PCI_DEVICE_ID_NX2_57840
193 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
195 #ifndef PCI_DEVICE_ID_NX2_57840_MF
196 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
198 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
213 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
215 /****************************************************************************
216 * General service functions
217 ****************************************************************************/
219 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
226 static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
232 __storm_memset_dma_mapping(bp, addr, mapping);
235 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
265 size_t size = sizeof(struct event_ring_data);
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
272 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
280 * locking is done by mcp
282 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
290 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
302 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306 #define DMAE_DP_DST_NONE "dst_addr [none]"
308 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
372 /* copy command into DMAE command memory and set DMAE command go */
373 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
388 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
394 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396 return opcode & ~DMAE_CMD_SRC_RESET;
399 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
424 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
428 memset(dmae, 0, sizeof(struct dmae_command));
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
440 /* issue a dmae command over the init-channel and wailt for completion */
441 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
457 spin_lock_bh(&bp->dmae_lock);
459 /* reset completion */
462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
465 /* wait for completion */
467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
471 BNX2X_ERR("DMAE timeout!\n");
478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
488 spin_unlock_bh(&bp->dmae_lock);
492 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
495 struct dmae_command dmae;
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
522 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
524 struct dmae_command dmae;
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
540 /* fill in addresses and len */
541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
553 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
559 while (len > dmae_wr_max) {
560 bnx2x_write_dmae(bp, phys_addr + offset,
561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
569 /* used only for slowpath so not inlined */
570 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
580 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
584 REG_RD_DMAE(bp, reg, wb_data, 2);
586 return HILO_U64(wb_data[0], wb_data[1]);
590 static int bnx2x_mc_assert(struct bnx2x *bp)
594 u32 row0, row1, row2, row3;
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
711 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
717 u32 trace_shmem_base;
719 BNX2X_ERR("NO MCP - can not dump\n");
722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
736 mark = REG_RD(bp, addr);
737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
743 for (word = 0; word < 8; word++)
744 data[word] = htonl(REG_RD(bp, offset + 4*word));
746 pr_cont("%s", (char *)data);
748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
749 for (word = 0; word < 8; word++)
750 data[word] = htonl(REG_RD(bp, offset + 4*word));
752 pr_cont("%s", (char *)data);
754 printk("%s" "end of fw dump\n", lvl);
757 static inline void bnx2x_fw_dump(struct bnx2x *bp)
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
762 void bnx2x_panic_dump(struct bnx2x *bp)
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768 #ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
776 BNX2X_ERR("begin crash dump -----------------\n");
780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
801 "pf_id(0x%x) vnic_id(0x%x) "
802 "vf_id(0x%x) vf_valid (0x%x) "
804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
809 sp_sb_data.p_func.vf_valid,
813 for_each_eth_queue(bp, i) {
814 struct bnx2x_fastpath *fp = &bp->fp[i];
816 struct hc_status_block_data_e2 sb_data_e2;
817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
822 struct hc_index_data *hc_index_p =
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
828 struct bnx2x_fp_txdata txdata;
831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
832 " rx_comp_prod(0x%x)"
833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
834 i, fp->rx_bd_prod, fp->rx_bd_cons,
836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
838 " fp_hc_idx(0x%x)\n",
839 fp->rx_sge_prod, fp->last_max_sge,
840 le16_to_cpu(fp->fp_hc_idx));
843 for_each_cos_in_tx_queue(fp, cos)
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
852 le16_to_cpu(*txdata.tx_cons_sb));
855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
879 data_size /= sizeof(u32);
880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
929 hc_index_p[j].timeout);
933 #ifdef BNX2X_STOP_ON_ERROR
936 for_each_rx_queue(bp, i) {
937 struct bnx2x_fastpath *fp = &bp->fp[i];
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
941 for (j = start; j != end; j = RX_BD(j + 1)) {
942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
951 for (j = start; j != end; j = RX_SGE(j + 1)) {
952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
970 for_each_tx_queue(bp, i) {
971 struct bnx2x_fastpath *fp = &bp->fp[i];
972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
994 i, cos, j, tx_bd[0], tx_bd[1],
1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
1006 * FLR Support for E2
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1011 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012 #define FLR_WAIT_INTERAVAL 50 /* usec */
1013 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1015 struct pbf_pN_buf_regs {
1022 struct pbf_pN_cmd_regs {
1028 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1063 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1095 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1098 u32 cur_cnt = poll_count;
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1107 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1118 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1127 return FLR_POLL_CNT;
1130 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1195 #define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1198 #define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1201 #define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1205 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1208 struct sdm_op_gen op_gen = {0};
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1237 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1242 pos = pci_pcie_cap(dev);
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1250 /* PF FLR specific routines
1252 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1299 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1329 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1353 /* Wait 100ms (not adjusted according to platform) */
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1361 bnx2x_hw_enable_status(bp);
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1372 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1374 int port = BP_PORT(bp);
1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1400 REG_WR(bp, addr, val);
1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1412 REG_WR(bp, addr, val);
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1419 if (!CHIP_IS_E1(bp)) {
1420 /* init leading/trailing edge */
1422 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1424 /* enable nig and gpio3 attention */
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1433 /* Make sure that interrupts are indeed enabled from here on */
1437 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1472 /* init leading/trailing edge */
1474 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1476 /* enable nig and gpio3 attention */
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1484 /* Make sure that interrupts are indeed enabled from here on */
1488 void bnx2x_int_enable(struct bnx2x *bp)
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1493 bnx2x_igu_int_enable(bp);
1496 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1498 int port = BP_PORT(bp);
1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1526 /* flush all outstanding writes */
1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1534 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1544 /* flush all outstanding writes */
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1552 void bnx2x_int_disable(struct bnx2x *bp)
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1557 bnx2x_igu_int_disable(bp);
1560 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
1569 /* make sure all ISRs are done */
1571 synchronize_irq(bp->msix_table[0].vector);
1576 for_each_eth_queue(bp, i)
1577 synchronize_irq(bp->msix_table[offset++].vector);
1579 synchronize_irq(bp->pdev->irq);
1581 /* make sure sp_task is not running */
1582 cancel_delayed_work(&bp->sp_task);
1583 cancel_delayed_work(&bp->period_task);
1584 flush_workqueue(bnx2x_wq);
1590 * General service functions
1593 /* Return true if succeeded to acquire the lock */
1594 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1630 * @bp: driver handle
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1635 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1646 * @bp: driver handle
1648 * Tries to aquire a leader lock for cuurent engine.
1650 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1656 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1659 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1669 fp->index, cid, command, bp->state,
1670 rr_cqe->ramrod_cqe.ramrod_type);
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1674 DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1677 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1678 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1679 drv_cmd = BNX2X_Q_CMD_SETUP;
1682 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1683 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1684 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1687 case (RAMROD_CMD_ID_ETH_HALT):
1688 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1689 drv_cmd = BNX2X_Q_CMD_HALT;
1692 case (RAMROD_CMD_ID_ETH_TERMINATE):
1693 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1694 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1697 case (RAMROD_CMD_ID_ETH_EMPTY):
1698 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
1699 drv_cmd = BNX2X_Q_CMD_EMPTY;
1703 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1704 command, fp->index);
1708 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1709 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1710 /* q_obj->complete_cmd() failure means that this was
1711 * an unexpected completion.
1713 * In this case we don't want to increase the bp->spq_left
1714 * because apparently we haven't sent this command the first
1717 #ifdef BNX2X_STOP_ON_ERROR
1723 smp_mb__before_atomic_inc();
1724 atomic_inc(&bp->cq_spq_left);
1725 /* push the change in bp->spq_left and towards the memory */
1726 smp_mb__after_atomic_inc();
1731 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1732 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1734 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1736 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1740 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1742 struct bnx2x *bp = netdev_priv(dev_instance);
1743 u16 status = bnx2x_ack_int(bp);
1748 /* Return here if interrupt is shared and it's not for us */
1749 if (unlikely(status == 0)) {
1750 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1753 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1755 #ifdef BNX2X_STOP_ON_ERROR
1756 if (unlikely(bp->panic))
1760 for_each_eth_queue(bp, i) {
1761 struct bnx2x_fastpath *fp = &bp->fp[i];
1763 mask = 0x2 << (fp->index + CNIC_PRESENT);
1764 if (status & mask) {
1765 /* Handle Rx or Tx according to SB id */
1766 prefetch(fp->rx_cons_sb);
1767 for_each_cos_in_tx_queue(fp, cos)
1768 prefetch(fp->txdata[cos].tx_cons_sb);
1769 prefetch(&fp->sb_running_index[SM_RX_ID]);
1770 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1777 if (status & (mask | 0x1)) {
1778 struct cnic_ops *c_ops = NULL;
1780 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1782 c_ops = rcu_dereference(bp->cnic_ops);
1784 c_ops->cnic_handler(bp->cnic_data, NULL);
1792 if (unlikely(status & 0x1)) {
1793 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1800 if (unlikely(status))
1801 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1810 * General service functions
1813 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1816 u32 resource_bit = (1 << resource);
1817 int func = BP_FUNC(bp);
1818 u32 hw_lock_control_reg;
1821 /* Validating that the resource is within range */
1822 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1824 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1825 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1830 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1832 hw_lock_control_reg =
1833 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1836 /* Validating that the resource is not already taken */
1837 lock_status = REG_RD(bp, hw_lock_control_reg);
1838 if (lock_status & resource_bit) {
1839 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1840 lock_status, resource_bit);
1844 /* Try for 5 second every 5ms */
1845 for (cnt = 0; cnt < 1000; cnt++) {
1846 /* Try to acquire the lock */
1847 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1848 lock_status = REG_RD(bp, hw_lock_control_reg);
1849 if (lock_status & resource_bit)
1854 DP(NETIF_MSG_HW, "Timeout\n");
1858 int bnx2x_release_leader_lock(struct bnx2x *bp)
1860 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1863 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1866 u32 resource_bit = (1 << resource);
1867 int func = BP_FUNC(bp);
1868 u32 hw_lock_control_reg;
1870 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1872 /* Validating that the resource is within range */
1873 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1875 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1876 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1881 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1883 hw_lock_control_reg =
1884 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1887 /* Validating that the resource is currently taken */
1888 lock_status = REG_RD(bp, hw_lock_control_reg);
1889 if (!(lock_status & resource_bit)) {
1890 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1891 lock_status, resource_bit);
1895 REG_WR(bp, hw_lock_control_reg, resource_bit);
1900 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1902 /* The GPIO should be swapped if swap register is set and active */
1903 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1904 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1905 int gpio_shift = gpio_num +
1906 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1907 u32 gpio_mask = (1 << gpio_shift);
1911 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1912 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1916 /* read GPIO value */
1917 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1919 /* get the requested pin value */
1920 if ((gpio_reg & gpio_mask) == gpio_mask)
1925 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1930 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1932 /* The GPIO should be swapped if swap register is set and active */
1933 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1934 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1935 int gpio_shift = gpio_num +
1936 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1937 u32 gpio_mask = (1 << gpio_shift);
1940 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1941 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1945 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1946 /* read GPIO and mask except the float bits */
1947 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1950 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1951 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1952 gpio_num, gpio_shift);
1953 /* clear FLOAT and set CLR */
1954 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1955 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1958 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1959 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1960 gpio_num, gpio_shift);
1961 /* clear FLOAT and set SET */
1962 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1963 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1966 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1967 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1968 gpio_num, gpio_shift);
1970 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1977 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1978 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1983 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1988 /* Any port swapping should be handled by caller. */
1990 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1991 /* read GPIO and mask except the float bits */
1992 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1993 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1998 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1999 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2001 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2004 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2005 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2007 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2010 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2011 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2013 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2017 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2023 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2025 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2030 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2047 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2050 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2051 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2052 "output low\n", gpio_num, gpio_shift);
2053 /* clear SET and set CLR */
2054 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2055 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2058 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2059 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2060 "output high\n", gpio_num, gpio_shift);
2061 /* clear CLR and set SET */
2062 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2063 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2070 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2071 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2076 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2078 u32 spio_mask = (1 << spio_num);
2081 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2082 (spio_num > MISC_REGISTERS_SPIO_7)) {
2083 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2087 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2088 /* read SPIO and mask except the float bits */
2089 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2092 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2093 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2094 /* clear FLOAT and set CLR */
2095 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2096 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2099 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2100 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2101 /* clear FLOAT and set SET */
2102 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2103 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2106 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2107 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2109 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2116 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2117 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2122 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2124 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2125 switch (bp->link_vars.ieee_fc &
2126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2128 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2132 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2133 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2137 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2138 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2142 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2148 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2150 if (!BP_NOMCP(bp)) {
2152 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2153 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2154 /* Initialize link parameters structure variables */
2155 /* It is recommended to turn off RX FC for jumbo frames
2156 for better performance */
2157 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
2158 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2160 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2162 bnx2x_acquire_phy_lock(bp);
2164 if (load_mode == LOAD_DIAG) {
2165 bp->link_params.loopback_mode = LOOPBACK_XGXS;
2166 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
2169 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2171 bnx2x_release_phy_lock(bp);
2173 bnx2x_calc_fc_adv(bp);
2175 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2176 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2177 bnx2x_link_report(bp);
2179 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2180 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2183 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2187 void bnx2x_link_set(struct bnx2x *bp)
2189 if (!BP_NOMCP(bp)) {
2190 bnx2x_acquire_phy_lock(bp);
2191 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2192 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2193 bnx2x_release_phy_lock(bp);
2195 bnx2x_calc_fc_adv(bp);
2197 BNX2X_ERR("Bootcode is missing - can not set link\n");
2200 static void bnx2x__link_reset(struct bnx2x *bp)
2202 if (!BP_NOMCP(bp)) {
2203 bnx2x_acquire_phy_lock(bp);
2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2205 bnx2x_release_phy_lock(bp);
2207 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2210 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2214 if (!BP_NOMCP(bp)) {
2215 bnx2x_acquire_phy_lock(bp);
2216 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2218 bnx2x_release_phy_lock(bp);
2220 BNX2X_ERR("Bootcode is missing - can not test link\n");
2225 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2227 u32 r_param = bp->link_vars.line_speed / 8;
2228 u32 fair_periodic_timeout_usec;
2231 memset(&(bp->cmng.rs_vars), 0,
2232 sizeof(struct rate_shaping_vars_per_port));
2233 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2235 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2236 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2238 /* this is the threshold below which no timer arming will occur
2239 1.25 coefficient is for the threshold to be a little bigger
2240 than the real time, to compensate for timer in-accuracy */
2241 bp->cmng.rs_vars.rs_threshold =
2242 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2244 /* resolution of fairness timer */
2245 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2246 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2247 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2249 /* this is the threshold below which we won't arm the timer anymore */
2250 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2252 /* we multiply by 1e3/8 to get bytes/msec.
2253 We don't want the credits to pass a credit
2254 of the t_fair*FAIR_MEM (algorithm resolution) */
2255 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2256 /* since each tick is 4 usec */
2257 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2260 /* Calculates the sum of vn_min_rates.
2261 It's needed for further normalizing of the min_rates.
2263 sum of vn_min_rates.
2265 0 - if all the min_rates are 0.
2266 In the later case fainess algorithm should be deactivated.
2267 If not all min_rates are zero then those that are zeroes will be set to 1.
2269 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2274 bp->vn_weight_sum = 0;
2275 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2276 u32 vn_cfg = bp->mf_config[vn];
2277 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2278 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2280 /* Skip hidden vns */
2281 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2284 /* If min rate is zero - set it to 1 */
2286 vn_min_rate = DEF_MIN_RATE;
2290 bp->vn_weight_sum += vn_min_rate;
2293 /* if ETS or all min rates are zeros - disable fairness */
2294 if (BNX2X_IS_ETS_ENABLED(bp)) {
2295 bp->cmng.flags.cmng_enables &=
2296 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2297 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2298 } else if (all_zero) {
2299 bp->cmng.flags.cmng_enables &=
2300 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2301 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2302 " fairness will be disabled\n");
2304 bp->cmng.flags.cmng_enables |=
2305 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2308 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2310 struct rate_shaping_vars_per_vn m_rs_vn;
2311 struct fairness_vars_per_vn m_fair_vn;
2312 u32 vn_cfg = bp->mf_config[vn];
2313 int func = 2*vn + BP_PORT(bp);
2314 u16 vn_min_rate, vn_max_rate;
2317 /* If function is hidden - set min and max to zeroes */
2318 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2323 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2325 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2326 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2327 /* If fairness is enabled (not all min rates are zeroes) and
2328 if current min rate is zero - set it to 1.
2329 This is a requirement of the algorithm. */
2330 if (bp->vn_weight_sum && (vn_min_rate == 0))
2331 vn_min_rate = DEF_MIN_RATE;
2334 /* maxCfg in percents of linkspeed */
2335 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2337 /* maxCfg is absolute in 100Mb units */
2338 vn_max_rate = maxCfg * 100;
2342 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2343 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2345 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2346 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2348 /* global vn counter - maximal Mbps for this vn */
2349 m_rs_vn.vn_counter.rate = vn_max_rate;
2351 /* quota - number of bytes transmitted in this period */
2352 m_rs_vn.vn_counter.quota =
2353 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2355 if (bp->vn_weight_sum) {
2356 /* credit for each period of the fairness algorithm:
2357 number of bytes in T_FAIR (the vn share the port rate).
2358 vn_weight_sum should not be larger than 10000, thus
2359 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2361 m_fair_vn.vn_credit_delta =
2362 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2363 (8 * bp->vn_weight_sum))),
2364 (bp->cmng.fair_vars.fair_threshold +
2366 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2367 m_fair_vn.vn_credit_delta);
2370 /* Store it to internal memory */
2371 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2372 REG_WR(bp, BAR_XSTRORM_INTMEM +
2373 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2374 ((u32 *)(&m_rs_vn))[i]);
2376 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2377 REG_WR(bp, BAR_XSTRORM_INTMEM +
2378 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2379 ((u32 *)(&m_fair_vn))[i]);
2382 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2384 if (CHIP_REV_IS_SLOW(bp))
2385 return CMNG_FNS_NONE;
2387 return CMNG_FNS_MINMAX;
2389 return CMNG_FNS_NONE;
2392 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2394 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2397 return; /* what should be the default bvalue in this case */
2399 /* For 2 port configuration the absolute function number formula
2401 * abs_func = 2 * vn + BP_PORT + BP_PATH
2403 * and there are 4 functions per port
2405 * For 4 port configuration it is
2406 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2408 * and there are 2 functions per port
2410 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2411 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2413 if (func >= E1H_FUNC_MAX)
2417 MF_CFG_RD(bp, func_mf_config[func].config);
2421 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2424 if (cmng_type == CMNG_FNS_MINMAX) {
2427 /* clear cmng_enables */
2428 bp->cmng.flags.cmng_enables = 0;
2430 /* read mf conf from shmem */
2432 bnx2x_read_mf_cfg(bp);
2434 /* Init rate shaping and fairness contexts */
2435 bnx2x_init_port_minmax(bp);
2437 /* vn_weight_sum and enable fairness if not 0 */
2438 bnx2x_calc_vn_weight_sum(bp);
2440 /* calculate and set min-max rate for each vn */
2442 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2443 bnx2x_init_vn_minmax(bp, vn);
2445 /* always enable rate shaping and fairness */
2446 bp->cmng.flags.cmng_enables |=
2447 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2448 if (!bp->vn_weight_sum)
2449 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2450 " fairness will be disabled\n");
2454 /* rate shaping and fairness are disabled */
2456 "rate shaping and fairness are disabled\n");
2459 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2461 int port = BP_PORT(bp);
2465 /* Set the attention towards other drivers on the same port */
2466 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2467 if (vn == BP_E1HVN(bp))
2470 func = ((vn << 1) | port);
2471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2472 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2476 /* This function is called upon link interrupt */
2477 static void bnx2x_link_attn(struct bnx2x *bp)
2479 /* Make sure that we are synced with the current statistics */
2480 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2482 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2484 if (bp->link_vars.link_up) {
2486 /* dropless flow control */
2487 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2488 int port = BP_PORT(bp);
2489 u32 pause_enabled = 0;
2491 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2494 REG_WR(bp, BAR_USTRORM_INTMEM +
2495 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2499 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2500 struct host_port_stats *pstats;
2502 pstats = bnx2x_sp(bp, port_stats);
2503 /* reset old mac stats */
2504 memset(&(pstats->mac_stx[0]), 0,
2505 sizeof(struct mac_stx));
2507 if (bp->state == BNX2X_STATE_OPEN)
2508 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2511 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2512 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2514 if (cmng_fns != CMNG_FNS_NONE) {
2515 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2516 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2518 /* rate shaping and fairness are disabled */
2520 "single function mode without fairness\n");
2523 __bnx2x_link_report(bp);
2526 bnx2x_link_sync_notify(bp);
2529 void bnx2x__link_status_update(struct bnx2x *bp)
2531 if (bp->state != BNX2X_STATE_OPEN)
2534 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2536 if (bp->link_vars.link_up)
2537 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2539 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2541 /* indicate link status */
2542 bnx2x_link_report(bp);
2545 static void bnx2x_pmf_update(struct bnx2x *bp)
2547 int port = BP_PORT(bp);
2551 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2554 * We need the mb() to ensure the ordering between the writing to
2555 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2559 /* queue a periodic task */
2560 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2562 bnx2x_dcbx_pmf_update(bp);
2564 /* enable nig attention */
2565 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2566 if (bp->common.int_block == INT_BLOCK_HC) {
2567 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2568 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2569 } else if (!CHIP_IS_E1x(bp)) {
2570 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2571 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2574 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2582 * General service functions
2585 /* send the MCP a request, block until there is a reply */
2586 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2588 int mb_idx = BP_FW_MB_IDX(bp);
2592 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2594 mutex_lock(&bp->fw_mb_mutex);
2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2597 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2599 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2600 (command | seq), param);
2603 /* let the FW do it's magic ... */
2606 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2608 /* Give the FW up to 5 second (500*10ms) */
2609 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2611 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2612 cnt*delay, rc, seq);
2614 /* is this a reply to our command? */
2615 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2616 rc &= FW_MSG_CODE_MASK;
2619 BNX2X_ERR("FW failed to respond!\n");
2623 mutex_unlock(&bp->fw_mb_mutex);
2628 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2631 /* Statistics are not supported for CNIC Clients at the moment */
2638 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2640 if (CHIP_IS_E1x(bp)) {
2641 struct tstorm_eth_function_common_config tcfg = {0};
2643 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2646 /* Enable the function in the FW */
2647 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2648 storm_memset_func_en(bp, p->func_id, 1);
2651 if (p->func_flgs & FUNC_FLG_SPQ) {
2652 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2653 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2654 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2659 * bnx2x_get_tx_only_flags - Return common flags
2663 * @zero_stats TRUE if statistics zeroing is needed
2665 * Return the flags that are common for the Tx-only and not normal connections.
2667 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2668 struct bnx2x_fastpath *fp,
2671 unsigned long flags = 0;
2673 /* PF driver will always initialize the Queue to an ACTIVE state */
2674 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2676 /* tx only connections collect statistics (on the same index as the
2677 * parent connection). The statistics are zeroed when the parent
2678 * connection is initialized.
2680 if (stat_counter_valid(bp, fp)) {
2681 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2683 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2689 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2690 struct bnx2x_fastpath *fp,
2693 unsigned long flags = 0;
2695 /* calculate other queue flags */
2697 __set_bit(BNX2X_Q_FLG_OV, &flags);
2700 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2702 if (!fp->disable_tpa) {
2703 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2704 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2708 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2709 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2712 /* Always set HW VLAN stripping */
2713 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2716 return flags | bnx2x_get_common_flags(bp, fp, true);
2719 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2720 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2723 gen_init->stat_id = bnx2x_stats_id(fp);
2724 gen_init->spcl_id = fp->cl_id;
2726 /* Always use mini-jumbo MTU for FCoE L2 ring */
2728 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2730 gen_init->mtu = bp->dev->mtu;
2732 gen_init->cos = cos;
2735 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2736 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2737 struct bnx2x_rxq_setup_params *rxq_init)
2741 u16 tpa_agg_size = 0;
2743 if (!fp->disable_tpa) {
2744 pause->sge_th_hi = 250;
2745 pause->sge_th_lo = 150;
2746 tpa_agg_size = min_t(u32,
2747 (min_t(u32, 8, MAX_SKB_FRAGS) *
2748 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2749 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2751 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2752 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2753 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2757 /* pause - not for e1 */
2758 if (!CHIP_IS_E1(bp)) {
2759 pause->bd_th_hi = 350;
2760 pause->bd_th_lo = 250;
2761 pause->rcq_th_hi = 350;
2762 pause->rcq_th_lo = 250;
2768 rxq_init->dscr_map = fp->rx_desc_mapping;
2769 rxq_init->sge_map = fp->rx_sge_mapping;
2770 rxq_init->rcq_map = fp->rx_comp_mapping;
2771 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2773 /* This should be a maximum number of data bytes that may be
2774 * placed on the BD (not including paddings).
2776 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2777 IP_HEADER_ALIGNMENT_PADDING;
2779 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2780 rxq_init->tpa_agg_sz = tpa_agg_size;
2781 rxq_init->sge_buf_sz = sge_sz;
2782 rxq_init->max_sges_pkt = max_sge;
2783 rxq_init->rss_engine_id = BP_FUNC(bp);
2785 /* Maximum number or simultaneous TPA aggregation for this Queue.
2787 * For PF Clients it should be the maximum avaliable number.
2788 * VF driver(s) may want to define it to a smaller value.
2790 rxq_init->max_tpa_queues =
2791 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2792 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2794 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2795 rxq_init->fw_sb_id = fp->fw_sb_id;
2798 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2800 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2803 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2804 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2807 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2808 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2809 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2810 txq_init->fw_sb_id = fp->fw_sb_id;
2813 * set the tss leading client id for TX classfication ==
2814 * leading RSS client id
2816 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2818 if (IS_FCOE_FP(fp)) {
2819 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2820 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2824 static void bnx2x_pf_init(struct bnx2x *bp)
2826 struct bnx2x_func_init_params func_init = {0};
2827 struct event_ring_data eq_data = { {0} };
2830 if (!CHIP_IS_E1x(bp)) {
2831 /* reset IGU PF statistics: MSIX + ATTN */
2833 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2834 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2835 (CHIP_MODE_IS_4_PORT(bp) ?
2836 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2838 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2839 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2840 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2841 (CHIP_MODE_IS_4_PORT(bp) ?
2842 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2845 /* function setup flags */
2846 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2848 /* This flag is relevant for E1x only.
2849 * E2 doesn't have a TPA configuration in a function level.
2851 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2853 func_init.func_flgs = flags;
2854 func_init.pf_id = BP_FUNC(bp);
2855 func_init.func_id = BP_FUNC(bp);
2856 func_init.spq_map = bp->spq_mapping;
2857 func_init.spq_prod = bp->spq_prod_idx;
2859 bnx2x_func_init(bp, &func_init);
2861 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2864 * Congestion management values depend on the link rate
2865 * There is no active link so initial link rate is set to 10 Gbps.
2866 * When the link comes up The congestion management values are
2867 * re-calculated according to the actual link rate.
2869 bp->link_vars.line_speed = SPEED_10000;
2870 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2872 /* Only the PMF sets the HW */
2874 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2876 /* init Event Queue */
2877 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2878 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2879 eq_data.producer = bp->eq_prod;
2880 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2881 eq_data.sb_id = DEF_SB_ID;
2882 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2886 static void bnx2x_e1h_disable(struct bnx2x *bp)
2888 int port = BP_PORT(bp);
2890 bnx2x_tx_disable(bp);
2892 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2895 static void bnx2x_e1h_enable(struct bnx2x *bp)
2897 int port = BP_PORT(bp);
2899 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2901 /* Tx queue should be only reenabled */
2902 netif_tx_wake_all_queues(bp->dev);
2905 * Should not call netif_carrier_on since it will be called if the link
2906 * is up when checking for link state
2910 /* called due to MCP event (on pmf):
2911 * reread new bandwidth configuration
2913 * notify others function about the change
2915 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2917 if (bp->link_vars.link_up) {
2918 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2919 bnx2x_link_sync_notify(bp);
2921 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2924 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2926 bnx2x_config_mf_bw(bp);
2927 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2930 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2932 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2934 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2937 * This is the only place besides the function initialization
2938 * where the bp->flags can change so it is done without any
2941 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2942 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2943 bp->flags |= MF_FUNC_DIS;
2945 bnx2x_e1h_disable(bp);
2947 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2948 bp->flags &= ~MF_FUNC_DIS;
2950 bnx2x_e1h_enable(bp);
2952 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2954 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2955 bnx2x_config_mf_bw(bp);
2956 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2959 /* Report results to MCP */
2961 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2963 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2966 /* must be called under the spq lock */
2967 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2969 struct eth_spe *next_spe = bp->spq_prod_bd;
2971 if (bp->spq_prod_bd == bp->spq_last_bd) {
2972 bp->spq_prod_bd = bp->spq;
2973 bp->spq_prod_idx = 0;
2974 DP(NETIF_MSG_TIMER, "end of spq\n");
2982 /* must be called under the spq lock */
2983 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2985 int func = BP_FUNC(bp);
2988 * Make sure that BD data is updated before writing the producer:
2989 * BD data is written to the memory, the producer is read from the
2990 * memory, thus we need a full memory barrier to ensure the ordering.
2994 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3000 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3002 * @cmd: command to check
3003 * @cmd_type: command type
3005 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3007 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3008 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3009 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3010 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3011 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3012 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3013 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3022 * bnx2x_sp_post - place a single command on an SP ring
3024 * @bp: driver handle
3025 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3026 * @cid: SW CID the command is related to
3027 * @data_hi: command private data address (high 32 bits)
3028 * @data_lo: command private data address (low 32 bits)
3029 * @cmd_type: command type (e.g. NONE, ETH)
3031 * SP data is handled as if it's always an address pair, thus data fields are
3032 * not swapped to little endian in upper functions. Instead this function swaps
3033 * data as if it's two u32 fields.
3035 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3036 u32 data_hi, u32 data_lo, int cmd_type)
3038 struct eth_spe *spe;
3040 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3042 #ifdef BNX2X_STOP_ON_ERROR
3043 if (unlikely(bp->panic))
3047 spin_lock_bh(&bp->spq_lock);
3050 if (!atomic_read(&bp->eq_spq_left)) {
3051 BNX2X_ERR("BUG! EQ ring full!\n");
3052 spin_unlock_bh(&bp->spq_lock);
3056 } else if (!atomic_read(&bp->cq_spq_left)) {
3057 BNX2X_ERR("BUG! SPQ ring full!\n");
3058 spin_unlock_bh(&bp->spq_lock);
3063 spe = bnx2x_sp_get_next(bp);
3065 /* CID needs port number to be encoded int it */
3066 spe->hdr.conn_and_cmd_data =
3067 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3070 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3072 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3073 SPE_HDR_FUNCTION_ID);
3075 spe->hdr.type = cpu_to_le16(type);
3077 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3078 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3080 /* stats ramrod has it's own slot on the spq */
3081 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
3083 * It's ok if the actual decrement is issued towards the memory
3084 * somewhere between the spin_lock and spin_unlock. Thus no
3085 * more explict memory barrier is needed.
3088 atomic_dec(&bp->eq_spq_left);
3090 atomic_dec(&bp->cq_spq_left);
3094 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3095 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
3096 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
3097 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3098 (u32)(U64_LO(bp->spq_mapping) +
3099 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
3100 HW_CID(bp, cid), data_hi, data_lo, type,
3101 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3103 bnx2x_sp_prod_update(bp);
3104 spin_unlock_bh(&bp->spq_lock);
3108 /* acquire split MCP access lock register */
3109 static int bnx2x_acquire_alr(struct bnx2x *bp)
3115 for (j = 0; j < 1000; j++) {
3117 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3118 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3119 if (val & (1L << 31))
3124 if (!(val & (1L << 31))) {
3125 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3132 /* release split MCP access lock register */
3133 static void bnx2x_release_alr(struct bnx2x *bp)
3135 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3138 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3139 #define BNX2X_DEF_SB_IDX 0x0002
3141 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3143 struct host_sp_status_block *def_sb = bp->def_status_blk;
3146 barrier(); /* status block is written to by the chip */
3147 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3148 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3149 rc |= BNX2X_DEF_SB_ATT_IDX;
3152 if (bp->def_idx != def_sb->sp_sb.running_index) {
3153 bp->def_idx = def_sb->sp_sb.running_index;
3154 rc |= BNX2X_DEF_SB_IDX;
3157 /* Do not reorder: indecies reading should complete before handling */
3163 * slow path service functions
3166 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3168 int port = BP_PORT(bp);
3169 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3170 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3171 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3172 NIG_REG_MASK_INTERRUPT_PORT0;
3177 if (bp->attn_state & asserted)
3178 BNX2X_ERR("IGU ERROR\n");
3180 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3181 aeu_mask = REG_RD(bp, aeu_addr);
3183 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3184 aeu_mask, asserted);
3185 aeu_mask &= ~(asserted & 0x3ff);
3186 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3188 REG_WR(bp, aeu_addr, aeu_mask);
3189 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3191 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3192 bp->attn_state |= asserted;
3193 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3195 if (asserted & ATTN_HARD_WIRED_MASK) {
3196 if (asserted & ATTN_NIG_FOR_FUNC) {
3198 bnx2x_acquire_phy_lock(bp);
3200 /* save nig interrupt mask */
3201 nig_mask = REG_RD(bp, nig_int_mask_addr);
3203 /* If nig_mask is not set, no need to call the update
3207 REG_WR(bp, nig_int_mask_addr, 0);
3209 bnx2x_link_attn(bp);
3212 /* handle unicore attn? */
3214 if (asserted & ATTN_SW_TIMER_4_FUNC)
3215 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3217 if (asserted & GPIO_2_FUNC)
3218 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3220 if (asserted & GPIO_3_FUNC)
3221 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3223 if (asserted & GPIO_4_FUNC)
3224 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3227 if (asserted & ATTN_GENERAL_ATTN_1) {
3228 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3229 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3231 if (asserted & ATTN_GENERAL_ATTN_2) {
3232 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3233 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3235 if (asserted & ATTN_GENERAL_ATTN_3) {
3236 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3237 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3240 if (asserted & ATTN_GENERAL_ATTN_4) {
3241 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3242 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3244 if (asserted & ATTN_GENERAL_ATTN_5) {
3245 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3246 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3248 if (asserted & ATTN_GENERAL_ATTN_6) {
3249 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3250 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3254 } /* if hardwired */
3256 if (bp->common.int_block == INT_BLOCK_HC)
3257 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3258 COMMAND_REG_ATTN_BITS_SET);
3260 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3262 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3263 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3264 REG_WR(bp, reg_addr, asserted);
3266 /* now set back the mask */
3267 if (asserted & ATTN_NIG_FOR_FUNC) {
3268 REG_WR(bp, nig_int_mask_addr, nig_mask);
3269 bnx2x_release_phy_lock(bp);
3273 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3275 int port = BP_PORT(bp);
3277 /* mark the failure */
3280 dev_info.port_hw_config[port].external_phy_config);
3282 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3283 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3284 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3287 /* log the failure */
3288 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3289 " the driver to shutdown the card to prevent permanent"
3290 " damage. Please contact OEM Support for assistance\n");
3293 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3295 int port = BP_PORT(bp);
3299 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3300 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3302 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3304 val = REG_RD(bp, reg_offset);
3305 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3306 REG_WR(bp, reg_offset, val);
3308 BNX2X_ERR("SPIO5 hw attention\n");
3310 /* Fan failure attention */
3311 bnx2x_hw_reset_phy(&bp->link_params);
3312 bnx2x_fan_failure(bp);
3315 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3316 bnx2x_acquire_phy_lock(bp);
3317 bnx2x_handle_module_detect_int(&bp->link_params);
3318 bnx2x_release_phy_lock(bp);
3321 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3323 val = REG_RD(bp, reg_offset);
3324 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3325 REG_WR(bp, reg_offset, val);
3327 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3328 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3333 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3337 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3339 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3340 BNX2X_ERR("DB hw attention 0x%x\n", val);
3341 /* DORQ discard attention */
3343 BNX2X_ERR("FATAL error from DORQ\n");
3346 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3348 int port = BP_PORT(bp);
3351 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3352 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3354 val = REG_RD(bp, reg_offset);
3355 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3356 REG_WR(bp, reg_offset, val);
3358 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3359 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3364 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3368 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3370 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3371 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3372 /* CFC error attention */
3374 BNX2X_ERR("FATAL error from CFC\n");
3377 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3378 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3379 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3380 /* RQ_USDMDP_FIFO_OVERFLOW */
3382 BNX2X_ERR("FATAL error from PXP\n");
3384 if (!CHIP_IS_E1x(bp)) {
3385 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3386 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3390 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3392 int port = BP_PORT(bp);
3395 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3396 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3398 val = REG_RD(bp, reg_offset);
3399 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3400 REG_WR(bp, reg_offset, val);
3402 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3403 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3408 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3412 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3414 if (attn & BNX2X_PMF_LINK_ASSERT) {
3415 int func = BP_FUNC(bp);
3417 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3418 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3419 func_mf_config[BP_ABS_FUNC(bp)].config);
3421 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3422 if (val & DRV_STATUS_DCC_EVENT_MASK)
3424 (val & DRV_STATUS_DCC_EVENT_MASK));
3426 if (val & DRV_STATUS_SET_MF_BW)
3427 bnx2x_set_mf_bw(bp);
3429 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3430 bnx2x_pmf_update(bp);
3433 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3434 bp->dcbx_enabled > 0)
3435 /* start dcbx state machine */
3436 bnx2x_dcbx_set_params(bp,
3437 BNX2X_DCBX_STATE_NEG_RECEIVED);
3438 if (bp->link_vars.periodic_flags &
3439 PERIODIC_FLAGS_LINK_EVENT) {
3440 /* sync with link */
3441 bnx2x_acquire_phy_lock(bp);
3442 bp->link_vars.periodic_flags &=
3443 ~PERIODIC_FLAGS_LINK_EVENT;
3444 bnx2x_release_phy_lock(bp);
3446 bnx2x_link_sync_notify(bp);
3447 bnx2x_link_report(bp);
3449 /* Always call it here: bnx2x_link_report() will
3450 * prevent the link indication duplication.
3452 bnx2x__link_status_update(bp);
3453 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3455 BNX2X_ERR("MC assert!\n");
3456 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3457 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3458 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3459 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3462 } else if (attn & BNX2X_MCP_ASSERT) {
3464 BNX2X_ERR("MCP assert!\n");
3465 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3469 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3472 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3473 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3474 if (attn & BNX2X_GRC_TIMEOUT) {
3475 val = CHIP_IS_E1(bp) ? 0 :
3476 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3477 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3479 if (attn & BNX2X_GRC_RSV) {
3480 val = CHIP_IS_E1(bp) ? 0 :
3481 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3482 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3484 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3490 * 0-7 - Engine0 load counter.
3491 * 8-15 - Engine1 load counter.
3492 * 16 - Engine0 RESET_IN_PROGRESS bit.
3493 * 17 - Engine1 RESET_IN_PROGRESS bit.
3494 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3496 * 19 - Engine1 ONE_IS_LOADED.
3497 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3498 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3499 * just the one belonging to its engine).
3502 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3504 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3505 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3506 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3507 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3508 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3509 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3510 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3513 * Set the GLOBAL_RESET bit.
3515 * Should be run under rtnl lock
3517 void bnx2x_set_reset_global(struct bnx2x *bp)
3519 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3521 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3527 * Clear the GLOBAL_RESET bit.
3529 * Should be run under rtnl lock
3531 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3533 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3535 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3541 * Checks the GLOBAL_RESET bit.
3543 * should be run under rtnl lock
3545 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3547 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3549 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3550 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3554 * Clear RESET_IN_PROGRESS bit for the current engine.
3556 * Should be run under rtnl lock
3558 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3560 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3561 u32 bit = BP_PATH(bp) ?
3562 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3566 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3572 * Set RESET_IN_PROGRESS for the current engine.
3574 * should be run under rtnl lock
3576 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3578 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3579 u32 bit = BP_PATH(bp) ?
3580 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3584 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3590 * Checks the RESET_IN_PROGRESS bit for the given engine.
3591 * should be run under rtnl lock
3593 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3595 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3597 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3599 /* return false if bit is set */
3600 return (val & bit) ? false : true;
3604 * Increment the load counter for the current engine.
3606 * should be run under rtnl lock
3608 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3610 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3611 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3612 BNX2X_PATH0_LOAD_CNT_MASK;
3613 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3614 BNX2X_PATH0_LOAD_CNT_SHIFT;
3616 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3618 /* get the current counter value */
3619 val1 = (val & mask) >> shift;
3624 /* clear the old value */
3627 /* set the new one */
3628 val |= ((val1 << shift) & mask);
3630 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3636 * bnx2x_dec_load_cnt - decrement the load counter
3638 * @bp: driver handle
3640 * Should be run under rtnl lock.
3641 * Decrements the load counter for the current engine. Returns
3642 * the new counter value.
3644 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3646 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3647 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3648 BNX2X_PATH0_LOAD_CNT_MASK;
3649 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3650 BNX2X_PATH0_LOAD_CNT_SHIFT;
3652 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3654 /* get the current counter value */
3655 val1 = (val & mask) >> shift;
3660 /* clear the old value */
3663 /* set the new one */
3664 val |= ((val1 << shift) & mask);
3666 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3674 * Read the load counter for the current engine.
3676 * should be run under rtnl lock
3678 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3680 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3681 BNX2X_PATH0_LOAD_CNT_MASK);
3682 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3683 BNX2X_PATH0_LOAD_CNT_SHIFT);
3684 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3686 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3688 val = (val & mask) >> shift;
3690 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3696 * Reset the load counter for the current engine.
3698 * should be run under rtnl lock
3700 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3702 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3703 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3704 BNX2X_PATH0_LOAD_CNT_MASK);
3706 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3709 static inline void _print_next_block(int idx, const char *blk)
3716 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3721 for (i = 0; sig; i++) {
3722 cur_bit = ((u32)0x1 << i);
3723 if (sig & cur_bit) {
3725 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3727 _print_next_block(par_num++, "BRB");
3729 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3731 _print_next_block(par_num++, "PARSER");
3733 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3735 _print_next_block(par_num++, "TSDM");
3737 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3739 _print_next_block(par_num++,
3742 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3744 _print_next_block(par_num++, "TCM");
3746 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3748 _print_next_block(par_num++, "TSEMI");
3750 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3752 _print_next_block(par_num++, "XPB");
3764 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3765 bool *global, bool print)
3769 for (i = 0; sig; i++) {
3770 cur_bit = ((u32)0x1 << i);
3771 if (sig & cur_bit) {
3773 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3775 _print_next_block(par_num++, "PBF");
3777 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3779 _print_next_block(par_num++, "QM");
3781 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3783 _print_next_block(par_num++, "TM");
3785 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3787 _print_next_block(par_num++, "XSDM");
3789 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3791 _print_next_block(par_num++, "XCM");
3793 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3795 _print_next_block(par_num++, "XSEMI");
3797 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3799 _print_next_block(par_num++,
3802 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3804 _print_next_block(par_num++, "NIG");
3806 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3808 _print_next_block(par_num++,
3812 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3814 _print_next_block(par_num++, "DEBUG");
3816 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3818 _print_next_block(par_num++, "USDM");
3820 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3822 _print_next_block(par_num++, "USEMI");
3824 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3826 _print_next_block(par_num++, "UPB");
3828 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3830 _print_next_block(par_num++, "CSDM");
3842 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3847 for (i = 0; sig; i++) {
3848 cur_bit = ((u32)0x1 << i);
3849 if (sig & cur_bit) {
3851 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3853 _print_next_block(par_num++, "CSEMI");
3855 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3857 _print_next_block(par_num++, "PXP");
3859 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3861 _print_next_block(par_num++,
3862 "PXPPCICLOCKCLIENT");
3864 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3866 _print_next_block(par_num++, "CFC");
3868 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3870 _print_next_block(par_num++, "CDU");
3872 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3874 _print_next_block(par_num++, "DMAE");
3876 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3878 _print_next_block(par_num++, "IGU");
3880 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3882 _print_next_block(par_num++, "MISC");
3894 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3895 bool *global, bool print)
3899 for (i = 0; sig; i++) {
3900 cur_bit = ((u32)0x1 << i);
3901 if (sig & cur_bit) {
3903 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3905 _print_next_block(par_num++, "MCP ROM");
3908 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3910 _print_next_block(par_num++,
3914 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3916 _print_next_block(par_num++,
3920 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3922 _print_next_block(par_num++,
3936 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3937 u32 sig0, u32 sig1, u32 sig2, u32 sig3)
3939 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3940 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3942 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3943 "[0]:0x%08x [1]:0x%08x "
3944 "[2]:0x%08x [3]:0x%08x\n",
3945 sig0 & HW_PRTY_ASSERT_SET_0,
3946 sig1 & HW_PRTY_ASSERT_SET_1,
3947 sig2 & HW_PRTY_ASSERT_SET_2,
3948 sig3 & HW_PRTY_ASSERT_SET_3);
3951 "Parity errors detected in blocks: ");
3952 par_num = bnx2x_check_blocks_with_parity0(
3953 sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
3954 par_num = bnx2x_check_blocks_with_parity1(
3955 sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
3956 par_num = bnx2x_check_blocks_with_parity2(
3957 sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
3958 par_num = bnx2x_check_blocks_with_parity3(
3959 sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
3968 * bnx2x_chk_parity_attn - checks for parity attentions.
3970 * @bp: driver handle
3971 * @global: true if there was a global attention
3972 * @print: show parity attention in syslog
3974 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
3976 struct attn_route attn;
3977 int port = BP_PORT(bp);
3979 attn.sig[0] = REG_RD(bp,
3980 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3982 attn.sig[1] = REG_RD(bp,
3983 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3985 attn.sig[2] = REG_RD(bp,
3986 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3988 attn.sig[3] = REG_RD(bp,
3989 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3992 return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
3993 attn.sig[2], attn.sig[3]);
3997 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4000 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4002 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4003 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4004 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4005 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4007 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4008 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4009 "INCORRECT_RCV_BEHAVIOR\n");
4010 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4011 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4012 "WAS_ERROR_ATTN\n");
4013 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4014 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4015 "VF_LENGTH_VIOLATION_ATTN\n");
4017 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4018 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4019 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4021 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4022 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4023 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4024 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4025 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4026 "TCPL_ERROR_ATTN\n");
4027 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4028 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4029 "TCPL_IN_TWO_RCBS_ATTN\n");
4030 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4031 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4032 "CSSNOOP_FIFO_OVERFLOW\n");
4034 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4035 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4036 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4037 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4038 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4039 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4040 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4041 "_ATC_TCPL_TO_NOT_PEND\n");
4042 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4043 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4044 "ATC_GPA_MULTIPLE_HITS\n");
4045 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4046 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4047 "ATC_RCPL_TO_EMPTY_CNT\n");
4048 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4049 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4050 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4051 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4052 "ATC_IREQ_LESS_THAN_STU\n");
4055 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4056 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4057 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4058 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4059 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4064 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4066 struct attn_route attn, *group_mask;
4067 int port = BP_PORT(bp);
4072 bool global = false;
4074 /* need to take HW lock because MCP or other port might also
4075 try to handle this event */
4076 bnx2x_acquire_alr(bp);
4078 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4079 #ifndef BNX2X_STOP_ON_ERROR
4080 bp->recovery_state = BNX2X_RECOVERY_INIT;
4081 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4082 /* Disable HW interrupts */
4083 bnx2x_int_disable(bp);
4084 /* In case of parity errors don't handle attentions so that
4085 * other function would "see" parity errors.
4090 bnx2x_release_alr(bp);
4094 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4095 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4096 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4097 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4098 if (!CHIP_IS_E1x(bp))
4100 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4104 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4105 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4107 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4108 if (deasserted & (1 << index)) {
4109 group_mask = &bp->attn_group[index];
4111 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4114 group_mask->sig[0], group_mask->sig[1],
4115 group_mask->sig[2], group_mask->sig[3],
4116 group_mask->sig[4]);
4118 bnx2x_attn_int_deasserted4(bp,
4119 attn.sig[4] & group_mask->sig[4]);
4120 bnx2x_attn_int_deasserted3(bp,
4121 attn.sig[3] & group_mask->sig[3]);
4122 bnx2x_attn_int_deasserted1(bp,
4123 attn.sig[1] & group_mask->sig[1]);
4124 bnx2x_attn_int_deasserted2(bp,
4125 attn.sig[2] & group_mask->sig[2]);
4126 bnx2x_attn_int_deasserted0(bp,
4127 attn.sig[0] & group_mask->sig[0]);
4131 bnx2x_release_alr(bp);
4133 if (bp->common.int_block == INT_BLOCK_HC)
4134 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4135 COMMAND_REG_ATTN_BITS_CLR);
4137 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4140 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4141 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4142 REG_WR(bp, reg_addr, val);
4144 if (~bp->attn_state & deasserted)
4145 BNX2X_ERR("IGU ERROR\n");
4147 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4148 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4150 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4151 aeu_mask = REG_RD(bp, reg_addr);
4153 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4154 aeu_mask, deasserted);
4155 aeu_mask |= (deasserted & 0x3ff);
4156 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4158 REG_WR(bp, reg_addr, aeu_mask);
4159 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4161 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4162 bp->attn_state &= ~deasserted;
4163 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4166 static void bnx2x_attn_int(struct bnx2x *bp)
4168 /* read local copy of bits */
4169 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4171 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4173 u32 attn_state = bp->attn_state;
4175 /* look for changed bits */
4176 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4177 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4180 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4181 attn_bits, attn_ack, asserted, deasserted);
4183 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4184 BNX2X_ERR("BAD attention state\n");
4186 /* handle bits that were raised */
4188 bnx2x_attn_int_asserted(bp, asserted);
4191 bnx2x_attn_int_deasserted(bp, deasserted);
4194 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4195 u16 index, u8 op, u8 update)
4197 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4199 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4203 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4205 /* No memory barriers */
4206 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4207 mmiowb(); /* keep prod updates ordered */
4211 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4212 union event_ring_elem *elem)
4214 u8 err = elem->message.error;
4216 if (!bp->cnic_eth_dev.starting_cid ||
4217 (cid < bp->cnic_eth_dev.starting_cid &&
4218 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4221 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4223 if (unlikely(err)) {
4225 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4227 bnx2x_panic_dump(bp);
4229 bnx2x_cnic_cfc_comp(bp, cid, err);
4234 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4236 struct bnx2x_mcast_ramrod_params rparam;
4239 memset(&rparam, 0, sizeof(rparam));
4241 rparam.mcast_obj = &bp->mcast_obj;
4243 netif_addr_lock_bh(bp->dev);
4245 /* Clear pending state for the last command */
4246 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4248 /* If there are pending mcast commands - send them */
4249 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4250 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4252 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4256 netif_addr_unlock_bh(bp->dev);
4259 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4260 union event_ring_elem *elem)
4262 unsigned long ramrod_flags = 0;
4264 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4265 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4267 /* Always push next commands out, don't wait here */
4268 __set_bit(RAMROD_CONT, &ramrod_flags);
4270 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4271 case BNX2X_FILTER_MAC_PENDING:
4273 if (cid == BNX2X_ISCSI_ETH_CID)
4274 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4277 vlan_mac_obj = &bp->fp[cid].mac_obj;
4280 vlan_mac_obj = &bp->fp[cid].mac_obj;
4282 case BNX2X_FILTER_MCAST_PENDING:
4283 /* This is only relevant for 57710 where multicast MACs are
4284 * configured as unicast MACs using the same ramrod.
4286 bnx2x_handle_mcast_eqe(bp);
4289 BNX2X_ERR("Unsupported classification command: %d\n",
4290 elem->message.data.eth_event.echo);
4294 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4297 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4299 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4304 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4307 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4309 netif_addr_lock_bh(bp->dev);
4311 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4313 /* Send rx_mode command again if was requested */
4314 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4315 bnx2x_set_storm_rx_mode(bp);
4317 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4319 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4320 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4322 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4325 netif_addr_unlock_bh(bp->dev);
4328 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4329 struct bnx2x *bp, u32 cid)
4331 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
4333 if (cid == BNX2X_FCOE_ETH_CID)
4334 return &bnx2x_fcoe(bp, q_obj);
4337 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4340 static void bnx2x_eq_int(struct bnx2x *bp)
4342 u16 hw_cons, sw_cons, sw_prod;
4343 union event_ring_elem *elem;
4347 struct bnx2x_queue_sp_obj *q_obj;
4348 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4349 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4351 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4353 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4354 * when we get the the next-page we nned to adjust so the loop
4355 * condition below will be met. The next element is the size of a
4356 * regular element and hence incrementing by 1
4358 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4361 /* This function may never run in parallel with itself for a
4362 * specific bp, thus there is no need in "paired" read memory
4365 sw_cons = bp->eq_cons;
4366 sw_prod = bp->eq_prod;
4368 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
4369 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4371 for (; sw_cons != hw_cons;
4372 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4375 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4377 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4378 opcode = elem->message.opcode;
4381 /* handle eq element */
4383 case EVENT_RING_OPCODE_STAT_QUERY:
4384 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4386 /* nothing to do with stats comp */
4389 case EVENT_RING_OPCODE_CFC_DEL:
4390 /* handle according to cid range */
4392 * we may want to verify here that the bp state is
4395 DP(NETIF_MSG_IFDOWN,
4396 "got delete ramrod for MULTI[%d]\n", cid);
4398 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4401 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4403 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4410 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4411 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
4412 if (f_obj->complete_cmd(bp, f_obj,
4413 BNX2X_F_CMD_TX_STOP))
4415 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4418 case EVENT_RING_OPCODE_START_TRAFFIC:
4419 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
4420 if (f_obj->complete_cmd(bp, f_obj,
4421 BNX2X_F_CMD_TX_START))
4423 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4425 case EVENT_RING_OPCODE_FUNCTION_START:
4426 DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
4427 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4432 case EVENT_RING_OPCODE_FUNCTION_STOP:
4433 DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
4434 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4440 switch (opcode | bp->state) {
4441 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4443 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4444 BNX2X_STATE_OPENING_WAIT4_PORT):
4445 cid = elem->message.data.eth_event.echo &
4447 DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
4449 rss_raw->clear_pending(rss_raw);
4452 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4453 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4454 case (EVENT_RING_OPCODE_SET_MAC |
4455 BNX2X_STATE_CLOSING_WAIT4_HALT):
4456 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4458 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4460 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4461 BNX2X_STATE_CLOSING_WAIT4_HALT):
4462 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
4463 bnx2x_handle_classification_eqe(bp, elem);
4466 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4468 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4470 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4471 BNX2X_STATE_CLOSING_WAIT4_HALT):
4472 DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
4473 bnx2x_handle_mcast_eqe(bp);
4476 case (EVENT_RING_OPCODE_FILTERS_RULES |
4478 case (EVENT_RING_OPCODE_FILTERS_RULES |
4480 case (EVENT_RING_OPCODE_FILTERS_RULES |
4481 BNX2X_STATE_CLOSING_WAIT4_HALT):
4482 DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
4483 bnx2x_handle_rx_mode_eqe(bp);
4486 /* unknown event log error and continue */
4487 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4488 elem->message.opcode, bp->state);
4494 smp_mb__before_atomic_inc();
4495 atomic_add(spqe_cnt, &bp->eq_spq_left);
4497 bp->eq_cons = sw_cons;
4498 bp->eq_prod = sw_prod;
4499 /* Make sure that above mem writes were issued towards the memory */
4502 /* update producer */
4503 bnx2x_update_eq_prod(bp, bp->eq_prod);
4506 static void bnx2x_sp_task(struct work_struct *work)
4508 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4511 status = bnx2x_update_dsb_idx(bp);
4512 /* if (status == 0) */
4513 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4515 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4518 if (status & BNX2X_DEF_SB_ATT_IDX) {
4520 status &= ~BNX2X_DEF_SB_ATT_IDX;
4523 /* SP events: STAT_QUERY and others */
4524 if (status & BNX2X_DEF_SB_IDX) {
4526 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4528 if ((!NO_FCOE(bp)) &&
4529 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4531 * Prevent local bottom-halves from running as
4532 * we are going to change the local NAPI list.
4535 napi_schedule(&bnx2x_fcoe(bp, napi));
4539 /* Handle EQ completions */
4542 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4543 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4545 status &= ~BNX2X_DEF_SB_IDX;
4548 if (unlikely(status))
4549 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4552 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4553 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4556 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4558 struct net_device *dev = dev_instance;
4559 struct bnx2x *bp = netdev_priv(dev);
4561 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4562 IGU_INT_DISABLE, 0);
4564 #ifdef BNX2X_STOP_ON_ERROR
4565 if (unlikely(bp->panic))
4571 struct cnic_ops *c_ops;
4574 c_ops = rcu_dereference(bp->cnic_ops);
4576 c_ops->cnic_handler(bp->cnic_data, NULL);
4580 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4585 /* end of slow path */
4588 void bnx2x_drv_pulse(struct bnx2x *bp)
4590 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4591 bp->fw_drv_pulse_wr_seq);
4595 static void bnx2x_timer(unsigned long data)
4598 struct bnx2x *bp = (struct bnx2x *) data;
4600 if (!netif_running(bp->dev))
4604 struct bnx2x_fastpath *fp = &bp->fp[0];
4606 for_each_cos_in_tx_queue(fp, cos)
4607 bnx2x_tx_int(bp, &fp->txdata[cos]);
4608 bnx2x_rx_int(fp, 1000);
4611 if (!BP_NOMCP(bp)) {
4612 int mb_idx = BP_FW_MB_IDX(bp);
4616 ++bp->fw_drv_pulse_wr_seq;
4617 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4618 /* TBD - add SYSTEM_TIME */
4619 drv_pulse = bp->fw_drv_pulse_wr_seq;
4620 bnx2x_drv_pulse(bp);
4622 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4623 MCP_PULSE_SEQ_MASK);
4624 /* The delta between driver pulse and mcp response
4625 * should be 1 (before mcp response) or 0 (after mcp response)
4627 if ((drv_pulse != mcp_pulse) &&
4628 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4629 /* someone lost a heartbeat... */
4630 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4631 drv_pulse, mcp_pulse);
4635 if (bp->state == BNX2X_STATE_OPEN)
4636 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4638 mod_timer(&bp->timer, jiffies + bp->current_interval);
4641 /* end of Statistics */
4646 * nic init service functions
4649 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4652 if (!(len%4) && !(addr%4))
4653 for (i = 0; i < len; i += 4)
4654 REG_WR(bp, addr + i, fill);
4656 for (i = 0; i < len; i++)
4657 REG_WR8(bp, addr + i, fill);
4661 /* helper: writes FP SP data to FW - data_size in dwords */
4662 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4668 for (index = 0; index < data_size; index++)
4669 REG_WR(bp, BAR_CSTRORM_INTMEM +
4670 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4672 *(sb_data_p + index));
4675 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4679 struct hc_status_block_data_e2 sb_data_e2;
4680 struct hc_status_block_data_e1x sb_data_e1x;
4682 /* disable the function first */
4683 if (!CHIP_IS_E1x(bp)) {
4684 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4685 sb_data_e2.common.state = SB_DISABLED;
4686 sb_data_e2.common.p_func.vf_valid = false;
4687 sb_data_p = (u32 *)&sb_data_e2;
4688 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4690 memset(&sb_data_e1x, 0,
4691 sizeof(struct hc_status_block_data_e1x));
4692 sb_data_e1x.common.state = SB_DISABLED;
4693 sb_data_e1x.common.p_func.vf_valid = false;
4694 sb_data_p = (u32 *)&sb_data_e1x;
4695 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4697 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4699 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4700 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4701 CSTORM_STATUS_BLOCK_SIZE);
4702 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4703 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4704 CSTORM_SYNC_BLOCK_SIZE);
4707 /* helper: writes SP SB data to FW */
4708 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4709 struct hc_sp_status_block_data *sp_sb_data)
4711 int func = BP_FUNC(bp);
4713 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4714 REG_WR(bp, BAR_CSTRORM_INTMEM +
4715 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4717 *((u32 *)sp_sb_data + i));
4720 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4722 int func = BP_FUNC(bp);
4723 struct hc_sp_status_block_data sp_sb_data;
4724 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4726 sp_sb_data.state = SB_DISABLED;
4727 sp_sb_data.p_func.vf_valid = false;
4729 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4731 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4732 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4733 CSTORM_SP_STATUS_BLOCK_SIZE);
4734 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4735 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4736 CSTORM_SP_SYNC_BLOCK_SIZE);
4742 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4743 int igu_sb_id, int igu_seg_id)
4745 hc_sm->igu_sb_id = igu_sb_id;
4746 hc_sm->igu_seg_id = igu_seg_id;
4747 hc_sm->timer_value = 0xFF;
4748 hc_sm->time_to_expire = 0xFFFFFFFF;
4751 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4752 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4756 struct hc_status_block_data_e2 sb_data_e2;
4757 struct hc_status_block_data_e1x sb_data_e1x;
4758 struct hc_status_block_sm *hc_sm_p;
4762 if (CHIP_INT_MODE_IS_BC(bp))
4763 igu_seg_id = HC_SEG_ACCESS_NORM;
4765 igu_seg_id = IGU_SEG_ACCESS_NORM;
4767 bnx2x_zero_fp_sb(bp, fw_sb_id);
4769 if (!CHIP_IS_E1x(bp)) {
4770 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4771 sb_data_e2.common.state = SB_ENABLED;
4772 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4773 sb_data_e2.common.p_func.vf_id = vfid;
4774 sb_data_e2.common.p_func.vf_valid = vf_valid;
4775 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4776 sb_data_e2.common.same_igu_sb_1b = true;
4777 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4778 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4779 hc_sm_p = sb_data_e2.common.state_machine;
4780 sb_data_p = (u32 *)&sb_data_e2;
4781 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4783 memset(&sb_data_e1x, 0,
4784 sizeof(struct hc_status_block_data_e1x));
4785 sb_data_e1x.common.state = SB_ENABLED;
4786 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4787 sb_data_e1x.common.p_func.vf_id = 0xff;
4788 sb_data_e1x.common.p_func.vf_valid = false;
4789 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4790 sb_data_e1x.common.same_igu_sb_1b = true;
4791 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4792 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4793 hc_sm_p = sb_data_e1x.common.state_machine;
4794 sb_data_p = (u32 *)&sb_data_e1x;
4795 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4798 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4799 igu_sb_id, igu_seg_id);
4800 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4801 igu_sb_id, igu_seg_id);
4803 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4805 /* write indecies to HW */
4806 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4809 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4810 u16 tx_usec, u16 rx_usec)
4812 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4814 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4815 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4817 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4818 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4820 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4821 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4825 static void bnx2x_init_def_sb(struct bnx2x *bp)
4827 struct host_sp_status_block *def_sb = bp->def_status_blk;
4828 dma_addr_t mapping = bp->def_status_blk_mapping;
4829 int igu_sp_sb_index;
4831 int port = BP_PORT(bp);
4832 int func = BP_FUNC(bp);
4836 struct hc_sp_status_block_data sp_sb_data;
4837 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4839 if (CHIP_INT_MODE_IS_BC(bp)) {
4840 igu_sp_sb_index = DEF_SB_IGU_ID;
4841 igu_seg_id = HC_SEG_ACCESS_DEF;
4843 igu_sp_sb_index = bp->igu_dsb_id;
4844 igu_seg_id = IGU_SEG_ACCESS_DEF;
4848 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4849 atten_status_block);
4850 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4854 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4855 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4856 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4858 /* take care of sig[0]..sig[4] */
4859 for (sindex = 0; sindex < 4; sindex++)
4860 bp->attn_group[index].sig[sindex] =
4861 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4863 if (!CHIP_IS_E1x(bp))
4865 * enable5 is separate from the rest of the registers,
4866 * and therefore the address skip is 4
4867 * and not 16 between the different groups
4869 bp->attn_group[index].sig[4] = REG_RD(bp,
4870 reg_offset + 0x10 + 0x4*index);
4872 bp->attn_group[index].sig[4] = 0;
4875 if (bp->common.int_block == INT_BLOCK_HC) {
4876 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4877 HC_REG_ATTN_MSG0_ADDR_L);
4879 REG_WR(bp, reg_offset, U64_LO(section));
4880 REG_WR(bp, reg_offset + 4, U64_HI(section));
4881 } else if (!CHIP_IS_E1x(bp)) {
4882 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4883 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4886 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4889 bnx2x_zero_sp_sb(bp);
4891 sp_sb_data.state = SB_ENABLED;
4892 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4893 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4894 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4895 sp_sb_data.igu_seg_id = igu_seg_id;
4896 sp_sb_data.p_func.pf_id = func;
4897 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4898 sp_sb_data.p_func.vf_id = 0xff;
4900 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4902 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4905 void bnx2x_update_coalesce(struct bnx2x *bp)
4909 for_each_eth_queue(bp, i)
4910 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4911 bp->tx_ticks, bp->rx_ticks);
4914 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4916 spin_lock_init(&bp->spq_lock);
4917 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4919 bp->spq_prod_idx = 0;
4920 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4921 bp->spq_prod_bd = bp->spq;
4922 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4925 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4928 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4929 union event_ring_elem *elem =
4930 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4932 elem->next_page.addr.hi =
4933 cpu_to_le32(U64_HI(bp->eq_mapping +
4934 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4935 elem->next_page.addr.lo =
4936 cpu_to_le32(U64_LO(bp->eq_mapping +
4937 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4940 bp->eq_prod = NUM_EQ_DESC;
4941 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4942 /* we want a warning message before it gets rought... */
4943 atomic_set(&bp->eq_spq_left,
4944 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
4948 /* called with netif_addr_lock_bh() */
4949 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
4950 unsigned long rx_mode_flags,
4951 unsigned long rx_accept_flags,
4952 unsigned long tx_accept_flags,
4953 unsigned long ramrod_flags)
4955 struct bnx2x_rx_mode_ramrod_params ramrod_param;
4958 memset(&ramrod_param, 0, sizeof(ramrod_param));
4960 /* Prepare ramrod parameters */
4961 ramrod_param.cid = 0;
4962 ramrod_param.cl_id = cl_id;
4963 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
4964 ramrod_param.func_id = BP_FUNC(bp);
4966 ramrod_param.pstate = &bp->sp_state;
4967 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
4969 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
4970 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
4972 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4974 ramrod_param.ramrod_flags = ramrod_flags;
4975 ramrod_param.rx_mode_flags = rx_mode_flags;
4977 ramrod_param.rx_accept_flags = rx_accept_flags;
4978 ramrod_param.tx_accept_flags = tx_accept_flags;
4980 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
4982 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
4987 /* called with netif_addr_lock_bh() */
4988 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4990 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
4991 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
4996 /* Configure rx_mode of FCoE Queue */
4997 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5000 switch (bp->rx_mode) {
5001 case BNX2X_RX_MODE_NONE:
5003 * 'drop all' supersedes any accept flags that may have been
5004 * passed to the function.
5007 case BNX2X_RX_MODE_NORMAL:
5008 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5009 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5010 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5012 /* internal switching mode */
5013 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5014 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5015 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5018 case BNX2X_RX_MODE_ALLMULTI:
5019 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5020 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5021 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5023 /* internal switching mode */
5024 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5025 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5026 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5029 case BNX2X_RX_MODE_PROMISC:
5030 /* According to deffinition of SI mode, iface in promisc mode
5031 * should receive matched and unmatched (in resolution of port)
5034 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5035 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5036 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5037 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5039 /* internal switching mode */
5040 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5041 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5044 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5046 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5050 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5054 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5055 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5056 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5059 __set_bit(RAMROD_RX, &ramrod_flags);
5060 __set_bit(RAMROD_TX, &ramrod_flags);
5062 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5063 tx_accept_flags, ramrod_flags);
5066 static void bnx2x_init_internal_common(struct bnx2x *bp)
5072 * In switch independent mode, the TSTORM needs to accept
5073 * packets that failed classification, since approximate match
5074 * mac addresses aren't written to NIG LLH
5076 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5077 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5078 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5079 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5080 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5082 /* Zero this manually as its initialization is
5083 currently missing in the initTool */
5084 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5085 REG_WR(bp, BAR_USTRORM_INTMEM +
5086 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5087 if (!CHIP_IS_E1x(bp)) {
5088 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5089 CHIP_INT_MODE_IS_BC(bp) ?
5090 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5094 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5096 switch (load_code) {
5097 case FW_MSG_CODE_DRV_LOAD_COMMON:
5098 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5099 bnx2x_init_internal_common(bp);
5102 case FW_MSG_CODE_DRV_LOAD_PORT:
5106 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5107 /* internal memory per function is
5108 initialized inside bnx2x_pf_init */
5112 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5117 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5119 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5122 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5124 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5127 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5129 if (CHIP_IS_E1x(fp->bp))
5130 return BP_L_ID(fp->bp) + fp->index;
5131 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5132 return bnx2x_fp_igu_sb_id(fp);
5135 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5137 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5139 unsigned long q_type = 0;
5140 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5143 fp->cl_id = bnx2x_fp_cl_id(fp);
5144 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5145 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5146 /* qZone id equals to FW (per path) client id */
5147 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5150 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5151 /* Setup SB indicies */
5152 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5154 /* Configure Queue State object */
5155 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5156 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5158 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5161 for_each_cos_in_tx_queue(fp, cos) {
5162 bnx2x_init_txdata(bp, &fp->txdata[cos],
5163 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5164 FP_COS_TO_TXQ(fp, cos),
5165 BNX2X_TX_SB_INDEX_BASE + cos);
5166 cids[cos] = fp->txdata[cos].cid;
5169 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5170 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5171 bnx2x_sp_mapping(bp, q_rdata), q_type);
5174 * Configure classification DBs: Always enable Tx switching
5176 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5178 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5179 "cl_id %d fw_sb %d igu_sb %d\n",
5180 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5182 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5183 fp->fw_sb_id, fp->igu_sb_id);
5185 bnx2x_update_fpsb_idx(fp);
5188 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5192 for_each_eth_queue(bp, i)
5193 bnx2x_init_eth_fp(bp, i);
5196 bnx2x_init_fcoe_fp(bp);
5198 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5199 BNX2X_VF_ID_INVALID, false,
5200 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5204 /* Initialize MOD_ABS interrupts */
5205 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5206 bp->common.shmem_base, bp->common.shmem2_base,
5208 /* ensure status block indices were read */
5211 bnx2x_init_def_sb(bp);
5212 bnx2x_update_dsb_idx(bp);
5213 bnx2x_init_rx_rings(bp);
5214 bnx2x_init_tx_rings(bp);
5215 bnx2x_init_sp_ring(bp);
5216 bnx2x_init_eq_ring(bp);
5217 bnx2x_init_internal(bp, load_code);
5219 bnx2x_stats_init(bp);
5221 /* flush all before enabling interrupts */
5225 bnx2x_int_enable(bp);
5227 /* Check for SPIO5 */
5228 bnx2x_attn_int_deasserted0(bp,
5229 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5230 AEU_INPUTS_ATTN_BITS_SPIO5);
5233 /* end of nic init */
5236 * gzip service functions
5239 static int bnx2x_gunzip_init(struct bnx2x *bp)
5241 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5242 &bp->gunzip_mapping, GFP_KERNEL);
5243 if (bp->gunzip_buf == NULL)
5246 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5247 if (bp->strm == NULL)
5250 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5251 if (bp->strm->workspace == NULL)
5261 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5262 bp->gunzip_mapping);
5263 bp->gunzip_buf = NULL;
5266 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5267 " un-compression\n");
5271 static void bnx2x_gunzip_end(struct bnx2x *bp)
5274 vfree(bp->strm->workspace);
5279 if (bp->gunzip_buf) {
5280 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5281 bp->gunzip_mapping);
5282 bp->gunzip_buf = NULL;
5286 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5290 /* check gzip header */
5291 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5292 BNX2X_ERR("Bad gzip header\n");
5300 if (zbuf[3] & FNAME)
5301 while ((zbuf[n++] != 0) && (n < len));
5303 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5304 bp->strm->avail_in = len - n;
5305 bp->strm->next_out = bp->gunzip_buf;
5306 bp->strm->avail_out = FW_BUF_SIZE;
5308 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5312 rc = zlib_inflate(bp->strm, Z_FINISH);
5313 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5314 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5317 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5318 if (bp->gunzip_outlen & 0x3)
5319 netdev_err(bp->dev, "Firmware decompression error:"
5320 " gunzip_outlen (%d) not aligned\n",
5322 bp->gunzip_outlen >>= 2;
5324 zlib_inflateEnd(bp->strm);
5326 if (rc == Z_STREAM_END)
5332 /* nic load/unload */
5335 * General service functions
5338 /* send a NIG loopback debug packet */
5339 static void bnx2x_lb_pckt(struct bnx2x *bp)
5343 /* Ethernet source and destination addresses */
5344 wb_write[0] = 0x55555555;
5345 wb_write[1] = 0x55555555;
5346 wb_write[2] = 0x20; /* SOP */
5347 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5349 /* NON-IP protocol */
5350 wb_write[0] = 0x09000000;
5351 wb_write[1] = 0x55555555;
5352 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5353 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5356 /* some of the internal memories
5357 * are not directly readable from the driver
5358 * to test them we send debug packets
5360 static int bnx2x_int_mem_test(struct bnx2x *bp)
5366 if (CHIP_REV_IS_FPGA(bp))
5368 else if (CHIP_REV_IS_EMUL(bp))
5373 /* Disable inputs of parser neighbor blocks */
5374 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5375 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5376 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5377 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5379 /* Write 0 to parser credits for CFC search request */
5380 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5382 /* send Ethernet packet */
5385 /* TODO do i reset NIG statistic? */
5386 /* Wait until NIG register shows 1 packet of size 0x10 */
5387 count = 1000 * factor;
5390 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5391 val = *bnx2x_sp(bp, wb_data[0]);
5399 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5403 /* Wait until PRS register shows 1 packet */
5404 count = 1000 * factor;
5406 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5414 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5418 /* Reset and init BRB, PRS */
5419 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5421 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5423 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5424 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5426 DP(NETIF_MSG_HW, "part2\n");
5428 /* Disable inputs of parser neighbor blocks */
5429 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5430 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5431 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5432 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5434 /* Write 0 to parser credits for CFC search request */
5435 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5437 /* send 10 Ethernet packets */
5438 for (i = 0; i < 10; i++)
5441 /* Wait until NIG register shows 10 + 1
5442 packets of size 11*0x10 = 0xb0 */
5443 count = 1000 * factor;
5446 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5447 val = *bnx2x_sp(bp, wb_data[0]);
5455 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5459 /* Wait until PRS register shows 2 packets */
5460 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5462 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5464 /* Write 1 to parser credits for CFC search request */
5465 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5467 /* Wait until PRS register shows 3 packets */
5468 msleep(10 * factor);
5469 /* Wait until NIG register shows 1 packet of size 0x10 */
5470 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5472 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5474 /* clear NIG EOP FIFO */
5475 for (i = 0; i < 11; i++)
5476 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5477 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5479 BNX2X_ERR("clear of NIG failed\n");
5483 /* Reset and init BRB, PRS, NIG */
5484 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5486 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5488 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5489 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5492 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5495 /* Enable inputs of parser neighbor blocks */
5496 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5497 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5498 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5499 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5501 DP(NETIF_MSG_HW, "done\n");
5506 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5508 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5509 if (!CHIP_IS_E1x(bp))
5510 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5512 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5513 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5514 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5516 * mask read length error interrupts in brb for parser
5517 * (parsing unit and 'checksum and crc' unit)
5518 * these errors are legal (PU reads fixed length and CAC can cause
5519 * read length error on truncated packets)
5521 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5522 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5523 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5524 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5525 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5526 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5527 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5528 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5529 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5530 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5531 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5532 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5533 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5534 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5535 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5536 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5537 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5538 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5539 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5541 if (CHIP_REV_IS_FPGA(bp))
5542 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5543 else if (!CHIP_IS_E1x(bp))
5544 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5545 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5546 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5547 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5548 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5549 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5551 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5552 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5553 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5554 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5555 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5557 if (!CHIP_IS_E1x(bp))
5558 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5559 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5561 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5562 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5563 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5564 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5567 static void bnx2x_reset_common(struct bnx2x *bp)
5572 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5575 if (CHIP_IS_E3(bp)) {
5576 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5577 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5580 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5583 static void bnx2x_setup_dmae(struct bnx2x *bp)
5586 spin_lock_init(&bp->dmae_lock);
5589 static void bnx2x_init_pxp(struct bnx2x *bp)
5592 int r_order, w_order;
5594 pci_read_config_word(bp->pdev,
5595 bp->pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl);
5596 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5597 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5599 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5601 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5605 bnx2x_init_pxp_arb(bp, r_order, w_order);
5608 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5618 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5619 SHARED_HW_CFG_FAN_FAILURE_MASK;
5621 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5625 * The fan failure mechanism is usually related to the PHY type since
5626 * the power consumption of the board is affected by the PHY. Currently,
5627 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5629 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5630 for (port = PORT_0; port < PORT_MAX; port++) {
5632 bnx2x_fan_failure_det_req(
5634 bp->common.shmem_base,
5635 bp->common.shmem2_base,
5639 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5641 if (is_required == 0)
5644 /* Fan failure is indicated by SPIO 5 */
5645 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5646 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5648 /* set to active low mode */
5649 val = REG_RD(bp, MISC_REG_SPIO_INT);
5650 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5651 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5652 REG_WR(bp, MISC_REG_SPIO_INT, val);
5654 /* enable interrupt to signal the IGU */
5655 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5656 val |= (1 << MISC_REGISTERS_SPIO_5);
5657 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5660 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5666 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5669 switch (BP_ABS_FUNC(bp)) {
5671 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5674 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5677 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5680 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5683 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5686 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5689 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5692 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5698 REG_WR(bp, offset, pretend_func_num);
5700 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5703 void bnx2x_pf_disable(struct bnx2x *bp)
5705 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5706 val &= ~IGU_PF_CONF_FUNC_EN;
5708 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5709 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5710 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5713 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5715 u32 shmem_base[2], shmem2_base[2];
5716 shmem_base[0] = bp->common.shmem_base;
5717 shmem2_base[0] = bp->common.shmem2_base;
5718 if (!CHIP_IS_E1x(bp)) {
5720 SHMEM2_RD(bp, other_shmem_base_addr);
5722 SHMEM2_RD(bp, other_shmem2_base_addr);
5724 bnx2x_acquire_phy_lock(bp);
5725 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5726 bp->common.chip_id);
5727 bnx2x_release_phy_lock(bp);
5731 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5733 * @bp: driver handle
5735 static int bnx2x_init_hw_common(struct bnx2x *bp)
5739 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5741 bnx2x_reset_common(bp);
5742 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5745 if (CHIP_IS_E3(bp)) {
5746 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5747 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5749 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5751 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5753 if (!CHIP_IS_E1x(bp)) {
5757 * 4-port mode or 2-port mode we need to turn of master-enable
5758 * for everyone, after that, turn it back on for self.
5759 * so, we disregard multi-function or not, and always disable
5760 * for all functions on the given path, this means 0,2,4,6 for
5761 * path 0 and 1,3,5,7 for path 1
5763 for (abs_func_id = BP_PATH(bp);
5764 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5765 if (abs_func_id == BP_ABS_FUNC(bp)) {
5767 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5772 bnx2x_pretend_func(bp, abs_func_id);
5773 /* clear pf enable */
5774 bnx2x_pf_disable(bp);
5775 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5779 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5780 if (CHIP_IS_E1(bp)) {
5781 /* enable HW interrupt from PXP on USDM overflow
5782 bit 16 on INT_MASK_0 */
5783 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5786 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5790 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5791 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5792 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5793 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5794 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5795 /* make sure this value is 0 */
5796 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5798 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5799 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5800 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5801 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5802 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5805 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5807 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5808 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5810 /* let the HW do it's magic ... */
5812 /* finish PXP init */
5813 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5815 BNX2X_ERR("PXP2 CFG failed\n");
5818 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5820 BNX2X_ERR("PXP2 RD_INIT failed\n");
5824 /* Timers bug workaround E2 only. We need to set the entire ILT to
5825 * have entries with value "0" and valid bit on.
5826 * This needs to be done by the first PF that is loaded in a path
5827 * (i.e. common phase)
5829 if (!CHIP_IS_E1x(bp)) {
5830 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5831 * (i.e. vnic3) to start even if it is marked as "scan-off".
5832 * This occurs when a different function (func2,3) is being marked
5833 * as "scan-off". Real-life scenario for example: if a driver is being
5834 * load-unloaded while func6,7 are down. This will cause the timer to access
5835 * the ilt, translate to a logical address and send a request to read/write.
5836 * Since the ilt for the function that is down is not valid, this will cause
5837 * a translation error which is unrecoverable.
5838 * The Workaround is intended to make sure that when this happens nothing fatal
5839 * will occur. The workaround:
5840 * 1. First PF driver which loads on a path will:
5841 * a. After taking the chip out of reset, by using pretend,
5842 * it will write "0" to the following registers of
5844 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5845 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5846 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5847 * And for itself it will write '1' to
5848 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5849 * dmae-operations (writing to pram for example.)
5850 * note: can be done for only function 6,7 but cleaner this
5852 * b. Write zero+valid to the entire ILT.
5853 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5854 * VNIC3 (of that port). The range allocated will be the
5855 * entire ILT. This is needed to prevent ILT range error.
5856 * 2. Any PF driver load flow:
5857 * a. ILT update with the physical addresses of the allocated
5859 * b. Wait 20msec. - note that this timeout is needed to make
5860 * sure there are no requests in one of the PXP internal
5861 * queues with "old" ILT addresses.
5862 * c. PF enable in the PGLC.
5863 * d. Clear the was_error of the PF in the PGLC. (could have
5864 * occured while driver was down)
5865 * e. PF enable in the CFC (WEAK + STRONG)
5866 * f. Timers scan enable
5867 * 3. PF driver unload flow:
5868 * a. Clear the Timers scan_en.
5869 * b. Polling for scan_on=0 for that PF.
5870 * c. Clear the PF enable bit in the PXP.
5871 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5872 * e. Write zero+valid to all ILT entries (The valid bit must
5874 * f. If this is VNIC 3 of a port then also init
5875 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5876 * to the last enrty in the ILT.
5879 * Currently the PF error in the PGLC is non recoverable.
5880 * In the future the there will be a recovery routine for this error.
5881 * Currently attention is masked.
5882 * Having an MCP lock on the load/unload process does not guarantee that
5883 * there is no Timer disable during Func6/7 enable. This is because the
5884 * Timers scan is currently being cleared by the MCP on FLR.
5885 * Step 2.d can be done only for PF6/7 and the driver can also check if
5886 * there is error before clearing it. But the flow above is simpler and
5888 * All ILT entries are written by zero+valid and not just PF6/7
5889 * ILT entries since in the future the ILT entries allocation for
5890 * PF-s might be dynamic.
5892 struct ilt_client_info ilt_cli;
5893 struct bnx2x_ilt ilt;
5894 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5895 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5897 /* initialize dummy TM client */
5899 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5900 ilt_cli.client_num = ILT_CLIENT_TM;
5902 /* Step 1: set zeroes to all ilt page entries with valid bit on
5903 * Step 2: set the timers first/last ilt entry to point
5904 * to the entire range to prevent ILT range error for 3rd/4th
5905 * vnic (this code assumes existance of the vnic)
5907 * both steps performed by call to bnx2x_ilt_client_init_op()
5908 * with dummy TM client
5910 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5911 * and his brother are split registers
5913 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5914 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5915 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5917 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5918 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5919 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5923 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5924 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5926 if (!CHIP_IS_E1x(bp)) {
5927 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5928 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5929 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
5931 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
5933 /* let the HW do it's magic ... */
5936 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5937 } while (factor-- && (val != 1));
5940 BNX2X_ERR("ATC_INIT failed\n");
5945 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
5947 /* clean the DMAE memory */
5949 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
5951 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
5953 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
5955 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
5957 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
5959 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5960 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5961 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5962 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5964 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
5967 /* QM queues pointers table */
5968 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5970 /* soft reset pulse */
5971 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5972 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5975 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
5978 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
5979 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5980 if (!CHIP_REV_IS_SLOW(bp))
5981 /* enable hw interrupt from doorbell Q */
5982 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5984 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5986 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5987 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5989 if (!CHIP_IS_E1(bp))
5990 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
5992 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
5993 /* Bit-map indicating which L2 hdrs may appear
5994 * after the basic Ethernet header
5996 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
5997 bp->path_has_ovlan ? 7 : 6);
5999 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6000 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6001 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6002 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6004 if (!CHIP_IS_E1x(bp)) {
6005 /* reset VFC memories */
6006 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6007 VFC_MEMORIES_RST_REG_CAM_RST |
6008 VFC_MEMORIES_RST_REG_RAM_RST);
6009 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6010 VFC_MEMORIES_RST_REG_CAM_RST |
6011 VFC_MEMORIES_RST_REG_RAM_RST);
6016 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6017 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6018 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6019 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6022 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6024 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6027 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6028 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6029 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6031 if (!CHIP_IS_E1x(bp))
6032 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6033 bp->path_has_ovlan ? 7 : 6);
6035 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6037 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6040 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6041 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6042 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6043 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6044 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6045 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6046 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6047 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6048 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6049 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6051 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6053 if (sizeof(union cdu_context) != 1024)
6054 /* we currently assume that a context is 1024 bytes */
6055 dev_alert(&bp->pdev->dev, "please adjust the size "
6056 "of cdu_context(%ld)\n",
6057 (long)sizeof(union cdu_context));
6059 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6060 val = (4 << 24) + (0 << 12) + 1024;
6061 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6063 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6064 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6065 /* enable context validation interrupt from CFC */
6066 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6068 /* set the thresholds to prevent CFC/CDU race */
6069 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6071 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6073 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6074 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6076 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6077 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6079 /* Reset PCIE errors for debug */
6080 REG_WR(bp, 0x2814, 0xffffffff);
6081 REG_WR(bp, 0x3820, 0xffffffff);
6083 if (!CHIP_IS_E1x(bp)) {
6084 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6085 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6086 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6087 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6088 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6089 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6090 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6091 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6092 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6093 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6094 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6097 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6098 if (!CHIP_IS_E1(bp)) {
6099 /* in E3 this done in per-port section */
6100 if (!CHIP_IS_E3(bp))
6101 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6103 if (CHIP_IS_E1H(bp))
6104 /* not applicable for E2 (and above ...) */
6105 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6107 if (CHIP_REV_IS_SLOW(bp))
6110 /* finish CFC init */
6111 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6113 BNX2X_ERR("CFC LL_INIT failed\n");
6116 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6118 BNX2X_ERR("CFC AC_INIT failed\n");
6121 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6123 BNX2X_ERR("CFC CAM_INIT failed\n");
6126 REG_WR(bp, CFC_REG_DEBUG0, 0);
6128 if (CHIP_IS_E1(bp)) {
6129 /* read NIG statistic
6130 to see if this is our first up since powerup */
6131 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6132 val = *bnx2x_sp(bp, wb_data[0]);
6134 /* do internal memory self test */
6135 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6136 BNX2X_ERR("internal mem self test failed\n");
6141 bnx2x_setup_fan_failure_detection(bp);
6143 /* clear PXP2 attentions */
6144 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6146 bnx2x_enable_blocks_attention(bp);
6147 bnx2x_enable_blocks_parity(bp);
6149 if (!BP_NOMCP(bp)) {
6150 if (CHIP_IS_E1x(bp))
6151 bnx2x__common_init_phy(bp);
6153 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6159 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6161 * @bp: driver handle
6163 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6165 int rc = bnx2x_init_hw_common(bp);
6170 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6172 bnx2x__common_init_phy(bp);
6177 static int bnx2x_init_hw_port(struct bnx2x *bp)
6179 int port = BP_PORT(bp);
6180 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6184 bnx2x__link_reset(bp);
6186 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6188 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6190 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6191 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6192 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6194 /* Timers bug workaround: disables the pf_master bit in pglue at
6195 * common phase, we need to enable it here before any dmae access are
6196 * attempted. Therefore we manually added the enable-master to the
6197 * port phase (it also happens in the function phase)
6199 if (!CHIP_IS_E1x(bp))
6200 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6202 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6203 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6204 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6205 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6207 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6208 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6209 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6210 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6212 /* QM cid (connection) count */
6213 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6216 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6217 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6218 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6221 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6223 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6224 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6227 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6228 else if (bp->dev->mtu > 4096) {
6229 if (bp->flags & ONE_PORT_FLAG)
6233 /* (24*1024 + val*4)/256 */
6234 low = 96 + (val/64) +
6235 ((val % 64) ? 1 : 0);
6238 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6239 high = low + 56; /* 14*1024/256 */
6240 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6241 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6244 if (CHIP_MODE_IS_4_PORT(bp))
6245 REG_WR(bp, (BP_PORT(bp) ?
6246 BRB1_REG_MAC_GUARANTIED_1 :
6247 BRB1_REG_MAC_GUARANTIED_0), 40);
6250 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6251 if (CHIP_IS_E3B0(bp))
6252 /* Ovlan exists only if we are in multi-function +
6253 * switch-dependent mode, in switch-independent there
6254 * is no ovlan headers
6256 REG_WR(bp, BP_PORT(bp) ?
6257 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6258 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6259 (bp->path_has_ovlan ? 7 : 6));
6261 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6262 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6263 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6264 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6266 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6267 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6268 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6269 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6271 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6272 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6274 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6276 if (CHIP_IS_E1x(bp)) {
6277 /* configure PBF to work without PAUSE mtu 9000 */
6278 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6280 /* update threshold */
6281 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6282 /* update init credit */
6283 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6286 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6288 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6292 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6294 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6295 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6297 if (CHIP_IS_E1(bp)) {
6298 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6299 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6301 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6303 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6305 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6306 /* init aeu_mask_attn_func_0/1:
6307 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6308 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6309 * bits 4-7 are used for "per vn group attention" */
6310 val = IS_MF(bp) ? 0xF7 : 0x7;
6311 /* Enable DCBX attention for all but E1 */
6312 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6313 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6315 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6317 if (!CHIP_IS_E1x(bp)) {
6318 /* Bit-map indicating which L2 hdrs may appear after the
6319 * basic Ethernet header
6321 REG_WR(bp, BP_PORT(bp) ?
6322 NIG_REG_P1_HDRS_AFTER_BASIC :
6323 NIG_REG_P0_HDRS_AFTER_BASIC,
6324 IS_MF_SD(bp) ? 7 : 6);
6327 REG_WR(bp, BP_PORT(bp) ?
6328 NIG_REG_LLH1_MF_MODE :
6329 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6331 if (!CHIP_IS_E3(bp))
6332 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6334 if (!CHIP_IS_E1(bp)) {
6335 /* 0x2 disable mf_ov, 0x1 enable */
6336 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6337 (IS_MF_SD(bp) ? 0x1 : 0x2));
6339 if (!CHIP_IS_E1x(bp)) {
6341 switch (bp->mf_mode) {
6342 case MULTI_FUNCTION_SD:
6345 case MULTI_FUNCTION_SI:
6350 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6351 NIG_REG_LLH0_CLS_TYPE), val);
6354 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6355 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6356 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6361 /* If SPIO5 is set to generate interrupts, enable it for this port */
6362 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6363 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6364 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6365 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6366 val = REG_RD(bp, reg_addr);
6367 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6368 REG_WR(bp, reg_addr, val);
6374 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6379 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6381 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6383 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6386 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6388 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6391 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6393 u32 i, base = FUNC_ILT_BASE(func);
6394 for (i = base; i < base + ILT_PER_FUNC; i++)
6395 bnx2x_ilt_wr(bp, i, 0);
6398 static int bnx2x_init_hw_func(struct bnx2x *bp)
6400 int port = BP_PORT(bp);
6401 int func = BP_FUNC(bp);
6402 int init_phase = PHASE_PF0 + func;
6403 struct bnx2x_ilt *ilt = BP_ILT(bp);
6406 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6407 int i, main_mem_width;
6409 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6411 /* FLR cleanup - hmmm */
6412 if (!CHIP_IS_E1x(bp))
6413 bnx2x_pf_flr_clnup(bp);
6415 /* set MSI reconfigure capability */
6416 if (bp->common.int_block == INT_BLOCK_HC) {
6417 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6418 val = REG_RD(bp, addr);
6419 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6420 REG_WR(bp, addr, val);
6423 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6424 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6427 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6429 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6430 ilt->lines[cdu_ilt_start + i].page =
6431 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6432 ilt->lines[cdu_ilt_start + i].page_mapping =
6433 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6434 /* cdu ilt pages are allocated manually so there's no need to
6437 bnx2x_ilt_init_op(bp, INITOP_SET);
6440 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6442 /* T1 hash bits value determines the T1 number of entries */
6443 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6448 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6449 #endif /* BCM_CNIC */
6451 if (!CHIP_IS_E1x(bp)) {
6452 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6454 /* Turn on a single ISR mode in IGU if driver is going to use
6457 if (!(bp->flags & USING_MSIX_FLAG))
6458 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6460 * Timers workaround bug: function init part.
6461 * Need to wait 20msec after initializing ILT,
6462 * needed to make sure there are no requests in
6463 * one of the PXP internal queues with "old" ILT addresses
6467 * Master enable - Due to WB DMAE writes performed before this
6468 * register is re-initialized as part of the regular function
6471 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6472 /* Enable the function in IGU */
6473 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6478 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6480 if (!CHIP_IS_E1x(bp))
6481 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6483 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6484 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6485 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6486 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6487 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6488 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6489 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6490 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6491 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6492 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6493 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6494 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6495 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6497 if (!CHIP_IS_E1x(bp))
6498 REG_WR(bp, QM_REG_PF_EN, 1);
6500 if (!CHIP_IS_E1x(bp)) {
6501 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6502 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6503 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6504 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6506 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6508 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6509 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6510 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6511 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6512 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6513 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6514 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6515 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6516 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6517 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6518 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6519 if (!CHIP_IS_E1x(bp))
6520 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6522 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6524 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6526 if (!CHIP_IS_E1x(bp))
6527 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6530 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6531 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6534 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6536 /* HC init per function */
6537 if (bp->common.int_block == INT_BLOCK_HC) {
6538 if (CHIP_IS_E1H(bp)) {
6539 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6541 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6542 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6544 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6547 int num_segs, sb_idx, prod_offset;
6549 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6551 if (!CHIP_IS_E1x(bp)) {
6552 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6553 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6556 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6558 if (!CHIP_IS_E1x(bp)) {
6562 * E2 mode: address 0-135 match to the mapping memory;
6563 * 136 - PF0 default prod; 137 - PF1 default prod;
6564 * 138 - PF2 default prod; 139 - PF3 default prod;
6565 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6566 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6569 * E1.5 mode - In backward compatible mode;
6570 * for non default SB; each even line in the memory
6571 * holds the U producer and each odd line hold
6572 * the C producer. The first 128 producers are for
6573 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6574 * producers are for the DSB for each PF.
6575 * Each PF has five segments: (the order inside each
6576 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6577 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6578 * 144-147 attn prods;
6580 /* non-default-status-blocks */
6581 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6582 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6583 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6584 prod_offset = (bp->igu_base_sb + sb_idx) *
6587 for (i = 0; i < num_segs; i++) {
6588 addr = IGU_REG_PROD_CONS_MEMORY +
6589 (prod_offset + i) * 4;
6590 REG_WR(bp, addr, 0);
6592 /* send consumer update with value 0 */
6593 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6594 USTORM_ID, 0, IGU_INT_NOP, 1);
6595 bnx2x_igu_clear_sb(bp,
6596 bp->igu_base_sb + sb_idx);
6599 /* default-status-blocks */
6600 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6601 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6603 if (CHIP_MODE_IS_4_PORT(bp))
6604 dsb_idx = BP_FUNC(bp);
6606 dsb_idx = BP_E1HVN(bp);
6608 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6609 IGU_BC_BASE_DSB_PROD + dsb_idx :
6610 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6612 for (i = 0; i < (num_segs * E1HVN_MAX);
6614 addr = IGU_REG_PROD_CONS_MEMORY +
6615 (prod_offset + i)*4;
6616 REG_WR(bp, addr, 0);
6618 /* send consumer update with 0 */
6619 if (CHIP_INT_MODE_IS_BC(bp)) {
6620 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6621 USTORM_ID, 0, IGU_INT_NOP, 1);
6622 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6623 CSTORM_ID, 0, IGU_INT_NOP, 1);
6624 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6625 XSTORM_ID, 0, IGU_INT_NOP, 1);
6626 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6627 TSTORM_ID, 0, IGU_INT_NOP, 1);
6628 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6629 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6631 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6632 USTORM_ID, 0, IGU_INT_NOP, 1);
6633 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6634 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6636 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6638 /* !!! these should become driver const once
6639 rf-tool supports split-68 const */
6640 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6641 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6642 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6643 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6644 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6645 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6649 /* Reset PCIE errors for debug */
6650 REG_WR(bp, 0x2114, 0xffffffff);
6651 REG_WR(bp, 0x2120, 0xffffffff);
6653 if (CHIP_IS_E1x(bp)) {
6654 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6655 main_mem_base = HC_REG_MAIN_MEMORY +
6656 BP_PORT(bp) * (main_mem_size * 4);
6657 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6660 val = REG_RD(bp, main_mem_prty_clr);
6662 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6664 "function init (0x%x)!\n", val);
6666 /* Clear "false" parity errors in MSI-X table */
6667 for (i = main_mem_base;
6668 i < main_mem_base + main_mem_size * 4;
6669 i += main_mem_width) {
6670 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6671 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6672 i, main_mem_width / 4);
6674 /* Clear HC parity attention */
6675 REG_RD(bp, main_mem_prty_clr);
6678 #ifdef BNX2X_STOP_ON_ERROR
6679 /* Enable STORMs SP logging */
6680 REG_WR8(bp, BAR_USTRORM_INTMEM +
6681 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6682 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6683 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6684 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6685 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6686 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6687 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6690 bnx2x_phy_probe(&bp->link_params);
6696 void bnx2x_free_mem(struct bnx2x *bp)
6699 bnx2x_free_fp_mem(bp);
6700 /* end of fastpath */
6702 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6703 sizeof(struct host_sp_status_block));
6705 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6706 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6708 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6709 sizeof(struct bnx2x_slowpath));
6711 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6714 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6716 BNX2X_FREE(bp->ilt->lines);
6719 if (!CHIP_IS_E1x(bp))
6720 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6721 sizeof(struct host_hc_status_block_e2));
6723 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6724 sizeof(struct host_hc_status_block_e1x));
6726 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6729 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6731 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6732 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6735 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6739 /* number of eth_queues */
6740 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6742 /* Total number of FW statistics requests =
6743 * 1 for port stats + 1 for PF stats + num_eth_queues */
6744 bp->fw_stats_num = 2 + num_queue_stats;
6747 /* Request is built from stats_query_header and an array of
6748 * stats_query_cmd_group each of which contains
6749 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6750 * configured in the stats_query_header.
6752 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6753 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6755 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6756 num_groups * sizeof(struct stats_query_cmd_group);
6758 /* Data for statistics requests + stats_conter
6760 * stats_counter holds per-STORM counters that are incremented
6761 * when STORM has finished with the current request.
6763 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6764 sizeof(struct per_pf_stats) +
6765 sizeof(struct per_queue_stats) * num_queue_stats +
6766 sizeof(struct stats_counter);
6768 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6769 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6772 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6773 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6775 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6776 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6778 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6779 bp->fw_stats_req_sz;
6783 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6784 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6789 int bnx2x_alloc_mem(struct bnx2x *bp)
6792 if (!CHIP_IS_E1x(bp))
6793 /* size = the status block + ramrod buffers */
6794 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6795 sizeof(struct host_hc_status_block_e2));
6797 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6798 sizeof(struct host_hc_status_block_e1x));
6800 /* allocate searcher T2 table */
6801 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6805 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6806 sizeof(struct host_sp_status_block));
6808 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6809 sizeof(struct bnx2x_slowpath));
6811 /* Allocated memory for FW statistics */
6812 if (bnx2x_alloc_fw_stats_mem(bp))
6815 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6817 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6820 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6822 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6825 /* Slow path ring */
6826 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6829 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6830 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6834 /* need to be done at the end, since it's self adjusting to amount
6835 * of memory available for RSS queues
6837 if (bnx2x_alloc_fp_mem(bp))
6847 * Init service functions
6850 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6851 struct bnx2x_vlan_mac_obj *obj, bool set,
6852 int mac_type, unsigned long *ramrod_flags)
6855 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6857 memset(&ramrod_param, 0, sizeof(ramrod_param));
6859 /* Fill general parameters */
6860 ramrod_param.vlan_mac_obj = obj;
6861 ramrod_param.ramrod_flags = *ramrod_flags;
6863 /* Fill a user request section if needed */
6864 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6865 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6867 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6869 /* Set the command: ADD or DEL */
6871 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6873 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6876 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6878 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6882 int bnx2x_del_all_macs(struct bnx2x *bp,
6883 struct bnx2x_vlan_mac_obj *mac_obj,
6884 int mac_type, bool wait_for_comp)
6887 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6889 /* Wait for completion of requested */
6891 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6893 /* Set the mac type of addresses we want to clear */
6894 __set_bit(mac_type, &vlan_mac_flags);
6896 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6898 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
6903 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
6905 unsigned long ramrod_flags = 0;
6907 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
6909 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6910 /* Eth MAC is set on RSS leading client (fp[0]) */
6911 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6912 BNX2X_ETH_MAC, &ramrod_flags);
6915 int bnx2x_setup_leading(struct bnx2x *bp)
6917 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
6921 * bnx2x_set_int_mode - configure interrupt mode
6923 * @bp: driver handle
6925 * In case of MSI-X it will also try to enable MSI-X.
6927 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6931 bnx2x_enable_msi(bp);
6932 /* falling through... */
6934 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
6935 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6938 /* Set number of queues according to bp->multi_mode value */
6939 bnx2x_set_num_queues(bp);
6941 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6944 /* if we can't use MSI-X we only need one fp,
6945 * so try to enable MSI-X with the requested number of fp's
6946 * and fallback to MSI or legacy INTx with one fp
6948 if (bnx2x_enable_msix(bp)) {
6949 /* failed to enable MSI-X */
6952 "Multi requested but failed to "
6953 "enable MSI-X (%d), "
6954 "set number of queues to %d\n",
6956 1 + NON_ETH_CONTEXT_USE);
6957 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
6959 /* Try to enable MSI */
6960 if (!(bp->flags & DISABLE_MSI_FLAG))
6961 bnx2x_enable_msi(bp);
6967 /* must be called prioir to any HW initializations */
6968 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6970 return L2_ILT_LINES(bp);
6973 void bnx2x_ilt_set_info(struct bnx2x *bp)
6975 struct ilt_client_info *ilt_client;
6976 struct bnx2x_ilt *ilt = BP_ILT(bp);
6979 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6980 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6983 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6984 ilt_client->client_num = ILT_CLIENT_CDU;
6985 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6986 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6987 ilt_client->start = line;
6988 line += bnx2x_cid_ilt_lines(bp);
6990 line += CNIC_ILT_LINES;
6992 ilt_client->end = line - 1;
6994 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6995 "flags 0x%x, hw psz %d\n",
6998 ilt_client->page_size,
7000 ilog2(ilt_client->page_size >> 12));
7003 if (QM_INIT(bp->qm_cid_count)) {
7004 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7005 ilt_client->client_num = ILT_CLIENT_QM;
7006 ilt_client->page_size = QM_ILT_PAGE_SZ;
7007 ilt_client->flags = 0;
7008 ilt_client->start = line;
7010 /* 4 bytes for each cid */
7011 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7014 ilt_client->end = line - 1;
7016 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7017 "flags 0x%x, hw psz %d\n",
7020 ilt_client->page_size,
7022 ilog2(ilt_client->page_size >> 12));
7026 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7028 ilt_client->client_num = ILT_CLIENT_SRC;
7029 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7030 ilt_client->flags = 0;
7031 ilt_client->start = line;
7032 line += SRC_ILT_LINES;
7033 ilt_client->end = line - 1;
7035 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7036 "flags 0x%x, hw psz %d\n",
7039 ilt_client->page_size,
7041 ilog2(ilt_client->page_size >> 12));
7044 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7048 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7050 ilt_client->client_num = ILT_CLIENT_TM;
7051 ilt_client->page_size = TM_ILT_PAGE_SZ;
7052 ilt_client->flags = 0;
7053 ilt_client->start = line;
7054 line += TM_ILT_LINES;
7055 ilt_client->end = line - 1;
7057 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7058 "flags 0x%x, hw psz %d\n",
7061 ilt_client->page_size,
7063 ilog2(ilt_client->page_size >> 12));
7066 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7068 BUG_ON(line > ILT_MAX_LINES);
7072 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7074 * @bp: driver handle
7075 * @fp: pointer to fastpath
7076 * @init_params: pointer to parameters structure
7078 * parameters configured:
7079 * - HC configuration
7080 * - Queue's CDU context
7082 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7083 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7087 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7088 if (!IS_FCOE_FP(fp)) {
7089 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7090 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7092 /* If HC is supporterd, enable host coalescing in the transition
7095 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7096 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7099 init_params->rx.hc_rate = bp->rx_ticks ?
7100 (1000000 / bp->rx_ticks) : 0;
7101 init_params->tx.hc_rate = bp->tx_ticks ?
7102 (1000000 / bp->tx_ticks) : 0;
7105 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7109 * CQ index among the SB indices: FCoE clients uses the default
7110 * SB, therefore it's different.
7112 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7113 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7116 /* set maximum number of COSs supported by this queue */
7117 init_params->max_cos = fp->max_cos;
7119 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7120 fp->index, init_params->max_cos);
7122 /* set the context pointers queue object */
7123 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7124 init_params->cxts[cos] =
7125 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7128 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7129 struct bnx2x_queue_state_params *q_params,
7130 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7131 int tx_index, bool leading)
7133 memset(tx_only_params, 0, sizeof(*tx_only_params));
7135 /* Set the command */
7136 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7138 /* Set tx-only QUEUE flags: don't zero statistics */
7139 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7141 /* choose the index of the cid to send the slow path on */
7142 tx_only_params->cid_index = tx_index;
7144 /* Set general TX_ONLY_SETUP parameters */
7145 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7147 /* Set Tx TX_ONLY_SETUP parameters */
7148 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7150 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7151 "cos %d, primary cid %d, cid %d, "
7152 "client id %d, sp-client id %d, flags %lx",
7153 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7154 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7155 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7157 /* send the ramrod */
7158 return bnx2x_queue_state_change(bp, q_params);
7163 * bnx2x_setup_queue - setup queue
7165 * @bp: driver handle
7166 * @fp: pointer to fastpath
7167 * @leading: is leading
7169 * This function performs 2 steps in a Queue state machine
7170 * actually: 1) RESET->INIT 2) INIT->SETUP
7173 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7176 struct bnx2x_queue_state_params q_params = {0};
7177 struct bnx2x_queue_setup_params *setup_params =
7178 &q_params.params.setup;
7179 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7180 &q_params.params.tx_only;
7184 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
7186 /* reset IGU state skip FCoE L2 queue */
7187 if (!IS_FCOE_FP(fp))
7188 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7191 q_params.q_obj = &fp->q_obj;
7192 /* We want to wait for completion in this context */
7193 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7195 /* Prepare the INIT parameters */
7196 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7198 /* Set the command */
7199 q_params.cmd = BNX2X_Q_CMD_INIT;
7201 /* Change the state to INIT */
7202 rc = bnx2x_queue_state_change(bp, &q_params);
7204 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7208 DP(BNX2X_MSG_SP, "init complete");
7211 /* Now move the Queue to the SETUP state... */
7212 memset(setup_params, 0, sizeof(*setup_params));
7214 /* Set QUEUE flags */
7215 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7217 /* Set general SETUP parameters */
7218 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7219 FIRST_TX_COS_INDEX);
7221 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7222 &setup_params->rxq_params);
7224 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7225 FIRST_TX_COS_INDEX);
7227 /* Set the command */
7228 q_params.cmd = BNX2X_Q_CMD_SETUP;
7230 /* Change the state to SETUP */
7231 rc = bnx2x_queue_state_change(bp, &q_params);
7233 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7237 /* loop through the relevant tx-only indices */
7238 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7239 tx_index < fp->max_cos;
7242 /* prepare and send tx-only ramrod*/
7243 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7244 tx_only_params, tx_index, leading);
7246 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7247 fp->index, tx_index);
7255 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7257 struct bnx2x_fastpath *fp = &bp->fp[index];
7258 struct bnx2x_fp_txdata *txdata;
7259 struct bnx2x_queue_state_params q_params = {0};
7262 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
7264 q_params.q_obj = &fp->q_obj;
7265 /* We want to wait for completion in this context */
7266 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7269 /* close tx-only connections */
7270 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7271 tx_index < fp->max_cos;
7274 /* ascertain this is a normal queue*/
7275 txdata = &fp->txdata[tx_index];
7277 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7280 /* send halt terminate on tx-only connection */
7281 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7282 memset(&q_params.params.terminate, 0,
7283 sizeof(q_params.params.terminate));
7284 q_params.params.terminate.cid_index = tx_index;
7286 rc = bnx2x_queue_state_change(bp, &q_params);
7290 /* send halt terminate on tx-only connection */
7291 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7292 memset(&q_params.params.cfc_del, 0,
7293 sizeof(q_params.params.cfc_del));
7294 q_params.params.cfc_del.cid_index = tx_index;
7295 rc = bnx2x_queue_state_change(bp, &q_params);
7299 /* Stop the primary connection: */
7300 /* ...halt the connection */
7301 q_params.cmd = BNX2X_Q_CMD_HALT;
7302 rc = bnx2x_queue_state_change(bp, &q_params);
7306 /* ...terminate the connection */
7307 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7308 memset(&q_params.params.terminate, 0,
7309 sizeof(q_params.params.terminate));
7310 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7311 rc = bnx2x_queue_state_change(bp, &q_params);
7314 /* ...delete cfc entry */
7315 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7316 memset(&q_params.params.cfc_del, 0,
7317 sizeof(q_params.params.cfc_del));
7318 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7319 return bnx2x_queue_state_change(bp, &q_params);
7323 static void bnx2x_reset_func(struct bnx2x *bp)
7325 int port = BP_PORT(bp);
7326 int func = BP_FUNC(bp);
7329 /* Disable the function in the FW */
7330 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7331 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7333 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7336 for_each_eth_queue(bp, i) {
7337 struct bnx2x_fastpath *fp = &bp->fp[i];
7338 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7339 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7345 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7346 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7350 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7351 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7354 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7355 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7359 if (bp->common.int_block == INT_BLOCK_HC) {
7360 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7361 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7363 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7364 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7368 /* Disable Timer scan */
7369 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7371 * Wait for at least 10ms and up to 2 second for the timers scan to
7374 for (i = 0; i < 200; i++) {
7376 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7381 bnx2x_clear_func_ilt(bp, func);
7383 /* Timers workaround bug for E2: if this is vnic-3,
7384 * we need to set the entire ilt range for this timers.
7386 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7387 struct ilt_client_info ilt_cli;
7388 /* use dummy TM client */
7389 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7391 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7392 ilt_cli.client_num = ILT_CLIENT_TM;
7394 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7397 /* this assumes that reset_port() called before reset_func()*/
7398 if (!CHIP_IS_E1x(bp))
7399 bnx2x_pf_disable(bp);
7404 static void bnx2x_reset_port(struct bnx2x *bp)
7406 int port = BP_PORT(bp);
7409 /* Reset physical Link */
7410 bnx2x__link_reset(bp);
7412 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7414 /* Do not rcv packets to BRB */
7415 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7416 /* Do not direct rcv packets that are not for MCP to the BRB */
7417 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7418 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7421 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7424 /* Check for BRB port occupancy */
7425 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7427 DP(NETIF_MSG_IFDOWN,
7428 "BRB1 is not empty %d blocks are occupied\n", val);
7430 /* TODO: Close Doorbell port? */
7433 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7435 struct bnx2x_func_state_params func_params = {0};
7437 /* Prepare parameters for function state transitions */
7438 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7440 func_params.f_obj = &bp->func_obj;
7441 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7443 func_params.params.hw_init.load_phase = load_code;
7445 return bnx2x_func_state_change(bp, &func_params);
7448 static inline int bnx2x_func_stop(struct bnx2x *bp)
7450 struct bnx2x_func_state_params func_params = {0};
7453 /* Prepare parameters for function state transitions */
7454 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7455 func_params.f_obj = &bp->func_obj;
7456 func_params.cmd = BNX2X_F_CMD_STOP;
7459 * Try to stop the function the 'good way'. If fails (in case
7460 * of a parity error during bnx2x_chip_cleanup()) and we are
7461 * not in a debug mode, perform a state transaction in order to
7462 * enable further HW_RESET transaction.
7464 rc = bnx2x_func_state_change(bp, &func_params);
7466 #ifdef BNX2X_STOP_ON_ERROR
7469 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7471 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7472 return bnx2x_func_state_change(bp, &func_params);
7480 * bnx2x_send_unload_req - request unload mode from the MCP.
7482 * @bp: driver handle
7483 * @unload_mode: requested function's unload mode
7485 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7487 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7490 int port = BP_PORT(bp);
7492 /* Select the UNLOAD request mode */
7493 if (unload_mode == UNLOAD_NORMAL)
7494 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7496 else if (bp->flags & NO_WOL_FLAG)
7497 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7500 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7501 u8 *mac_addr = bp->dev->dev_addr;
7503 /* The mac address is written to entries 1-4 to
7504 preserve entry 0 which is used by the PMF */
7505 u8 entry = (BP_E1HVN(bp) + 1)*8;
7507 val = (mac_addr[0] << 8) | mac_addr[1];
7508 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7510 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7511 (mac_addr[4] << 8) | mac_addr[5];
7512 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7514 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7517 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7519 /* Send the request to the MCP */
7521 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7523 int path = BP_PATH(bp);
7525 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7527 path, load_count[path][0], load_count[path][1],
7528 load_count[path][2]);
7529 load_count[path][0]--;
7530 load_count[path][1 + port]--;
7531 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7533 path, load_count[path][0], load_count[path][1],
7534 load_count[path][2]);
7535 if (load_count[path][0] == 0)
7536 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7537 else if (load_count[path][1 + port] == 0)
7538 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7540 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7547 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7549 * @bp: driver handle
7551 void bnx2x_send_unload_done(struct bnx2x *bp)
7553 /* Report UNLOAD_DONE to MCP */
7555 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7558 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7561 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7567 * (assumption: No Attention from MCP at this stage)
7568 * PMF probably in the middle of TXdisable/enable transaction
7569 * 1. Sync IRS for default SB
7570 * 2. Sync SP queue - this guarantes us that attention handling started
7571 * 3. Wait, that TXdisable/enable transaction completes
7573 * 1+2 guranty that if DCBx attention was scheduled it already changed
7574 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7575 * received complettion for the transaction the state is TX_STOPPED.
7576 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7580 /* make sure default SB ISR is done */
7582 synchronize_irq(bp->msix_table[0].vector);
7584 synchronize_irq(bp->pdev->irq);
7586 flush_workqueue(bnx2x_wq);
7588 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7589 BNX2X_F_STATE_STARTED && tout--)
7592 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7593 BNX2X_F_STATE_STARTED) {
7594 #ifdef BNX2X_STOP_ON_ERROR
7598 * Failed to complete the transaction in a "good way"
7599 * Force both transactions with CLR bit
7601 struct bnx2x_func_state_params func_params = {0};
7603 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7604 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7606 func_params.f_obj = &bp->func_obj;
7607 __set_bit(RAMROD_DRV_CLR_ONLY,
7608 &func_params.ramrod_flags);
7610 /* STARTED-->TX_ST0PPED */
7611 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7612 bnx2x_func_state_change(bp, &func_params);
7614 /* TX_ST0PPED-->STARTED */
7615 func_params.cmd = BNX2X_F_CMD_TX_START;
7616 return bnx2x_func_state_change(bp, &func_params);
7623 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7625 int port = BP_PORT(bp);
7628 struct bnx2x_mcast_ramrod_params rparam = {0};
7631 /* Wait until tx fastpath tasks complete */
7632 for_each_tx_queue(bp, i) {
7633 struct bnx2x_fastpath *fp = &bp->fp[i];
7635 for_each_cos_in_tx_queue(fp, cos)
7636 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7637 #ifdef BNX2X_STOP_ON_ERROR
7643 /* Give HW time to discard old tx messages */
7644 usleep_range(1000, 1000);
7646 /* Clean all ETH MACs */
7647 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7649 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7651 /* Clean up UC list */
7652 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7655 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7659 if (!CHIP_IS_E1(bp))
7660 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7662 /* Set "drop all" (stop Rx).
7663 * We need to take a netif_addr_lock() here in order to prevent
7664 * a race between the completion code and this code.
7666 netif_addr_lock_bh(bp->dev);
7667 /* Schedule the rx_mode command */
7668 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7669 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7671 bnx2x_set_storm_rx_mode(bp);
7673 /* Cleanup multicast configuration */
7674 rparam.mcast_obj = &bp->mcast_obj;
7675 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7677 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7679 netif_addr_unlock_bh(bp->dev);
7684 * Send the UNLOAD_REQUEST to the MCP. This will return if
7685 * this function should perform FUNC, PORT or COMMON HW
7688 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7691 * (assumption: No Attention from MCP at this stage)
7692 * PMF probably in the middle of TXdisable/enable transaction
7694 rc = bnx2x_func_wait_started(bp);
7696 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7697 #ifdef BNX2X_STOP_ON_ERROR
7702 /* Close multi and leading connections
7703 * Completions for ramrods are collected in a synchronous way
7705 for_each_queue(bp, i)
7706 if (bnx2x_stop_queue(bp, i))
7707 #ifdef BNX2X_STOP_ON_ERROR
7712 /* If SP settings didn't get completed so far - something
7713 * very wrong has happen.
7715 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7716 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7718 #ifndef BNX2X_STOP_ON_ERROR
7721 rc = bnx2x_func_stop(bp);
7723 BNX2X_ERR("Function stop failed!\n");
7724 #ifdef BNX2X_STOP_ON_ERROR
7729 /* Disable HW interrupts, NAPI */
7730 bnx2x_netif_stop(bp, 1);
7735 /* Reset the chip */
7736 rc = bnx2x_reset_hw(bp, reset_code);
7738 BNX2X_ERR("HW_RESET failed\n");
7741 /* Report UNLOAD_DONE to MCP */
7742 bnx2x_send_unload_done(bp);
7745 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7749 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7751 if (CHIP_IS_E1(bp)) {
7752 int port = BP_PORT(bp);
7753 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7754 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7756 val = REG_RD(bp, addr);
7758 REG_WR(bp, addr, val);
7760 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7761 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7762 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7763 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7767 /* Close gates #2, #3 and #4: */
7768 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7772 /* Gates #2 and #4a are closed/opened for "not E1" only */
7773 if (!CHIP_IS_E1(bp)) {
7775 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7777 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7781 if (CHIP_IS_E1x(bp)) {
7782 /* Prevent interrupts from HC on both ports */
7783 val = REG_RD(bp, HC_REG_CONFIG_1);
7784 REG_WR(bp, HC_REG_CONFIG_1,
7785 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7786 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7788 val = REG_RD(bp, HC_REG_CONFIG_0);
7789 REG_WR(bp, HC_REG_CONFIG_0,
7790 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7791 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7793 /* Prevent incomming interrupts in IGU */
7794 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7796 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7798 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7799 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7802 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7803 close ? "closing" : "opening");
7807 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7809 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7811 /* Do some magic... */
7812 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7813 *magic_val = val & SHARED_MF_CLP_MAGIC;
7814 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7818 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7820 * @bp: driver handle
7821 * @magic_val: old value of the `magic' bit.
7823 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7825 /* Restore the `magic' bit value... */
7826 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7827 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7828 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7832 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7834 * @bp: driver handle
7835 * @magic_val: old value of 'magic' bit.
7837 * Takes care of CLP configurations.
7839 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7842 u32 validity_offset;
7844 DP(NETIF_MSG_HW, "Starting\n");
7846 /* Set `magic' bit in order to save MF config */
7847 if (!CHIP_IS_E1(bp))
7848 bnx2x_clp_reset_prep(bp, magic_val);
7850 /* Get shmem offset */
7851 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7852 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7854 /* Clear validity map flags */
7856 REG_WR(bp, shmem + validity_offset, 0);
7859 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7860 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7863 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7865 * @bp: driver handle
7867 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7869 /* special handling for emulation and FPGA,
7870 wait 10 times longer */
7871 if (CHIP_REV_IS_SLOW(bp))
7872 msleep(MCP_ONE_TIMEOUT*10);
7874 msleep(MCP_ONE_TIMEOUT);
7878 * initializes bp->common.shmem_base and waits for validity signature to appear
7880 static int bnx2x_init_shmem(struct bnx2x *bp)
7886 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7887 if (bp->common.shmem_base) {
7888 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7889 if (val & SHR_MEM_VALIDITY_MB)
7893 bnx2x_mcp_wait_one(bp);
7895 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7897 BNX2X_ERR("BAD MCP validity signature\n");
7902 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7904 int rc = bnx2x_init_shmem(bp);
7906 /* Restore the `magic' bit value */
7907 if (!CHIP_IS_E1(bp))
7908 bnx2x_clp_reset_done(bp, magic_val);
7913 static void bnx2x_pxp_prep(struct bnx2x *bp)
7915 if (!CHIP_IS_E1(bp)) {
7916 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7917 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7923 * Reset the whole chip except for:
7925 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7928 * - MISC (including AEU)
7932 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
7934 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7938 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7939 * (per chip) blocks.
7942 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7943 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
7946 MISC_REGISTERS_RESET_REG_1_RST_HC |
7947 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7948 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7951 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
7952 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7953 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7954 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7955 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7956 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7957 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7958 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7960 reset_mask1 = 0xffffffff;
7963 reset_mask2 = 0xffff;
7965 reset_mask2 = 0x1ffff;
7967 if (CHIP_IS_E3(bp)) {
7968 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7969 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7972 /* Don't reset global blocks unless we need to */
7974 reset_mask2 &= ~global_bits2;
7977 * In case of attention in the QM, we need to reset PXP
7978 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
7979 * because otherwise QM reset would release 'close the gates' shortly
7980 * before resetting the PXP, then the PSWRQ would send a write
7981 * request to PGLUE. Then when PXP is reset, PGLUE would try to
7982 * read the payload data from PSWWR, but PSWWR would not
7983 * respond. The write queue in PGLUE would stuck, dmae commands
7984 * would not return. Therefore it's important to reset the second
7985 * reset register (containing the
7986 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
7987 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
7990 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7991 reset_mask2 & (~not_reset_mask2));
7993 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7994 reset_mask1 & (~not_reset_mask1));
7999 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
8000 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8005 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8006 * It should get cleared in no more than 1s.
8008 * @bp: driver handle
8010 * It should get cleared in no more than 1s. Returns 0 if
8011 * pending writes bit gets cleared.
8013 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8019 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8024 usleep_range(1000, 1000);
8025 } while (cnt-- > 0);
8028 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8036 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8040 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8043 /* Empty the Tetris buffer, wait for 1s */
8045 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8046 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8047 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8048 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8049 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8050 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8051 ((port_is_idle_0 & 0x1) == 0x1) &&
8052 ((port_is_idle_1 & 0x1) == 0x1) &&
8053 (pgl_exp_rom2 == 0xffffffff))
8055 usleep_range(1000, 1000);
8056 } while (cnt-- > 0);
8059 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8061 " outstanding read requests after 1s!\n");
8062 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8063 " port_is_idle_0=0x%08x,"
8064 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8065 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8072 /* Close gates #2, #3 and #4 */
8073 bnx2x_set_234_gates(bp, true);
8075 /* Poll for IGU VQs for 57712 and newer chips */
8076 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8080 /* TBD: Indicate that "process kill" is in progress to MCP */
8082 /* Clear "unprepared" bit */
8083 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8086 /* Make sure all is written to the chip before the reset */
8089 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8090 * PSWHST, GRC and PSWRD Tetris buffer.
8092 usleep_range(1000, 1000);
8094 /* Prepare to chip reset: */
8097 bnx2x_reset_mcp_prep(bp, &val);
8103 /* reset the chip */
8104 bnx2x_process_kill_chip_reset(bp, global);
8107 /* Recover after reset: */
8109 if (global && bnx2x_reset_mcp_comp(bp, val))
8112 /* TBD: Add resetting the NO_MCP mode DB here */
8117 /* Open the gates #2, #3 and #4 */
8118 bnx2x_set_234_gates(bp, false);
8120 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8121 * reset state, re-enable attentions. */
8126 int bnx2x_leader_reset(struct bnx2x *bp)
8129 bool global = bnx2x_reset_is_global(bp);
8131 /* Try to recover after the failure */
8132 if (bnx2x_process_kill(bp, global)) {
8133 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8134 "Aii!\n", BP_PATH(bp));
8136 goto exit_leader_reset;
8140 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8143 bnx2x_set_reset_done(bp);
8145 bnx2x_clear_reset_global(bp);
8149 bnx2x_release_leader_lock(bp);
8154 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8156 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8158 /* Disconnect this device */
8159 netif_device_detach(bp->dev);
8162 * Block ifup for all function on this engine until "process kill"
8165 bnx2x_set_reset_in_progress(bp);
8167 /* Shut down the power */
8168 bnx2x_set_power_state(bp, PCI_D3hot);
8170 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8176 * Assumption: runs under rtnl lock. This together with the fact
8177 * that it's called only from bnx2x_sp_rtnl() ensure that it
8178 * will never be called when netif_running(bp->dev) is false.
8180 static void bnx2x_parity_recover(struct bnx2x *bp)
8182 bool global = false;
8184 DP(NETIF_MSG_HW, "Handling parity\n");
8186 switch (bp->recovery_state) {
8187 case BNX2X_RECOVERY_INIT:
8188 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8189 bnx2x_chk_parity_attn(bp, &global, false);
8191 /* Try to get a LEADER_LOCK HW lock */
8192 if (bnx2x_trylock_leader_lock(bp)) {
8193 bnx2x_set_reset_in_progress(bp);
8195 * Check if there is a global attention and if
8196 * there was a global attention, set the global
8201 bnx2x_set_reset_global(bp);
8206 /* Stop the driver */
8207 /* If interface has been removed - break */
8208 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8211 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8214 * Reset MCP command sequence number and MCP mail box
8215 * sequence as we are going to reset the MCP.
8219 bp->fw_drv_pulse_wr_seq = 0;
8222 /* Ensure "is_leader", MCP command sequence and
8223 * "recovery_state" update values are seen on other
8229 case BNX2X_RECOVERY_WAIT:
8230 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8231 if (bp->is_leader) {
8232 int other_engine = BP_PATH(bp) ? 0 : 1;
8233 u32 other_load_counter =
8234 bnx2x_get_load_cnt(bp, other_engine);
8236 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8237 global = bnx2x_reset_is_global(bp);
8240 * In case of a parity in a global block, let
8241 * the first leader that performs a
8242 * leader_reset() reset the global blocks in
8243 * order to clear global attentions. Otherwise
8244 * the the gates will remain closed for that
8248 (global && other_load_counter)) {
8249 /* Wait until all other functions get
8252 schedule_delayed_work(&bp->sp_rtnl_task,
8256 /* If all other functions got down -
8257 * try to bring the chip back to
8258 * normal. In any case it's an exit
8259 * point for a leader.
8261 if (bnx2x_leader_reset(bp)) {
8262 bnx2x_recovery_failed(bp);
8266 /* If we are here, means that the
8267 * leader has succeeded and doesn't
8268 * want to be a leader any more. Try
8269 * to continue as a none-leader.
8273 } else { /* non-leader */
8274 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8275 /* Try to get a LEADER_LOCK HW lock as
8276 * long as a former leader may have
8277 * been unloaded by the user or
8278 * released a leadership by another
8281 if (bnx2x_trylock_leader_lock(bp)) {
8282 /* I'm a leader now! Restart a
8289 schedule_delayed_work(&bp->sp_rtnl_task,
8295 * If there was a global attention, wait
8296 * for it to be cleared.
8298 if (bnx2x_reset_is_global(bp)) {
8299 schedule_delayed_work(
8305 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8306 bnx2x_recovery_failed(bp);
8308 bp->recovery_state =
8309 BNX2X_RECOVERY_DONE;
8322 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8323 * scheduled on a general queue in order to prevent a dead lock.
8325 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8327 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8331 if (!netif_running(bp->dev))
8334 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8335 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8337 /* if stop on error is defined no recovery flows should be executed */
8338 #ifdef BNX2X_STOP_ON_ERROR
8339 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8340 "so reset not done to allow debug dump,\n"
8341 "you will need to reboot when done\n");
8345 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8347 * Clear TX_TIMEOUT bit as we are going to reset the function
8350 smp_mb__before_clear_bit();
8351 clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state);
8352 smp_mb__after_clear_bit();
8353 bnx2x_parity_recover(bp);
8354 } else if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT,
8355 &bp->sp_rtnl_state)){
8356 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8357 bnx2x_nic_load(bp, LOAD_NORMAL);
8364 /* end of nic load/unload */
8366 static void bnx2x_period_task(struct work_struct *work)
8368 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8370 if (!netif_running(bp->dev))
8371 goto period_task_exit;
8373 if (CHIP_REV_IS_SLOW(bp)) {
8374 BNX2X_ERR("period task called on emulation, ignoring\n");
8375 goto period_task_exit;
8378 bnx2x_acquire_phy_lock(bp);
8380 * The barrier is needed to ensure the ordering between the writing to
8381 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8386 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8388 /* Re-queue task in 1 sec */
8389 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8392 bnx2x_release_phy_lock(bp);
8398 * Init service functions
8401 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8403 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8404 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8405 return base + (BP_ABS_FUNC(bp)) * stride;
8408 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8410 u32 reg = bnx2x_get_pretend_reg(bp);
8412 /* Flush all outstanding writes */
8415 /* Pretend to be function 0 */
8417 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8419 /* From now we are in the "like-E1" mode */
8420 bnx2x_int_disable(bp);
8422 /* Flush all outstanding writes */
8425 /* Restore the original function */
8426 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8430 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8433 bnx2x_int_disable(bp);
8435 bnx2x_undi_int_disable_e1h(bp);
8438 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8442 /* Check if there is any driver already loaded */
8443 val = REG_RD(bp, MISC_REG_UNPREPARED);
8445 /* Check if it is the UNDI driver
8446 * UNDI driver initializes CID offset for normal bell to 0x7
8448 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8449 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8451 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8452 /* save our pf_num */
8453 int orig_pf_num = bp->pf_num;
8455 u32 swap_en, swap_val, value;
8457 /* clear the UNDI indication */
8458 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8460 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8462 /* try unload UNDI on port 0 */
8465 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8466 DRV_MSG_SEQ_NUMBER_MASK);
8467 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8469 /* if UNDI is loaded on the other port */
8470 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8472 /* send "DONE" for previous unload */
8473 bnx2x_fw_command(bp,
8474 DRV_MSG_CODE_UNLOAD_DONE, 0);
8476 /* unload UNDI on port 1 */
8479 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8480 DRV_MSG_SEQ_NUMBER_MASK);
8481 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8483 bnx2x_fw_command(bp, reset_code, 0);
8486 /* now it's safe to release the lock */
8487 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8489 bnx2x_undi_int_disable(bp);
8492 /* close input traffic and wait for it */
8493 /* Do not rcv packets to BRB */
8494 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8495 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8496 /* Do not direct rcv packets that are not for MCP to
8498 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8499 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8501 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8502 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8505 /* save NIG port swap info */
8506 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8507 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8510 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8514 if (CHIP_IS_E3(bp)) {
8515 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8516 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8520 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8523 /* take the NIG out of reset and restore swap values */
8525 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8526 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8527 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8528 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8530 /* send unload done to the MCP */
8531 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8533 /* restore our func and fw_seq */
8534 bp->pf_num = orig_pf_num;
8536 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8537 DRV_MSG_SEQ_NUMBER_MASK);
8539 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8543 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8545 u32 val, val2, val3, val4, id;
8548 /* Get the chip revision id and number. */
8549 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8550 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8551 id = ((val & 0xffff) << 16);
8552 val = REG_RD(bp, MISC_REG_CHIP_REV);
8553 id |= ((val & 0xf) << 12);
8554 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8555 id |= ((val & 0xff) << 4);
8556 val = REG_RD(bp, MISC_REG_BOND_ID);
8558 bp->common.chip_id = id;
8560 /* Set doorbell size */
8561 bp->db_size = (1 << BNX2X_DB_SHIFT);
8563 if (!CHIP_IS_E1x(bp)) {
8564 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8566 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8568 val = (val >> 1) & 1;
8569 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8571 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8574 if (CHIP_MODE_IS_4_PORT(bp))
8575 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8577 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8579 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8580 bp->pfid = bp->pf_num; /* 0..7 */
8583 bp->link_params.chip_id = bp->common.chip_id;
8584 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8586 val = (REG_RD(bp, 0x2874) & 0x55);
8587 if ((bp->common.chip_id & 0x1) ||
8588 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8589 bp->flags |= ONE_PORT_FLAG;
8590 BNX2X_DEV_INFO("single port device\n");
8593 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8594 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8595 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8596 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8597 bp->common.flash_size, bp->common.flash_size);
8599 bnx2x_init_shmem(bp);
8603 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8604 MISC_REG_GENERIC_CR_1 :
8605 MISC_REG_GENERIC_CR_0));
8607 bp->link_params.shmem_base = bp->common.shmem_base;
8608 bp->link_params.shmem2_base = bp->common.shmem2_base;
8609 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8610 bp->common.shmem_base, bp->common.shmem2_base);
8612 if (!bp->common.shmem_base) {
8613 BNX2X_DEV_INFO("MCP not active\n");
8614 bp->flags |= NO_MCP_FLAG;
8618 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8619 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8621 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8622 SHARED_HW_CFG_LED_MODE_MASK) >>
8623 SHARED_HW_CFG_LED_MODE_SHIFT);
8625 bp->link_params.feature_config_flags = 0;
8626 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8627 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8628 bp->link_params.feature_config_flags |=
8629 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8631 bp->link_params.feature_config_flags &=
8632 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8634 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8635 bp->common.bc_ver = val;
8636 BNX2X_DEV_INFO("bc_ver %X\n", val);
8637 if (val < BNX2X_BC_VER) {
8638 /* for now only warn
8639 * later we might need to enforce this */
8640 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8641 "please upgrade BC\n", BNX2X_BC_VER, val);
8643 bp->link_params.feature_config_flags |=
8644 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8645 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8647 bp->link_params.feature_config_flags |=
8648 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8649 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8651 bp->link_params.feature_config_flags |=
8652 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8653 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8655 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8656 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8658 BNX2X_DEV_INFO("%sWoL capable\n",
8659 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8661 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8662 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8663 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8664 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8666 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8667 val, val2, val3, val4);
8670 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8671 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8673 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8675 int pfid = BP_FUNC(bp);
8676 int vn = BP_E1HVN(bp);
8679 u8 fid, igu_sb_cnt = 0;
8681 bp->igu_base_sb = 0xff;
8682 if (CHIP_INT_MODE_IS_BC(bp)) {
8683 igu_sb_cnt = bp->igu_sb_cnt;
8684 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8687 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8688 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8693 /* IGU in normal mode - read CAM */
8694 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8696 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8697 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8700 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8701 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8703 if (IGU_VEC(val) == 0)
8704 /* default status block */
8705 bp->igu_dsb_id = igu_sb_id;
8707 if (bp->igu_base_sb == 0xff)
8708 bp->igu_base_sb = igu_sb_id;
8714 #ifdef CONFIG_PCI_MSI
8716 * It's expected that number of CAM entries for this functions is equal
8717 * to the number evaluated based on the MSI-X table size. We want a
8718 * harsh warning if these values are different!
8720 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8723 if (igu_sb_cnt == 0)
8724 BNX2X_ERR("CAM configuration error\n");
8727 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8730 int cfg_size = 0, idx, port = BP_PORT(bp);
8732 /* Aggregation of supported attributes of all external phys */
8733 bp->port.supported[0] = 0;
8734 bp->port.supported[1] = 0;
8735 switch (bp->link_params.num_phys) {
8737 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8741 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8745 if (bp->link_params.multi_phy_config &
8746 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8747 bp->port.supported[1] =
8748 bp->link_params.phy[EXT_PHY1].supported;
8749 bp->port.supported[0] =
8750 bp->link_params.phy[EXT_PHY2].supported;
8752 bp->port.supported[0] =
8753 bp->link_params.phy[EXT_PHY1].supported;
8754 bp->port.supported[1] =
8755 bp->link_params.phy[EXT_PHY2].supported;
8761 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8762 BNX2X_ERR("NVRAM config error. BAD phy config."
8763 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8765 dev_info.port_hw_config[port].external_phy_config),
8767 dev_info.port_hw_config[port].external_phy_config2));
8772 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8774 switch (switch_cfg) {
8776 bp->port.phy_addr = REG_RD(
8777 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8779 case SWITCH_CFG_10G:
8780 bp->port.phy_addr = REG_RD(
8781 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8784 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8785 bp->port.link_config[0]);
8789 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8790 /* mask what we support according to speed_cap_mask per configuration */
8791 for (idx = 0; idx < cfg_size; idx++) {
8792 if (!(bp->link_params.speed_cap_mask[idx] &
8793 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8794 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8796 if (!(bp->link_params.speed_cap_mask[idx] &
8797 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8798 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8800 if (!(bp->link_params.speed_cap_mask[idx] &
8801 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8802 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8804 if (!(bp->link_params.speed_cap_mask[idx] &
8805 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8806 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8808 if (!(bp->link_params.speed_cap_mask[idx] &
8809 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8810 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8811 SUPPORTED_1000baseT_Full);
8813 if (!(bp->link_params.speed_cap_mask[idx] &
8814 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8815 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8817 if (!(bp->link_params.speed_cap_mask[idx] &
8818 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8819 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8823 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8824 bp->port.supported[1]);
8827 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8829 u32 link_config, idx, cfg_size = 0;
8830 bp->port.advertising[0] = 0;
8831 bp->port.advertising[1] = 0;
8832 switch (bp->link_params.num_phys) {
8841 for (idx = 0; idx < cfg_size; idx++) {
8842 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8843 link_config = bp->port.link_config[idx];
8844 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8845 case PORT_FEATURE_LINK_SPEED_AUTO:
8846 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8847 bp->link_params.req_line_speed[idx] =
8849 bp->port.advertising[idx] |=
8850 bp->port.supported[idx];
8852 /* force 10G, no AN */
8853 bp->link_params.req_line_speed[idx] =
8855 bp->port.advertising[idx] |=
8856 (ADVERTISED_10000baseT_Full |
8862 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8863 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8864 bp->link_params.req_line_speed[idx] =
8866 bp->port.advertising[idx] |=
8867 (ADVERTISED_10baseT_Full |
8870 BNX2X_ERR("NVRAM config error. "
8871 "Invalid link_config 0x%x"
8872 " speed_cap_mask 0x%x\n",
8874 bp->link_params.speed_cap_mask[idx]);
8879 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8880 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8881 bp->link_params.req_line_speed[idx] =
8883 bp->link_params.req_duplex[idx] =
8885 bp->port.advertising[idx] |=
8886 (ADVERTISED_10baseT_Half |
8889 BNX2X_ERR("NVRAM config error. "
8890 "Invalid link_config 0x%x"
8891 " speed_cap_mask 0x%x\n",
8893 bp->link_params.speed_cap_mask[idx]);
8898 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8899 if (bp->port.supported[idx] &
8900 SUPPORTED_100baseT_Full) {
8901 bp->link_params.req_line_speed[idx] =
8903 bp->port.advertising[idx] |=
8904 (ADVERTISED_100baseT_Full |
8907 BNX2X_ERR("NVRAM config error. "
8908 "Invalid link_config 0x%x"
8909 " speed_cap_mask 0x%x\n",
8911 bp->link_params.speed_cap_mask[idx]);
8916 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8917 if (bp->port.supported[idx] &
8918 SUPPORTED_100baseT_Half) {
8919 bp->link_params.req_line_speed[idx] =
8921 bp->link_params.req_duplex[idx] =
8923 bp->port.advertising[idx] |=
8924 (ADVERTISED_100baseT_Half |
8927 BNX2X_ERR("NVRAM config error. "
8928 "Invalid link_config 0x%x"
8929 " speed_cap_mask 0x%x\n",
8931 bp->link_params.speed_cap_mask[idx]);
8936 case PORT_FEATURE_LINK_SPEED_1G:
8937 if (bp->port.supported[idx] &
8938 SUPPORTED_1000baseT_Full) {
8939 bp->link_params.req_line_speed[idx] =
8941 bp->port.advertising[idx] |=
8942 (ADVERTISED_1000baseT_Full |
8945 BNX2X_ERR("NVRAM config error. "
8946 "Invalid link_config 0x%x"
8947 " speed_cap_mask 0x%x\n",
8949 bp->link_params.speed_cap_mask[idx]);
8954 case PORT_FEATURE_LINK_SPEED_2_5G:
8955 if (bp->port.supported[idx] &
8956 SUPPORTED_2500baseX_Full) {
8957 bp->link_params.req_line_speed[idx] =
8959 bp->port.advertising[idx] |=
8960 (ADVERTISED_2500baseX_Full |
8963 BNX2X_ERR("NVRAM config error. "
8964 "Invalid link_config 0x%x"
8965 " speed_cap_mask 0x%x\n",
8967 bp->link_params.speed_cap_mask[idx]);
8972 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8973 if (bp->port.supported[idx] &
8974 SUPPORTED_10000baseT_Full) {
8975 bp->link_params.req_line_speed[idx] =
8977 bp->port.advertising[idx] |=
8978 (ADVERTISED_10000baseT_Full |
8981 BNX2X_ERR("NVRAM config error. "
8982 "Invalid link_config 0x%x"
8983 " speed_cap_mask 0x%x\n",
8985 bp->link_params.speed_cap_mask[idx]);
8989 case PORT_FEATURE_LINK_SPEED_20G:
8990 bp->link_params.req_line_speed[idx] = SPEED_20000;
8994 BNX2X_ERR("NVRAM config error. "
8995 "BAD link speed link_config 0x%x\n",
8997 bp->link_params.req_line_speed[idx] =
8999 bp->port.advertising[idx] =
9000 bp->port.supported[idx];
9004 bp->link_params.req_flow_ctrl[idx] = (link_config &
9005 PORT_FEATURE_FLOW_CONTROL_MASK);
9006 if ((bp->link_params.req_flow_ctrl[idx] ==
9007 BNX2X_FLOW_CTRL_AUTO) &&
9008 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9009 bp->link_params.req_flow_ctrl[idx] =
9010 BNX2X_FLOW_CTRL_NONE;
9013 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9014 " 0x%x advertising 0x%x\n",
9015 bp->link_params.req_line_speed[idx],
9016 bp->link_params.req_duplex[idx],
9017 bp->link_params.req_flow_ctrl[idx],
9018 bp->port.advertising[idx]);
9022 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9024 mac_hi = cpu_to_be16(mac_hi);
9025 mac_lo = cpu_to_be32(mac_lo);
9026 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9027 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9030 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9032 int port = BP_PORT(bp);
9034 u32 ext_phy_type, ext_phy_config;
9036 bp->link_params.bp = bp;
9037 bp->link_params.port = port;
9039 bp->link_params.lane_config =
9040 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9042 bp->link_params.speed_cap_mask[0] =
9044 dev_info.port_hw_config[port].speed_capability_mask);
9045 bp->link_params.speed_cap_mask[1] =
9047 dev_info.port_hw_config[port].speed_capability_mask2);
9048 bp->port.link_config[0] =
9049 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9051 bp->port.link_config[1] =
9052 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9054 bp->link_params.multi_phy_config =
9055 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9056 /* If the device is capable of WoL, set the default state according
9059 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9060 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9061 (config & PORT_FEATURE_WOL_ENABLED));
9063 BNX2X_DEV_INFO("lane_config 0x%08x "
9064 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9065 bp->link_params.lane_config,
9066 bp->link_params.speed_cap_mask[0],
9067 bp->port.link_config[0]);
9069 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9070 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9071 bnx2x_phy_probe(&bp->link_params);
9072 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9074 bnx2x_link_settings_requested(bp);
9077 * If connected directly, work with the internal PHY, otherwise, work
9078 * with the external PHY
9082 dev_info.port_hw_config[port].external_phy_config);
9083 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9084 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9085 bp->mdio.prtad = bp->port.phy_addr;
9087 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9088 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9090 XGXS_EXT_PHY_ADDR(ext_phy_config);
9093 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9094 * In MF mode, it is set to cover self test cases
9097 bp->port.need_hw_lock = 1;
9099 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9100 bp->common.shmem_base,
9101 bp->common.shmem2_base);
9105 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9107 int port = BP_PORT(bp);
9108 int func = BP_ABS_FUNC(bp);
9110 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9111 drv_lic_key[port].max_iscsi_conn);
9112 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9113 drv_lic_key[port].max_fcoe_conn);
9115 /* Get the number of maximum allowed iSCSI and FCoE connections */
9116 bp->cnic_eth_dev.max_iscsi_conn =
9117 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9118 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9120 bp->cnic_eth_dev.max_fcoe_conn =
9121 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9122 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9127 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9129 dev_info.port_hw_config[port].
9130 fcoe_wwn_port_name_upper);
9131 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9133 dev_info.port_hw_config[port].
9134 fcoe_wwn_port_name_lower);
9137 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9139 dev_info.port_hw_config[port].
9140 fcoe_wwn_node_name_upper);
9141 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9143 dev_info.port_hw_config[port].
9144 fcoe_wwn_node_name_lower);
9145 } else if (!IS_MF_SD(bp)) {
9146 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9149 * Read the WWN info only if the FCoE feature is enabled for
9152 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9154 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9155 MF_CFG_RD(bp, func_ext_config[func].
9156 fcoe_wwn_port_name_upper);
9157 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9158 MF_CFG_RD(bp, func_ext_config[func].
9159 fcoe_wwn_port_name_lower);
9162 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9163 MF_CFG_RD(bp, func_ext_config[func].
9164 fcoe_wwn_node_name_upper);
9165 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9166 MF_CFG_RD(bp, func_ext_config[func].
9167 fcoe_wwn_node_name_lower);
9171 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9172 bp->cnic_eth_dev.max_iscsi_conn,
9173 bp->cnic_eth_dev.max_fcoe_conn);
9176 * If maximum allowed number of connections is zero -
9177 * disable the feature.
9179 if (!bp->cnic_eth_dev.max_iscsi_conn)
9180 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9182 if (!bp->cnic_eth_dev.max_fcoe_conn)
9183 bp->flags |= NO_FCOE_FLAG;
9187 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9190 int func = BP_ABS_FUNC(bp);
9191 int port = BP_PORT(bp);
9193 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9194 u8 *fip_mac = bp->fip_mac;
9197 /* Zero primary MAC configuration */
9198 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9201 BNX2X_ERROR("warning: random MAC workaround active\n");
9202 random_ether_addr(bp->dev->dev_addr);
9203 } else if (IS_MF(bp)) {
9204 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9205 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9206 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9207 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9208 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9211 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9212 * FCoE MAC then the appropriate feature should be disabled.
9215 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9216 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9217 val2 = MF_CFG_RD(bp, func_ext_config[func].
9218 iscsi_mac_addr_upper);
9219 val = MF_CFG_RD(bp, func_ext_config[func].
9220 iscsi_mac_addr_lower);
9221 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9222 BNX2X_DEV_INFO("Read iSCSI MAC: "
9224 BNX2X_MAC_PRN_LIST(iscsi_mac));
9226 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9228 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9229 val2 = MF_CFG_RD(bp, func_ext_config[func].
9230 fcoe_mac_addr_upper);
9231 val = MF_CFG_RD(bp, func_ext_config[func].
9232 fcoe_mac_addr_lower);
9233 bnx2x_set_mac_buf(fip_mac, val, val2);
9234 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9236 BNX2X_MAC_PRN_LIST(fip_mac));
9239 bp->flags |= NO_FCOE_FLAG;
9243 /* in SF read MACs from port configuration */
9244 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9245 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9246 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9249 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9251 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9253 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9257 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9258 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9261 /* Set the FCoE MAC in modes other then MF_SI */
9262 if (!CHIP_IS_E1x(bp)) {
9264 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9265 else if (!IS_MF(bp))
9266 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
9269 /* Disable iSCSI if MAC configuration is
9272 if (!is_valid_ether_addr(iscsi_mac)) {
9273 bp->flags |= NO_ISCSI_FLAG;
9274 memset(iscsi_mac, 0, ETH_ALEN);
9277 /* Disable FCoE if MAC configuration is
9280 if (!is_valid_ether_addr(fip_mac)) {
9281 bp->flags |= NO_FCOE_FLAG;
9282 memset(bp->fip_mac, 0, ETH_ALEN);
9286 if (!is_valid_ether_addr(bp->dev->dev_addr))
9287 dev_err(&bp->pdev->dev,
9288 "bad Ethernet MAC address configuration: "
9289 BNX2X_MAC_FMT", change it manually before bringing up "
9290 "the appropriate network interface\n",
9291 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
9294 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9296 int /*abs*/func = BP_ABS_FUNC(bp);
9301 bnx2x_get_common_hwinfo(bp);
9304 * initialize IGU parameters
9306 if (CHIP_IS_E1x(bp)) {
9307 bp->common.int_block = INT_BLOCK_HC;
9309 bp->igu_dsb_id = DEF_SB_IGU_ID;
9310 bp->igu_base_sb = 0;
9312 bp->common.int_block = INT_BLOCK_IGU;
9313 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9315 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9318 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9320 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9321 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9322 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9324 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9326 usleep_range(1000, 1000);
9329 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9330 dev_err(&bp->pdev->dev,
9331 "FORCING Normal Mode failed!!!\n");
9336 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9337 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9338 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9340 BNX2X_DEV_INFO("IGU Normal Mode\n");
9342 bnx2x_get_igu_cam_info(bp);
9347 * set base FW non-default (fast path) status block id, this value is
9348 * used to initialize the fw_sb_id saved on the fp/queue structure to
9349 * determine the id used by the FW.
9351 if (CHIP_IS_E1x(bp))
9352 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9354 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9355 * the same queue are indicated on the same IGU SB). So we prefer
9356 * FW and IGU SBs to be the same value.
9358 bp->base_fw_ndsb = bp->igu_base_sb;
9360 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9361 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9362 bp->igu_sb_cnt, bp->base_fw_ndsb);
9365 * Initialize MF configuration
9372 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9373 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9374 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9375 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9377 if (SHMEM2_HAS(bp, mf_cfg_addr))
9378 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9380 bp->common.mf_cfg_base = bp->common.shmem_base +
9381 offsetof(struct shmem_region, func_mb) +
9382 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9384 * get mf configuration:
9385 * 1. existence of MF configuration
9386 * 2. MAC address must be legal (check only upper bytes)
9387 * for Switch-Independent mode;
9388 * OVLAN must be legal for Switch-Dependent mode
9389 * 3. SF_MODE configures specific MF mode
9391 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9392 /* get mf configuration */
9394 dev_info.shared_feature_config.config);
9395 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9398 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9399 val = MF_CFG_RD(bp, func_mf_config[func].
9401 /* check for legal mac (upper bytes)*/
9402 if (val != 0xffff) {
9403 bp->mf_mode = MULTI_FUNCTION_SI;
9404 bp->mf_config[vn] = MF_CFG_RD(bp,
9405 func_mf_config[func].config);
9407 BNX2X_DEV_INFO("illegal MAC address "
9410 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9411 /* get OV configuration */
9413 func_mf_config[FUNC_0].e1hov_tag);
9414 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9416 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9417 bp->mf_mode = MULTI_FUNCTION_SD;
9418 bp->mf_config[vn] = MF_CFG_RD(bp,
9419 func_mf_config[func].config);
9421 BNX2X_DEV_INFO("illegal OV for SD\n");
9424 /* Unknown configuration: reset mf_config */
9425 bp->mf_config[vn] = 0;
9426 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9430 BNX2X_DEV_INFO("%s function mode\n",
9431 IS_MF(bp) ? "multi" : "single");
9433 switch (bp->mf_mode) {
9434 case MULTI_FUNCTION_SD:
9435 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9436 FUNC_MF_CFG_E1HOV_TAG_MASK;
9437 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9439 bp->path_has_ovlan = true;
9441 BNX2X_DEV_INFO("MF OV for func %d is %d "
9442 "(0x%04x)\n", func, bp->mf_ov,
9445 dev_err(&bp->pdev->dev,
9446 "No valid MF OV for func %d, "
9447 "aborting\n", func);
9451 case MULTI_FUNCTION_SI:
9452 BNX2X_DEV_INFO("func %d is in MF "
9453 "switch-independent mode\n", func);
9457 dev_err(&bp->pdev->dev,
9458 "VN %d is in a single function mode, "
9465 /* check if other port on the path needs ovlan:
9466 * Since MF configuration is shared between ports
9467 * Possible mixed modes are only
9468 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9470 if (CHIP_MODE_IS_4_PORT(bp) &&
9471 !bp->path_has_ovlan &&
9473 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9474 u8 other_port = !BP_PORT(bp);
9475 u8 other_func = BP_PATH(bp) + 2*other_port;
9477 func_mf_config[other_func].e1hov_tag);
9478 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9479 bp->path_has_ovlan = true;
9483 /* adjust igu_sb_cnt to MF for E1x */
9484 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9485 bp->igu_sb_cnt /= E1HVN_MAX;
9488 bnx2x_get_port_hwinfo(bp);
9490 if (!BP_NOMCP(bp)) {
9492 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9493 DRV_MSG_SEQ_NUMBER_MASK);
9494 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9497 /* Get MAC addresses */
9498 bnx2x_get_mac_hwinfo(bp);
9501 bnx2x_get_cnic_info(bp);
9504 /* Get current FW pulse sequence */
9505 if (!BP_NOMCP(bp)) {
9506 int mb_idx = BP_FW_MB_IDX(bp);
9508 bp->fw_drv_pulse_wr_seq =
9509 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9510 DRV_PULSE_SEQ_MASK);
9511 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9517 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9519 int cnt, i, block_end, rodi;
9520 char vpd_data[BNX2X_VPD_LEN+1];
9521 char str_id_reg[VENDOR_ID_LEN+1];
9522 char str_id_cap[VENDOR_ID_LEN+1];
9525 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9526 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9528 if (cnt < BNX2X_VPD_LEN)
9531 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9532 PCI_VPD_LRDT_RO_DATA);
9537 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9538 pci_vpd_lrdt_size(&vpd_data[i]);
9540 i += PCI_VPD_LRDT_TAG_SIZE;
9542 if (block_end > BNX2X_VPD_LEN)
9545 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9546 PCI_VPD_RO_KEYWORD_MFR_ID);
9550 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9552 if (len != VENDOR_ID_LEN)
9555 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9557 /* vendor specific info */
9558 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9559 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9560 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9561 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9563 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9564 PCI_VPD_RO_KEYWORD_VENDOR0);
9566 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9568 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9570 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9571 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9572 bp->fw_ver[len] = ' ';
9581 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9585 if (CHIP_REV_IS_FPGA(bp))
9586 SET_FLAGS(flags, MODE_FPGA);
9587 else if (CHIP_REV_IS_EMUL(bp))
9588 SET_FLAGS(flags, MODE_EMUL);
9590 SET_FLAGS(flags, MODE_ASIC);
9592 if (CHIP_MODE_IS_4_PORT(bp))
9593 SET_FLAGS(flags, MODE_PORT4);
9595 SET_FLAGS(flags, MODE_PORT2);
9598 SET_FLAGS(flags, MODE_E2);
9599 else if (CHIP_IS_E3(bp)) {
9600 SET_FLAGS(flags, MODE_E3);
9601 if (CHIP_REV(bp) == CHIP_REV_Ax)
9602 SET_FLAGS(flags, MODE_E3_A0);
9603 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9604 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9608 SET_FLAGS(flags, MODE_MF);
9609 switch (bp->mf_mode) {
9610 case MULTI_FUNCTION_SD:
9611 SET_FLAGS(flags, MODE_MF_SD);
9613 case MULTI_FUNCTION_SI:
9614 SET_FLAGS(flags, MODE_MF_SI);
9618 SET_FLAGS(flags, MODE_SF);
9620 #if defined(__LITTLE_ENDIAN)
9621 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9622 #else /*(__BIG_ENDIAN)*/
9623 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9625 INIT_MODE_FLAGS(bp) = flags;
9628 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9634 mutex_init(&bp->port.phy_mutex);
9635 mutex_init(&bp->fw_mb_mutex);
9636 spin_lock_init(&bp->stats_lock);
9638 mutex_init(&bp->cnic_mutex);
9641 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9642 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9643 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9644 rc = bnx2x_get_hwinfo(bp);
9648 bnx2x_set_modes_bitmap(bp);
9650 rc = bnx2x_alloc_mem_bp(bp);
9654 bnx2x_read_fwinfo(bp);
9658 /* need to reset chip if undi was active */
9660 bnx2x_undi_unload(bp);
9662 if (CHIP_REV_IS_FPGA(bp))
9663 dev_err(&bp->pdev->dev, "FPGA detected\n");
9665 if (BP_NOMCP(bp) && (func == 0))
9666 dev_err(&bp->pdev->dev, "MCP disabled, "
9667 "must load devices in order!\n");
9669 bp->multi_mode = multi_mode;
9673 bp->flags &= ~TPA_ENABLE_FLAG;
9674 bp->dev->features &= ~NETIF_F_LRO;
9676 bp->flags |= TPA_ENABLE_FLAG;
9677 bp->dev->features |= NETIF_F_LRO;
9679 bp->disable_tpa = disable_tpa;
9682 bp->dropless_fc = 0;
9684 bp->dropless_fc = dropless_fc;
9688 bp->tx_ring_size = MAX_TX_AVAIL;
9690 /* make sure that the numbers are in the right granularity */
9691 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9692 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9694 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9695 bp->current_interval = (poll ? poll : timer_interval);
9697 init_timer(&bp->timer);
9698 bp->timer.expires = jiffies + bp->current_interval;
9699 bp->timer.data = (unsigned long) bp;
9700 bp->timer.function = bnx2x_timer;
9702 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9703 bnx2x_dcbx_init_params(bp);
9706 if (CHIP_IS_E1x(bp))
9707 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9709 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9712 /* multiple tx priority */
9713 if (CHIP_IS_E1x(bp))
9714 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9715 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9716 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9717 if (CHIP_IS_E3B0(bp))
9718 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9724 /****************************************************************************
9725 * General service functions
9726 ****************************************************************************/
9729 * net_device service functions
9732 /* called with rtnl_lock */
9733 static int bnx2x_open(struct net_device *dev)
9735 struct bnx2x *bp = netdev_priv(dev);
9736 bool global = false;
9737 int other_engine = BP_PATH(bp) ? 0 : 1;
9738 u32 other_load_counter, load_counter;
9740 netif_carrier_off(dev);
9742 bnx2x_set_power_state(bp, PCI_D0);
9744 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9745 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9748 * If parity had happen during the unload, then attentions
9749 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9750 * want the first function loaded on the current engine to
9751 * complete the recovery.
9753 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9754 bnx2x_chk_parity_attn(bp, &global, true))
9757 * If there are attentions and they are in a global
9758 * blocks, set the GLOBAL_RESET bit regardless whether
9759 * it will be this function that will complete the
9763 bnx2x_set_reset_global(bp);
9766 * Only the first function on the current engine should
9767 * try to recover in open. In case of attentions in
9768 * global blocks only the first in the chip should try
9771 if ((!load_counter &&
9772 (!global || !other_load_counter)) &&
9773 bnx2x_trylock_leader_lock(bp) &&
9774 !bnx2x_leader_reset(bp)) {
9775 netdev_info(bp->dev, "Recovered in open\n");
9779 /* recovery has failed... */
9780 bnx2x_set_power_state(bp, PCI_D3hot);
9781 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9783 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9784 " completed yet. Try again later. If u still see this"
9785 " message after a few retries then power cycle is"
9791 bp->recovery_state = BNX2X_RECOVERY_DONE;
9792 return bnx2x_nic_load(bp, LOAD_OPEN);
9795 /* called with rtnl_lock */
9796 static int bnx2x_close(struct net_device *dev)
9798 struct bnx2x *bp = netdev_priv(dev);
9800 /* Unload the driver, release IRQs */
9801 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9804 bnx2x_set_power_state(bp, PCI_D3hot);
9809 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9810 struct bnx2x_mcast_ramrod_params *p)
9812 int mc_count = netdev_mc_count(bp->dev);
9813 struct bnx2x_mcast_list_elem *mc_mac =
9814 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9815 struct netdev_hw_addr *ha;
9820 INIT_LIST_HEAD(&p->mcast_list);
9822 netdev_for_each_mc_addr(ha, bp->dev) {
9823 mc_mac->mac = bnx2x_mc_addr(ha);
9824 list_add_tail(&mc_mac->link, &p->mcast_list);
9828 p->mcast_list_len = mc_count;
9833 static inline void bnx2x_free_mcast_macs_list(
9834 struct bnx2x_mcast_ramrod_params *p)
9836 struct bnx2x_mcast_list_elem *mc_mac =
9837 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9845 * bnx2x_set_uc_list - configure a new unicast MACs list.
9847 * @bp: driver handle
9849 * We will use zero (0) as a MAC type for these MACs.
9851 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
9854 struct net_device *dev = bp->dev;
9855 struct netdev_hw_addr *ha;
9856 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9857 unsigned long ramrod_flags = 0;
9859 /* First schedule a cleanup up of old configuration */
9860 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9862 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9866 netdev_for_each_uc_addr(ha, dev) {
9867 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9868 BNX2X_UC_LIST_MAC, &ramrod_flags);
9870 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9876 /* Execute the pending commands */
9877 __set_bit(RAMROD_CONT, &ramrod_flags);
9878 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9879 BNX2X_UC_LIST_MAC, &ramrod_flags);
9882 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9884 struct net_device *dev = bp->dev;
9885 struct bnx2x_mcast_ramrod_params rparam = {0};
9888 rparam.mcast_obj = &bp->mcast_obj;
9890 /* first, clear all configured multicast MACs */
9891 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9893 BNX2X_ERR("Failed to clear multicast "
9894 "configuration: %d\n", rc);
9898 /* then, configure a new MACs list */
9899 if (netdev_mc_count(dev)) {
9900 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9902 BNX2X_ERR("Failed to create multicast MACs "
9907 /* Now add the new MACs */
9908 rc = bnx2x_config_mcast(bp, &rparam,
9909 BNX2X_MCAST_CMD_ADD);
9911 BNX2X_ERR("Failed to set a new multicast "
9912 "configuration: %d\n", rc);
9914 bnx2x_free_mcast_macs_list(&rparam);
9921 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9922 void bnx2x_set_rx_mode(struct net_device *dev)
9924 struct bnx2x *bp = netdev_priv(dev);
9925 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9927 if (bp->state != BNX2X_STATE_OPEN) {
9928 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9932 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
9934 if (dev->flags & IFF_PROMISC)
9935 rx_mode = BNX2X_RX_MODE_PROMISC;
9936 else if ((dev->flags & IFF_ALLMULTI) ||
9937 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
9939 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9941 /* some multicasts */
9942 if (bnx2x_set_mc_list(bp) < 0)
9943 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9945 if (bnx2x_set_uc_list(bp) < 0)
9946 rx_mode = BNX2X_RX_MODE_PROMISC;
9949 bp->rx_mode = rx_mode;
9951 /* Schedule the rx_mode command */
9952 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
9953 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9957 bnx2x_set_storm_rx_mode(bp);
9960 /* called with rtnl_lock */
9961 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9962 int devad, u16 addr)
9964 struct bnx2x *bp = netdev_priv(netdev);
9968 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9969 prtad, devad, addr);
9971 /* The HW expects different devad if CL22 is used */
9972 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9974 bnx2x_acquire_phy_lock(bp);
9975 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
9976 bnx2x_release_phy_lock(bp);
9977 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
9984 /* called with rtnl_lock */
9985 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9986 u16 addr, u16 value)
9988 struct bnx2x *bp = netdev_priv(netdev);
9991 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9992 " value 0x%x\n", prtad, devad, addr, value);
9994 /* The HW expects different devad if CL22 is used */
9995 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9997 bnx2x_acquire_phy_lock(bp);
9998 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
9999 bnx2x_release_phy_lock(bp);
10003 /* called with rtnl_lock */
10004 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10006 struct bnx2x *bp = netdev_priv(dev);
10007 struct mii_ioctl_data *mdio = if_mii(ifr);
10009 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10010 mdio->phy_id, mdio->reg_num, mdio->val_in);
10012 if (!netif_running(dev))
10015 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10018 #ifdef CONFIG_NET_POLL_CONTROLLER
10019 static void poll_bnx2x(struct net_device *dev)
10021 struct bnx2x *bp = netdev_priv(dev);
10023 disable_irq(bp->pdev->irq);
10024 bnx2x_interrupt(bp->pdev->irq, dev);
10025 enable_irq(bp->pdev->irq);
10029 static const struct net_device_ops bnx2x_netdev_ops = {
10030 .ndo_open = bnx2x_open,
10031 .ndo_stop = bnx2x_close,
10032 .ndo_start_xmit = bnx2x_start_xmit,
10033 .ndo_select_queue = bnx2x_select_queue,
10034 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10035 .ndo_set_mac_address = bnx2x_change_mac_addr,
10036 .ndo_validate_addr = eth_validate_addr,
10037 .ndo_do_ioctl = bnx2x_ioctl,
10038 .ndo_change_mtu = bnx2x_change_mtu,
10039 .ndo_fix_features = bnx2x_fix_features,
10040 .ndo_set_features = bnx2x_set_features,
10041 .ndo_tx_timeout = bnx2x_tx_timeout,
10042 #ifdef CONFIG_NET_POLL_CONTROLLER
10043 .ndo_poll_controller = poll_bnx2x,
10045 .ndo_setup_tc = bnx2x_setup_tc,
10047 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10048 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10052 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10054 struct device *dev = &bp->pdev->dev;
10056 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10057 bp->flags |= USING_DAC_FLAG;
10058 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10059 dev_err(dev, "dma_set_coherent_mask failed, "
10063 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10064 dev_err(dev, "System does not support DMA, aborting\n");
10071 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10072 struct net_device *dev,
10073 unsigned long board_type)
10078 SET_NETDEV_DEV(dev, &pdev->dev);
10079 bp = netdev_priv(dev);
10084 bp->pf_num = PCI_FUNC(pdev->devfn);
10086 rc = pci_enable_device(pdev);
10088 dev_err(&bp->pdev->dev,
10089 "Cannot enable PCI device, aborting\n");
10093 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10094 dev_err(&bp->pdev->dev,
10095 "Cannot find PCI device base address, aborting\n");
10097 goto err_out_disable;
10100 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10101 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10102 " base address, aborting\n");
10104 goto err_out_disable;
10107 if (atomic_read(&pdev->enable_cnt) == 1) {
10108 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10110 dev_err(&bp->pdev->dev,
10111 "Cannot obtain PCI resources, aborting\n");
10112 goto err_out_disable;
10115 pci_set_master(pdev);
10116 pci_save_state(pdev);
10119 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10120 if (bp->pm_cap == 0) {
10121 dev_err(&bp->pdev->dev,
10122 "Cannot find power management capability, aborting\n");
10124 goto err_out_release;
10127 if (!pci_is_pcie(pdev)) {
10128 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10130 goto err_out_release;
10133 rc = bnx2x_set_coherency_mask(bp);
10135 goto err_out_release;
10137 dev->mem_start = pci_resource_start(pdev, 0);
10138 dev->base_addr = dev->mem_start;
10139 dev->mem_end = pci_resource_end(pdev, 0);
10141 dev->irq = pdev->irq;
10143 bp->regview = pci_ioremap_bar(pdev, 0);
10144 if (!bp->regview) {
10145 dev_err(&bp->pdev->dev,
10146 "Cannot map register space, aborting\n");
10148 goto err_out_release;
10151 bnx2x_set_power_state(bp, PCI_D0);
10153 /* clean indirect addresses */
10154 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10155 PCICFG_VENDOR_ID_OFFSET);
10156 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10157 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10158 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10159 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
10162 * Enable internal target-read (in case we are probed after PF FLR).
10163 * Must be done prior to any BAR read access
10165 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10167 /* Reset the load counter */
10168 bnx2x_clear_load_cnt(bp);
10170 dev->watchdog_timeo = TX_TIMEOUT;
10172 dev->netdev_ops = &bnx2x_netdev_ops;
10173 bnx2x_set_ethtool_ops(dev);
10175 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10176 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10177 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10179 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10180 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10182 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10183 if (bp->flags & USING_DAC_FLAG)
10184 dev->features |= NETIF_F_HIGHDMA;
10186 /* Add Loopback capability to the device */
10187 dev->hw_features |= NETIF_F_LOOPBACK;
10190 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10193 /* get_port_hwinfo() will set prtad and mmds properly */
10194 bp->mdio.prtad = MDIO_PRTAD_NONE;
10196 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10197 bp->mdio.dev = dev;
10198 bp->mdio.mdio_read = bnx2x_mdio_read;
10199 bp->mdio.mdio_write = bnx2x_mdio_write;
10204 if (atomic_read(&pdev->enable_cnt) == 1)
10205 pci_release_regions(pdev);
10208 pci_disable_device(pdev);
10209 pci_set_drvdata(pdev, NULL);
10215 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10216 int *width, int *speed)
10218 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10220 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10222 /* return value of 1=2.5GHz 2=5GHz */
10223 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10226 static int bnx2x_check_firmware(struct bnx2x *bp)
10228 const struct firmware *firmware = bp->firmware;
10229 struct bnx2x_fw_file_hdr *fw_hdr;
10230 struct bnx2x_fw_file_section *sections;
10231 u32 offset, len, num_ops;
10236 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10239 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10240 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10242 /* Make sure none of the offsets and sizes make us read beyond
10243 * the end of the firmware data */
10244 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10245 offset = be32_to_cpu(sections[i].offset);
10246 len = be32_to_cpu(sections[i].len);
10247 if (offset + len > firmware->size) {
10248 dev_err(&bp->pdev->dev,
10249 "Section %d length is out of bounds\n", i);
10254 /* Likewise for the init_ops offsets */
10255 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10256 ops_offsets = (u16 *)(firmware->data + offset);
10257 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10259 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10260 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10261 dev_err(&bp->pdev->dev,
10262 "Section offset %d is out of bounds\n", i);
10267 /* Check FW version */
10268 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10269 fw_ver = firmware->data + offset;
10270 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10271 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10272 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10273 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10274 dev_err(&bp->pdev->dev,
10275 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10276 fw_ver[0], fw_ver[1], fw_ver[2],
10277 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10278 BCM_5710_FW_MINOR_VERSION,
10279 BCM_5710_FW_REVISION_VERSION,
10280 BCM_5710_FW_ENGINEERING_VERSION);
10287 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10289 const __be32 *source = (const __be32 *)_source;
10290 u32 *target = (u32 *)_target;
10293 for (i = 0; i < n/4; i++)
10294 target[i] = be32_to_cpu(source[i]);
10298 Ops array is stored in the following format:
10299 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10301 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10303 const __be32 *source = (const __be32 *)_source;
10304 struct raw_op *target = (struct raw_op *)_target;
10307 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10308 tmp = be32_to_cpu(source[j]);
10309 target[i].op = (tmp >> 24) & 0xff;
10310 target[i].offset = tmp & 0xffffff;
10311 target[i].raw_data = be32_to_cpu(source[j + 1]);
10316 * IRO array is stored in the following format:
10317 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10319 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10321 const __be32 *source = (const __be32 *)_source;
10322 struct iro *target = (struct iro *)_target;
10325 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10326 target[i].base = be32_to_cpu(source[j]);
10328 tmp = be32_to_cpu(source[j]);
10329 target[i].m1 = (tmp >> 16) & 0xffff;
10330 target[i].m2 = tmp & 0xffff;
10332 tmp = be32_to_cpu(source[j]);
10333 target[i].m3 = (tmp >> 16) & 0xffff;
10334 target[i].size = tmp & 0xffff;
10339 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10341 const __be16 *source = (const __be16 *)_source;
10342 u16 *target = (u16 *)_target;
10345 for (i = 0; i < n/2; i++)
10346 target[i] = be16_to_cpu(source[i]);
10349 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10351 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10352 bp->arr = kmalloc(len, GFP_KERNEL); \
10354 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10357 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10358 (u8 *)bp->arr, len); \
10361 int bnx2x_init_firmware(struct bnx2x *bp)
10363 const char *fw_file_name;
10364 struct bnx2x_fw_file_hdr *fw_hdr;
10367 if (CHIP_IS_E1(bp))
10368 fw_file_name = FW_FILE_NAME_E1;
10369 else if (CHIP_IS_E1H(bp))
10370 fw_file_name = FW_FILE_NAME_E1H;
10371 else if (!CHIP_IS_E1x(bp))
10372 fw_file_name = FW_FILE_NAME_E2;
10374 BNX2X_ERR("Unsupported chip revision\n");
10378 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10380 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10382 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10383 goto request_firmware_exit;
10386 rc = bnx2x_check_firmware(bp);
10388 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10389 goto request_firmware_exit;
10392 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10394 /* Initialize the pointers to the init arrays */
10396 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10399 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10402 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10405 /* STORMs firmware */
10406 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10407 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10408 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10409 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10410 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10411 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10412 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10413 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10414 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10415 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10416 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10417 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10418 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10419 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10420 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10421 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10423 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10428 kfree(bp->init_ops_offsets);
10429 init_offsets_alloc_err:
10430 kfree(bp->init_ops);
10431 init_ops_alloc_err:
10432 kfree(bp->init_data);
10433 request_firmware_exit:
10434 release_firmware(bp->firmware);
10439 static void bnx2x_release_firmware(struct bnx2x *bp)
10441 kfree(bp->init_ops_offsets);
10442 kfree(bp->init_ops);
10443 kfree(bp->init_data);
10444 release_firmware(bp->firmware);
10448 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10449 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10450 .init_hw_cmn = bnx2x_init_hw_common,
10451 .init_hw_port = bnx2x_init_hw_port,
10452 .init_hw_func = bnx2x_init_hw_func,
10454 .reset_hw_cmn = bnx2x_reset_common,
10455 .reset_hw_port = bnx2x_reset_port,
10456 .reset_hw_func = bnx2x_reset_func,
10458 .gunzip_init = bnx2x_gunzip_init,
10459 .gunzip_end = bnx2x_gunzip_end,
10461 .init_fw = bnx2x_init_firmware,
10462 .release_fw = bnx2x_release_firmware,
10465 void bnx2x__init_func_obj(struct bnx2x *bp)
10467 /* Prepare DMAE related driver resources */
10468 bnx2x_setup_dmae(bp);
10470 bnx2x_init_func_obj(bp, &bp->func_obj,
10471 bnx2x_sp(bp, func_rdata),
10472 bnx2x_sp_mapping(bp, func_rdata),
10473 &bnx2x_func_sp_drv);
10476 /* must be called after sriov-enable */
10477 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10479 int cid_count = BNX2X_L2_CID_COUNT(bp);
10482 cid_count += CNIC_CID_MAX;
10484 return roundup(cid_count, QM_CID_ROUND);
10488 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10493 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10498 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10501 * If MSI-X is not supported - return number of SBs needed to support
10502 * one fast path queue: one FP queue + SB for CNIC
10505 return 1 + CNIC_PRESENT;
10508 * The value in the PCI configuration space is the index of the last
10509 * entry, namely one less than the actual size of the table, which is
10510 * exactly what we want to return from this function: number of all SBs
10511 * without the default SB.
10513 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10514 return control & PCI_MSIX_FLAGS_QSIZE;
10517 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10518 const struct pci_device_id *ent)
10520 struct net_device *dev = NULL;
10522 int pcie_width, pcie_speed;
10523 int rc, max_non_def_sbs;
10524 int rx_count, tx_count, rss_count;
10526 * An estimated maximum supported CoS number according to the chip
10528 * We will try to roughly estimate the maximum number of CoSes this chip
10529 * may support in order to minimize the memory allocated for Tx
10530 * netdev_queue's. This number will be accurately calculated during the
10531 * initialization of bp->max_cos based on the chip versions AND chip
10532 * revision in the bnx2x_init_bp().
10534 u8 max_cos_est = 0;
10536 switch (ent->driver_data) {
10540 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10545 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10554 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10558 pr_err("Unknown board_type (%ld), aborting\n",
10563 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10566 * Do not allow the maximum SB count to grow above 16
10567 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10568 * We will use the FP_SB_MAX_E1x macro for this matter.
10570 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10572 WARN_ON(!max_non_def_sbs);
10574 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10575 rss_count = max_non_def_sbs - CNIC_PRESENT;
10577 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10578 rx_count = rss_count + FCOE_PRESENT;
10581 * Maximum number of netdev Tx queues:
10582 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10584 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10586 /* dev zeroed in init_etherdev */
10587 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10589 dev_err(&pdev->dev, "Cannot allocate net device\n");
10593 bp = netdev_priv(dev);
10595 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10596 tx_count, rx_count);
10598 bp->igu_sb_cnt = max_non_def_sbs;
10599 bp->msg_enable = debug;
10600 pci_set_drvdata(pdev, dev);
10602 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10608 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
10610 rc = bnx2x_init_bp(bp);
10612 goto init_one_exit;
10615 * Map doorbels here as we need the real value of bp->max_cos which
10616 * is initialized in bnx2x_init_bp().
10618 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10619 min_t(u64, BNX2X_DB_SIZE(bp),
10620 pci_resource_len(pdev, 2)));
10621 if (!bp->doorbells) {
10622 dev_err(&bp->pdev->dev,
10623 "Cannot map doorbell space, aborting\n");
10625 goto init_one_exit;
10628 /* calc qm_cid_count */
10629 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10632 /* disable FCOE L2 queue for E1x and E3*/
10633 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
10634 bp->flags |= NO_FCOE_FLAG;
10638 /* Configure interrupt mode: try to enable MSI-X/MSI if
10639 * needed, set bp->num_queues appropriately.
10641 bnx2x_set_int_mode(bp);
10643 /* Add all NAPI objects */
10644 bnx2x_add_all_napi(bp);
10646 rc = register_netdev(dev);
10648 dev_err(&pdev->dev, "Cannot register net device\n");
10649 goto init_one_exit;
10653 if (!NO_FCOE(bp)) {
10654 /* Add storage MAC address */
10656 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10661 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10663 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10664 " IRQ %d, ", board_info[ent->driver_data].name,
10665 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10667 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10668 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10669 "5GHz (Gen2)" : "2.5GHz",
10670 dev->base_addr, bp->pdev->irq);
10671 pr_cont("node addr %pM\n", dev->dev_addr);
10677 iounmap(bp->regview);
10680 iounmap(bp->doorbells);
10684 if (atomic_read(&pdev->enable_cnt) == 1)
10685 pci_release_regions(pdev);
10687 pci_disable_device(pdev);
10688 pci_set_drvdata(pdev, NULL);
10693 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10695 struct net_device *dev = pci_get_drvdata(pdev);
10699 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10702 bp = netdev_priv(dev);
10705 /* Delete storage MAC address */
10706 if (!NO_FCOE(bp)) {
10708 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10714 /* Delete app tlvs from dcbnl */
10715 bnx2x_dcbnl_update_applist(bp, true);
10718 unregister_netdev(dev);
10720 /* Delete all NAPI objects */
10721 bnx2x_del_all_napi(bp);
10723 /* Power on: we can't let PCI layer write to us while we are in D3 */
10724 bnx2x_set_power_state(bp, PCI_D0);
10726 /* Disable MSI/MSI-X */
10727 bnx2x_disable_msi(bp);
10730 bnx2x_set_power_state(bp, PCI_D3hot);
10732 /* Make sure RESET task is not scheduled before continuing */
10733 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10736 iounmap(bp->regview);
10739 iounmap(bp->doorbells);
10741 bnx2x_free_mem_bp(bp);
10745 if (atomic_read(&pdev->enable_cnt) == 1)
10746 pci_release_regions(pdev);
10748 pci_disable_device(pdev);
10749 pci_set_drvdata(pdev, NULL);
10752 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10756 bp->state = BNX2X_STATE_ERROR;
10758 bp->rx_mode = BNX2X_RX_MODE_NONE;
10761 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10764 bnx2x_tx_disable(bp);
10766 bnx2x_netif_stop(bp, 0);
10768 del_timer_sync(&bp->timer);
10770 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10773 bnx2x_free_irq(bp);
10775 /* Free SKBs, SGEs, TPA pool and driver internals */
10776 bnx2x_free_skbs(bp);
10778 for_each_rx_queue(bp, i)
10779 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10781 bnx2x_free_mem(bp);
10783 bp->state = BNX2X_STATE_CLOSED;
10785 netif_carrier_off(bp->dev);
10790 static void bnx2x_eeh_recover(struct bnx2x *bp)
10794 mutex_init(&bp->port.phy_mutex);
10796 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10797 bp->link_params.shmem_base = bp->common.shmem_base;
10798 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10800 if (!bp->common.shmem_base ||
10801 (bp->common.shmem_base < 0xA0000) ||
10802 (bp->common.shmem_base >= 0xC0000)) {
10803 BNX2X_DEV_INFO("MCP not active\n");
10804 bp->flags |= NO_MCP_FLAG;
10808 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10809 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10810 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10811 BNX2X_ERR("BAD MCP validity signature\n");
10813 if (!BP_NOMCP(bp)) {
10815 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10816 DRV_MSG_SEQ_NUMBER_MASK);
10817 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10822 * bnx2x_io_error_detected - called when PCI error is detected
10823 * @pdev: Pointer to PCI device
10824 * @state: The current pci connection state
10826 * This function is called after a PCI bus error affecting
10827 * this device has been detected.
10829 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10830 pci_channel_state_t state)
10832 struct net_device *dev = pci_get_drvdata(pdev);
10833 struct bnx2x *bp = netdev_priv(dev);
10837 netif_device_detach(dev);
10839 if (state == pci_channel_io_perm_failure) {
10841 return PCI_ERS_RESULT_DISCONNECT;
10844 if (netif_running(dev))
10845 bnx2x_eeh_nic_unload(bp);
10847 pci_disable_device(pdev);
10851 /* Request a slot reset */
10852 return PCI_ERS_RESULT_NEED_RESET;
10856 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10857 * @pdev: Pointer to PCI device
10859 * Restart the card from scratch, as if from a cold-boot.
10861 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10863 struct net_device *dev = pci_get_drvdata(pdev);
10864 struct bnx2x *bp = netdev_priv(dev);
10868 if (pci_enable_device(pdev)) {
10869 dev_err(&pdev->dev,
10870 "Cannot re-enable PCI device after reset\n");
10872 return PCI_ERS_RESULT_DISCONNECT;
10875 pci_set_master(pdev);
10876 pci_restore_state(pdev);
10878 if (netif_running(dev))
10879 bnx2x_set_power_state(bp, PCI_D0);
10883 return PCI_ERS_RESULT_RECOVERED;
10887 * bnx2x_io_resume - called when traffic can start flowing again
10888 * @pdev: Pointer to PCI device
10890 * This callback is called when the error recovery driver tells us that
10891 * its OK to resume normal operation.
10893 static void bnx2x_io_resume(struct pci_dev *pdev)
10895 struct net_device *dev = pci_get_drvdata(pdev);
10896 struct bnx2x *bp = netdev_priv(dev);
10898 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10899 netdev_err(bp->dev, "Handling parity error recovery. "
10900 "Try again later\n");
10906 bnx2x_eeh_recover(bp);
10908 if (netif_running(dev))
10909 bnx2x_nic_load(bp, LOAD_NORMAL);
10911 netif_device_attach(dev);
10916 static struct pci_error_handlers bnx2x_err_handler = {
10917 .error_detected = bnx2x_io_error_detected,
10918 .slot_reset = bnx2x_io_slot_reset,
10919 .resume = bnx2x_io_resume,
10922 static struct pci_driver bnx2x_pci_driver = {
10923 .name = DRV_MODULE_NAME,
10924 .id_table = bnx2x_pci_tbl,
10925 .probe = bnx2x_init_one,
10926 .remove = __devexit_p(bnx2x_remove_one),
10927 .suspend = bnx2x_suspend,
10928 .resume = bnx2x_resume,
10929 .err_handler = &bnx2x_err_handler,
10932 static int __init bnx2x_init(void)
10936 pr_info("%s", version);
10938 bnx2x_wq = create_singlethread_workqueue("bnx2x");
10939 if (bnx2x_wq == NULL) {
10940 pr_err("Cannot create workqueue\n");
10944 ret = pci_register_driver(&bnx2x_pci_driver);
10946 pr_err("Cannot register driver\n");
10947 destroy_workqueue(bnx2x_wq);
10952 static void __exit bnx2x_cleanup(void)
10954 pci_unregister_driver(&bnx2x_pci_driver);
10956 destroy_workqueue(bnx2x_wq);
10959 void bnx2x_notify_link_changed(struct bnx2x *bp)
10961 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
10964 module_init(bnx2x_init);
10965 module_exit(bnx2x_cleanup);
10969 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
10971 * @bp: driver handle
10972 * @set: set or clear the CAM entry
10974 * This function will wait until the ramdord completion returns.
10975 * Return 0 if success, -ENODEV if ramrod doesn't return.
10977 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
10979 unsigned long ramrod_flags = 0;
10981 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
10982 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
10983 &bp->iscsi_l2_mac_obj, true,
10984 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
10987 /* count denotes the number of new completions we have seen */
10988 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
10990 struct eth_spe *spe;
10992 #ifdef BNX2X_STOP_ON_ERROR
10993 if (unlikely(bp->panic))
10997 spin_lock_bh(&bp->spq_lock);
10998 BUG_ON(bp->cnic_spq_pending < count);
10999 bp->cnic_spq_pending -= count;
11002 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11003 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11004 & SPE_HDR_CONN_TYPE) >>
11005 SPE_HDR_CONN_TYPE_SHIFT;
11006 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11007 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11009 /* Set validation for iSCSI L2 client before sending SETUP
11012 if (type == ETH_CONNECTION_TYPE) {
11013 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11014 bnx2x_set_ctx_validation(bp, &bp->context.
11015 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11016 BNX2X_ISCSI_ETH_CID);
11020 * There may be not more than 8 L2, not more than 8 L5 SPEs
11021 * and in the air. We also check that number of outstanding
11022 * COMMON ramrods is not more than the EQ and SPQ can
11025 if (type == ETH_CONNECTION_TYPE) {
11026 if (!atomic_read(&bp->cq_spq_left))
11029 atomic_dec(&bp->cq_spq_left);
11030 } else if (type == NONE_CONNECTION_TYPE) {
11031 if (!atomic_read(&bp->eq_spq_left))
11034 atomic_dec(&bp->eq_spq_left);
11035 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11036 (type == FCOE_CONNECTION_TYPE)) {
11037 if (bp->cnic_spq_pending >=
11038 bp->cnic_eth_dev.max_kwqe_pending)
11041 bp->cnic_spq_pending++;
11043 BNX2X_ERR("Unknown SPE type: %d\n", type);
11048 spe = bnx2x_sp_get_next(bp);
11049 *spe = *bp->cnic_kwq_cons;
11051 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11052 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11054 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11055 bp->cnic_kwq_cons = bp->cnic_kwq;
11057 bp->cnic_kwq_cons++;
11059 bnx2x_sp_prod_update(bp);
11060 spin_unlock_bh(&bp->spq_lock);
11063 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11064 struct kwqe_16 *kwqes[], u32 count)
11066 struct bnx2x *bp = netdev_priv(dev);
11069 #ifdef BNX2X_STOP_ON_ERROR
11070 if (unlikely(bp->panic))
11074 spin_lock_bh(&bp->spq_lock);
11076 for (i = 0; i < count; i++) {
11077 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11079 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11082 *bp->cnic_kwq_prod = *spe;
11084 bp->cnic_kwq_pending++;
11086 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11087 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11088 spe->data.update_data_addr.hi,
11089 spe->data.update_data_addr.lo,
11090 bp->cnic_kwq_pending);
11092 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11093 bp->cnic_kwq_prod = bp->cnic_kwq;
11095 bp->cnic_kwq_prod++;
11098 spin_unlock_bh(&bp->spq_lock);
11100 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11101 bnx2x_cnic_sp_post(bp, 0);
11106 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11108 struct cnic_ops *c_ops;
11111 mutex_lock(&bp->cnic_mutex);
11112 c_ops = rcu_dereference_protected(bp->cnic_ops,
11113 lockdep_is_held(&bp->cnic_mutex));
11115 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11116 mutex_unlock(&bp->cnic_mutex);
11121 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11123 struct cnic_ops *c_ops;
11127 c_ops = rcu_dereference(bp->cnic_ops);
11129 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11136 * for commands that have no data
11138 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11140 struct cnic_ctl_info ctl = {0};
11144 return bnx2x_cnic_ctl_send(bp, &ctl);
11147 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11149 struct cnic_ctl_info ctl = {0};
11151 /* first we tell CNIC and only then we count this as a completion */
11152 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11153 ctl.data.comp.cid = cid;
11154 ctl.data.comp.error = err;
11156 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11157 bnx2x_cnic_sp_post(bp, 0);
11161 /* Called with netif_addr_lock_bh() taken.
11162 * Sets an rx_mode config for an iSCSI ETH client.
11164 * Completion should be checked outside.
11166 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11168 unsigned long accept_flags = 0, ramrod_flags = 0;
11169 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11170 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11173 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11174 * because it's the only way for UIO Queue to accept
11175 * multicasts (in non-promiscuous mode only one Queue per
11176 * function will receive multicast packets (leading in our
11179 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11180 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11181 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11182 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11184 /* Clear STOP_PENDING bit if START is requested */
11185 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11187 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11189 /* Clear START_PENDING bit if STOP is requested */
11190 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11192 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11193 set_bit(sched_state, &bp->sp_state);
11195 __set_bit(RAMROD_RX, &ramrod_flags);
11196 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11202 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11204 struct bnx2x *bp = netdev_priv(dev);
11207 switch (ctl->cmd) {
11208 case DRV_CTL_CTXTBL_WR_CMD: {
11209 u32 index = ctl->data.io.offset;
11210 dma_addr_t addr = ctl->data.io.dma_addr;
11212 bnx2x_ilt_wr(bp, index, addr);
11216 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11217 int count = ctl->data.credit.credit_count;
11219 bnx2x_cnic_sp_post(bp, count);
11223 /* rtnl_lock is held. */
11224 case DRV_CTL_START_L2_CMD: {
11225 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11226 unsigned long sp_bits = 0;
11228 /* Configure the iSCSI classification object */
11229 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11230 cp->iscsi_l2_client_id,
11231 cp->iscsi_l2_cid, BP_FUNC(bp),
11232 bnx2x_sp(bp, mac_rdata),
11233 bnx2x_sp_mapping(bp, mac_rdata),
11234 BNX2X_FILTER_MAC_PENDING,
11235 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11238 /* Set iSCSI MAC address */
11239 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11246 /* Start accepting on iSCSI L2 ring */
11248 netif_addr_lock_bh(dev);
11249 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11250 netif_addr_unlock_bh(dev);
11252 /* bits to wait on */
11253 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11254 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11256 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11257 BNX2X_ERR("rx_mode completion timed out!\n");
11262 /* rtnl_lock is held. */
11263 case DRV_CTL_STOP_L2_CMD: {
11264 unsigned long sp_bits = 0;
11266 /* Stop accepting on iSCSI L2 ring */
11267 netif_addr_lock_bh(dev);
11268 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11269 netif_addr_unlock_bh(dev);
11271 /* bits to wait on */
11272 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11273 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11275 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11276 BNX2X_ERR("rx_mode completion timed out!\n");
11281 /* Unset iSCSI L2 MAC */
11282 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11283 BNX2X_ISCSI_ETH_MAC, true);
11286 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11287 int count = ctl->data.credit.credit_count;
11289 smp_mb__before_atomic_inc();
11290 atomic_add(count, &bp->cq_spq_left);
11291 smp_mb__after_atomic_inc();
11296 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11303 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11305 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11307 if (bp->flags & USING_MSIX_FLAG) {
11308 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11309 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11310 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11312 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11313 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11315 if (!CHIP_IS_E1x(bp))
11316 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11318 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11320 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11321 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11322 cp->irq_arr[1].status_blk = bp->def_status_blk;
11323 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11324 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11329 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11332 struct bnx2x *bp = netdev_priv(dev);
11333 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11338 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11342 bp->cnic_kwq_cons = bp->cnic_kwq;
11343 bp->cnic_kwq_prod = bp->cnic_kwq;
11344 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11346 bp->cnic_spq_pending = 0;
11347 bp->cnic_kwq_pending = 0;
11349 bp->cnic_data = data;
11352 cp->drv_state |= CNIC_DRV_STATE_REGD;
11353 cp->iro_arr = bp->iro_arr;
11355 bnx2x_setup_cnic_irq_info(bp);
11357 rcu_assign_pointer(bp->cnic_ops, ops);
11362 static int bnx2x_unregister_cnic(struct net_device *dev)
11364 struct bnx2x *bp = netdev_priv(dev);
11365 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11367 mutex_lock(&bp->cnic_mutex);
11369 rcu_assign_pointer(bp->cnic_ops, NULL);
11370 mutex_unlock(&bp->cnic_mutex);
11372 kfree(bp->cnic_kwq);
11373 bp->cnic_kwq = NULL;
11378 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11380 struct bnx2x *bp = netdev_priv(dev);
11381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11383 /* If both iSCSI and FCoE are disabled - return NULL in
11384 * order to indicate CNIC that it should not try to work
11385 * with this device.
11387 if (NO_ISCSI(bp) && NO_FCOE(bp))
11390 cp->drv_owner = THIS_MODULE;
11391 cp->chip_id = CHIP_ID(bp);
11392 cp->pdev = bp->pdev;
11393 cp->io_base = bp->regview;
11394 cp->io_base2 = bp->doorbells;
11395 cp->max_kwqe_pending = 8;
11396 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11397 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11398 bnx2x_cid_ilt_lines(bp);
11399 cp->ctx_tbl_len = CNIC_ILT_LINES;
11400 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11401 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11402 cp->drv_ctl = bnx2x_drv_ctl;
11403 cp->drv_register_cnic = bnx2x_register_cnic;
11404 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11405 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11406 cp->iscsi_l2_client_id =
11407 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11408 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11410 if (NO_ISCSI_OOO(bp))
11411 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11414 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11417 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11419 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11420 "starting cid %d\n",
11422 cp->ctx_tbl_offset,
11427 EXPORT_SYMBOL(bnx2x_cnic_probe);
11429 #endif /* BCM_CNIC */