1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
52 #include <linux/stringify.h>
53 #include <linux/vmalloc.h>
56 #include "bnx2x_init.h"
57 #include "bnx2x_init_ops.h"
58 #include "bnx2x_cmn.h"
59 #include "bnx2x_dcb.h"
62 #include <linux/firmware.h>
63 #include "bnx2x_fw_file_hdr.h"
65 #define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
70 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
72 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
74 /* Time in jiffies before concluding the transmitter is hung */
75 #define TX_TIMEOUT (5*HZ)
77 static char version[] __devinitdata =
78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
81 MODULE_AUTHOR("Eliezer Tamir");
82 MODULE_DESCRIPTION("Broadcom NetXtreme II "
83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
86 MODULE_LICENSE("GPL");
87 MODULE_VERSION(DRV_MODULE_VERSION);
88 MODULE_FIRMWARE(FW_FILE_NAME_E1);
89 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
90 MODULE_FIRMWARE(FW_FILE_NAME_E2);
92 static int multi_mode = 1;
93 module_param(multi_mode, int, 0);
94 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
98 module_param(num_queues, int, 0);
99 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
102 static int disable_tpa;
103 module_param(disable_tpa, int, 0);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 #define INT_MODE_INTx 1
107 #define INT_MODE_MSI 2
109 module_param(int_mode, int, 0);
110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
113 static int dropless_fc;
114 module_param(dropless_fc, int, 0);
115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118 module_param(poll, int, 0);
119 MODULE_PARM_DESC(poll, " Use polling (for debug)");
121 static int mrrs = -1;
122 module_param(mrrs, int, 0);
123 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
126 module_param(debug, int, 0);
127 MODULE_PARM_DESC(debug, " Default debug msglevel");
131 struct workqueue_struct *bnx2x_wq;
133 enum bnx2x_board_type {
147 /* indexed by board_type, above */
150 } board_info[] __devinitdata = {
151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
165 #ifndef PCI_DEVICE_ID_NX2_57710
166 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
168 #ifndef PCI_DEVICE_ID_NX2_57711
169 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
171 #ifndef PCI_DEVICE_ID_NX2_57711E
172 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
174 #ifndef PCI_DEVICE_ID_NX2_57712
175 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
177 #ifndef PCI_DEVICE_ID_NX2_57712_MF
178 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
180 #ifndef PCI_DEVICE_ID_NX2_57800
181 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
183 #ifndef PCI_DEVICE_ID_NX2_57800_MF
184 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
186 #ifndef PCI_DEVICE_ID_NX2_57810
187 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
189 #ifndef PCI_DEVICE_ID_NX2_57810_MF
190 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
192 #ifndef PCI_DEVICE_ID_NX2_57840
193 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
195 #ifndef PCI_DEVICE_ID_NX2_57840_MF
196 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
198 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
213 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
215 /****************************************************************************
216 * General service functions
217 ****************************************************************************/
219 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
226 static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
232 __storm_memset_dma_mapping(bp, addr, mapping);
235 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
265 size_t size = sizeof(struct event_ring_data);
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
272 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
280 * locking is done by mcp
282 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
290 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
302 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306 #define DMAE_DP_DST_NONE "dst_addr [none]"
308 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
372 /* copy command into DMAE command memory and set DMAE command go */
373 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
388 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
394 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396 return opcode & ~DMAE_CMD_SRC_RESET;
399 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
424 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
428 memset(dmae, 0, sizeof(struct dmae_command));
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
440 /* issue a dmae command over the init-channel and wailt for completion */
441 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
457 spin_lock_bh(&bp->dmae_lock);
459 /* reset completion */
462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
465 /* wait for completion */
467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
471 BNX2X_ERR("DMAE timeout!\n");
478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
488 spin_unlock_bh(&bp->dmae_lock);
492 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
495 struct dmae_command dmae;
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
522 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
524 struct dmae_command dmae;
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
540 /* fill in addresses and len */
541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
553 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
559 while (len > dmae_wr_max) {
560 bnx2x_write_dmae(bp, phys_addr + offset,
561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
569 /* used only for slowpath so not inlined */
570 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
580 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
584 REG_RD_DMAE(bp, reg, wb_data, 2);
586 return HILO_U64(wb_data[0], wb_data[1]);
590 static int bnx2x_mc_assert(struct bnx2x *bp)
594 u32 row0, row1, row2, row3;
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
711 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
717 u32 trace_shmem_base;
719 BNX2X_ERR("NO MCP - can not dump\n");
722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
736 mark = REG_RD(bp, addr);
737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
743 for (word = 0; word < 8; word++)
744 data[word] = htonl(REG_RD(bp, offset + 4*word));
746 pr_cont("%s", (char *)data);
748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
749 for (word = 0; word < 8; word++)
750 data[word] = htonl(REG_RD(bp, offset + 4*word));
752 pr_cont("%s", (char *)data);
754 printk("%s" "end of fw dump\n", lvl);
757 static inline void bnx2x_fw_dump(struct bnx2x *bp)
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
762 void bnx2x_panic_dump(struct bnx2x *bp)
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768 #ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
776 BNX2X_ERR("begin crash dump -----------------\n");
780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
801 "pf_id(0x%x) vnic_id(0x%x) "
802 "vf_id(0x%x) vf_valid (0x%x) "
804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
809 sp_sb_data.p_func.vf_valid,
813 for_each_eth_queue(bp, i) {
814 struct bnx2x_fastpath *fp = &bp->fp[i];
816 struct hc_status_block_data_e2 sb_data_e2;
817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
822 struct hc_index_data *hc_index_p =
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
828 struct bnx2x_fp_txdata txdata;
831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
832 " rx_comp_prod(0x%x)"
833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
834 i, fp->rx_bd_prod, fp->rx_bd_cons,
836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
838 " fp_hc_idx(0x%x)\n",
839 fp->rx_sge_prod, fp->last_max_sge,
840 le16_to_cpu(fp->fp_hc_idx));
843 for_each_cos_in_tx_queue(fp, cos)
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
852 le16_to_cpu(*txdata.tx_cons_sb));
855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
879 data_size /= sizeof(u32);
880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
929 hc_index_p[j].timeout);
933 #ifdef BNX2X_STOP_ON_ERROR
936 for_each_rx_queue(bp, i) {
937 struct bnx2x_fastpath *fp = &bp->fp[i];
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
941 for (j = start; j != end; j = RX_BD(j + 1)) {
942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
951 for (j = start; j != end; j = RX_SGE(j + 1)) {
952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
970 for_each_tx_queue(bp, i) {
971 struct bnx2x_fastpath *fp = &bp->fp[i];
972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
994 i, cos, j, tx_bd[0], tx_bd[1],
1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
1006 * FLR Support for E2
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1011 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012 #define FLR_WAIT_INTERAVAL 50 /* usec */
1013 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1015 struct pbf_pN_buf_regs {
1022 struct pbf_pN_cmd_regs {
1028 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1063 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1095 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1098 u32 cur_cnt = poll_count;
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1107 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1118 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1127 return FLR_POLL_CNT;
1130 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1195 #define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1198 #define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1201 #define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1205 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1208 struct sdm_op_gen op_gen = {0};
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1237 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1242 pos = pci_pcie_cap(dev);
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1250 /* PF FLR specific routines
1252 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1299 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1329 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1353 /* Wait 100ms (not adjusted according to platform) */
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1361 bnx2x_hw_enable_status(bp);
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1372 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1374 int port = BP_PORT(bp);
1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1400 REG_WR(bp, addr, val);
1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1412 REG_WR(bp, addr, val);
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1419 if (!CHIP_IS_E1(bp)) {
1420 /* init leading/trailing edge */
1422 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1424 /* enable nig and gpio3 attention */
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1433 /* Make sure that interrupts are indeed enabled from here on */
1437 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1472 /* init leading/trailing edge */
1474 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1476 /* enable nig and gpio3 attention */
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1484 /* Make sure that interrupts are indeed enabled from here on */
1488 void bnx2x_int_enable(struct bnx2x *bp)
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1493 bnx2x_igu_int_enable(bp);
1496 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1498 int port = BP_PORT(bp);
1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1526 /* flush all outstanding writes */
1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1534 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1544 /* flush all outstanding writes */
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1552 void bnx2x_int_disable(struct bnx2x *bp)
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1557 bnx2x_igu_int_disable(bp);
1560 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
1569 /* make sure all ISRs are done */
1571 synchronize_irq(bp->msix_table[0].vector);
1576 for_each_eth_queue(bp, i)
1577 synchronize_irq(bp->msix_table[offset++].vector);
1579 synchronize_irq(bp->pdev->irq);
1581 /* make sure sp_task is not running */
1582 cancel_delayed_work(&bp->sp_task);
1583 cancel_delayed_work(&bp->period_task);
1584 flush_workqueue(bnx2x_wq);
1590 * General service functions
1593 /* Return true if succeeded to acquire the lock */
1594 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1630 * @bp: driver handle
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1635 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1646 * @bp: driver handle
1648 * Tries to aquire a leader lock for cuurent engine.
1650 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1656 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1659 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1669 fp->index, cid, command, bp->state,
1670 rr_cqe->ramrod_cqe.ramrod_type);
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1674 DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1677 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1678 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1679 drv_cmd = BNX2X_Q_CMD_SETUP;
1682 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1683 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1684 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1687 case (RAMROD_CMD_ID_ETH_HALT):
1688 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1689 drv_cmd = BNX2X_Q_CMD_HALT;
1692 case (RAMROD_CMD_ID_ETH_TERMINATE):
1693 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1694 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1697 case (RAMROD_CMD_ID_ETH_EMPTY):
1698 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
1699 drv_cmd = BNX2X_Q_CMD_EMPTY;
1703 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1704 command, fp->index);
1708 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1709 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1710 /* q_obj->complete_cmd() failure means that this was
1711 * an unexpected completion.
1713 * In this case we don't want to increase the bp->spq_left
1714 * because apparently we haven't sent this command the first
1717 #ifdef BNX2X_STOP_ON_ERROR
1723 smp_mb__before_atomic_inc();
1724 atomic_inc(&bp->cq_spq_left);
1725 /* push the change in bp->spq_left and towards the memory */
1726 smp_mb__after_atomic_inc();
1731 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1732 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1734 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1736 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1740 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1742 struct bnx2x *bp = netdev_priv(dev_instance);
1743 u16 status = bnx2x_ack_int(bp);
1748 /* Return here if interrupt is shared and it's not for us */
1749 if (unlikely(status == 0)) {
1750 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1753 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1755 #ifdef BNX2X_STOP_ON_ERROR
1756 if (unlikely(bp->panic))
1760 for_each_eth_queue(bp, i) {
1761 struct bnx2x_fastpath *fp = &bp->fp[i];
1763 mask = 0x2 << (fp->index + CNIC_PRESENT);
1764 if (status & mask) {
1765 /* Handle Rx or Tx according to SB id */
1766 prefetch(fp->rx_cons_sb);
1767 for_each_cos_in_tx_queue(fp, cos)
1768 prefetch(fp->txdata[cos].tx_cons_sb);
1769 prefetch(&fp->sb_running_index[SM_RX_ID]);
1770 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1777 if (status & (mask | 0x1)) {
1778 struct cnic_ops *c_ops = NULL;
1780 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1782 c_ops = rcu_dereference(bp->cnic_ops);
1784 c_ops->cnic_handler(bp->cnic_data, NULL);
1792 if (unlikely(status & 0x1)) {
1793 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1800 if (unlikely(status))
1801 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1810 * General service functions
1813 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1816 u32 resource_bit = (1 << resource);
1817 int func = BP_FUNC(bp);
1818 u32 hw_lock_control_reg;
1821 /* Validating that the resource is within range */
1822 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1824 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1825 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1830 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1832 hw_lock_control_reg =
1833 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1836 /* Validating that the resource is not already taken */
1837 lock_status = REG_RD(bp, hw_lock_control_reg);
1838 if (lock_status & resource_bit) {
1839 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1840 lock_status, resource_bit);
1844 /* Try for 5 second every 5ms */
1845 for (cnt = 0; cnt < 1000; cnt++) {
1846 /* Try to acquire the lock */
1847 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1848 lock_status = REG_RD(bp, hw_lock_control_reg);
1849 if (lock_status & resource_bit)
1854 DP(NETIF_MSG_HW, "Timeout\n");
1858 int bnx2x_release_leader_lock(struct bnx2x *bp)
1860 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1863 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1866 u32 resource_bit = (1 << resource);
1867 int func = BP_FUNC(bp);
1868 u32 hw_lock_control_reg;
1870 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1872 /* Validating that the resource is within range */
1873 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1875 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1876 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1881 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1883 hw_lock_control_reg =
1884 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1887 /* Validating that the resource is currently taken */
1888 lock_status = REG_RD(bp, hw_lock_control_reg);
1889 if (!(lock_status & resource_bit)) {
1890 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1891 lock_status, resource_bit);
1895 REG_WR(bp, hw_lock_control_reg, resource_bit);
1900 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1902 /* The GPIO should be swapped if swap register is set and active */
1903 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1904 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1905 int gpio_shift = gpio_num +
1906 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1907 u32 gpio_mask = (1 << gpio_shift);
1911 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1912 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1916 /* read GPIO value */
1917 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1919 /* get the requested pin value */
1920 if ((gpio_reg & gpio_mask) == gpio_mask)
1925 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1930 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1932 /* The GPIO should be swapped if swap register is set and active */
1933 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1934 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1935 int gpio_shift = gpio_num +
1936 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1937 u32 gpio_mask = (1 << gpio_shift);
1940 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1941 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1945 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1946 /* read GPIO and mask except the float bits */
1947 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1950 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1951 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1952 gpio_num, gpio_shift);
1953 /* clear FLOAT and set CLR */
1954 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1955 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1958 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1959 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1960 gpio_num, gpio_shift);
1961 /* clear FLOAT and set SET */
1962 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1963 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1966 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1967 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1968 gpio_num, gpio_shift);
1970 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1977 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1978 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1983 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1988 /* Any port swapping should be handled by caller. */
1990 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1991 /* read GPIO and mask except the float bits */
1992 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1993 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1994 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1995 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1998 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1999 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2001 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2004 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2005 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2007 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2010 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2011 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2013 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2017 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2023 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2025 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2030 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2032 /* The GPIO should be swapped if swap register is set and active */
2033 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035 int gpio_shift = gpio_num +
2036 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037 u32 gpio_mask = (1 << gpio_shift);
2040 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2047 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2050 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2051 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2052 "output low\n", gpio_num, gpio_shift);
2053 /* clear SET and set CLR */
2054 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2055 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2058 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2059 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2060 "output high\n", gpio_num, gpio_shift);
2061 /* clear CLR and set SET */
2062 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2063 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2070 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2071 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2076 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2078 u32 spio_mask = (1 << spio_num);
2081 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2082 (spio_num > MISC_REGISTERS_SPIO_7)) {
2083 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2087 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2088 /* read SPIO and mask except the float bits */
2089 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2092 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2093 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2094 /* clear FLOAT and set CLR */
2095 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2096 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2099 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2100 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2101 /* clear FLOAT and set SET */
2102 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2103 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2106 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2107 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2109 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2116 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2117 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2122 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2124 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2125 switch (bp->link_vars.ieee_fc &
2126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2128 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2132 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2133 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2137 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2138 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2142 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2148 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2150 if (!BP_NOMCP(bp)) {
2152 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2153 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2154 /* Initialize link parameters structure variables */
2155 /* It is recommended to turn off RX FC for jumbo frames
2156 for better performance */
2157 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
2158 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2160 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2162 bnx2x_acquire_phy_lock(bp);
2164 if (load_mode == LOAD_DIAG) {
2165 bp->link_params.loopback_mode = LOOPBACK_XGXS;
2166 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
2169 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2171 bnx2x_release_phy_lock(bp);
2173 bnx2x_calc_fc_adv(bp);
2175 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2176 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2177 bnx2x_link_report(bp);
2179 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2180 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2183 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2187 void bnx2x_link_set(struct bnx2x *bp)
2189 if (!BP_NOMCP(bp)) {
2190 bnx2x_acquire_phy_lock(bp);
2191 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2192 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2193 bnx2x_release_phy_lock(bp);
2195 bnx2x_calc_fc_adv(bp);
2197 BNX2X_ERR("Bootcode is missing - can not set link\n");
2200 static void bnx2x__link_reset(struct bnx2x *bp)
2202 if (!BP_NOMCP(bp)) {
2203 bnx2x_acquire_phy_lock(bp);
2204 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2205 bnx2x_release_phy_lock(bp);
2207 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2210 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2214 if (!BP_NOMCP(bp)) {
2215 bnx2x_acquire_phy_lock(bp);
2216 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2218 bnx2x_release_phy_lock(bp);
2220 BNX2X_ERR("Bootcode is missing - can not test link\n");
2225 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2227 u32 r_param = bp->link_vars.line_speed / 8;
2228 u32 fair_periodic_timeout_usec;
2231 memset(&(bp->cmng.rs_vars), 0,
2232 sizeof(struct rate_shaping_vars_per_port));
2233 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2235 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2236 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2238 /* this is the threshold below which no timer arming will occur
2239 1.25 coefficient is for the threshold to be a little bigger
2240 than the real time, to compensate for timer in-accuracy */
2241 bp->cmng.rs_vars.rs_threshold =
2242 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2244 /* resolution of fairness timer */
2245 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2246 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2247 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2249 /* this is the threshold below which we won't arm the timer anymore */
2250 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2252 /* we multiply by 1e3/8 to get bytes/msec.
2253 We don't want the credits to pass a credit
2254 of the t_fair*FAIR_MEM (algorithm resolution) */
2255 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2256 /* since each tick is 4 usec */
2257 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2260 /* Calculates the sum of vn_min_rates.
2261 It's needed for further normalizing of the min_rates.
2263 sum of vn_min_rates.
2265 0 - if all the min_rates are 0.
2266 In the later case fainess algorithm should be deactivated.
2267 If not all min_rates are zero then those that are zeroes will be set to 1.
2269 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2274 bp->vn_weight_sum = 0;
2275 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2276 u32 vn_cfg = bp->mf_config[vn];
2277 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2278 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2280 /* Skip hidden vns */
2281 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2284 /* If min rate is zero - set it to 1 */
2286 vn_min_rate = DEF_MIN_RATE;
2290 bp->vn_weight_sum += vn_min_rate;
2293 /* if ETS or all min rates are zeros - disable fairness */
2294 if (BNX2X_IS_ETS_ENABLED(bp)) {
2295 bp->cmng.flags.cmng_enables &=
2296 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2297 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2298 } else if (all_zero) {
2299 bp->cmng.flags.cmng_enables &=
2300 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2301 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2302 " fairness will be disabled\n");
2304 bp->cmng.flags.cmng_enables |=
2305 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2308 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2310 struct rate_shaping_vars_per_vn m_rs_vn;
2311 struct fairness_vars_per_vn m_fair_vn;
2312 u32 vn_cfg = bp->mf_config[vn];
2313 int func = 2*vn + BP_PORT(bp);
2314 u16 vn_min_rate, vn_max_rate;
2317 /* If function is hidden - set min and max to zeroes */
2318 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2323 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2325 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2326 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2327 /* If fairness is enabled (not all min rates are zeroes) and
2328 if current min rate is zero - set it to 1.
2329 This is a requirement of the algorithm. */
2330 if (bp->vn_weight_sum && (vn_min_rate == 0))
2331 vn_min_rate = DEF_MIN_RATE;
2334 /* maxCfg in percents of linkspeed */
2335 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2337 /* maxCfg is absolute in 100Mb units */
2338 vn_max_rate = maxCfg * 100;
2342 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2343 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2345 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2346 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2348 /* global vn counter - maximal Mbps for this vn */
2349 m_rs_vn.vn_counter.rate = vn_max_rate;
2351 /* quota - number of bytes transmitted in this period */
2352 m_rs_vn.vn_counter.quota =
2353 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2355 if (bp->vn_weight_sum) {
2356 /* credit for each period of the fairness algorithm:
2357 number of bytes in T_FAIR (the vn share the port rate).
2358 vn_weight_sum should not be larger than 10000, thus
2359 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2361 m_fair_vn.vn_credit_delta =
2362 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2363 (8 * bp->vn_weight_sum))),
2364 (bp->cmng.fair_vars.fair_threshold +
2366 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2367 m_fair_vn.vn_credit_delta);
2370 /* Store it to internal memory */
2371 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2372 REG_WR(bp, BAR_XSTRORM_INTMEM +
2373 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2374 ((u32 *)(&m_rs_vn))[i]);
2376 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2377 REG_WR(bp, BAR_XSTRORM_INTMEM +
2378 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2379 ((u32 *)(&m_fair_vn))[i]);
2382 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2384 if (CHIP_REV_IS_SLOW(bp))
2385 return CMNG_FNS_NONE;
2387 return CMNG_FNS_MINMAX;
2389 return CMNG_FNS_NONE;
2392 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2394 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2397 return; /* what should be the default bvalue in this case */
2399 /* For 2 port configuration the absolute function number formula
2401 * abs_func = 2 * vn + BP_PORT + BP_PATH
2403 * and there are 4 functions per port
2405 * For 4 port configuration it is
2406 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2408 * and there are 2 functions per port
2410 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2411 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2413 if (func >= E1H_FUNC_MAX)
2417 MF_CFG_RD(bp, func_mf_config[func].config);
2421 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2424 if (cmng_type == CMNG_FNS_MINMAX) {
2427 /* clear cmng_enables */
2428 bp->cmng.flags.cmng_enables = 0;
2430 /* read mf conf from shmem */
2432 bnx2x_read_mf_cfg(bp);
2434 /* Init rate shaping and fairness contexts */
2435 bnx2x_init_port_minmax(bp);
2437 /* vn_weight_sum and enable fairness if not 0 */
2438 bnx2x_calc_vn_weight_sum(bp);
2440 /* calculate and set min-max rate for each vn */
2442 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2443 bnx2x_init_vn_minmax(bp, vn);
2445 /* always enable rate shaping and fairness */
2446 bp->cmng.flags.cmng_enables |=
2447 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2448 if (!bp->vn_weight_sum)
2449 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2450 " fairness will be disabled\n");
2454 /* rate shaping and fairness are disabled */
2456 "rate shaping and fairness are disabled\n");
2459 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2461 int port = BP_PORT(bp);
2465 /* Set the attention towards other drivers on the same port */
2466 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2467 if (vn == BP_E1HVN(bp))
2470 func = ((vn << 1) | port);
2471 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2472 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2476 /* This function is called upon link interrupt */
2477 static void bnx2x_link_attn(struct bnx2x *bp)
2479 /* Make sure that we are synced with the current statistics */
2480 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2482 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2484 if (bp->link_vars.link_up) {
2486 /* dropless flow control */
2487 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2488 int port = BP_PORT(bp);
2489 u32 pause_enabled = 0;
2491 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2494 REG_WR(bp, BAR_USTRORM_INTMEM +
2495 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2499 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2500 struct host_port_stats *pstats;
2502 pstats = bnx2x_sp(bp, port_stats);
2503 /* reset old mac stats */
2504 memset(&(pstats->mac_stx[0]), 0,
2505 sizeof(struct mac_stx));
2507 if (bp->state == BNX2X_STATE_OPEN)
2508 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2511 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2512 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2514 if (cmng_fns != CMNG_FNS_NONE) {
2515 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2516 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2518 /* rate shaping and fairness are disabled */
2520 "single function mode without fairness\n");
2523 __bnx2x_link_report(bp);
2526 bnx2x_link_sync_notify(bp);
2529 void bnx2x__link_status_update(struct bnx2x *bp)
2531 if (bp->state != BNX2X_STATE_OPEN)
2534 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2536 if (bp->link_vars.link_up)
2537 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2539 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2541 /* indicate link status */
2542 bnx2x_link_report(bp);
2545 static void bnx2x_pmf_update(struct bnx2x *bp)
2547 int port = BP_PORT(bp);
2551 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2554 * We need the mb() to ensure the ordering between the writing to
2555 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2559 /* queue a periodic task */
2560 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2562 bnx2x_dcbx_pmf_update(bp);
2564 /* enable nig attention */
2565 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2566 if (bp->common.int_block == INT_BLOCK_HC) {
2567 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2568 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2569 } else if (!CHIP_IS_E1x(bp)) {
2570 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2571 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2574 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2582 * General service functions
2585 /* send the MCP a request, block until there is a reply */
2586 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2588 int mb_idx = BP_FW_MB_IDX(bp);
2592 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2594 mutex_lock(&bp->fw_mb_mutex);
2596 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2597 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2599 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2600 (command | seq), param);
2603 /* let the FW do it's magic ... */
2606 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2608 /* Give the FW up to 5 second (500*10ms) */
2609 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2611 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2612 cnt*delay, rc, seq);
2614 /* is this a reply to our command? */
2615 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2616 rc &= FW_MSG_CODE_MASK;
2619 BNX2X_ERR("FW failed to respond!\n");
2623 mutex_unlock(&bp->fw_mb_mutex);
2628 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2631 /* Statistics are not supported for CNIC Clients at the moment */
2638 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2640 if (CHIP_IS_E1x(bp)) {
2641 struct tstorm_eth_function_common_config tcfg = {0};
2643 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2646 /* Enable the function in the FW */
2647 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2648 storm_memset_func_en(bp, p->func_id, 1);
2651 if (p->func_flgs & FUNC_FLG_SPQ) {
2652 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2653 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2654 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2659 * bnx2x_get_tx_only_flags - Return common flags
2663 * @zero_stats TRUE if statistics zeroing is needed
2665 * Return the flags that are common for the Tx-only and not normal connections.
2667 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2668 struct bnx2x_fastpath *fp,
2671 unsigned long flags = 0;
2673 /* PF driver will always initialize the Queue to an ACTIVE state */
2674 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2676 /* tx only connections collect statistics (on the same index as the
2677 * parent connection). The statistics are zeroed when the parent
2678 * connection is initialized.
2680 if (stat_counter_valid(bp, fp)) {
2681 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2683 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2689 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2690 struct bnx2x_fastpath *fp,
2693 unsigned long flags = 0;
2695 /* calculate other queue flags */
2697 __set_bit(BNX2X_Q_FLG_OV, &flags);
2700 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2702 if (!fp->disable_tpa) {
2703 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2704 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2708 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2709 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2712 /* Always set HW VLAN stripping */
2713 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2716 return flags | bnx2x_get_common_flags(bp, fp, true);
2719 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2720 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2723 gen_init->stat_id = bnx2x_stats_id(fp);
2724 gen_init->spcl_id = fp->cl_id;
2726 /* Always use mini-jumbo MTU for FCoE L2 ring */
2728 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2730 gen_init->mtu = bp->dev->mtu;
2732 gen_init->cos = cos;
2735 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2736 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2737 struct bnx2x_rxq_setup_params *rxq_init)
2741 u16 tpa_agg_size = 0;
2743 if (!fp->disable_tpa) {
2744 pause->sge_th_hi = 250;
2745 pause->sge_th_lo = 150;
2746 tpa_agg_size = min_t(u32,
2747 (min_t(u32, 8, MAX_SKB_FRAGS) *
2748 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2749 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2751 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2752 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2753 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2757 /* pause - not for e1 */
2758 if (!CHIP_IS_E1(bp)) {
2759 pause->bd_th_hi = 350;
2760 pause->bd_th_lo = 250;
2761 pause->rcq_th_hi = 350;
2762 pause->rcq_th_lo = 250;
2768 rxq_init->dscr_map = fp->rx_desc_mapping;
2769 rxq_init->sge_map = fp->rx_sge_mapping;
2770 rxq_init->rcq_map = fp->rx_comp_mapping;
2771 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2773 /* This should be a maximum number of data bytes that may be
2774 * placed on the BD (not including paddings).
2776 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2777 IP_HEADER_ALIGNMENT_PADDING;
2779 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2780 rxq_init->tpa_agg_sz = tpa_agg_size;
2781 rxq_init->sge_buf_sz = sge_sz;
2782 rxq_init->max_sges_pkt = max_sge;
2783 rxq_init->rss_engine_id = BP_FUNC(bp);
2785 /* Maximum number or simultaneous TPA aggregation for this Queue.
2787 * For PF Clients it should be the maximum avaliable number.
2788 * VF driver(s) may want to define it to a smaller value.
2790 rxq_init->max_tpa_queues =
2791 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2792 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2794 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2795 rxq_init->fw_sb_id = fp->fw_sb_id;
2798 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2800 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2803 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2804 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2807 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2808 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2809 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2810 txq_init->fw_sb_id = fp->fw_sb_id;
2813 * set the tss leading client id for TX classfication ==
2814 * leading RSS client id
2816 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2818 if (IS_FCOE_FP(fp)) {
2819 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2820 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2824 static void bnx2x_pf_init(struct bnx2x *bp)
2826 struct bnx2x_func_init_params func_init = {0};
2827 struct event_ring_data eq_data = { {0} };
2830 if (!CHIP_IS_E1x(bp)) {
2831 /* reset IGU PF statistics: MSIX + ATTN */
2833 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2834 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2835 (CHIP_MODE_IS_4_PORT(bp) ?
2836 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2838 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2839 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2840 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2841 (CHIP_MODE_IS_4_PORT(bp) ?
2842 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2845 /* function setup flags */
2846 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2848 /* This flag is relevant for E1x only.
2849 * E2 doesn't have a TPA configuration in a function level.
2851 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2853 func_init.func_flgs = flags;
2854 func_init.pf_id = BP_FUNC(bp);
2855 func_init.func_id = BP_FUNC(bp);
2856 func_init.spq_map = bp->spq_mapping;
2857 func_init.spq_prod = bp->spq_prod_idx;
2859 bnx2x_func_init(bp, &func_init);
2861 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2864 * Congestion management values depend on the link rate
2865 * There is no active link so initial link rate is set to 10 Gbps.
2866 * When the link comes up The congestion management values are
2867 * re-calculated according to the actual link rate.
2869 bp->link_vars.line_speed = SPEED_10000;
2870 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2872 /* Only the PMF sets the HW */
2874 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2876 /* init Event Queue */
2877 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2878 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2879 eq_data.producer = bp->eq_prod;
2880 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2881 eq_data.sb_id = DEF_SB_ID;
2882 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2886 static void bnx2x_e1h_disable(struct bnx2x *bp)
2888 int port = BP_PORT(bp);
2890 bnx2x_tx_disable(bp);
2892 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2895 static void bnx2x_e1h_enable(struct bnx2x *bp)
2897 int port = BP_PORT(bp);
2899 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2901 /* Tx queue should be only reenabled */
2902 netif_tx_wake_all_queues(bp->dev);
2905 * Should not call netif_carrier_on since it will be called if the link
2906 * is up when checking for link state
2910 /* called due to MCP event (on pmf):
2911 * reread new bandwidth configuration
2913 * notify others function about the change
2915 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2917 if (bp->link_vars.link_up) {
2918 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2919 bnx2x_link_sync_notify(bp);
2921 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2924 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2926 bnx2x_config_mf_bw(bp);
2927 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2930 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2932 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2934 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2937 * This is the only place besides the function initialization
2938 * where the bp->flags can change so it is done without any
2941 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2942 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2943 bp->flags |= MF_FUNC_DIS;
2945 bnx2x_e1h_disable(bp);
2947 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2948 bp->flags &= ~MF_FUNC_DIS;
2950 bnx2x_e1h_enable(bp);
2952 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2954 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2955 bnx2x_config_mf_bw(bp);
2956 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2959 /* Report results to MCP */
2961 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2963 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2966 /* must be called under the spq lock */
2967 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2969 struct eth_spe *next_spe = bp->spq_prod_bd;
2971 if (bp->spq_prod_bd == bp->spq_last_bd) {
2972 bp->spq_prod_bd = bp->spq;
2973 bp->spq_prod_idx = 0;
2974 DP(NETIF_MSG_TIMER, "end of spq\n");
2982 /* must be called under the spq lock */
2983 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2985 int func = BP_FUNC(bp);
2987 /* Make sure that BD data is updated before writing the producer */
2990 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2996 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
2998 * @cmd: command to check
2999 * @cmd_type: command type
3001 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3003 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3004 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3005 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3006 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3007 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3008 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3009 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3018 * bnx2x_sp_post - place a single command on an SP ring
3020 * @bp: driver handle
3021 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3022 * @cid: SW CID the command is related to
3023 * @data_hi: command private data address (high 32 bits)
3024 * @data_lo: command private data address (low 32 bits)
3025 * @cmd_type: command type (e.g. NONE, ETH)
3027 * SP data is handled as if it's always an address pair, thus data fields are
3028 * not swapped to little endian in upper functions. Instead this function swaps
3029 * data as if it's two u32 fields.
3031 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3032 u32 data_hi, u32 data_lo, int cmd_type)
3034 struct eth_spe *spe;
3036 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3038 #ifdef BNX2X_STOP_ON_ERROR
3039 if (unlikely(bp->panic))
3043 spin_lock_bh(&bp->spq_lock);
3046 if (!atomic_read(&bp->eq_spq_left)) {
3047 BNX2X_ERR("BUG! EQ ring full!\n");
3048 spin_unlock_bh(&bp->spq_lock);
3052 } else if (!atomic_read(&bp->cq_spq_left)) {
3053 BNX2X_ERR("BUG! SPQ ring full!\n");
3054 spin_unlock_bh(&bp->spq_lock);
3059 spe = bnx2x_sp_get_next(bp);
3061 /* CID needs port number to be encoded int it */
3062 spe->hdr.conn_and_cmd_data =
3063 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3066 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3068 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3069 SPE_HDR_FUNCTION_ID);
3071 spe->hdr.type = cpu_to_le16(type);
3073 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3074 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3076 /* stats ramrod has it's own slot on the spq */
3077 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
3079 * It's ok if the actual decrement is issued towards the memory
3080 * somewhere between the spin_lock and spin_unlock. Thus no
3081 * more explict memory barrier is needed.
3084 atomic_dec(&bp->eq_spq_left);
3086 atomic_dec(&bp->cq_spq_left);
3090 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3091 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
3092 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
3093 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3094 (u32)(U64_LO(bp->spq_mapping) +
3095 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
3096 HW_CID(bp, cid), data_hi, data_lo, type,
3097 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3099 bnx2x_sp_prod_update(bp);
3100 spin_unlock_bh(&bp->spq_lock);
3104 /* acquire split MCP access lock register */
3105 static int bnx2x_acquire_alr(struct bnx2x *bp)
3111 for (j = 0; j < 1000; j++) {
3113 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3114 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3115 if (val & (1L << 31))
3120 if (!(val & (1L << 31))) {
3121 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3128 /* release split MCP access lock register */
3129 static void bnx2x_release_alr(struct bnx2x *bp)
3131 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3134 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3135 #define BNX2X_DEF_SB_IDX 0x0002
3137 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3139 struct host_sp_status_block *def_sb = bp->def_status_blk;
3142 barrier(); /* status block is written to by the chip */
3143 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3144 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3145 rc |= BNX2X_DEF_SB_ATT_IDX;
3148 if (bp->def_idx != def_sb->sp_sb.running_index) {
3149 bp->def_idx = def_sb->sp_sb.running_index;
3150 rc |= BNX2X_DEF_SB_IDX;
3153 /* Do not reorder: indecies reading should complete before handling */
3159 * slow path service functions
3162 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3164 int port = BP_PORT(bp);
3165 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3166 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3167 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3168 NIG_REG_MASK_INTERRUPT_PORT0;
3173 if (bp->attn_state & asserted)
3174 BNX2X_ERR("IGU ERROR\n");
3176 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3177 aeu_mask = REG_RD(bp, aeu_addr);
3179 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3180 aeu_mask, asserted);
3181 aeu_mask &= ~(asserted & 0x3ff);
3182 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3184 REG_WR(bp, aeu_addr, aeu_mask);
3185 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3187 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3188 bp->attn_state |= asserted;
3189 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3191 if (asserted & ATTN_HARD_WIRED_MASK) {
3192 if (asserted & ATTN_NIG_FOR_FUNC) {
3194 bnx2x_acquire_phy_lock(bp);
3196 /* save nig interrupt mask */
3197 nig_mask = REG_RD(bp, nig_int_mask_addr);
3199 /* If nig_mask is not set, no need to call the update
3203 REG_WR(bp, nig_int_mask_addr, 0);
3205 bnx2x_link_attn(bp);
3208 /* handle unicore attn? */
3210 if (asserted & ATTN_SW_TIMER_4_FUNC)
3211 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3213 if (asserted & GPIO_2_FUNC)
3214 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3216 if (asserted & GPIO_3_FUNC)
3217 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3219 if (asserted & GPIO_4_FUNC)
3220 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3223 if (asserted & ATTN_GENERAL_ATTN_1) {
3224 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3225 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3227 if (asserted & ATTN_GENERAL_ATTN_2) {
3228 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3229 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3231 if (asserted & ATTN_GENERAL_ATTN_3) {
3232 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3233 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3236 if (asserted & ATTN_GENERAL_ATTN_4) {
3237 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3238 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3240 if (asserted & ATTN_GENERAL_ATTN_5) {
3241 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3242 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3244 if (asserted & ATTN_GENERAL_ATTN_6) {
3245 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3246 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3250 } /* if hardwired */
3252 if (bp->common.int_block == INT_BLOCK_HC)
3253 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3254 COMMAND_REG_ATTN_BITS_SET);
3256 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3258 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3259 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3260 REG_WR(bp, reg_addr, asserted);
3262 /* now set back the mask */
3263 if (asserted & ATTN_NIG_FOR_FUNC) {
3264 REG_WR(bp, nig_int_mask_addr, nig_mask);
3265 bnx2x_release_phy_lock(bp);
3269 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3271 int port = BP_PORT(bp);
3273 /* mark the failure */
3276 dev_info.port_hw_config[port].external_phy_config);
3278 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3279 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3280 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3283 /* log the failure */
3284 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3285 " the driver to shutdown the card to prevent permanent"
3286 " damage. Please contact OEM Support for assistance\n");
3289 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3291 int port = BP_PORT(bp);
3295 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3296 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3298 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3300 val = REG_RD(bp, reg_offset);
3301 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3302 REG_WR(bp, reg_offset, val);
3304 BNX2X_ERR("SPIO5 hw attention\n");
3306 /* Fan failure attention */
3307 bnx2x_hw_reset_phy(&bp->link_params);
3308 bnx2x_fan_failure(bp);
3311 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3312 bnx2x_acquire_phy_lock(bp);
3313 bnx2x_handle_module_detect_int(&bp->link_params);
3314 bnx2x_release_phy_lock(bp);
3317 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3319 val = REG_RD(bp, reg_offset);
3320 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3321 REG_WR(bp, reg_offset, val);
3323 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3324 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3329 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3333 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3335 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3336 BNX2X_ERR("DB hw attention 0x%x\n", val);
3337 /* DORQ discard attention */
3339 BNX2X_ERR("FATAL error from DORQ\n");
3342 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3344 int port = BP_PORT(bp);
3347 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3348 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3350 val = REG_RD(bp, reg_offset);
3351 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3352 REG_WR(bp, reg_offset, val);
3354 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3355 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3360 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3364 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3366 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3367 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3368 /* CFC error attention */
3370 BNX2X_ERR("FATAL error from CFC\n");
3373 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3374 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3375 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3376 /* RQ_USDMDP_FIFO_OVERFLOW */
3378 BNX2X_ERR("FATAL error from PXP\n");
3380 if (!CHIP_IS_E1x(bp)) {
3381 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3382 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3386 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3388 int port = BP_PORT(bp);
3391 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3392 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3394 val = REG_RD(bp, reg_offset);
3395 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3396 REG_WR(bp, reg_offset, val);
3398 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3399 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3404 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3408 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3410 if (attn & BNX2X_PMF_LINK_ASSERT) {
3411 int func = BP_FUNC(bp);
3413 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3414 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3415 func_mf_config[BP_ABS_FUNC(bp)].config);
3417 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3418 if (val & DRV_STATUS_DCC_EVENT_MASK)
3420 (val & DRV_STATUS_DCC_EVENT_MASK));
3422 if (val & DRV_STATUS_SET_MF_BW)
3423 bnx2x_set_mf_bw(bp);
3425 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3426 bnx2x_pmf_update(bp);
3429 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3430 bp->dcbx_enabled > 0)
3431 /* start dcbx state machine */
3432 bnx2x_dcbx_set_params(bp,
3433 BNX2X_DCBX_STATE_NEG_RECEIVED);
3434 if (bp->link_vars.periodic_flags &
3435 PERIODIC_FLAGS_LINK_EVENT) {
3436 /* sync with link */
3437 bnx2x_acquire_phy_lock(bp);
3438 bp->link_vars.periodic_flags &=
3439 ~PERIODIC_FLAGS_LINK_EVENT;
3440 bnx2x_release_phy_lock(bp);
3442 bnx2x_link_sync_notify(bp);
3443 bnx2x_link_report(bp);
3445 /* Always call it here: bnx2x_link_report() will
3446 * prevent the link indication duplication.
3448 bnx2x__link_status_update(bp);
3449 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3451 BNX2X_ERR("MC assert!\n");
3452 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3453 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3454 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3455 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3458 } else if (attn & BNX2X_MCP_ASSERT) {
3460 BNX2X_ERR("MCP assert!\n");
3461 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3465 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3468 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3469 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3470 if (attn & BNX2X_GRC_TIMEOUT) {
3471 val = CHIP_IS_E1(bp) ? 0 :
3472 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3473 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3475 if (attn & BNX2X_GRC_RSV) {
3476 val = CHIP_IS_E1(bp) ? 0 :
3477 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3478 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3480 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3486 * 0-7 - Engine0 load counter.
3487 * 8-15 - Engine1 load counter.
3488 * 16 - Engine0 RESET_IN_PROGRESS bit.
3489 * 17 - Engine1 RESET_IN_PROGRESS bit.
3490 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3492 * 19 - Engine1 ONE_IS_LOADED.
3493 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3494 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3495 * just the one belonging to its engine).
3498 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3500 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3501 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3502 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3503 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3504 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3505 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3506 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3509 * Set the GLOBAL_RESET bit.
3511 * Should be run under rtnl lock
3513 void bnx2x_set_reset_global(struct bnx2x *bp)
3515 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3517 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3523 * Clear the GLOBAL_RESET bit.
3525 * Should be run under rtnl lock
3527 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3529 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3531 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3537 * Checks the GLOBAL_RESET bit.
3539 * should be run under rtnl lock
3541 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3543 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3545 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3546 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3550 * Clear RESET_IN_PROGRESS bit for the current engine.
3552 * Should be run under rtnl lock
3554 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3556 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3557 u32 bit = BP_PATH(bp) ?
3558 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3562 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3568 * Set RESET_IN_PROGRESS for the current engine.
3570 * should be run under rtnl lock
3572 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3574 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3575 u32 bit = BP_PATH(bp) ?
3576 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3580 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3586 * Checks the RESET_IN_PROGRESS bit for the given engine.
3587 * should be run under rtnl lock
3589 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3591 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3593 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3595 /* return false if bit is set */
3596 return (val & bit) ? false : true;
3600 * Increment the load counter for the current engine.
3602 * should be run under rtnl lock
3604 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3606 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3607 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3608 BNX2X_PATH0_LOAD_CNT_MASK;
3609 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3610 BNX2X_PATH0_LOAD_CNT_SHIFT;
3612 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3614 /* get the current counter value */
3615 val1 = (val & mask) >> shift;
3620 /* clear the old value */
3623 /* set the new one */
3624 val |= ((val1 << shift) & mask);
3626 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3632 * bnx2x_dec_load_cnt - decrement the load counter
3634 * @bp: driver handle
3636 * Should be run under rtnl lock.
3637 * Decrements the load counter for the current engine. Returns
3638 * the new counter value.
3640 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3642 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3643 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3644 BNX2X_PATH0_LOAD_CNT_MASK;
3645 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3646 BNX2X_PATH0_LOAD_CNT_SHIFT;
3648 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3650 /* get the current counter value */
3651 val1 = (val & mask) >> shift;
3656 /* clear the old value */
3659 /* set the new one */
3660 val |= ((val1 << shift) & mask);
3662 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3670 * Read the load counter for the current engine.
3672 * should be run under rtnl lock
3674 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3676 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3677 BNX2X_PATH0_LOAD_CNT_MASK);
3678 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3679 BNX2X_PATH0_LOAD_CNT_SHIFT);
3680 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3682 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3684 val = (val & mask) >> shift;
3686 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3692 * Reset the load counter for the current engine.
3694 * should be run under rtnl lock
3696 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3698 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3699 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3700 BNX2X_PATH0_LOAD_CNT_MASK);
3702 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3705 static inline void _print_next_block(int idx, const char *blk)
3712 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3717 for (i = 0; sig; i++) {
3718 cur_bit = ((u32)0x1 << i);
3719 if (sig & cur_bit) {
3721 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3723 _print_next_block(par_num++, "BRB");
3725 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3727 _print_next_block(par_num++, "PARSER");
3729 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3731 _print_next_block(par_num++, "TSDM");
3733 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3735 _print_next_block(par_num++,
3738 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3740 _print_next_block(par_num++, "TCM");
3742 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3744 _print_next_block(par_num++, "TSEMI");
3746 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3748 _print_next_block(par_num++, "XPB");
3760 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3761 bool *global, bool print)
3765 for (i = 0; sig; i++) {
3766 cur_bit = ((u32)0x1 << i);
3767 if (sig & cur_bit) {
3769 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3771 _print_next_block(par_num++, "PBF");
3773 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3775 _print_next_block(par_num++, "QM");
3777 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3779 _print_next_block(par_num++, "TM");
3781 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3783 _print_next_block(par_num++, "XSDM");
3785 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3787 _print_next_block(par_num++, "XCM");
3789 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3791 _print_next_block(par_num++, "XSEMI");
3793 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3795 _print_next_block(par_num++,
3798 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3800 _print_next_block(par_num++, "NIG");
3802 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3804 _print_next_block(par_num++,
3808 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3810 _print_next_block(par_num++, "DEBUG");
3812 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3814 _print_next_block(par_num++, "USDM");
3816 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3818 _print_next_block(par_num++, "USEMI");
3820 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3822 _print_next_block(par_num++, "UPB");
3824 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3826 _print_next_block(par_num++, "CSDM");
3838 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3843 for (i = 0; sig; i++) {
3844 cur_bit = ((u32)0x1 << i);
3845 if (sig & cur_bit) {
3847 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3849 _print_next_block(par_num++, "CSEMI");
3851 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3853 _print_next_block(par_num++, "PXP");
3855 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3857 _print_next_block(par_num++,
3858 "PXPPCICLOCKCLIENT");
3860 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3862 _print_next_block(par_num++, "CFC");
3864 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3866 _print_next_block(par_num++, "CDU");
3868 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3870 _print_next_block(par_num++, "DMAE");
3872 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3874 _print_next_block(par_num++, "IGU");
3876 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3878 _print_next_block(par_num++, "MISC");
3890 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3891 bool *global, bool print)
3895 for (i = 0; sig; i++) {
3896 cur_bit = ((u32)0x1 << i);
3897 if (sig & cur_bit) {
3899 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3901 _print_next_block(par_num++, "MCP ROM");
3904 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3906 _print_next_block(par_num++,
3910 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3912 _print_next_block(par_num++,
3916 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3918 _print_next_block(par_num++,
3932 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3933 u32 sig0, u32 sig1, u32 sig2, u32 sig3)
3935 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3936 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3938 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3939 "[0]:0x%08x [1]:0x%08x "
3940 "[2]:0x%08x [3]:0x%08x\n",
3941 sig0 & HW_PRTY_ASSERT_SET_0,
3942 sig1 & HW_PRTY_ASSERT_SET_1,
3943 sig2 & HW_PRTY_ASSERT_SET_2,
3944 sig3 & HW_PRTY_ASSERT_SET_3);
3947 "Parity errors detected in blocks: ");
3948 par_num = bnx2x_check_blocks_with_parity0(
3949 sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
3950 par_num = bnx2x_check_blocks_with_parity1(
3951 sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
3952 par_num = bnx2x_check_blocks_with_parity2(
3953 sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
3954 par_num = bnx2x_check_blocks_with_parity3(
3955 sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
3964 * bnx2x_chk_parity_attn - checks for parity attentions.
3966 * @bp: driver handle
3967 * @global: true if there was a global attention
3968 * @print: show parity attention in syslog
3970 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
3972 struct attn_route attn;
3973 int port = BP_PORT(bp);
3975 attn.sig[0] = REG_RD(bp,
3976 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3978 attn.sig[1] = REG_RD(bp,
3979 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3981 attn.sig[2] = REG_RD(bp,
3982 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3984 attn.sig[3] = REG_RD(bp,
3985 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3988 return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
3989 attn.sig[2], attn.sig[3]);
3993 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3996 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3998 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3999 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4000 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4001 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4003 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4004 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4005 "INCORRECT_RCV_BEHAVIOR\n");
4006 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4007 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4008 "WAS_ERROR_ATTN\n");
4009 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4010 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4011 "VF_LENGTH_VIOLATION_ATTN\n");
4013 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4014 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4015 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4017 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4018 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4019 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4020 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4021 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4022 "TCPL_ERROR_ATTN\n");
4023 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4024 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4025 "TCPL_IN_TWO_RCBS_ATTN\n");
4026 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4027 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4028 "CSSNOOP_FIFO_OVERFLOW\n");
4030 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4031 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4032 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4033 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4034 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4035 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4036 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4037 "_ATC_TCPL_TO_NOT_PEND\n");
4038 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4039 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4040 "ATC_GPA_MULTIPLE_HITS\n");
4041 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4042 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4043 "ATC_RCPL_TO_EMPTY_CNT\n");
4044 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4045 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4046 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4047 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4048 "ATC_IREQ_LESS_THAN_STU\n");
4051 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4052 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4053 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4054 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4055 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4060 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4062 struct attn_route attn, *group_mask;
4063 int port = BP_PORT(bp);
4068 bool global = false;
4070 /* need to take HW lock because MCP or other port might also
4071 try to handle this event */
4072 bnx2x_acquire_alr(bp);
4074 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4075 #ifndef BNX2X_STOP_ON_ERROR
4076 bp->recovery_state = BNX2X_RECOVERY_INIT;
4077 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4078 /* Disable HW interrupts */
4079 bnx2x_int_disable(bp);
4080 /* In case of parity errors don't handle attentions so that
4081 * other function would "see" parity errors.
4086 bnx2x_release_alr(bp);
4090 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4091 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4092 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4093 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4094 if (!CHIP_IS_E1x(bp))
4096 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4100 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4101 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4103 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4104 if (deasserted & (1 << index)) {
4105 group_mask = &bp->attn_group[index];
4107 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4110 group_mask->sig[0], group_mask->sig[1],
4111 group_mask->sig[2], group_mask->sig[3],
4112 group_mask->sig[4]);
4114 bnx2x_attn_int_deasserted4(bp,
4115 attn.sig[4] & group_mask->sig[4]);
4116 bnx2x_attn_int_deasserted3(bp,
4117 attn.sig[3] & group_mask->sig[3]);
4118 bnx2x_attn_int_deasserted1(bp,
4119 attn.sig[1] & group_mask->sig[1]);
4120 bnx2x_attn_int_deasserted2(bp,
4121 attn.sig[2] & group_mask->sig[2]);
4122 bnx2x_attn_int_deasserted0(bp,
4123 attn.sig[0] & group_mask->sig[0]);
4127 bnx2x_release_alr(bp);
4129 if (bp->common.int_block == INT_BLOCK_HC)
4130 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4131 COMMAND_REG_ATTN_BITS_CLR);
4133 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4136 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4137 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4138 REG_WR(bp, reg_addr, val);
4140 if (~bp->attn_state & deasserted)
4141 BNX2X_ERR("IGU ERROR\n");
4143 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4144 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4146 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4147 aeu_mask = REG_RD(bp, reg_addr);
4149 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4150 aeu_mask, deasserted);
4151 aeu_mask |= (deasserted & 0x3ff);
4152 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4154 REG_WR(bp, reg_addr, aeu_mask);
4155 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4157 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4158 bp->attn_state &= ~deasserted;
4159 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4162 static void bnx2x_attn_int(struct bnx2x *bp)
4164 /* read local copy of bits */
4165 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4167 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4169 u32 attn_state = bp->attn_state;
4171 /* look for changed bits */
4172 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4173 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4176 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4177 attn_bits, attn_ack, asserted, deasserted);
4179 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4180 BNX2X_ERR("BAD attention state\n");
4182 /* handle bits that were raised */
4184 bnx2x_attn_int_asserted(bp, asserted);
4187 bnx2x_attn_int_deasserted(bp, deasserted);
4190 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4191 u16 index, u8 op, u8 update)
4193 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4195 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4199 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4201 /* No memory barriers */
4202 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4203 mmiowb(); /* keep prod updates ordered */
4207 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4208 union event_ring_elem *elem)
4210 u8 err = elem->message.error;
4212 if (!bp->cnic_eth_dev.starting_cid ||
4213 (cid < bp->cnic_eth_dev.starting_cid &&
4214 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4217 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4219 if (unlikely(err)) {
4221 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4223 bnx2x_panic_dump(bp);
4225 bnx2x_cnic_cfc_comp(bp, cid, err);
4230 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4232 struct bnx2x_mcast_ramrod_params rparam;
4235 memset(&rparam, 0, sizeof(rparam));
4237 rparam.mcast_obj = &bp->mcast_obj;
4239 netif_addr_lock_bh(bp->dev);
4241 /* Clear pending state for the last command */
4242 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4244 /* If there are pending mcast commands - send them */
4245 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4246 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4248 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4252 netif_addr_unlock_bh(bp->dev);
4255 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4256 union event_ring_elem *elem)
4258 unsigned long ramrod_flags = 0;
4260 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4261 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4263 /* Always push next commands out, don't wait here */
4264 __set_bit(RAMROD_CONT, &ramrod_flags);
4266 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4267 case BNX2X_FILTER_MAC_PENDING:
4269 if (cid == BNX2X_ISCSI_ETH_CID)
4270 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4273 vlan_mac_obj = &bp->fp[cid].mac_obj;
4276 vlan_mac_obj = &bp->fp[cid].mac_obj;
4278 case BNX2X_FILTER_MCAST_PENDING:
4279 /* This is only relevant for 57710 where multicast MACs are
4280 * configured as unicast MACs using the same ramrod.
4282 bnx2x_handle_mcast_eqe(bp);
4285 BNX2X_ERR("Unsupported classification command: %d\n",
4286 elem->message.data.eth_event.echo);
4290 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4293 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4295 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4300 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4303 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4305 netif_addr_lock_bh(bp->dev);
4307 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4309 /* Send rx_mode command again if was requested */
4310 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4311 bnx2x_set_storm_rx_mode(bp);
4313 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4315 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4316 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4318 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4321 netif_addr_unlock_bh(bp->dev);
4324 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4325 struct bnx2x *bp, u32 cid)
4327 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
4329 if (cid == BNX2X_FCOE_ETH_CID)
4330 return &bnx2x_fcoe(bp, q_obj);
4333 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4336 static void bnx2x_eq_int(struct bnx2x *bp)
4338 u16 hw_cons, sw_cons, sw_prod;
4339 union event_ring_elem *elem;
4343 struct bnx2x_queue_sp_obj *q_obj;
4344 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4345 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4347 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4349 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4350 * when we get the the next-page we nned to adjust so the loop
4351 * condition below will be met. The next element is the size of a
4352 * regular element and hence incrementing by 1
4354 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4357 /* This function may never run in parallel with itself for a
4358 * specific bp, thus there is no need in "paired" read memory
4361 sw_cons = bp->eq_cons;
4362 sw_prod = bp->eq_prod;
4364 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
4365 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4367 for (; sw_cons != hw_cons;
4368 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4371 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4373 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4374 opcode = elem->message.opcode;
4377 /* handle eq element */
4379 case EVENT_RING_OPCODE_STAT_QUERY:
4380 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4382 /* nothing to do with stats comp */
4385 case EVENT_RING_OPCODE_CFC_DEL:
4386 /* handle according to cid range */
4388 * we may want to verify here that the bp state is
4391 DP(NETIF_MSG_IFDOWN,
4392 "got delete ramrod for MULTI[%d]\n", cid);
4394 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4397 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4399 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4406 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4407 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
4408 if (f_obj->complete_cmd(bp, f_obj,
4409 BNX2X_F_CMD_TX_STOP))
4411 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4414 case EVENT_RING_OPCODE_START_TRAFFIC:
4415 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
4416 if (f_obj->complete_cmd(bp, f_obj,
4417 BNX2X_F_CMD_TX_START))
4419 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4421 case EVENT_RING_OPCODE_FUNCTION_START:
4422 DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
4423 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4428 case EVENT_RING_OPCODE_FUNCTION_STOP:
4429 DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
4430 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4436 switch (opcode | bp->state) {
4437 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4439 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4440 BNX2X_STATE_OPENING_WAIT4_PORT):
4441 cid = elem->message.data.eth_event.echo &
4443 DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
4445 rss_raw->clear_pending(rss_raw);
4448 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4449 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4450 case (EVENT_RING_OPCODE_SET_MAC |
4451 BNX2X_STATE_CLOSING_WAIT4_HALT):
4452 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4454 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4456 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4457 BNX2X_STATE_CLOSING_WAIT4_HALT):
4458 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
4459 bnx2x_handle_classification_eqe(bp, elem);
4462 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4464 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4466 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4467 BNX2X_STATE_CLOSING_WAIT4_HALT):
4468 DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
4469 bnx2x_handle_mcast_eqe(bp);
4472 case (EVENT_RING_OPCODE_FILTERS_RULES |
4474 case (EVENT_RING_OPCODE_FILTERS_RULES |
4476 case (EVENT_RING_OPCODE_FILTERS_RULES |
4477 BNX2X_STATE_CLOSING_WAIT4_HALT):
4478 DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
4479 bnx2x_handle_rx_mode_eqe(bp);
4482 /* unknown event log error and continue */
4483 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4484 elem->message.opcode, bp->state);
4490 smp_mb__before_atomic_inc();
4491 atomic_add(spqe_cnt, &bp->eq_spq_left);
4493 bp->eq_cons = sw_cons;
4494 bp->eq_prod = sw_prod;
4495 /* Make sure that above mem writes were issued towards the memory */
4498 /* update producer */
4499 bnx2x_update_eq_prod(bp, bp->eq_prod);
4502 static void bnx2x_sp_task(struct work_struct *work)
4504 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4507 status = bnx2x_update_dsb_idx(bp);
4508 /* if (status == 0) */
4509 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4511 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4514 if (status & BNX2X_DEF_SB_ATT_IDX) {
4516 status &= ~BNX2X_DEF_SB_ATT_IDX;
4519 /* SP events: STAT_QUERY and others */
4520 if (status & BNX2X_DEF_SB_IDX) {
4522 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4524 if ((!NO_FCOE(bp)) &&
4525 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4527 * Prevent local bottom-halves from running as
4528 * we are going to change the local NAPI list.
4531 napi_schedule(&bnx2x_fcoe(bp, napi));
4535 /* Handle EQ completions */
4538 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4539 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4541 status &= ~BNX2X_DEF_SB_IDX;
4544 if (unlikely(status))
4545 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4548 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4549 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4552 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4554 struct net_device *dev = dev_instance;
4555 struct bnx2x *bp = netdev_priv(dev);
4557 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4558 IGU_INT_DISABLE, 0);
4560 #ifdef BNX2X_STOP_ON_ERROR
4561 if (unlikely(bp->panic))
4567 struct cnic_ops *c_ops;
4570 c_ops = rcu_dereference(bp->cnic_ops);
4572 c_ops->cnic_handler(bp->cnic_data, NULL);
4576 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4581 /* end of slow path */
4584 void bnx2x_drv_pulse(struct bnx2x *bp)
4586 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4587 bp->fw_drv_pulse_wr_seq);
4591 static void bnx2x_timer(unsigned long data)
4594 struct bnx2x *bp = (struct bnx2x *) data;
4596 if (!netif_running(bp->dev))
4600 struct bnx2x_fastpath *fp = &bp->fp[0];
4602 for_each_cos_in_tx_queue(fp, cos)
4603 bnx2x_tx_int(bp, &fp->txdata[cos]);
4604 bnx2x_rx_int(fp, 1000);
4607 if (!BP_NOMCP(bp)) {
4608 int mb_idx = BP_FW_MB_IDX(bp);
4612 ++bp->fw_drv_pulse_wr_seq;
4613 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4614 /* TBD - add SYSTEM_TIME */
4615 drv_pulse = bp->fw_drv_pulse_wr_seq;
4616 bnx2x_drv_pulse(bp);
4618 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4619 MCP_PULSE_SEQ_MASK);
4620 /* The delta between driver pulse and mcp response
4621 * should be 1 (before mcp response) or 0 (after mcp response)
4623 if ((drv_pulse != mcp_pulse) &&
4624 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4625 /* someone lost a heartbeat... */
4626 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4627 drv_pulse, mcp_pulse);
4631 if (bp->state == BNX2X_STATE_OPEN)
4632 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4634 mod_timer(&bp->timer, jiffies + bp->current_interval);
4637 /* end of Statistics */
4642 * nic init service functions
4645 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4648 if (!(len%4) && !(addr%4))
4649 for (i = 0; i < len; i += 4)
4650 REG_WR(bp, addr + i, fill);
4652 for (i = 0; i < len; i++)
4653 REG_WR8(bp, addr + i, fill);
4657 /* helper: writes FP SP data to FW - data_size in dwords */
4658 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4664 for (index = 0; index < data_size; index++)
4665 REG_WR(bp, BAR_CSTRORM_INTMEM +
4666 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4668 *(sb_data_p + index));
4671 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4675 struct hc_status_block_data_e2 sb_data_e2;
4676 struct hc_status_block_data_e1x sb_data_e1x;
4678 /* disable the function first */
4679 if (!CHIP_IS_E1x(bp)) {
4680 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4681 sb_data_e2.common.state = SB_DISABLED;
4682 sb_data_e2.common.p_func.vf_valid = false;
4683 sb_data_p = (u32 *)&sb_data_e2;
4684 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4686 memset(&sb_data_e1x, 0,
4687 sizeof(struct hc_status_block_data_e1x));
4688 sb_data_e1x.common.state = SB_DISABLED;
4689 sb_data_e1x.common.p_func.vf_valid = false;
4690 sb_data_p = (u32 *)&sb_data_e1x;
4691 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4693 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4695 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4696 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4697 CSTORM_STATUS_BLOCK_SIZE);
4698 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4699 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4700 CSTORM_SYNC_BLOCK_SIZE);
4703 /* helper: writes SP SB data to FW */
4704 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4705 struct hc_sp_status_block_data *sp_sb_data)
4707 int func = BP_FUNC(bp);
4709 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4710 REG_WR(bp, BAR_CSTRORM_INTMEM +
4711 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4713 *((u32 *)sp_sb_data + i));
4716 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4718 int func = BP_FUNC(bp);
4719 struct hc_sp_status_block_data sp_sb_data;
4720 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4722 sp_sb_data.state = SB_DISABLED;
4723 sp_sb_data.p_func.vf_valid = false;
4725 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4727 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4728 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4729 CSTORM_SP_STATUS_BLOCK_SIZE);
4730 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4731 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4732 CSTORM_SP_SYNC_BLOCK_SIZE);
4738 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4739 int igu_sb_id, int igu_seg_id)
4741 hc_sm->igu_sb_id = igu_sb_id;
4742 hc_sm->igu_seg_id = igu_seg_id;
4743 hc_sm->timer_value = 0xFF;
4744 hc_sm->time_to_expire = 0xFFFFFFFF;
4747 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4748 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4752 struct hc_status_block_data_e2 sb_data_e2;
4753 struct hc_status_block_data_e1x sb_data_e1x;
4754 struct hc_status_block_sm *hc_sm_p;
4758 if (CHIP_INT_MODE_IS_BC(bp))
4759 igu_seg_id = HC_SEG_ACCESS_NORM;
4761 igu_seg_id = IGU_SEG_ACCESS_NORM;
4763 bnx2x_zero_fp_sb(bp, fw_sb_id);
4765 if (!CHIP_IS_E1x(bp)) {
4766 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4767 sb_data_e2.common.state = SB_ENABLED;
4768 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4769 sb_data_e2.common.p_func.vf_id = vfid;
4770 sb_data_e2.common.p_func.vf_valid = vf_valid;
4771 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4772 sb_data_e2.common.same_igu_sb_1b = true;
4773 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4774 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4775 hc_sm_p = sb_data_e2.common.state_machine;
4776 sb_data_p = (u32 *)&sb_data_e2;
4777 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4779 memset(&sb_data_e1x, 0,
4780 sizeof(struct hc_status_block_data_e1x));
4781 sb_data_e1x.common.state = SB_ENABLED;
4782 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4783 sb_data_e1x.common.p_func.vf_id = 0xff;
4784 sb_data_e1x.common.p_func.vf_valid = false;
4785 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4786 sb_data_e1x.common.same_igu_sb_1b = true;
4787 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4788 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4789 hc_sm_p = sb_data_e1x.common.state_machine;
4790 sb_data_p = (u32 *)&sb_data_e1x;
4791 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4794 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4795 igu_sb_id, igu_seg_id);
4796 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4797 igu_sb_id, igu_seg_id);
4799 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4801 /* write indecies to HW */
4802 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4805 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4806 u16 tx_usec, u16 rx_usec)
4808 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4810 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4811 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4813 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4814 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4816 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4817 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4821 static void bnx2x_init_def_sb(struct bnx2x *bp)
4823 struct host_sp_status_block *def_sb = bp->def_status_blk;
4824 dma_addr_t mapping = bp->def_status_blk_mapping;
4825 int igu_sp_sb_index;
4827 int port = BP_PORT(bp);
4828 int func = BP_FUNC(bp);
4832 struct hc_sp_status_block_data sp_sb_data;
4833 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4835 if (CHIP_INT_MODE_IS_BC(bp)) {
4836 igu_sp_sb_index = DEF_SB_IGU_ID;
4837 igu_seg_id = HC_SEG_ACCESS_DEF;
4839 igu_sp_sb_index = bp->igu_dsb_id;
4840 igu_seg_id = IGU_SEG_ACCESS_DEF;
4844 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4845 atten_status_block);
4846 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4850 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4851 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4852 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4854 /* take care of sig[0]..sig[4] */
4855 for (sindex = 0; sindex < 4; sindex++)
4856 bp->attn_group[index].sig[sindex] =
4857 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4859 if (!CHIP_IS_E1x(bp))
4861 * enable5 is separate from the rest of the registers,
4862 * and therefore the address skip is 4
4863 * and not 16 between the different groups
4865 bp->attn_group[index].sig[4] = REG_RD(bp,
4866 reg_offset + 0x10 + 0x4*index);
4868 bp->attn_group[index].sig[4] = 0;
4871 if (bp->common.int_block == INT_BLOCK_HC) {
4872 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4873 HC_REG_ATTN_MSG0_ADDR_L);
4875 REG_WR(bp, reg_offset, U64_LO(section));
4876 REG_WR(bp, reg_offset + 4, U64_HI(section));
4877 } else if (!CHIP_IS_E1x(bp)) {
4878 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4879 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4882 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4885 bnx2x_zero_sp_sb(bp);
4887 sp_sb_data.state = SB_ENABLED;
4888 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4889 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4890 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4891 sp_sb_data.igu_seg_id = igu_seg_id;
4892 sp_sb_data.p_func.pf_id = func;
4893 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4894 sp_sb_data.p_func.vf_id = 0xff;
4896 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4898 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4901 void bnx2x_update_coalesce(struct bnx2x *bp)
4905 for_each_eth_queue(bp, i)
4906 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4907 bp->tx_ticks, bp->rx_ticks);
4910 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4912 spin_lock_init(&bp->spq_lock);
4913 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4915 bp->spq_prod_idx = 0;
4916 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4917 bp->spq_prod_bd = bp->spq;
4918 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4921 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4924 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4925 union event_ring_elem *elem =
4926 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4928 elem->next_page.addr.hi =
4929 cpu_to_le32(U64_HI(bp->eq_mapping +
4930 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4931 elem->next_page.addr.lo =
4932 cpu_to_le32(U64_LO(bp->eq_mapping +
4933 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4936 bp->eq_prod = NUM_EQ_DESC;
4937 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4938 /* we want a warning message before it gets rought... */
4939 atomic_set(&bp->eq_spq_left,
4940 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
4944 /* called with netif_addr_lock_bh() */
4945 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
4946 unsigned long rx_mode_flags,
4947 unsigned long rx_accept_flags,
4948 unsigned long tx_accept_flags,
4949 unsigned long ramrod_flags)
4951 struct bnx2x_rx_mode_ramrod_params ramrod_param;
4954 memset(&ramrod_param, 0, sizeof(ramrod_param));
4956 /* Prepare ramrod parameters */
4957 ramrod_param.cid = 0;
4958 ramrod_param.cl_id = cl_id;
4959 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
4960 ramrod_param.func_id = BP_FUNC(bp);
4962 ramrod_param.pstate = &bp->sp_state;
4963 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
4965 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
4966 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
4968 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4970 ramrod_param.ramrod_flags = ramrod_flags;
4971 ramrod_param.rx_mode_flags = rx_mode_flags;
4973 ramrod_param.rx_accept_flags = rx_accept_flags;
4974 ramrod_param.tx_accept_flags = tx_accept_flags;
4976 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
4978 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
4983 /* called with netif_addr_lock_bh() */
4984 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4986 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
4987 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
4992 /* Configure rx_mode of FCoE Queue */
4993 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
4996 switch (bp->rx_mode) {
4997 case BNX2X_RX_MODE_NONE:
4999 * 'drop all' supersedes any accept flags that may have been
5000 * passed to the function.
5003 case BNX2X_RX_MODE_NORMAL:
5004 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5005 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5006 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5008 /* internal switching mode */
5009 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5010 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5011 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5014 case BNX2X_RX_MODE_ALLMULTI:
5015 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5016 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5017 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5019 /* internal switching mode */
5020 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5021 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5022 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5025 case BNX2X_RX_MODE_PROMISC:
5026 /* According to deffinition of SI mode, iface in promisc mode
5027 * should receive matched and unmatched (in resolution of port)
5030 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5031 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5032 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5033 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5035 /* internal switching mode */
5036 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5037 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5040 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5042 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5046 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5050 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5051 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5052 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5055 __set_bit(RAMROD_RX, &ramrod_flags);
5056 __set_bit(RAMROD_TX, &ramrod_flags);
5058 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5059 tx_accept_flags, ramrod_flags);
5062 static void bnx2x_init_internal_common(struct bnx2x *bp)
5068 * In switch independent mode, the TSTORM needs to accept
5069 * packets that failed classification, since approximate match
5070 * mac addresses aren't written to NIG LLH
5072 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5073 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5074 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5075 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5076 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5078 /* Zero this manually as its initialization is
5079 currently missing in the initTool */
5080 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5081 REG_WR(bp, BAR_USTRORM_INTMEM +
5082 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5083 if (!CHIP_IS_E1x(bp)) {
5084 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5085 CHIP_INT_MODE_IS_BC(bp) ?
5086 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5090 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5092 switch (load_code) {
5093 case FW_MSG_CODE_DRV_LOAD_COMMON:
5094 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5095 bnx2x_init_internal_common(bp);
5098 case FW_MSG_CODE_DRV_LOAD_PORT:
5102 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5103 /* internal memory per function is
5104 initialized inside bnx2x_pf_init */
5108 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5113 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5115 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5118 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5120 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5123 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5125 if (CHIP_IS_E1x(fp->bp))
5126 return BP_L_ID(fp->bp) + fp->index;
5127 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5128 return bnx2x_fp_igu_sb_id(fp);
5131 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5133 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5135 unsigned long q_type = 0;
5136 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5139 fp->cl_id = bnx2x_fp_cl_id(fp);
5140 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5141 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5142 /* qZone id equals to FW (per path) client id */
5143 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5146 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5147 /* Setup SB indicies */
5148 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5150 /* Configure Queue State object */
5151 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5152 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5154 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5157 for_each_cos_in_tx_queue(fp, cos) {
5158 bnx2x_init_txdata(bp, &fp->txdata[cos],
5159 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5160 FP_COS_TO_TXQ(fp, cos),
5161 BNX2X_TX_SB_INDEX_BASE + cos);
5162 cids[cos] = fp->txdata[cos].cid;
5165 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5166 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5167 bnx2x_sp_mapping(bp, q_rdata), q_type);
5170 * Configure classification DBs: Always enable Tx switching
5172 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5174 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5175 "cl_id %d fw_sb %d igu_sb %d\n",
5176 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5178 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5179 fp->fw_sb_id, fp->igu_sb_id);
5181 bnx2x_update_fpsb_idx(fp);
5184 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5188 for_each_eth_queue(bp, i)
5189 bnx2x_init_eth_fp(bp, i);
5192 bnx2x_init_fcoe_fp(bp);
5194 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5195 BNX2X_VF_ID_INVALID, false,
5196 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5200 /* Initialize MOD_ABS interrupts */
5201 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5202 bp->common.shmem_base, bp->common.shmem2_base,
5204 /* ensure status block indices were read */
5207 bnx2x_init_def_sb(bp);
5208 bnx2x_update_dsb_idx(bp);
5209 bnx2x_init_rx_rings(bp);
5210 bnx2x_init_tx_rings(bp);
5211 bnx2x_init_sp_ring(bp);
5212 bnx2x_init_eq_ring(bp);
5213 bnx2x_init_internal(bp, load_code);
5215 bnx2x_stats_init(bp);
5217 /* flush all before enabling interrupts */
5221 bnx2x_int_enable(bp);
5223 /* Check for SPIO5 */
5224 bnx2x_attn_int_deasserted0(bp,
5225 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5226 AEU_INPUTS_ATTN_BITS_SPIO5);
5229 /* end of nic init */
5232 * gzip service functions
5235 static int bnx2x_gunzip_init(struct bnx2x *bp)
5237 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5238 &bp->gunzip_mapping, GFP_KERNEL);
5239 if (bp->gunzip_buf == NULL)
5242 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5243 if (bp->strm == NULL)
5246 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5247 if (bp->strm->workspace == NULL)
5257 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5258 bp->gunzip_mapping);
5259 bp->gunzip_buf = NULL;
5262 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5263 " un-compression\n");
5267 static void bnx2x_gunzip_end(struct bnx2x *bp)
5270 vfree(bp->strm->workspace);
5275 if (bp->gunzip_buf) {
5276 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5277 bp->gunzip_mapping);
5278 bp->gunzip_buf = NULL;
5282 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5286 /* check gzip header */
5287 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5288 BNX2X_ERR("Bad gzip header\n");
5296 if (zbuf[3] & FNAME)
5297 while ((zbuf[n++] != 0) && (n < len));
5299 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5300 bp->strm->avail_in = len - n;
5301 bp->strm->next_out = bp->gunzip_buf;
5302 bp->strm->avail_out = FW_BUF_SIZE;
5304 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5308 rc = zlib_inflate(bp->strm, Z_FINISH);
5309 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5310 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5313 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5314 if (bp->gunzip_outlen & 0x3)
5315 netdev_err(bp->dev, "Firmware decompression error:"
5316 " gunzip_outlen (%d) not aligned\n",
5318 bp->gunzip_outlen >>= 2;
5320 zlib_inflateEnd(bp->strm);
5322 if (rc == Z_STREAM_END)
5328 /* nic load/unload */
5331 * General service functions
5334 /* send a NIG loopback debug packet */
5335 static void bnx2x_lb_pckt(struct bnx2x *bp)
5339 /* Ethernet source and destination addresses */
5340 wb_write[0] = 0x55555555;
5341 wb_write[1] = 0x55555555;
5342 wb_write[2] = 0x20; /* SOP */
5343 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5345 /* NON-IP protocol */
5346 wb_write[0] = 0x09000000;
5347 wb_write[1] = 0x55555555;
5348 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5349 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5352 /* some of the internal memories
5353 * are not directly readable from the driver
5354 * to test them we send debug packets
5356 static int bnx2x_int_mem_test(struct bnx2x *bp)
5362 if (CHIP_REV_IS_FPGA(bp))
5364 else if (CHIP_REV_IS_EMUL(bp))
5369 /* Disable inputs of parser neighbor blocks */
5370 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5371 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5372 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5373 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5375 /* Write 0 to parser credits for CFC search request */
5376 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5378 /* send Ethernet packet */
5381 /* TODO do i reset NIG statistic? */
5382 /* Wait until NIG register shows 1 packet of size 0x10 */
5383 count = 1000 * factor;
5386 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5387 val = *bnx2x_sp(bp, wb_data[0]);
5395 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5399 /* Wait until PRS register shows 1 packet */
5400 count = 1000 * factor;
5402 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5410 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5414 /* Reset and init BRB, PRS */
5415 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5417 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5419 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5420 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5422 DP(NETIF_MSG_HW, "part2\n");
5424 /* Disable inputs of parser neighbor blocks */
5425 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5426 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5427 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5428 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5430 /* Write 0 to parser credits for CFC search request */
5431 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5433 /* send 10 Ethernet packets */
5434 for (i = 0; i < 10; i++)
5437 /* Wait until NIG register shows 10 + 1
5438 packets of size 11*0x10 = 0xb0 */
5439 count = 1000 * factor;
5442 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5443 val = *bnx2x_sp(bp, wb_data[0]);
5451 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5455 /* Wait until PRS register shows 2 packets */
5456 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5458 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5460 /* Write 1 to parser credits for CFC search request */
5461 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5463 /* Wait until PRS register shows 3 packets */
5464 msleep(10 * factor);
5465 /* Wait until NIG register shows 1 packet of size 0x10 */
5466 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5468 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5470 /* clear NIG EOP FIFO */
5471 for (i = 0; i < 11; i++)
5472 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5473 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5475 BNX2X_ERR("clear of NIG failed\n");
5479 /* Reset and init BRB, PRS, NIG */
5480 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5482 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5484 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5485 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5488 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5491 /* Enable inputs of parser neighbor blocks */
5492 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5493 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5494 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5495 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5497 DP(NETIF_MSG_HW, "done\n");
5502 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5504 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5505 if (!CHIP_IS_E1x(bp))
5506 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5508 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5509 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5510 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5512 * mask read length error interrupts in brb for parser
5513 * (parsing unit and 'checksum and crc' unit)
5514 * these errors are legal (PU reads fixed length and CAC can cause
5515 * read length error on truncated packets)
5517 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5518 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5519 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5520 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5521 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5522 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5523 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5524 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5525 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5526 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5527 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5528 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5529 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5530 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5531 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5532 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5533 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5534 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5535 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5537 if (CHIP_REV_IS_FPGA(bp))
5538 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5539 else if (!CHIP_IS_E1x(bp))
5540 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5541 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5542 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5543 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5544 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5545 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5547 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5548 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5549 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5550 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5551 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5553 if (!CHIP_IS_E1x(bp))
5554 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5555 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5557 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5558 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5559 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5560 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5563 static void bnx2x_reset_common(struct bnx2x *bp)
5568 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5571 if (CHIP_IS_E3(bp)) {
5572 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5573 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5576 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5579 static void bnx2x_setup_dmae(struct bnx2x *bp)
5582 spin_lock_init(&bp->dmae_lock);
5585 static void bnx2x_init_pxp(struct bnx2x *bp)
5588 int r_order, w_order;
5590 pci_read_config_word(bp->pdev,
5591 bp->pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl);
5592 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5593 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5595 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5597 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5601 bnx2x_init_pxp_arb(bp, r_order, w_order);
5604 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5614 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5615 SHARED_HW_CFG_FAN_FAILURE_MASK;
5617 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5621 * The fan failure mechanism is usually related to the PHY type since
5622 * the power consumption of the board is affected by the PHY. Currently,
5623 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5625 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5626 for (port = PORT_0; port < PORT_MAX; port++) {
5628 bnx2x_fan_failure_det_req(
5630 bp->common.shmem_base,
5631 bp->common.shmem2_base,
5635 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5637 if (is_required == 0)
5640 /* Fan failure is indicated by SPIO 5 */
5641 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5642 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5644 /* set to active low mode */
5645 val = REG_RD(bp, MISC_REG_SPIO_INT);
5646 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5647 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5648 REG_WR(bp, MISC_REG_SPIO_INT, val);
5650 /* enable interrupt to signal the IGU */
5651 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5652 val |= (1 << MISC_REGISTERS_SPIO_5);
5653 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5656 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5662 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5665 switch (BP_ABS_FUNC(bp)) {
5667 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5670 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5673 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5676 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5679 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5682 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5685 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5688 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5694 REG_WR(bp, offset, pretend_func_num);
5696 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5699 void bnx2x_pf_disable(struct bnx2x *bp)
5701 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5702 val &= ~IGU_PF_CONF_FUNC_EN;
5704 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5705 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5706 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5709 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5711 u32 shmem_base[2], shmem2_base[2];
5712 shmem_base[0] = bp->common.shmem_base;
5713 shmem2_base[0] = bp->common.shmem2_base;
5714 if (!CHIP_IS_E1x(bp)) {
5716 SHMEM2_RD(bp, other_shmem_base_addr);
5718 SHMEM2_RD(bp, other_shmem2_base_addr);
5720 bnx2x_acquire_phy_lock(bp);
5721 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5722 bp->common.chip_id);
5723 bnx2x_release_phy_lock(bp);
5727 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5729 * @bp: driver handle
5731 static int bnx2x_init_hw_common(struct bnx2x *bp)
5735 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5737 bnx2x_reset_common(bp);
5738 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5741 if (CHIP_IS_E3(bp)) {
5742 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5743 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5745 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5747 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5749 if (!CHIP_IS_E1x(bp)) {
5753 * 4-port mode or 2-port mode we need to turn of master-enable
5754 * for everyone, after that, turn it back on for self.
5755 * so, we disregard multi-function or not, and always disable
5756 * for all functions on the given path, this means 0,2,4,6 for
5757 * path 0 and 1,3,5,7 for path 1
5759 for (abs_func_id = BP_PATH(bp);
5760 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5761 if (abs_func_id == BP_ABS_FUNC(bp)) {
5763 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5768 bnx2x_pretend_func(bp, abs_func_id);
5769 /* clear pf enable */
5770 bnx2x_pf_disable(bp);
5771 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5775 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5776 if (CHIP_IS_E1(bp)) {
5777 /* enable HW interrupt from PXP on USDM overflow
5778 bit 16 on INT_MASK_0 */
5779 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5782 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5786 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5787 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5788 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5789 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5790 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5791 /* make sure this value is 0 */
5792 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5794 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5795 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5796 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5797 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5798 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5801 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5803 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5804 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5806 /* let the HW do it's magic ... */
5808 /* finish PXP init */
5809 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5811 BNX2X_ERR("PXP2 CFG failed\n");
5814 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5816 BNX2X_ERR("PXP2 RD_INIT failed\n");
5820 /* Timers bug workaround E2 only. We need to set the entire ILT to
5821 * have entries with value "0" and valid bit on.
5822 * This needs to be done by the first PF that is loaded in a path
5823 * (i.e. common phase)
5825 if (!CHIP_IS_E1x(bp)) {
5826 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5827 * (i.e. vnic3) to start even if it is marked as "scan-off".
5828 * This occurs when a different function (func2,3) is being marked
5829 * as "scan-off". Real-life scenario for example: if a driver is being
5830 * load-unloaded while func6,7 are down. This will cause the timer to access
5831 * the ilt, translate to a logical address and send a request to read/write.
5832 * Since the ilt for the function that is down is not valid, this will cause
5833 * a translation error which is unrecoverable.
5834 * The Workaround is intended to make sure that when this happens nothing fatal
5835 * will occur. The workaround:
5836 * 1. First PF driver which loads on a path will:
5837 * a. After taking the chip out of reset, by using pretend,
5838 * it will write "0" to the following registers of
5840 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5841 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5842 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5843 * And for itself it will write '1' to
5844 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5845 * dmae-operations (writing to pram for example.)
5846 * note: can be done for only function 6,7 but cleaner this
5848 * b. Write zero+valid to the entire ILT.
5849 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5850 * VNIC3 (of that port). The range allocated will be the
5851 * entire ILT. This is needed to prevent ILT range error.
5852 * 2. Any PF driver load flow:
5853 * a. ILT update with the physical addresses of the allocated
5855 * b. Wait 20msec. - note that this timeout is needed to make
5856 * sure there are no requests in one of the PXP internal
5857 * queues with "old" ILT addresses.
5858 * c. PF enable in the PGLC.
5859 * d. Clear the was_error of the PF in the PGLC. (could have
5860 * occured while driver was down)
5861 * e. PF enable in the CFC (WEAK + STRONG)
5862 * f. Timers scan enable
5863 * 3. PF driver unload flow:
5864 * a. Clear the Timers scan_en.
5865 * b. Polling for scan_on=0 for that PF.
5866 * c. Clear the PF enable bit in the PXP.
5867 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5868 * e. Write zero+valid to all ILT entries (The valid bit must
5870 * f. If this is VNIC 3 of a port then also init
5871 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5872 * to the last enrty in the ILT.
5875 * Currently the PF error in the PGLC is non recoverable.
5876 * In the future the there will be a recovery routine for this error.
5877 * Currently attention is masked.
5878 * Having an MCP lock on the load/unload process does not guarantee that
5879 * there is no Timer disable during Func6/7 enable. This is because the
5880 * Timers scan is currently being cleared by the MCP on FLR.
5881 * Step 2.d can be done only for PF6/7 and the driver can also check if
5882 * there is error before clearing it. But the flow above is simpler and
5884 * All ILT entries are written by zero+valid and not just PF6/7
5885 * ILT entries since in the future the ILT entries allocation for
5886 * PF-s might be dynamic.
5888 struct ilt_client_info ilt_cli;
5889 struct bnx2x_ilt ilt;
5890 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5891 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5893 /* initialize dummy TM client */
5895 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5896 ilt_cli.client_num = ILT_CLIENT_TM;
5898 /* Step 1: set zeroes to all ilt page entries with valid bit on
5899 * Step 2: set the timers first/last ilt entry to point
5900 * to the entire range to prevent ILT range error for 3rd/4th
5901 * vnic (this code assumes existance of the vnic)
5903 * both steps performed by call to bnx2x_ilt_client_init_op()
5904 * with dummy TM client
5906 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5907 * and his brother are split registers
5909 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5910 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5911 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5913 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5914 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5915 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5919 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5920 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5922 if (!CHIP_IS_E1x(bp)) {
5923 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5924 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5925 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
5927 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
5929 /* let the HW do it's magic ... */
5932 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5933 } while (factor-- && (val != 1));
5936 BNX2X_ERR("ATC_INIT failed\n");
5941 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
5943 /* clean the DMAE memory */
5945 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
5947 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
5949 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
5951 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
5953 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
5955 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5956 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5957 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5958 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5960 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
5963 /* QM queues pointers table */
5964 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5966 /* soft reset pulse */
5967 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5968 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5971 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
5974 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
5975 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5976 if (!CHIP_REV_IS_SLOW(bp))
5977 /* enable hw interrupt from doorbell Q */
5978 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5980 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5982 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5983 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5985 if (!CHIP_IS_E1(bp))
5986 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
5988 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
5989 /* Bit-map indicating which L2 hdrs may appear
5990 * after the basic Ethernet header
5992 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
5993 bp->path_has_ovlan ? 7 : 6);
5995 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
5996 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
5997 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
5998 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6000 if (!CHIP_IS_E1x(bp)) {
6001 /* reset VFC memories */
6002 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6003 VFC_MEMORIES_RST_REG_CAM_RST |
6004 VFC_MEMORIES_RST_REG_RAM_RST);
6005 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6006 VFC_MEMORIES_RST_REG_CAM_RST |
6007 VFC_MEMORIES_RST_REG_RAM_RST);
6012 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6013 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6014 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6015 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6018 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6020 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6023 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6024 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6025 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6027 if (!CHIP_IS_E1x(bp))
6028 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6029 bp->path_has_ovlan ? 7 : 6);
6031 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6033 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6036 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6037 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6038 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6039 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6040 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6041 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6042 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6043 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6044 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6045 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6047 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6049 if (sizeof(union cdu_context) != 1024)
6050 /* we currently assume that a context is 1024 bytes */
6051 dev_alert(&bp->pdev->dev, "please adjust the size "
6052 "of cdu_context(%ld)\n",
6053 (long)sizeof(union cdu_context));
6055 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6056 val = (4 << 24) + (0 << 12) + 1024;
6057 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6059 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6060 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6061 /* enable context validation interrupt from CFC */
6062 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6064 /* set the thresholds to prevent CFC/CDU race */
6065 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6067 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6069 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6070 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6072 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6073 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6075 /* Reset PCIE errors for debug */
6076 REG_WR(bp, 0x2814, 0xffffffff);
6077 REG_WR(bp, 0x3820, 0xffffffff);
6079 if (!CHIP_IS_E1x(bp)) {
6080 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6081 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6082 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6083 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6084 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6085 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6086 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6087 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6088 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6089 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6090 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6093 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6094 if (!CHIP_IS_E1(bp)) {
6095 /* in E3 this done in per-port section */
6096 if (!CHIP_IS_E3(bp))
6097 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6099 if (CHIP_IS_E1H(bp))
6100 /* not applicable for E2 (and above ...) */
6101 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6103 if (CHIP_REV_IS_SLOW(bp))
6106 /* finish CFC init */
6107 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6109 BNX2X_ERR("CFC LL_INIT failed\n");
6112 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6114 BNX2X_ERR("CFC AC_INIT failed\n");
6117 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6119 BNX2X_ERR("CFC CAM_INIT failed\n");
6122 REG_WR(bp, CFC_REG_DEBUG0, 0);
6124 if (CHIP_IS_E1(bp)) {
6125 /* read NIG statistic
6126 to see if this is our first up since powerup */
6127 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6128 val = *bnx2x_sp(bp, wb_data[0]);
6130 /* do internal memory self test */
6131 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6132 BNX2X_ERR("internal mem self test failed\n");
6137 bnx2x_setup_fan_failure_detection(bp);
6139 /* clear PXP2 attentions */
6140 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6142 bnx2x_enable_blocks_attention(bp);
6143 bnx2x_enable_blocks_parity(bp);
6145 if (!BP_NOMCP(bp)) {
6146 if (CHIP_IS_E1x(bp))
6147 bnx2x__common_init_phy(bp);
6149 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6155 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6157 * @bp: driver handle
6159 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6161 int rc = bnx2x_init_hw_common(bp);
6166 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6168 bnx2x__common_init_phy(bp);
6173 static int bnx2x_init_hw_port(struct bnx2x *bp)
6175 int port = BP_PORT(bp);
6176 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6180 bnx2x__link_reset(bp);
6182 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6184 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6186 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6187 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6188 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6190 /* Timers bug workaround: disables the pf_master bit in pglue at
6191 * common phase, we need to enable it here before any dmae access are
6192 * attempted. Therefore we manually added the enable-master to the
6193 * port phase (it also happens in the function phase)
6195 if (!CHIP_IS_E1x(bp))
6196 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6198 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6199 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6200 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6201 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6203 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6204 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6205 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6206 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6208 /* QM cid (connection) count */
6209 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6212 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6213 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6214 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6217 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6219 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6220 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6223 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6224 else if (bp->dev->mtu > 4096) {
6225 if (bp->flags & ONE_PORT_FLAG)
6229 /* (24*1024 + val*4)/256 */
6230 low = 96 + (val/64) +
6231 ((val % 64) ? 1 : 0);
6234 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6235 high = low + 56; /* 14*1024/256 */
6236 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6237 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6240 if (CHIP_MODE_IS_4_PORT(bp))
6241 REG_WR(bp, (BP_PORT(bp) ?
6242 BRB1_REG_MAC_GUARANTIED_1 :
6243 BRB1_REG_MAC_GUARANTIED_0), 40);
6246 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6247 if (CHIP_IS_E3B0(bp))
6248 /* Ovlan exists only if we are in multi-function +
6249 * switch-dependent mode, in switch-independent there
6250 * is no ovlan headers
6252 REG_WR(bp, BP_PORT(bp) ?
6253 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6254 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6255 (bp->path_has_ovlan ? 7 : 6));
6257 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6258 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6259 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6260 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6262 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6263 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6264 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6265 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6267 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6268 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6270 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6272 if (CHIP_IS_E1x(bp)) {
6273 /* configure PBF to work without PAUSE mtu 9000 */
6274 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6276 /* update threshold */
6277 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6278 /* update init credit */
6279 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6282 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6284 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6288 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6290 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6291 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6293 if (CHIP_IS_E1(bp)) {
6294 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6295 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6297 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6299 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6301 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6302 /* init aeu_mask_attn_func_0/1:
6303 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6304 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6305 * bits 4-7 are used for "per vn group attention" */
6306 val = IS_MF(bp) ? 0xF7 : 0x7;
6307 /* Enable DCBX attention for all but E1 */
6308 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6309 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6311 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6313 if (!CHIP_IS_E1x(bp)) {
6314 /* Bit-map indicating which L2 hdrs may appear after the
6315 * basic Ethernet header
6317 REG_WR(bp, BP_PORT(bp) ?
6318 NIG_REG_P1_HDRS_AFTER_BASIC :
6319 NIG_REG_P0_HDRS_AFTER_BASIC,
6320 IS_MF_SD(bp) ? 7 : 6);
6323 REG_WR(bp, BP_PORT(bp) ?
6324 NIG_REG_LLH1_MF_MODE :
6325 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6327 if (!CHIP_IS_E3(bp))
6328 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6330 if (!CHIP_IS_E1(bp)) {
6331 /* 0x2 disable mf_ov, 0x1 enable */
6332 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6333 (IS_MF_SD(bp) ? 0x1 : 0x2));
6335 if (!CHIP_IS_E1x(bp)) {
6337 switch (bp->mf_mode) {
6338 case MULTI_FUNCTION_SD:
6341 case MULTI_FUNCTION_SI:
6346 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6347 NIG_REG_LLH0_CLS_TYPE), val);
6350 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6351 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6352 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6357 /* If SPIO5 is set to generate interrupts, enable it for this port */
6358 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6359 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6360 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6361 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6362 val = REG_RD(bp, reg_addr);
6363 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6364 REG_WR(bp, reg_addr, val);
6370 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6375 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6377 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6379 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6382 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6384 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6387 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6389 u32 i, base = FUNC_ILT_BASE(func);
6390 for (i = base; i < base + ILT_PER_FUNC; i++)
6391 bnx2x_ilt_wr(bp, i, 0);
6394 static int bnx2x_init_hw_func(struct bnx2x *bp)
6396 int port = BP_PORT(bp);
6397 int func = BP_FUNC(bp);
6398 int init_phase = PHASE_PF0 + func;
6399 struct bnx2x_ilt *ilt = BP_ILT(bp);
6402 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6403 int i, main_mem_width;
6405 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6407 /* FLR cleanup - hmmm */
6408 if (!CHIP_IS_E1x(bp))
6409 bnx2x_pf_flr_clnup(bp);
6411 /* set MSI reconfigure capability */
6412 if (bp->common.int_block == INT_BLOCK_HC) {
6413 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6414 val = REG_RD(bp, addr);
6415 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6416 REG_WR(bp, addr, val);
6419 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6420 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6423 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6425 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6426 ilt->lines[cdu_ilt_start + i].page =
6427 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6428 ilt->lines[cdu_ilt_start + i].page_mapping =
6429 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6430 /* cdu ilt pages are allocated manually so there's no need to
6433 bnx2x_ilt_init_op(bp, INITOP_SET);
6436 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6438 /* T1 hash bits value determines the T1 number of entries */
6439 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6444 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6445 #endif /* BCM_CNIC */
6447 if (!CHIP_IS_E1x(bp)) {
6448 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6450 /* Turn on a single ISR mode in IGU if driver is going to use
6453 if (!(bp->flags & USING_MSIX_FLAG))
6454 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6456 * Timers workaround bug: function init part.
6457 * Need to wait 20msec after initializing ILT,
6458 * needed to make sure there are no requests in
6459 * one of the PXP internal queues with "old" ILT addresses
6463 * Master enable - Due to WB DMAE writes performed before this
6464 * register is re-initialized as part of the regular function
6467 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6468 /* Enable the function in IGU */
6469 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6474 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6476 if (!CHIP_IS_E1x(bp))
6477 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6479 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6480 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6481 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6482 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6483 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6484 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6485 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6486 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6487 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6488 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6489 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6490 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6491 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6493 if (!CHIP_IS_E1x(bp))
6494 REG_WR(bp, QM_REG_PF_EN, 1);
6496 if (!CHIP_IS_E1x(bp)) {
6497 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6498 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6499 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6500 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6502 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6504 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6505 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6506 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6507 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6508 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6509 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6510 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6511 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6512 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6513 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6514 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6515 if (!CHIP_IS_E1x(bp))
6516 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6518 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6520 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6522 if (!CHIP_IS_E1x(bp))
6523 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6526 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6527 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6530 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6532 /* HC init per function */
6533 if (bp->common.int_block == INT_BLOCK_HC) {
6534 if (CHIP_IS_E1H(bp)) {
6535 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6537 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6538 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6540 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6543 int num_segs, sb_idx, prod_offset;
6545 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6547 if (!CHIP_IS_E1x(bp)) {
6548 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6549 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6552 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6554 if (!CHIP_IS_E1x(bp)) {
6558 * E2 mode: address 0-135 match to the mapping memory;
6559 * 136 - PF0 default prod; 137 - PF1 default prod;
6560 * 138 - PF2 default prod; 139 - PF3 default prod;
6561 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6562 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6565 * E1.5 mode - In backward compatible mode;
6566 * for non default SB; each even line in the memory
6567 * holds the U producer and each odd line hold
6568 * the C producer. The first 128 producers are for
6569 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6570 * producers are for the DSB for each PF.
6571 * Each PF has five segments: (the order inside each
6572 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6573 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6574 * 144-147 attn prods;
6576 /* non-default-status-blocks */
6577 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6578 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6579 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6580 prod_offset = (bp->igu_base_sb + sb_idx) *
6583 for (i = 0; i < num_segs; i++) {
6584 addr = IGU_REG_PROD_CONS_MEMORY +
6585 (prod_offset + i) * 4;
6586 REG_WR(bp, addr, 0);
6588 /* send consumer update with value 0 */
6589 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6590 USTORM_ID, 0, IGU_INT_NOP, 1);
6591 bnx2x_igu_clear_sb(bp,
6592 bp->igu_base_sb + sb_idx);
6595 /* default-status-blocks */
6596 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6597 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6599 if (CHIP_MODE_IS_4_PORT(bp))
6600 dsb_idx = BP_FUNC(bp);
6602 dsb_idx = BP_E1HVN(bp);
6604 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6605 IGU_BC_BASE_DSB_PROD + dsb_idx :
6606 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6608 for (i = 0; i < (num_segs * E1HVN_MAX);
6610 addr = IGU_REG_PROD_CONS_MEMORY +
6611 (prod_offset + i)*4;
6612 REG_WR(bp, addr, 0);
6614 /* send consumer update with 0 */
6615 if (CHIP_INT_MODE_IS_BC(bp)) {
6616 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6617 USTORM_ID, 0, IGU_INT_NOP, 1);
6618 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6619 CSTORM_ID, 0, IGU_INT_NOP, 1);
6620 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6621 XSTORM_ID, 0, IGU_INT_NOP, 1);
6622 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6623 TSTORM_ID, 0, IGU_INT_NOP, 1);
6624 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6625 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6627 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6628 USTORM_ID, 0, IGU_INT_NOP, 1);
6629 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6630 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6632 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6634 /* !!! these should become driver const once
6635 rf-tool supports split-68 const */
6636 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6637 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6638 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6639 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6640 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6641 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6645 /* Reset PCIE errors for debug */
6646 REG_WR(bp, 0x2114, 0xffffffff);
6647 REG_WR(bp, 0x2120, 0xffffffff);
6649 if (CHIP_IS_E1x(bp)) {
6650 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6651 main_mem_base = HC_REG_MAIN_MEMORY +
6652 BP_PORT(bp) * (main_mem_size * 4);
6653 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6656 val = REG_RD(bp, main_mem_prty_clr);
6658 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6660 "function init (0x%x)!\n", val);
6662 /* Clear "false" parity errors in MSI-X table */
6663 for (i = main_mem_base;
6664 i < main_mem_base + main_mem_size * 4;
6665 i += main_mem_width) {
6666 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6667 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6668 i, main_mem_width / 4);
6670 /* Clear HC parity attention */
6671 REG_RD(bp, main_mem_prty_clr);
6674 #ifdef BNX2X_STOP_ON_ERROR
6675 /* Enable STORMs SP logging */
6676 REG_WR8(bp, BAR_USTRORM_INTMEM +
6677 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6678 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6679 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6680 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6681 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6682 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6683 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6686 bnx2x_phy_probe(&bp->link_params);
6692 void bnx2x_free_mem(struct bnx2x *bp)
6695 bnx2x_free_fp_mem(bp);
6696 /* end of fastpath */
6698 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6699 sizeof(struct host_sp_status_block));
6701 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6702 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6704 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6705 sizeof(struct bnx2x_slowpath));
6707 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6710 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6712 BNX2X_FREE(bp->ilt->lines);
6715 if (!CHIP_IS_E1x(bp))
6716 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6717 sizeof(struct host_hc_status_block_e2));
6719 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6720 sizeof(struct host_hc_status_block_e1x));
6722 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6725 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6727 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6728 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6731 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6735 /* number of eth_queues */
6736 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6738 /* Total number of FW statistics requests =
6739 * 1 for port stats + 1 for PF stats + num_eth_queues */
6740 bp->fw_stats_num = 2 + num_queue_stats;
6743 /* Request is built from stats_query_header and an array of
6744 * stats_query_cmd_group each of which contains
6745 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6746 * configured in the stats_query_header.
6748 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6749 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6751 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6752 num_groups * sizeof(struct stats_query_cmd_group);
6754 /* Data for statistics requests + stats_conter
6756 * stats_counter holds per-STORM counters that are incremented
6757 * when STORM has finished with the current request.
6759 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6760 sizeof(struct per_pf_stats) +
6761 sizeof(struct per_queue_stats) * num_queue_stats +
6762 sizeof(struct stats_counter);
6764 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6765 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6768 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6769 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6771 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6772 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6774 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6775 bp->fw_stats_req_sz;
6779 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6780 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6785 int bnx2x_alloc_mem(struct bnx2x *bp)
6788 if (!CHIP_IS_E1x(bp))
6789 /* size = the status block + ramrod buffers */
6790 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6791 sizeof(struct host_hc_status_block_e2));
6793 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6794 sizeof(struct host_hc_status_block_e1x));
6796 /* allocate searcher T2 table */
6797 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6801 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6802 sizeof(struct host_sp_status_block));
6804 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6805 sizeof(struct bnx2x_slowpath));
6807 /* Allocated memory for FW statistics */
6808 if (bnx2x_alloc_fw_stats_mem(bp))
6811 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6813 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6816 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6818 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6821 /* Slow path ring */
6822 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6825 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6826 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6830 /* need to be done at the end, since it's self adjusting to amount
6831 * of memory available for RSS queues
6833 if (bnx2x_alloc_fp_mem(bp))
6843 * Init service functions
6846 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6847 struct bnx2x_vlan_mac_obj *obj, bool set,
6848 int mac_type, unsigned long *ramrod_flags)
6851 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6853 memset(&ramrod_param, 0, sizeof(ramrod_param));
6855 /* Fill general parameters */
6856 ramrod_param.vlan_mac_obj = obj;
6857 ramrod_param.ramrod_flags = *ramrod_flags;
6859 /* Fill a user request section if needed */
6860 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6861 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6863 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6865 /* Set the command: ADD or DEL */
6867 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6869 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6872 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6874 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6878 int bnx2x_del_all_macs(struct bnx2x *bp,
6879 struct bnx2x_vlan_mac_obj *mac_obj,
6880 int mac_type, bool wait_for_comp)
6883 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6885 /* Wait for completion of requested */
6887 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6889 /* Set the mac type of addresses we want to clear */
6890 __set_bit(mac_type, &vlan_mac_flags);
6892 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6894 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
6899 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
6901 unsigned long ramrod_flags = 0;
6903 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
6905 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6906 /* Eth MAC is set on RSS leading client (fp[0]) */
6907 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6908 BNX2X_ETH_MAC, &ramrod_flags);
6911 int bnx2x_setup_leading(struct bnx2x *bp)
6913 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
6917 * bnx2x_set_int_mode - configure interrupt mode
6919 * @bp: driver handle
6921 * In case of MSI-X it will also try to enable MSI-X.
6923 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6927 bnx2x_enable_msi(bp);
6928 /* falling through... */
6930 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
6931 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6934 /* Set number of queues according to bp->multi_mode value */
6935 bnx2x_set_num_queues(bp);
6937 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6940 /* if we can't use MSI-X we only need one fp,
6941 * so try to enable MSI-X with the requested number of fp's
6942 * and fallback to MSI or legacy INTx with one fp
6944 if (bnx2x_enable_msix(bp)) {
6945 /* failed to enable MSI-X */
6948 "Multi requested but failed to "
6949 "enable MSI-X (%d), "
6950 "set number of queues to %d\n",
6952 1 + NON_ETH_CONTEXT_USE);
6953 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
6955 /* Try to enable MSI */
6956 if (!(bp->flags & DISABLE_MSI_FLAG))
6957 bnx2x_enable_msi(bp);
6963 /* must be called prioir to any HW initializations */
6964 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6966 return L2_ILT_LINES(bp);
6969 void bnx2x_ilt_set_info(struct bnx2x *bp)
6971 struct ilt_client_info *ilt_client;
6972 struct bnx2x_ilt *ilt = BP_ILT(bp);
6975 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6976 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6979 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6980 ilt_client->client_num = ILT_CLIENT_CDU;
6981 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6982 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6983 ilt_client->start = line;
6984 line += bnx2x_cid_ilt_lines(bp);
6986 line += CNIC_ILT_LINES;
6988 ilt_client->end = line - 1;
6990 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6991 "flags 0x%x, hw psz %d\n",
6994 ilt_client->page_size,
6996 ilog2(ilt_client->page_size >> 12));
6999 if (QM_INIT(bp->qm_cid_count)) {
7000 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7001 ilt_client->client_num = ILT_CLIENT_QM;
7002 ilt_client->page_size = QM_ILT_PAGE_SZ;
7003 ilt_client->flags = 0;
7004 ilt_client->start = line;
7006 /* 4 bytes for each cid */
7007 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7010 ilt_client->end = line - 1;
7012 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7013 "flags 0x%x, hw psz %d\n",
7016 ilt_client->page_size,
7018 ilog2(ilt_client->page_size >> 12));
7022 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7024 ilt_client->client_num = ILT_CLIENT_SRC;
7025 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7026 ilt_client->flags = 0;
7027 ilt_client->start = line;
7028 line += SRC_ILT_LINES;
7029 ilt_client->end = line - 1;
7031 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7032 "flags 0x%x, hw psz %d\n",
7035 ilt_client->page_size,
7037 ilog2(ilt_client->page_size >> 12));
7040 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7044 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7046 ilt_client->client_num = ILT_CLIENT_TM;
7047 ilt_client->page_size = TM_ILT_PAGE_SZ;
7048 ilt_client->flags = 0;
7049 ilt_client->start = line;
7050 line += TM_ILT_LINES;
7051 ilt_client->end = line - 1;
7053 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7054 "flags 0x%x, hw psz %d\n",
7057 ilt_client->page_size,
7059 ilog2(ilt_client->page_size >> 12));
7062 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7064 BUG_ON(line > ILT_MAX_LINES);
7068 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7070 * @bp: driver handle
7071 * @fp: pointer to fastpath
7072 * @init_params: pointer to parameters structure
7074 * parameters configured:
7075 * - HC configuration
7076 * - Queue's CDU context
7078 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7079 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7083 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7084 if (!IS_FCOE_FP(fp)) {
7085 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7086 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7088 /* If HC is supporterd, enable host coalescing in the transition
7091 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7092 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7095 init_params->rx.hc_rate = bp->rx_ticks ?
7096 (1000000 / bp->rx_ticks) : 0;
7097 init_params->tx.hc_rate = bp->tx_ticks ?
7098 (1000000 / bp->tx_ticks) : 0;
7101 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7105 * CQ index among the SB indices: FCoE clients uses the default
7106 * SB, therefore it's different.
7108 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7109 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7112 /* set maximum number of COSs supported by this queue */
7113 init_params->max_cos = fp->max_cos;
7115 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7116 fp->index, init_params->max_cos);
7118 /* set the context pointers queue object */
7119 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7120 init_params->cxts[cos] =
7121 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7124 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7125 struct bnx2x_queue_state_params *q_params,
7126 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7127 int tx_index, bool leading)
7129 memset(tx_only_params, 0, sizeof(*tx_only_params));
7131 /* Set the command */
7132 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7134 /* Set tx-only QUEUE flags: don't zero statistics */
7135 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7137 /* choose the index of the cid to send the slow path on */
7138 tx_only_params->cid_index = tx_index;
7140 /* Set general TX_ONLY_SETUP parameters */
7141 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7143 /* Set Tx TX_ONLY_SETUP parameters */
7144 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7146 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7147 "cos %d, primary cid %d, cid %d, "
7148 "client id %d, sp-client id %d, flags %lx",
7149 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7150 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7151 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7153 /* send the ramrod */
7154 return bnx2x_queue_state_change(bp, q_params);
7159 * bnx2x_setup_queue - setup queue
7161 * @bp: driver handle
7162 * @fp: pointer to fastpath
7163 * @leading: is leading
7165 * This function performs 2 steps in a Queue state machine
7166 * actually: 1) RESET->INIT 2) INIT->SETUP
7169 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7172 struct bnx2x_queue_state_params q_params = {0};
7173 struct bnx2x_queue_setup_params *setup_params =
7174 &q_params.params.setup;
7175 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7176 &q_params.params.tx_only;
7180 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
7182 /* reset IGU state skip FCoE L2 queue */
7183 if (!IS_FCOE_FP(fp))
7184 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7187 q_params.q_obj = &fp->q_obj;
7188 /* We want to wait for completion in this context */
7189 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7191 /* Prepare the INIT parameters */
7192 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7194 /* Set the command */
7195 q_params.cmd = BNX2X_Q_CMD_INIT;
7197 /* Change the state to INIT */
7198 rc = bnx2x_queue_state_change(bp, &q_params);
7200 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7204 DP(BNX2X_MSG_SP, "init complete");
7207 /* Now move the Queue to the SETUP state... */
7208 memset(setup_params, 0, sizeof(*setup_params));
7210 /* Set QUEUE flags */
7211 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7213 /* Set general SETUP parameters */
7214 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7215 FIRST_TX_COS_INDEX);
7217 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7218 &setup_params->rxq_params);
7220 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7221 FIRST_TX_COS_INDEX);
7223 /* Set the command */
7224 q_params.cmd = BNX2X_Q_CMD_SETUP;
7226 /* Change the state to SETUP */
7227 rc = bnx2x_queue_state_change(bp, &q_params);
7229 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7233 /* loop through the relevant tx-only indices */
7234 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7235 tx_index < fp->max_cos;
7238 /* prepare and send tx-only ramrod*/
7239 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7240 tx_only_params, tx_index, leading);
7242 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7243 fp->index, tx_index);
7251 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7253 struct bnx2x_fastpath *fp = &bp->fp[index];
7254 struct bnx2x_fp_txdata *txdata;
7255 struct bnx2x_queue_state_params q_params = {0};
7258 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
7260 q_params.q_obj = &fp->q_obj;
7261 /* We want to wait for completion in this context */
7262 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7265 /* close tx-only connections */
7266 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7267 tx_index < fp->max_cos;
7270 /* ascertain this is a normal queue*/
7271 txdata = &fp->txdata[tx_index];
7273 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7276 /* send halt terminate on tx-only connection */
7277 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7278 memset(&q_params.params.terminate, 0,
7279 sizeof(q_params.params.terminate));
7280 q_params.params.terminate.cid_index = tx_index;
7282 rc = bnx2x_queue_state_change(bp, &q_params);
7286 /* send halt terminate on tx-only connection */
7287 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7288 memset(&q_params.params.cfc_del, 0,
7289 sizeof(q_params.params.cfc_del));
7290 q_params.params.cfc_del.cid_index = tx_index;
7291 rc = bnx2x_queue_state_change(bp, &q_params);
7295 /* Stop the primary connection: */
7296 /* ...halt the connection */
7297 q_params.cmd = BNX2X_Q_CMD_HALT;
7298 rc = bnx2x_queue_state_change(bp, &q_params);
7302 /* ...terminate the connection */
7303 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7304 memset(&q_params.params.terminate, 0,
7305 sizeof(q_params.params.terminate));
7306 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7307 rc = bnx2x_queue_state_change(bp, &q_params);
7310 /* ...delete cfc entry */
7311 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7312 memset(&q_params.params.cfc_del, 0,
7313 sizeof(q_params.params.cfc_del));
7314 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7315 return bnx2x_queue_state_change(bp, &q_params);
7319 static void bnx2x_reset_func(struct bnx2x *bp)
7321 int port = BP_PORT(bp);
7322 int func = BP_FUNC(bp);
7325 /* Disable the function in the FW */
7326 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7327 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7328 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7329 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7332 for_each_eth_queue(bp, i) {
7333 struct bnx2x_fastpath *fp = &bp->fp[i];
7334 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7335 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7341 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7342 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7346 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7347 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7350 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7351 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7355 if (bp->common.int_block == INT_BLOCK_HC) {
7356 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7357 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7359 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7360 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7364 /* Disable Timer scan */
7365 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7367 * Wait for at least 10ms and up to 2 second for the timers scan to
7370 for (i = 0; i < 200; i++) {
7372 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7377 bnx2x_clear_func_ilt(bp, func);
7379 /* Timers workaround bug for E2: if this is vnic-3,
7380 * we need to set the entire ilt range for this timers.
7382 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7383 struct ilt_client_info ilt_cli;
7384 /* use dummy TM client */
7385 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7387 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7388 ilt_cli.client_num = ILT_CLIENT_TM;
7390 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7393 /* this assumes that reset_port() called before reset_func()*/
7394 if (!CHIP_IS_E1x(bp))
7395 bnx2x_pf_disable(bp);
7400 static void bnx2x_reset_port(struct bnx2x *bp)
7402 int port = BP_PORT(bp);
7405 /* Reset physical Link */
7406 bnx2x__link_reset(bp);
7408 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7410 /* Do not rcv packets to BRB */
7411 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7412 /* Do not direct rcv packets that are not for MCP to the BRB */
7413 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7414 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7417 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7420 /* Check for BRB port occupancy */
7421 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7423 DP(NETIF_MSG_IFDOWN,
7424 "BRB1 is not empty %d blocks are occupied\n", val);
7426 /* TODO: Close Doorbell port? */
7429 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7431 struct bnx2x_func_state_params func_params = {0};
7433 /* Prepare parameters for function state transitions */
7434 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7436 func_params.f_obj = &bp->func_obj;
7437 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7439 func_params.params.hw_init.load_phase = load_code;
7441 return bnx2x_func_state_change(bp, &func_params);
7444 static inline int bnx2x_func_stop(struct bnx2x *bp)
7446 struct bnx2x_func_state_params func_params = {0};
7449 /* Prepare parameters for function state transitions */
7450 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7451 func_params.f_obj = &bp->func_obj;
7452 func_params.cmd = BNX2X_F_CMD_STOP;
7455 * Try to stop the function the 'good way'. If fails (in case
7456 * of a parity error during bnx2x_chip_cleanup()) and we are
7457 * not in a debug mode, perform a state transaction in order to
7458 * enable further HW_RESET transaction.
7460 rc = bnx2x_func_state_change(bp, &func_params);
7462 #ifdef BNX2X_STOP_ON_ERROR
7465 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7467 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7468 return bnx2x_func_state_change(bp, &func_params);
7476 * bnx2x_send_unload_req - request unload mode from the MCP.
7478 * @bp: driver handle
7479 * @unload_mode: requested function's unload mode
7481 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7483 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7486 int port = BP_PORT(bp);
7488 /* Select the UNLOAD request mode */
7489 if (unload_mode == UNLOAD_NORMAL)
7490 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7492 else if (bp->flags & NO_WOL_FLAG)
7493 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7496 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7497 u8 *mac_addr = bp->dev->dev_addr;
7499 /* The mac address is written to entries 1-4 to
7500 preserve entry 0 which is used by the PMF */
7501 u8 entry = (BP_E1HVN(bp) + 1)*8;
7503 val = (mac_addr[0] << 8) | mac_addr[1];
7504 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7506 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7507 (mac_addr[4] << 8) | mac_addr[5];
7508 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7510 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7513 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7515 /* Send the request to the MCP */
7517 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7519 int path = BP_PATH(bp);
7521 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7523 path, load_count[path][0], load_count[path][1],
7524 load_count[path][2]);
7525 load_count[path][0]--;
7526 load_count[path][1 + port]--;
7527 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7529 path, load_count[path][0], load_count[path][1],
7530 load_count[path][2]);
7531 if (load_count[path][0] == 0)
7532 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7533 else if (load_count[path][1 + port] == 0)
7534 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7536 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7543 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7545 * @bp: driver handle
7547 void bnx2x_send_unload_done(struct bnx2x *bp)
7549 /* Report UNLOAD_DONE to MCP */
7551 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7554 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7557 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7563 * (assumption: No Attention from MCP at this stage)
7564 * PMF probably in the middle of TXdisable/enable transaction
7565 * 1. Sync IRS for default SB
7566 * 2. Sync SP queue - this guarantes us that attention handling started
7567 * 3. Wait, that TXdisable/enable transaction completes
7569 * 1+2 guranty that if DCBx attention was scheduled it already changed
7570 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7571 * received complettion for the transaction the state is TX_STOPPED.
7572 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7576 /* make sure default SB ISR is done */
7578 synchronize_irq(bp->msix_table[0].vector);
7580 synchronize_irq(bp->pdev->irq);
7582 flush_workqueue(bnx2x_wq);
7584 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7585 BNX2X_F_STATE_STARTED && tout--)
7588 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7589 BNX2X_F_STATE_STARTED) {
7590 #ifdef BNX2X_STOP_ON_ERROR
7594 * Failed to complete the transaction in a "good way"
7595 * Force both transactions with CLR bit
7597 struct bnx2x_func_state_params func_params = {0};
7599 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7600 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7602 func_params.f_obj = &bp->func_obj;
7603 __set_bit(RAMROD_DRV_CLR_ONLY,
7604 &func_params.ramrod_flags);
7606 /* STARTED-->TX_ST0PPED */
7607 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7608 bnx2x_func_state_change(bp, &func_params);
7610 /* TX_ST0PPED-->STARTED */
7611 func_params.cmd = BNX2X_F_CMD_TX_START;
7612 return bnx2x_func_state_change(bp, &func_params);
7619 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7621 int port = BP_PORT(bp);
7624 struct bnx2x_mcast_ramrod_params rparam = {0};
7627 /* Wait until tx fastpath tasks complete */
7628 for_each_tx_queue(bp, i) {
7629 struct bnx2x_fastpath *fp = &bp->fp[i];
7631 for_each_cos_in_tx_queue(fp, cos)
7632 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7633 #ifdef BNX2X_STOP_ON_ERROR
7639 /* Give HW time to discard old tx messages */
7640 usleep_range(1000, 1000);
7642 /* Clean all ETH MACs */
7643 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7645 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7647 /* Clean up UC list */
7648 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7651 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7655 if (!CHIP_IS_E1(bp))
7656 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7658 /* Set "drop all" (stop Rx).
7659 * We need to take a netif_addr_lock() here in order to prevent
7660 * a race between the completion code and this code.
7662 netif_addr_lock_bh(bp->dev);
7663 /* Schedule the rx_mode command */
7664 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7665 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7667 bnx2x_set_storm_rx_mode(bp);
7669 /* Cleanup multicast configuration */
7670 rparam.mcast_obj = &bp->mcast_obj;
7671 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7673 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7675 netif_addr_unlock_bh(bp->dev);
7680 * Send the UNLOAD_REQUEST to the MCP. This will return if
7681 * this function should perform FUNC, PORT or COMMON HW
7684 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7687 * (assumption: No Attention from MCP at this stage)
7688 * PMF probably in the middle of TXdisable/enable transaction
7690 rc = bnx2x_func_wait_started(bp);
7692 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7693 #ifdef BNX2X_STOP_ON_ERROR
7698 /* Close multi and leading connections
7699 * Completions for ramrods are collected in a synchronous way
7701 for_each_queue(bp, i)
7702 if (bnx2x_stop_queue(bp, i))
7703 #ifdef BNX2X_STOP_ON_ERROR
7708 /* If SP settings didn't get completed so far - something
7709 * very wrong has happen.
7711 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7712 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7714 #ifndef BNX2X_STOP_ON_ERROR
7717 rc = bnx2x_func_stop(bp);
7719 BNX2X_ERR("Function stop failed!\n");
7720 #ifdef BNX2X_STOP_ON_ERROR
7725 /* Disable HW interrupts, NAPI */
7726 bnx2x_netif_stop(bp, 1);
7731 /* Reset the chip */
7732 rc = bnx2x_reset_hw(bp, reset_code);
7734 BNX2X_ERR("HW_RESET failed\n");
7737 /* Report UNLOAD_DONE to MCP */
7738 bnx2x_send_unload_done(bp);
7741 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7745 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7747 if (CHIP_IS_E1(bp)) {
7748 int port = BP_PORT(bp);
7749 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7750 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7752 val = REG_RD(bp, addr);
7754 REG_WR(bp, addr, val);
7756 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7757 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7758 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7759 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7763 /* Close gates #2, #3 and #4: */
7764 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7768 /* Gates #2 and #4a are closed/opened for "not E1" only */
7769 if (!CHIP_IS_E1(bp)) {
7771 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7773 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7777 if (CHIP_IS_E1x(bp)) {
7778 /* Prevent interrupts from HC on both ports */
7779 val = REG_RD(bp, HC_REG_CONFIG_1);
7780 REG_WR(bp, HC_REG_CONFIG_1,
7781 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7782 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7784 val = REG_RD(bp, HC_REG_CONFIG_0);
7785 REG_WR(bp, HC_REG_CONFIG_0,
7786 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7787 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7789 /* Prevent incomming interrupts in IGU */
7790 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7792 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7794 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7795 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7798 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7799 close ? "closing" : "opening");
7803 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7805 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7807 /* Do some magic... */
7808 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7809 *magic_val = val & SHARED_MF_CLP_MAGIC;
7810 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7814 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7816 * @bp: driver handle
7817 * @magic_val: old value of the `magic' bit.
7819 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7821 /* Restore the `magic' bit value... */
7822 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7823 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7824 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7828 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7830 * @bp: driver handle
7831 * @magic_val: old value of 'magic' bit.
7833 * Takes care of CLP configurations.
7835 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7838 u32 validity_offset;
7840 DP(NETIF_MSG_HW, "Starting\n");
7842 /* Set `magic' bit in order to save MF config */
7843 if (!CHIP_IS_E1(bp))
7844 bnx2x_clp_reset_prep(bp, magic_val);
7846 /* Get shmem offset */
7847 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7848 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7850 /* Clear validity map flags */
7852 REG_WR(bp, shmem + validity_offset, 0);
7855 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7856 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7859 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7861 * @bp: driver handle
7863 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7865 /* special handling for emulation and FPGA,
7866 wait 10 times longer */
7867 if (CHIP_REV_IS_SLOW(bp))
7868 msleep(MCP_ONE_TIMEOUT*10);
7870 msleep(MCP_ONE_TIMEOUT);
7874 * initializes bp->common.shmem_base and waits for validity signature to appear
7876 static int bnx2x_init_shmem(struct bnx2x *bp)
7882 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7883 if (bp->common.shmem_base) {
7884 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7885 if (val & SHR_MEM_VALIDITY_MB)
7889 bnx2x_mcp_wait_one(bp);
7891 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7893 BNX2X_ERR("BAD MCP validity signature\n");
7898 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7900 int rc = bnx2x_init_shmem(bp);
7902 /* Restore the `magic' bit value */
7903 if (!CHIP_IS_E1(bp))
7904 bnx2x_clp_reset_done(bp, magic_val);
7909 static void bnx2x_pxp_prep(struct bnx2x *bp)
7911 if (!CHIP_IS_E1(bp)) {
7912 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7913 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7919 * Reset the whole chip except for:
7921 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7924 * - MISC (including AEU)
7928 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
7930 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7934 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7935 * (per chip) blocks.
7938 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7939 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
7942 MISC_REGISTERS_RESET_REG_1_RST_HC |
7943 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7944 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7947 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
7948 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7949 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7950 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7951 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7952 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7953 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7954 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7956 reset_mask1 = 0xffffffff;
7959 reset_mask2 = 0xffff;
7961 reset_mask2 = 0x1ffff;
7963 if (CHIP_IS_E3(bp)) {
7964 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7965 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7968 /* Don't reset global blocks unless we need to */
7970 reset_mask2 &= ~global_bits2;
7973 * In case of attention in the QM, we need to reset PXP
7974 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
7975 * because otherwise QM reset would release 'close the gates' shortly
7976 * before resetting the PXP, then the PSWRQ would send a write
7977 * request to PGLUE. Then when PXP is reset, PGLUE would try to
7978 * read the payload data from PSWWR, but PSWWR would not
7979 * respond. The write queue in PGLUE would stuck, dmae commands
7980 * would not return. Therefore it's important to reset the second
7981 * reset register (containing the
7982 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
7983 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
7986 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7987 reset_mask2 & (~not_reset_mask2));
7989 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7990 reset_mask1 & (~not_reset_mask1));
7995 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7996 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8001 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8002 * It should get cleared in no more than 1s.
8004 * @bp: driver handle
8006 * It should get cleared in no more than 1s. Returns 0 if
8007 * pending writes bit gets cleared.
8009 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8015 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8020 usleep_range(1000, 1000);
8021 } while (cnt-- > 0);
8024 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8032 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8036 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8039 /* Empty the Tetris buffer, wait for 1s */
8041 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8042 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8043 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8044 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8045 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8046 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8047 ((port_is_idle_0 & 0x1) == 0x1) &&
8048 ((port_is_idle_1 & 0x1) == 0x1) &&
8049 (pgl_exp_rom2 == 0xffffffff))
8051 usleep_range(1000, 1000);
8052 } while (cnt-- > 0);
8055 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8057 " outstanding read requests after 1s!\n");
8058 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8059 " port_is_idle_0=0x%08x,"
8060 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8061 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8068 /* Close gates #2, #3 and #4 */
8069 bnx2x_set_234_gates(bp, true);
8071 /* Poll for IGU VQs for 57712 and newer chips */
8072 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8076 /* TBD: Indicate that "process kill" is in progress to MCP */
8078 /* Clear "unprepared" bit */
8079 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8082 /* Make sure all is written to the chip before the reset */
8085 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8086 * PSWHST, GRC and PSWRD Tetris buffer.
8088 usleep_range(1000, 1000);
8090 /* Prepare to chip reset: */
8093 bnx2x_reset_mcp_prep(bp, &val);
8099 /* reset the chip */
8100 bnx2x_process_kill_chip_reset(bp, global);
8103 /* Recover after reset: */
8105 if (global && bnx2x_reset_mcp_comp(bp, val))
8108 /* TBD: Add resetting the NO_MCP mode DB here */
8113 /* Open the gates #2, #3 and #4 */
8114 bnx2x_set_234_gates(bp, false);
8116 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8117 * reset state, re-enable attentions. */
8122 int bnx2x_leader_reset(struct bnx2x *bp)
8125 bool global = bnx2x_reset_is_global(bp);
8127 /* Try to recover after the failure */
8128 if (bnx2x_process_kill(bp, global)) {
8129 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8130 "Aii!\n", BP_PATH(bp));
8132 goto exit_leader_reset;
8136 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8139 bnx2x_set_reset_done(bp);
8141 bnx2x_clear_reset_global(bp);
8145 bnx2x_release_leader_lock(bp);
8150 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8152 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8154 /* Disconnect this device */
8155 netif_device_detach(bp->dev);
8158 * Block ifup for all function on this engine until "process kill"
8161 bnx2x_set_reset_in_progress(bp);
8163 /* Shut down the power */
8164 bnx2x_set_power_state(bp, PCI_D3hot);
8166 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8172 * Assumption: runs under rtnl lock. This together with the fact
8173 * that it's called only from bnx2x_sp_rtnl() ensure that it
8174 * will never be called when netif_running(bp->dev) is false.
8176 static void bnx2x_parity_recover(struct bnx2x *bp)
8178 bool global = false;
8180 DP(NETIF_MSG_HW, "Handling parity\n");
8182 switch (bp->recovery_state) {
8183 case BNX2X_RECOVERY_INIT:
8184 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8185 bnx2x_chk_parity_attn(bp, &global, false);
8187 /* Try to get a LEADER_LOCK HW lock */
8188 if (bnx2x_trylock_leader_lock(bp)) {
8189 bnx2x_set_reset_in_progress(bp);
8191 * Check if there is a global attention and if
8192 * there was a global attention, set the global
8197 bnx2x_set_reset_global(bp);
8202 /* Stop the driver */
8203 /* If interface has been removed - break */
8204 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8207 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8210 * Reset MCP command sequence number and MCP mail box
8211 * sequence as we are going to reset the MCP.
8215 bp->fw_drv_pulse_wr_seq = 0;
8218 /* Ensure "is_leader", MCP command sequence and
8219 * "recovery_state" update values are seen on other
8225 case BNX2X_RECOVERY_WAIT:
8226 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8227 if (bp->is_leader) {
8228 int other_engine = BP_PATH(bp) ? 0 : 1;
8229 u32 other_load_counter =
8230 bnx2x_get_load_cnt(bp, other_engine);
8232 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8233 global = bnx2x_reset_is_global(bp);
8236 * In case of a parity in a global block, let
8237 * the first leader that performs a
8238 * leader_reset() reset the global blocks in
8239 * order to clear global attentions. Otherwise
8240 * the the gates will remain closed for that
8244 (global && other_load_counter)) {
8245 /* Wait until all other functions get
8248 schedule_delayed_work(&bp->sp_rtnl_task,
8252 /* If all other functions got down -
8253 * try to bring the chip back to
8254 * normal. In any case it's an exit
8255 * point for a leader.
8257 if (bnx2x_leader_reset(bp)) {
8258 bnx2x_recovery_failed(bp);
8262 /* If we are here, means that the
8263 * leader has succeeded and doesn't
8264 * want to be a leader any more. Try
8265 * to continue as a none-leader.
8269 } else { /* non-leader */
8270 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8271 /* Try to get a LEADER_LOCK HW lock as
8272 * long as a former leader may have
8273 * been unloaded by the user or
8274 * released a leadership by another
8277 if (bnx2x_trylock_leader_lock(bp)) {
8278 /* I'm a leader now! Restart a
8285 schedule_delayed_work(&bp->sp_rtnl_task,
8291 * If there was a global attention, wait
8292 * for it to be cleared.
8294 if (bnx2x_reset_is_global(bp)) {
8295 schedule_delayed_work(
8301 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8302 bnx2x_recovery_failed(bp);
8304 bp->recovery_state =
8305 BNX2X_RECOVERY_DONE;
8318 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8319 * scheduled on a general queue in order to prevent a dead lock.
8321 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8323 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8327 if (!netif_running(bp->dev))
8330 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8331 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8333 /* if stop on error is defined no recovery flows should be executed */
8334 #ifdef BNX2X_STOP_ON_ERROR
8335 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8336 "so reset not done to allow debug dump,\n"
8337 "you will need to reboot when done\n");
8341 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8343 * Clear TX_TIMEOUT bit as we are going to reset the function
8346 smp_mb__before_clear_bit();
8347 clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state);
8348 smp_mb__after_clear_bit();
8349 bnx2x_parity_recover(bp);
8350 } else if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT,
8351 &bp->sp_rtnl_state)){
8352 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8353 bnx2x_nic_load(bp, LOAD_NORMAL);
8360 /* end of nic load/unload */
8362 static void bnx2x_period_task(struct work_struct *work)
8364 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8366 if (!netif_running(bp->dev))
8367 goto period_task_exit;
8369 if (CHIP_REV_IS_SLOW(bp)) {
8370 BNX2X_ERR("period task called on emulation, ignoring\n");
8371 goto period_task_exit;
8374 bnx2x_acquire_phy_lock(bp);
8376 * The barrier is needed to ensure the ordering between the writing to
8377 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8382 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8384 /* Re-queue task in 1 sec */
8385 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8388 bnx2x_release_phy_lock(bp);
8394 * Init service functions
8397 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8399 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8400 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8401 return base + (BP_ABS_FUNC(bp)) * stride;
8404 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8406 u32 reg = bnx2x_get_pretend_reg(bp);
8408 /* Flush all outstanding writes */
8411 /* Pretend to be function 0 */
8413 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8415 /* From now we are in the "like-E1" mode */
8416 bnx2x_int_disable(bp);
8418 /* Flush all outstanding writes */
8421 /* Restore the original function */
8422 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8426 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8429 bnx2x_int_disable(bp);
8431 bnx2x_undi_int_disable_e1h(bp);
8434 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8438 /* Check if there is any driver already loaded */
8439 val = REG_RD(bp, MISC_REG_UNPREPARED);
8441 /* Check if it is the UNDI driver
8442 * UNDI driver initializes CID offset for normal bell to 0x7
8444 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8445 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8447 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8448 /* save our pf_num */
8449 int orig_pf_num = bp->pf_num;
8451 u32 swap_en, swap_val, value;
8453 /* clear the UNDI indication */
8454 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8456 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8458 /* try unload UNDI on port 0 */
8461 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8462 DRV_MSG_SEQ_NUMBER_MASK);
8463 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8465 /* if UNDI is loaded on the other port */
8466 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8468 /* send "DONE" for previous unload */
8469 bnx2x_fw_command(bp,
8470 DRV_MSG_CODE_UNLOAD_DONE, 0);
8472 /* unload UNDI on port 1 */
8475 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8476 DRV_MSG_SEQ_NUMBER_MASK);
8477 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8479 bnx2x_fw_command(bp, reset_code, 0);
8482 /* now it's safe to release the lock */
8483 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8485 bnx2x_undi_int_disable(bp);
8488 /* close input traffic and wait for it */
8489 /* Do not rcv packets to BRB */
8490 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8491 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8492 /* Do not direct rcv packets that are not for MCP to
8494 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8495 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8497 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8498 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8501 /* save NIG port swap info */
8502 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8503 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8506 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8510 if (CHIP_IS_E3(bp)) {
8511 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8512 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8516 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8519 /* take the NIG out of reset and restore swap values */
8521 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8522 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8523 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8524 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8526 /* send unload done to the MCP */
8527 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8529 /* restore our func and fw_seq */
8530 bp->pf_num = orig_pf_num;
8532 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8533 DRV_MSG_SEQ_NUMBER_MASK);
8535 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8539 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8541 u32 val, val2, val3, val4, id;
8544 /* Get the chip revision id and number. */
8545 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8546 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8547 id = ((val & 0xffff) << 16);
8548 val = REG_RD(bp, MISC_REG_CHIP_REV);
8549 id |= ((val & 0xf) << 12);
8550 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8551 id |= ((val & 0xff) << 4);
8552 val = REG_RD(bp, MISC_REG_BOND_ID);
8554 bp->common.chip_id = id;
8556 /* Set doorbell size */
8557 bp->db_size = (1 << BNX2X_DB_SHIFT);
8559 if (!CHIP_IS_E1x(bp)) {
8560 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8562 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8564 val = (val >> 1) & 1;
8565 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8567 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8570 if (CHIP_MODE_IS_4_PORT(bp))
8571 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8573 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8575 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8576 bp->pfid = bp->pf_num; /* 0..7 */
8579 bp->link_params.chip_id = bp->common.chip_id;
8580 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8582 val = (REG_RD(bp, 0x2874) & 0x55);
8583 if ((bp->common.chip_id & 0x1) ||
8584 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8585 bp->flags |= ONE_PORT_FLAG;
8586 BNX2X_DEV_INFO("single port device\n");
8589 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8590 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8591 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8592 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8593 bp->common.flash_size, bp->common.flash_size);
8595 bnx2x_init_shmem(bp);
8599 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8600 MISC_REG_GENERIC_CR_1 :
8601 MISC_REG_GENERIC_CR_0));
8603 bp->link_params.shmem_base = bp->common.shmem_base;
8604 bp->link_params.shmem2_base = bp->common.shmem2_base;
8605 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8606 bp->common.shmem_base, bp->common.shmem2_base);
8608 if (!bp->common.shmem_base) {
8609 BNX2X_DEV_INFO("MCP not active\n");
8610 bp->flags |= NO_MCP_FLAG;
8614 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8615 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8617 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8618 SHARED_HW_CFG_LED_MODE_MASK) >>
8619 SHARED_HW_CFG_LED_MODE_SHIFT);
8621 bp->link_params.feature_config_flags = 0;
8622 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8623 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8624 bp->link_params.feature_config_flags |=
8625 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8627 bp->link_params.feature_config_flags &=
8628 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8630 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8631 bp->common.bc_ver = val;
8632 BNX2X_DEV_INFO("bc_ver %X\n", val);
8633 if (val < BNX2X_BC_VER) {
8634 /* for now only warn
8635 * later we might need to enforce this */
8636 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8637 "please upgrade BC\n", BNX2X_BC_VER, val);
8639 bp->link_params.feature_config_flags |=
8640 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8641 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8643 bp->link_params.feature_config_flags |=
8644 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8645 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8647 bp->link_params.feature_config_flags |=
8648 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8649 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8651 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8652 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8654 BNX2X_DEV_INFO("%sWoL capable\n",
8655 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8657 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8658 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8659 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8660 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8662 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8663 val, val2, val3, val4);
8666 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8667 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8669 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8671 int pfid = BP_FUNC(bp);
8672 int vn = BP_E1HVN(bp);
8675 u8 fid, igu_sb_cnt = 0;
8677 bp->igu_base_sb = 0xff;
8678 if (CHIP_INT_MODE_IS_BC(bp)) {
8679 igu_sb_cnt = bp->igu_sb_cnt;
8680 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8683 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8684 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8689 /* IGU in normal mode - read CAM */
8690 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8692 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8693 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8696 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8697 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8699 if (IGU_VEC(val) == 0)
8700 /* default status block */
8701 bp->igu_dsb_id = igu_sb_id;
8703 if (bp->igu_base_sb == 0xff)
8704 bp->igu_base_sb = igu_sb_id;
8710 #ifdef CONFIG_PCI_MSI
8712 * It's expected that number of CAM entries for this functions is equal
8713 * to the number evaluated based on the MSI-X table size. We want a
8714 * harsh warning if these values are different!
8716 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8719 if (igu_sb_cnt == 0)
8720 BNX2X_ERR("CAM configuration error\n");
8723 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8726 int cfg_size = 0, idx, port = BP_PORT(bp);
8728 /* Aggregation of supported attributes of all external phys */
8729 bp->port.supported[0] = 0;
8730 bp->port.supported[1] = 0;
8731 switch (bp->link_params.num_phys) {
8733 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8737 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8741 if (bp->link_params.multi_phy_config &
8742 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8743 bp->port.supported[1] =
8744 bp->link_params.phy[EXT_PHY1].supported;
8745 bp->port.supported[0] =
8746 bp->link_params.phy[EXT_PHY2].supported;
8748 bp->port.supported[0] =
8749 bp->link_params.phy[EXT_PHY1].supported;
8750 bp->port.supported[1] =
8751 bp->link_params.phy[EXT_PHY2].supported;
8757 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8758 BNX2X_ERR("NVRAM config error. BAD phy config."
8759 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8761 dev_info.port_hw_config[port].external_phy_config),
8763 dev_info.port_hw_config[port].external_phy_config2));
8768 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8770 switch (switch_cfg) {
8772 bp->port.phy_addr = REG_RD(
8773 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8775 case SWITCH_CFG_10G:
8776 bp->port.phy_addr = REG_RD(
8777 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8780 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8781 bp->port.link_config[0]);
8785 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8786 /* mask what we support according to speed_cap_mask per configuration */
8787 for (idx = 0; idx < cfg_size; idx++) {
8788 if (!(bp->link_params.speed_cap_mask[idx] &
8789 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8790 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8792 if (!(bp->link_params.speed_cap_mask[idx] &
8793 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8794 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8796 if (!(bp->link_params.speed_cap_mask[idx] &
8797 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8798 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8800 if (!(bp->link_params.speed_cap_mask[idx] &
8801 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8802 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8804 if (!(bp->link_params.speed_cap_mask[idx] &
8805 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8806 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8807 SUPPORTED_1000baseT_Full);
8809 if (!(bp->link_params.speed_cap_mask[idx] &
8810 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8811 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8813 if (!(bp->link_params.speed_cap_mask[idx] &
8814 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8815 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8819 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8820 bp->port.supported[1]);
8823 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8825 u32 link_config, idx, cfg_size = 0;
8826 bp->port.advertising[0] = 0;
8827 bp->port.advertising[1] = 0;
8828 switch (bp->link_params.num_phys) {
8837 for (idx = 0; idx < cfg_size; idx++) {
8838 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8839 link_config = bp->port.link_config[idx];
8840 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8841 case PORT_FEATURE_LINK_SPEED_AUTO:
8842 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8843 bp->link_params.req_line_speed[idx] =
8845 bp->port.advertising[idx] |=
8846 bp->port.supported[idx];
8848 /* force 10G, no AN */
8849 bp->link_params.req_line_speed[idx] =
8851 bp->port.advertising[idx] |=
8852 (ADVERTISED_10000baseT_Full |
8858 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8859 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8860 bp->link_params.req_line_speed[idx] =
8862 bp->port.advertising[idx] |=
8863 (ADVERTISED_10baseT_Full |
8866 BNX2X_ERR("NVRAM config error. "
8867 "Invalid link_config 0x%x"
8868 " speed_cap_mask 0x%x\n",
8870 bp->link_params.speed_cap_mask[idx]);
8875 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8876 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8877 bp->link_params.req_line_speed[idx] =
8879 bp->link_params.req_duplex[idx] =
8881 bp->port.advertising[idx] |=
8882 (ADVERTISED_10baseT_Half |
8885 BNX2X_ERR("NVRAM config error. "
8886 "Invalid link_config 0x%x"
8887 " speed_cap_mask 0x%x\n",
8889 bp->link_params.speed_cap_mask[idx]);
8894 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8895 if (bp->port.supported[idx] &
8896 SUPPORTED_100baseT_Full) {
8897 bp->link_params.req_line_speed[idx] =
8899 bp->port.advertising[idx] |=
8900 (ADVERTISED_100baseT_Full |
8903 BNX2X_ERR("NVRAM config error. "
8904 "Invalid link_config 0x%x"
8905 " speed_cap_mask 0x%x\n",
8907 bp->link_params.speed_cap_mask[idx]);
8912 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8913 if (bp->port.supported[idx] &
8914 SUPPORTED_100baseT_Half) {
8915 bp->link_params.req_line_speed[idx] =
8917 bp->link_params.req_duplex[idx] =
8919 bp->port.advertising[idx] |=
8920 (ADVERTISED_100baseT_Half |
8923 BNX2X_ERR("NVRAM config error. "
8924 "Invalid link_config 0x%x"
8925 " speed_cap_mask 0x%x\n",
8927 bp->link_params.speed_cap_mask[idx]);
8932 case PORT_FEATURE_LINK_SPEED_1G:
8933 if (bp->port.supported[idx] &
8934 SUPPORTED_1000baseT_Full) {
8935 bp->link_params.req_line_speed[idx] =
8937 bp->port.advertising[idx] |=
8938 (ADVERTISED_1000baseT_Full |
8941 BNX2X_ERR("NVRAM config error. "
8942 "Invalid link_config 0x%x"
8943 " speed_cap_mask 0x%x\n",
8945 bp->link_params.speed_cap_mask[idx]);
8950 case PORT_FEATURE_LINK_SPEED_2_5G:
8951 if (bp->port.supported[idx] &
8952 SUPPORTED_2500baseX_Full) {
8953 bp->link_params.req_line_speed[idx] =
8955 bp->port.advertising[idx] |=
8956 (ADVERTISED_2500baseX_Full |
8959 BNX2X_ERR("NVRAM config error. "
8960 "Invalid link_config 0x%x"
8961 " speed_cap_mask 0x%x\n",
8963 bp->link_params.speed_cap_mask[idx]);
8968 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8969 if (bp->port.supported[idx] &
8970 SUPPORTED_10000baseT_Full) {
8971 bp->link_params.req_line_speed[idx] =
8973 bp->port.advertising[idx] |=
8974 (ADVERTISED_10000baseT_Full |
8977 BNX2X_ERR("NVRAM config error. "
8978 "Invalid link_config 0x%x"
8979 " speed_cap_mask 0x%x\n",
8981 bp->link_params.speed_cap_mask[idx]);
8985 case PORT_FEATURE_LINK_SPEED_20G:
8986 bp->link_params.req_line_speed[idx] = SPEED_20000;
8990 BNX2X_ERR("NVRAM config error. "
8991 "BAD link speed link_config 0x%x\n",
8993 bp->link_params.req_line_speed[idx] =
8995 bp->port.advertising[idx] =
8996 bp->port.supported[idx];
9000 bp->link_params.req_flow_ctrl[idx] = (link_config &
9001 PORT_FEATURE_FLOW_CONTROL_MASK);
9002 if ((bp->link_params.req_flow_ctrl[idx] ==
9003 BNX2X_FLOW_CTRL_AUTO) &&
9004 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9005 bp->link_params.req_flow_ctrl[idx] =
9006 BNX2X_FLOW_CTRL_NONE;
9009 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9010 " 0x%x advertising 0x%x\n",
9011 bp->link_params.req_line_speed[idx],
9012 bp->link_params.req_duplex[idx],
9013 bp->link_params.req_flow_ctrl[idx],
9014 bp->port.advertising[idx]);
9018 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9020 mac_hi = cpu_to_be16(mac_hi);
9021 mac_lo = cpu_to_be32(mac_lo);
9022 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9023 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9026 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9028 int port = BP_PORT(bp);
9030 u32 ext_phy_type, ext_phy_config;
9032 bp->link_params.bp = bp;
9033 bp->link_params.port = port;
9035 bp->link_params.lane_config =
9036 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9038 bp->link_params.speed_cap_mask[0] =
9040 dev_info.port_hw_config[port].speed_capability_mask);
9041 bp->link_params.speed_cap_mask[1] =
9043 dev_info.port_hw_config[port].speed_capability_mask2);
9044 bp->port.link_config[0] =
9045 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9047 bp->port.link_config[1] =
9048 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9050 bp->link_params.multi_phy_config =
9051 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9052 /* If the device is capable of WoL, set the default state according
9055 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9056 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9057 (config & PORT_FEATURE_WOL_ENABLED));
9059 BNX2X_DEV_INFO("lane_config 0x%08x "
9060 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9061 bp->link_params.lane_config,
9062 bp->link_params.speed_cap_mask[0],
9063 bp->port.link_config[0]);
9065 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9066 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9067 bnx2x_phy_probe(&bp->link_params);
9068 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9070 bnx2x_link_settings_requested(bp);
9073 * If connected directly, work with the internal PHY, otherwise, work
9074 * with the external PHY
9078 dev_info.port_hw_config[port].external_phy_config);
9079 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9080 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9081 bp->mdio.prtad = bp->port.phy_addr;
9083 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9084 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9086 XGXS_EXT_PHY_ADDR(ext_phy_config);
9089 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9090 * In MF mode, it is set to cover self test cases
9093 bp->port.need_hw_lock = 1;
9095 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9096 bp->common.shmem_base,
9097 bp->common.shmem2_base);
9101 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9103 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9104 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
9105 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9106 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
9108 /* Get the number of maximum allowed iSCSI and FCoE connections */
9109 bp->cnic_eth_dev.max_iscsi_conn =
9110 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9111 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9113 bp->cnic_eth_dev.max_fcoe_conn =
9114 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9115 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9117 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9118 bp->cnic_eth_dev.max_iscsi_conn,
9119 bp->cnic_eth_dev.max_fcoe_conn);
9121 /* If mamimum allowed number of connections is zero -
9122 * disable the feature.
9124 if (!bp->cnic_eth_dev.max_iscsi_conn)
9125 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9127 if (!bp->cnic_eth_dev.max_fcoe_conn)
9128 bp->flags |= NO_FCOE_FLAG;
9132 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9135 int func = BP_ABS_FUNC(bp);
9136 int port = BP_PORT(bp);
9138 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9139 u8 *fip_mac = bp->fip_mac;
9142 /* Zero primary MAC configuration */
9143 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9146 BNX2X_ERROR("warning: random MAC workaround active\n");
9147 random_ether_addr(bp->dev->dev_addr);
9148 } else if (IS_MF(bp)) {
9149 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9150 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9151 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9152 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9153 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9156 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9157 * FCoE MAC then the appropriate feature should be disabled.
9160 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9161 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9162 val2 = MF_CFG_RD(bp, func_ext_config[func].
9163 iscsi_mac_addr_upper);
9164 val = MF_CFG_RD(bp, func_ext_config[func].
9165 iscsi_mac_addr_lower);
9166 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9167 BNX2X_DEV_INFO("Read iSCSI MAC: "
9169 BNX2X_MAC_PRN_LIST(iscsi_mac));
9171 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9173 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9174 val2 = MF_CFG_RD(bp, func_ext_config[func].
9175 fcoe_mac_addr_upper);
9176 val = MF_CFG_RD(bp, func_ext_config[func].
9177 fcoe_mac_addr_lower);
9178 bnx2x_set_mac_buf(fip_mac, val, val2);
9179 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9181 BNX2X_MAC_PRN_LIST(fip_mac));
9184 bp->flags |= NO_FCOE_FLAG;
9188 /* in SF read MACs from port configuration */
9189 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9190 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9191 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9194 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9196 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9198 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9202 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9203 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9206 /* Set the FCoE MAC in modes other then MF_SI */
9207 if (!CHIP_IS_E1x(bp)) {
9209 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9210 else if (!IS_MF(bp))
9211 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
9214 /* Disable iSCSI if MAC configuration is
9217 if (!is_valid_ether_addr(iscsi_mac)) {
9218 bp->flags |= NO_ISCSI_FLAG;
9219 memset(iscsi_mac, 0, ETH_ALEN);
9222 /* Disable FCoE if MAC configuration is
9225 if (!is_valid_ether_addr(fip_mac)) {
9226 bp->flags |= NO_FCOE_FLAG;
9227 memset(bp->fip_mac, 0, ETH_ALEN);
9231 if (!is_valid_ether_addr(bp->dev->dev_addr))
9232 dev_err(&bp->pdev->dev,
9233 "bad Ethernet MAC address configuration: "
9234 BNX2X_MAC_FMT", change it manually before bringing up "
9235 "the appropriate network interface\n",
9236 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
9239 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9241 int /*abs*/func = BP_ABS_FUNC(bp);
9246 bnx2x_get_common_hwinfo(bp);
9249 * initialize IGU parameters
9251 if (CHIP_IS_E1x(bp)) {
9252 bp->common.int_block = INT_BLOCK_HC;
9254 bp->igu_dsb_id = DEF_SB_IGU_ID;
9255 bp->igu_base_sb = 0;
9257 bp->common.int_block = INT_BLOCK_IGU;
9258 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9260 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9263 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9265 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9266 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9267 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9269 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9271 usleep_range(1000, 1000);
9274 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9275 dev_err(&bp->pdev->dev,
9276 "FORCING Normal Mode failed!!!\n");
9281 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9282 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9283 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9285 BNX2X_DEV_INFO("IGU Normal Mode\n");
9287 bnx2x_get_igu_cam_info(bp);
9292 * set base FW non-default (fast path) status block id, this value is
9293 * used to initialize the fw_sb_id saved on the fp/queue structure to
9294 * determine the id used by the FW.
9296 if (CHIP_IS_E1x(bp))
9297 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9299 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9300 * the same queue are indicated on the same IGU SB). So we prefer
9301 * FW and IGU SBs to be the same value.
9303 bp->base_fw_ndsb = bp->igu_base_sb;
9305 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9306 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9307 bp->igu_sb_cnt, bp->base_fw_ndsb);
9310 * Initialize MF configuration
9317 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9318 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9319 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9320 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9322 if (SHMEM2_HAS(bp, mf_cfg_addr))
9323 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9325 bp->common.mf_cfg_base = bp->common.shmem_base +
9326 offsetof(struct shmem_region, func_mb) +
9327 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9329 * get mf configuration:
9330 * 1. existence of MF configuration
9331 * 2. MAC address must be legal (check only upper bytes)
9332 * for Switch-Independent mode;
9333 * OVLAN must be legal for Switch-Dependent mode
9334 * 3. SF_MODE configures specific MF mode
9336 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9337 /* get mf configuration */
9339 dev_info.shared_feature_config.config);
9340 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9343 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9344 val = MF_CFG_RD(bp, func_mf_config[func].
9346 /* check for legal mac (upper bytes)*/
9347 if (val != 0xffff) {
9348 bp->mf_mode = MULTI_FUNCTION_SI;
9349 bp->mf_config[vn] = MF_CFG_RD(bp,
9350 func_mf_config[func].config);
9352 BNX2X_DEV_INFO("illegal MAC address "
9355 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9356 /* get OV configuration */
9358 func_mf_config[FUNC_0].e1hov_tag);
9359 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9361 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9362 bp->mf_mode = MULTI_FUNCTION_SD;
9363 bp->mf_config[vn] = MF_CFG_RD(bp,
9364 func_mf_config[func].config);
9366 BNX2X_DEV_INFO("illegal OV for SD\n");
9369 /* Unknown configuration: reset mf_config */
9370 bp->mf_config[vn] = 0;
9371 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9375 BNX2X_DEV_INFO("%s function mode\n",
9376 IS_MF(bp) ? "multi" : "single");
9378 switch (bp->mf_mode) {
9379 case MULTI_FUNCTION_SD:
9380 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9381 FUNC_MF_CFG_E1HOV_TAG_MASK;
9382 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9384 bp->path_has_ovlan = true;
9386 BNX2X_DEV_INFO("MF OV for func %d is %d "
9387 "(0x%04x)\n", func, bp->mf_ov,
9390 dev_err(&bp->pdev->dev,
9391 "No valid MF OV for func %d, "
9392 "aborting\n", func);
9396 case MULTI_FUNCTION_SI:
9397 BNX2X_DEV_INFO("func %d is in MF "
9398 "switch-independent mode\n", func);
9402 dev_err(&bp->pdev->dev,
9403 "VN %d is in a single function mode, "
9410 /* check if other port on the path needs ovlan:
9411 * Since MF configuration is shared between ports
9412 * Possible mixed modes are only
9413 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9415 if (CHIP_MODE_IS_4_PORT(bp) &&
9416 !bp->path_has_ovlan &&
9418 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9419 u8 other_port = !BP_PORT(bp);
9420 u8 other_func = BP_PATH(bp) + 2*other_port;
9422 func_mf_config[other_func].e1hov_tag);
9423 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9424 bp->path_has_ovlan = true;
9428 /* adjust igu_sb_cnt to MF for E1x */
9429 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9430 bp->igu_sb_cnt /= E1HVN_MAX;
9433 bnx2x_get_port_hwinfo(bp);
9435 if (!BP_NOMCP(bp)) {
9437 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9438 DRV_MSG_SEQ_NUMBER_MASK);
9439 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9442 /* Get MAC addresses */
9443 bnx2x_get_mac_hwinfo(bp);
9446 bnx2x_get_cnic_info(bp);
9449 /* Get current FW pulse sequence */
9450 if (!BP_NOMCP(bp)) {
9451 int mb_idx = BP_FW_MB_IDX(bp);
9453 bp->fw_drv_pulse_wr_seq =
9454 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9455 DRV_PULSE_SEQ_MASK);
9456 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9462 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9464 int cnt, i, block_end, rodi;
9465 char vpd_data[BNX2X_VPD_LEN+1];
9466 char str_id_reg[VENDOR_ID_LEN+1];
9467 char str_id_cap[VENDOR_ID_LEN+1];
9470 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9471 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9473 if (cnt < BNX2X_VPD_LEN)
9476 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9477 PCI_VPD_LRDT_RO_DATA);
9482 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9483 pci_vpd_lrdt_size(&vpd_data[i]);
9485 i += PCI_VPD_LRDT_TAG_SIZE;
9487 if (block_end > BNX2X_VPD_LEN)
9490 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9491 PCI_VPD_RO_KEYWORD_MFR_ID);
9495 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9497 if (len != VENDOR_ID_LEN)
9500 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9502 /* vendor specific info */
9503 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9504 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9505 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9506 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9508 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9509 PCI_VPD_RO_KEYWORD_VENDOR0);
9511 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9513 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9515 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9516 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9517 bp->fw_ver[len] = ' ';
9526 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9530 if (CHIP_REV_IS_FPGA(bp))
9531 SET_FLAGS(flags, MODE_FPGA);
9532 else if (CHIP_REV_IS_EMUL(bp))
9533 SET_FLAGS(flags, MODE_EMUL);
9535 SET_FLAGS(flags, MODE_ASIC);
9537 if (CHIP_MODE_IS_4_PORT(bp))
9538 SET_FLAGS(flags, MODE_PORT4);
9540 SET_FLAGS(flags, MODE_PORT2);
9543 SET_FLAGS(flags, MODE_E2);
9544 else if (CHIP_IS_E3(bp)) {
9545 SET_FLAGS(flags, MODE_E3);
9546 if (CHIP_REV(bp) == CHIP_REV_Ax)
9547 SET_FLAGS(flags, MODE_E3_A0);
9548 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9549 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9553 SET_FLAGS(flags, MODE_MF);
9554 switch (bp->mf_mode) {
9555 case MULTI_FUNCTION_SD:
9556 SET_FLAGS(flags, MODE_MF_SD);
9558 case MULTI_FUNCTION_SI:
9559 SET_FLAGS(flags, MODE_MF_SI);
9563 SET_FLAGS(flags, MODE_SF);
9565 #if defined(__LITTLE_ENDIAN)
9566 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9567 #else /*(__BIG_ENDIAN)*/
9568 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9570 INIT_MODE_FLAGS(bp) = flags;
9573 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9579 mutex_init(&bp->port.phy_mutex);
9580 mutex_init(&bp->fw_mb_mutex);
9581 spin_lock_init(&bp->stats_lock);
9583 mutex_init(&bp->cnic_mutex);
9586 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9587 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9588 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9589 rc = bnx2x_get_hwinfo(bp);
9593 bnx2x_set_modes_bitmap(bp);
9595 rc = bnx2x_alloc_mem_bp(bp);
9599 bnx2x_read_fwinfo(bp);
9603 /* need to reset chip if undi was active */
9605 bnx2x_undi_unload(bp);
9607 if (CHIP_REV_IS_FPGA(bp))
9608 dev_err(&bp->pdev->dev, "FPGA detected\n");
9610 if (BP_NOMCP(bp) && (func == 0))
9611 dev_err(&bp->pdev->dev, "MCP disabled, "
9612 "must load devices in order!\n");
9614 bp->multi_mode = multi_mode;
9618 bp->flags &= ~TPA_ENABLE_FLAG;
9619 bp->dev->features &= ~NETIF_F_LRO;
9621 bp->flags |= TPA_ENABLE_FLAG;
9622 bp->dev->features |= NETIF_F_LRO;
9624 bp->disable_tpa = disable_tpa;
9627 bp->dropless_fc = 0;
9629 bp->dropless_fc = dropless_fc;
9633 bp->tx_ring_size = MAX_TX_AVAIL;
9635 /* make sure that the numbers are in the right granularity */
9636 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9637 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9639 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9640 bp->current_interval = (poll ? poll : timer_interval);
9642 init_timer(&bp->timer);
9643 bp->timer.expires = jiffies + bp->current_interval;
9644 bp->timer.data = (unsigned long) bp;
9645 bp->timer.function = bnx2x_timer;
9647 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9648 bnx2x_dcbx_init_params(bp);
9651 if (CHIP_IS_E1x(bp))
9652 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9654 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9657 /* multiple tx priority */
9658 if (CHIP_IS_E1x(bp))
9659 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9660 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9661 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9662 if (CHIP_IS_E3B0(bp))
9663 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9669 /****************************************************************************
9670 * General service functions
9671 ****************************************************************************/
9674 * net_device service functions
9677 /* called with rtnl_lock */
9678 static int bnx2x_open(struct net_device *dev)
9680 struct bnx2x *bp = netdev_priv(dev);
9681 bool global = false;
9682 int other_engine = BP_PATH(bp) ? 0 : 1;
9683 u32 other_load_counter, load_counter;
9685 netif_carrier_off(dev);
9687 bnx2x_set_power_state(bp, PCI_D0);
9689 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9690 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9693 * If parity had happen during the unload, then attentions
9694 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9695 * want the first function loaded on the current engine to
9696 * complete the recovery.
9698 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9699 bnx2x_chk_parity_attn(bp, &global, true))
9702 * If there are attentions and they are in a global
9703 * blocks, set the GLOBAL_RESET bit regardless whether
9704 * it will be this function that will complete the
9708 bnx2x_set_reset_global(bp);
9711 * Only the first function on the current engine should
9712 * try to recover in open. In case of attentions in
9713 * global blocks only the first in the chip should try
9716 if ((!load_counter &&
9717 (!global || !other_load_counter)) &&
9718 bnx2x_trylock_leader_lock(bp) &&
9719 !bnx2x_leader_reset(bp)) {
9720 netdev_info(bp->dev, "Recovered in open\n");
9724 /* recovery has failed... */
9725 bnx2x_set_power_state(bp, PCI_D3hot);
9726 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9728 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9729 " completed yet. Try again later. If u still see this"
9730 " message after a few retries then power cycle is"
9736 bp->recovery_state = BNX2X_RECOVERY_DONE;
9737 return bnx2x_nic_load(bp, LOAD_OPEN);
9740 /* called with rtnl_lock */
9741 static int bnx2x_close(struct net_device *dev)
9743 struct bnx2x *bp = netdev_priv(dev);
9745 /* Unload the driver, release IRQs */
9746 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9749 bnx2x_set_power_state(bp, PCI_D3hot);
9754 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9755 struct bnx2x_mcast_ramrod_params *p)
9757 int mc_count = netdev_mc_count(bp->dev);
9758 struct bnx2x_mcast_list_elem *mc_mac =
9759 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9760 struct netdev_hw_addr *ha;
9765 INIT_LIST_HEAD(&p->mcast_list);
9767 netdev_for_each_mc_addr(ha, bp->dev) {
9768 mc_mac->mac = bnx2x_mc_addr(ha);
9769 list_add_tail(&mc_mac->link, &p->mcast_list);
9773 p->mcast_list_len = mc_count;
9778 static inline void bnx2x_free_mcast_macs_list(
9779 struct bnx2x_mcast_ramrod_params *p)
9781 struct bnx2x_mcast_list_elem *mc_mac =
9782 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9790 * bnx2x_set_uc_list - configure a new unicast MACs list.
9792 * @bp: driver handle
9794 * We will use zero (0) as a MAC type for these MACs.
9796 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
9799 struct net_device *dev = bp->dev;
9800 struct netdev_hw_addr *ha;
9801 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9802 unsigned long ramrod_flags = 0;
9804 /* First schedule a cleanup up of old configuration */
9805 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9807 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9811 netdev_for_each_uc_addr(ha, dev) {
9812 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9813 BNX2X_UC_LIST_MAC, &ramrod_flags);
9815 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9821 /* Execute the pending commands */
9822 __set_bit(RAMROD_CONT, &ramrod_flags);
9823 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9824 BNX2X_UC_LIST_MAC, &ramrod_flags);
9827 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9829 struct net_device *dev = bp->dev;
9830 struct bnx2x_mcast_ramrod_params rparam = {0};
9833 rparam.mcast_obj = &bp->mcast_obj;
9835 /* first, clear all configured multicast MACs */
9836 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9838 BNX2X_ERR("Failed to clear multicast "
9839 "configuration: %d\n", rc);
9843 /* then, configure a new MACs list */
9844 if (netdev_mc_count(dev)) {
9845 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9847 BNX2X_ERR("Failed to create multicast MACs "
9852 /* Now add the new MACs */
9853 rc = bnx2x_config_mcast(bp, &rparam,
9854 BNX2X_MCAST_CMD_ADD);
9856 BNX2X_ERR("Failed to set a new multicast "
9857 "configuration: %d\n", rc);
9859 bnx2x_free_mcast_macs_list(&rparam);
9866 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9867 void bnx2x_set_rx_mode(struct net_device *dev)
9869 struct bnx2x *bp = netdev_priv(dev);
9870 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9872 if (bp->state != BNX2X_STATE_OPEN) {
9873 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9877 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
9879 if (dev->flags & IFF_PROMISC)
9880 rx_mode = BNX2X_RX_MODE_PROMISC;
9881 else if ((dev->flags & IFF_ALLMULTI) ||
9882 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
9884 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9886 /* some multicasts */
9887 if (bnx2x_set_mc_list(bp) < 0)
9888 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9890 if (bnx2x_set_uc_list(bp) < 0)
9891 rx_mode = BNX2X_RX_MODE_PROMISC;
9894 bp->rx_mode = rx_mode;
9896 /* Schedule the rx_mode command */
9897 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
9898 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9902 bnx2x_set_storm_rx_mode(bp);
9905 /* called with rtnl_lock */
9906 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9907 int devad, u16 addr)
9909 struct bnx2x *bp = netdev_priv(netdev);
9913 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9914 prtad, devad, addr);
9916 /* The HW expects different devad if CL22 is used */
9917 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9919 bnx2x_acquire_phy_lock(bp);
9920 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
9921 bnx2x_release_phy_lock(bp);
9922 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
9929 /* called with rtnl_lock */
9930 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9931 u16 addr, u16 value)
9933 struct bnx2x *bp = netdev_priv(netdev);
9936 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9937 " value 0x%x\n", prtad, devad, addr, value);
9939 /* The HW expects different devad if CL22 is used */
9940 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9942 bnx2x_acquire_phy_lock(bp);
9943 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
9944 bnx2x_release_phy_lock(bp);
9948 /* called with rtnl_lock */
9949 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9951 struct bnx2x *bp = netdev_priv(dev);
9952 struct mii_ioctl_data *mdio = if_mii(ifr);
9954 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9955 mdio->phy_id, mdio->reg_num, mdio->val_in);
9957 if (!netif_running(dev))
9960 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
9963 #ifdef CONFIG_NET_POLL_CONTROLLER
9964 static void poll_bnx2x(struct net_device *dev)
9966 struct bnx2x *bp = netdev_priv(dev);
9968 disable_irq(bp->pdev->irq);
9969 bnx2x_interrupt(bp->pdev->irq, dev);
9970 enable_irq(bp->pdev->irq);
9974 static const struct net_device_ops bnx2x_netdev_ops = {
9975 .ndo_open = bnx2x_open,
9976 .ndo_stop = bnx2x_close,
9977 .ndo_start_xmit = bnx2x_start_xmit,
9978 .ndo_select_queue = bnx2x_select_queue,
9979 .ndo_set_rx_mode = bnx2x_set_rx_mode,
9980 .ndo_set_mac_address = bnx2x_change_mac_addr,
9981 .ndo_validate_addr = eth_validate_addr,
9982 .ndo_do_ioctl = bnx2x_ioctl,
9983 .ndo_change_mtu = bnx2x_change_mtu,
9984 .ndo_fix_features = bnx2x_fix_features,
9985 .ndo_set_features = bnx2x_set_features,
9986 .ndo_tx_timeout = bnx2x_tx_timeout,
9987 #ifdef CONFIG_NET_POLL_CONTROLLER
9988 .ndo_poll_controller = poll_bnx2x,
9990 .ndo_setup_tc = bnx2x_setup_tc,
9994 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
9996 struct device *dev = &bp->pdev->dev;
9998 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
9999 bp->flags |= USING_DAC_FLAG;
10000 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10001 dev_err(dev, "dma_set_coherent_mask failed, "
10005 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10006 dev_err(dev, "System does not support DMA, aborting\n");
10013 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10014 struct net_device *dev,
10015 unsigned long board_type)
10020 SET_NETDEV_DEV(dev, &pdev->dev);
10021 bp = netdev_priv(dev);
10026 bp->pf_num = PCI_FUNC(pdev->devfn);
10028 rc = pci_enable_device(pdev);
10030 dev_err(&bp->pdev->dev,
10031 "Cannot enable PCI device, aborting\n");
10035 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10036 dev_err(&bp->pdev->dev,
10037 "Cannot find PCI device base address, aborting\n");
10039 goto err_out_disable;
10042 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10043 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10044 " base address, aborting\n");
10046 goto err_out_disable;
10049 if (atomic_read(&pdev->enable_cnt) == 1) {
10050 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10052 dev_err(&bp->pdev->dev,
10053 "Cannot obtain PCI resources, aborting\n");
10054 goto err_out_disable;
10057 pci_set_master(pdev);
10058 pci_save_state(pdev);
10061 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10062 if (bp->pm_cap == 0) {
10063 dev_err(&bp->pdev->dev,
10064 "Cannot find power management capability, aborting\n");
10066 goto err_out_release;
10069 if (!pci_is_pcie(pdev)) {
10070 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10072 goto err_out_release;
10075 rc = bnx2x_set_coherency_mask(bp);
10077 goto err_out_release;
10079 dev->mem_start = pci_resource_start(pdev, 0);
10080 dev->base_addr = dev->mem_start;
10081 dev->mem_end = pci_resource_end(pdev, 0);
10083 dev->irq = pdev->irq;
10085 bp->regview = pci_ioremap_bar(pdev, 0);
10086 if (!bp->regview) {
10087 dev_err(&bp->pdev->dev,
10088 "Cannot map register space, aborting\n");
10090 goto err_out_release;
10093 bnx2x_set_power_state(bp, PCI_D0);
10095 /* clean indirect addresses */
10096 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10097 PCICFG_VENDOR_ID_OFFSET);
10098 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10099 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10100 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10101 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
10104 * Enable internal target-read (in case we are probed after PF FLR).
10105 * Must be done prior to any BAR read access
10107 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10109 /* Reset the load counter */
10110 bnx2x_clear_load_cnt(bp);
10112 dev->watchdog_timeo = TX_TIMEOUT;
10114 dev->netdev_ops = &bnx2x_netdev_ops;
10115 bnx2x_set_ethtool_ops(dev);
10117 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10118 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10119 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10121 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10122 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10124 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10125 if (bp->flags & USING_DAC_FLAG)
10126 dev->features |= NETIF_F_HIGHDMA;
10128 /* Add Loopback capability to the device */
10129 dev->hw_features |= NETIF_F_LOOPBACK;
10132 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10135 /* get_port_hwinfo() will set prtad and mmds properly */
10136 bp->mdio.prtad = MDIO_PRTAD_NONE;
10138 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10139 bp->mdio.dev = dev;
10140 bp->mdio.mdio_read = bnx2x_mdio_read;
10141 bp->mdio.mdio_write = bnx2x_mdio_write;
10146 if (atomic_read(&pdev->enable_cnt) == 1)
10147 pci_release_regions(pdev);
10150 pci_disable_device(pdev);
10151 pci_set_drvdata(pdev, NULL);
10157 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10158 int *width, int *speed)
10160 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10162 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10164 /* return value of 1=2.5GHz 2=5GHz */
10165 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10168 static int bnx2x_check_firmware(struct bnx2x *bp)
10170 const struct firmware *firmware = bp->firmware;
10171 struct bnx2x_fw_file_hdr *fw_hdr;
10172 struct bnx2x_fw_file_section *sections;
10173 u32 offset, len, num_ops;
10178 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10181 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10182 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10184 /* Make sure none of the offsets and sizes make us read beyond
10185 * the end of the firmware data */
10186 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10187 offset = be32_to_cpu(sections[i].offset);
10188 len = be32_to_cpu(sections[i].len);
10189 if (offset + len > firmware->size) {
10190 dev_err(&bp->pdev->dev,
10191 "Section %d length is out of bounds\n", i);
10196 /* Likewise for the init_ops offsets */
10197 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10198 ops_offsets = (u16 *)(firmware->data + offset);
10199 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10201 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10202 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10203 dev_err(&bp->pdev->dev,
10204 "Section offset %d is out of bounds\n", i);
10209 /* Check FW version */
10210 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10211 fw_ver = firmware->data + offset;
10212 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10213 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10214 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10215 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10216 dev_err(&bp->pdev->dev,
10217 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10218 fw_ver[0], fw_ver[1], fw_ver[2],
10219 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10220 BCM_5710_FW_MINOR_VERSION,
10221 BCM_5710_FW_REVISION_VERSION,
10222 BCM_5710_FW_ENGINEERING_VERSION);
10229 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10231 const __be32 *source = (const __be32 *)_source;
10232 u32 *target = (u32 *)_target;
10235 for (i = 0; i < n/4; i++)
10236 target[i] = be32_to_cpu(source[i]);
10240 Ops array is stored in the following format:
10241 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10243 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10245 const __be32 *source = (const __be32 *)_source;
10246 struct raw_op *target = (struct raw_op *)_target;
10249 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10250 tmp = be32_to_cpu(source[j]);
10251 target[i].op = (tmp >> 24) & 0xff;
10252 target[i].offset = tmp & 0xffffff;
10253 target[i].raw_data = be32_to_cpu(source[j + 1]);
10258 * IRO array is stored in the following format:
10259 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10261 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10263 const __be32 *source = (const __be32 *)_source;
10264 struct iro *target = (struct iro *)_target;
10267 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10268 target[i].base = be32_to_cpu(source[j]);
10270 tmp = be32_to_cpu(source[j]);
10271 target[i].m1 = (tmp >> 16) & 0xffff;
10272 target[i].m2 = tmp & 0xffff;
10274 tmp = be32_to_cpu(source[j]);
10275 target[i].m3 = (tmp >> 16) & 0xffff;
10276 target[i].size = tmp & 0xffff;
10281 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10283 const __be16 *source = (const __be16 *)_source;
10284 u16 *target = (u16 *)_target;
10287 for (i = 0; i < n/2; i++)
10288 target[i] = be16_to_cpu(source[i]);
10291 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10293 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10294 bp->arr = kmalloc(len, GFP_KERNEL); \
10296 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10299 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10300 (u8 *)bp->arr, len); \
10303 int bnx2x_init_firmware(struct bnx2x *bp)
10305 const char *fw_file_name;
10306 struct bnx2x_fw_file_hdr *fw_hdr;
10309 if (CHIP_IS_E1(bp))
10310 fw_file_name = FW_FILE_NAME_E1;
10311 else if (CHIP_IS_E1H(bp))
10312 fw_file_name = FW_FILE_NAME_E1H;
10313 else if (!CHIP_IS_E1x(bp))
10314 fw_file_name = FW_FILE_NAME_E2;
10316 BNX2X_ERR("Unsupported chip revision\n");
10320 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10322 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10324 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10325 goto request_firmware_exit;
10328 rc = bnx2x_check_firmware(bp);
10330 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10331 goto request_firmware_exit;
10334 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10336 /* Initialize the pointers to the init arrays */
10338 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10341 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10344 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10347 /* STORMs firmware */
10348 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10349 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10350 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10351 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10352 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10353 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10354 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10355 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10356 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10357 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10358 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10359 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10360 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10361 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10362 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10363 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10365 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10370 kfree(bp->init_ops_offsets);
10371 init_offsets_alloc_err:
10372 kfree(bp->init_ops);
10373 init_ops_alloc_err:
10374 kfree(bp->init_data);
10375 request_firmware_exit:
10376 release_firmware(bp->firmware);
10381 static void bnx2x_release_firmware(struct bnx2x *bp)
10383 kfree(bp->init_ops_offsets);
10384 kfree(bp->init_ops);
10385 kfree(bp->init_data);
10386 release_firmware(bp->firmware);
10390 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10391 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10392 .init_hw_cmn = bnx2x_init_hw_common,
10393 .init_hw_port = bnx2x_init_hw_port,
10394 .init_hw_func = bnx2x_init_hw_func,
10396 .reset_hw_cmn = bnx2x_reset_common,
10397 .reset_hw_port = bnx2x_reset_port,
10398 .reset_hw_func = bnx2x_reset_func,
10400 .gunzip_init = bnx2x_gunzip_init,
10401 .gunzip_end = bnx2x_gunzip_end,
10403 .init_fw = bnx2x_init_firmware,
10404 .release_fw = bnx2x_release_firmware,
10407 void bnx2x__init_func_obj(struct bnx2x *bp)
10409 /* Prepare DMAE related driver resources */
10410 bnx2x_setup_dmae(bp);
10412 bnx2x_init_func_obj(bp, &bp->func_obj,
10413 bnx2x_sp(bp, func_rdata),
10414 bnx2x_sp_mapping(bp, func_rdata),
10415 &bnx2x_func_sp_drv);
10418 /* must be called after sriov-enable */
10419 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10421 int cid_count = BNX2X_L2_CID_COUNT(bp);
10424 cid_count += CNIC_CID_MAX;
10426 return roundup(cid_count, QM_CID_ROUND);
10430 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10435 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10440 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10443 * If MSI-X is not supported - return number of SBs needed to support
10444 * one fast path queue: one FP queue + SB for CNIC
10447 return 1 + CNIC_PRESENT;
10450 * The value in the PCI configuration space is the index of the last
10451 * entry, namely one less than the actual size of the table, which is
10452 * exactly what we want to return from this function: number of all SBs
10453 * without the default SB.
10455 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10456 return control & PCI_MSIX_FLAGS_QSIZE;
10459 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10460 const struct pci_device_id *ent)
10462 struct net_device *dev = NULL;
10464 int pcie_width, pcie_speed;
10465 int rc, max_non_def_sbs;
10466 int rx_count, tx_count, rss_count;
10468 * An estimated maximum supported CoS number according to the chip
10470 * We will try to roughly estimate the maximum number of CoSes this chip
10471 * may support in order to minimize the memory allocated for Tx
10472 * netdev_queue's. This number will be accurately calculated during the
10473 * initialization of bp->max_cos based on the chip versions AND chip
10474 * revision in the bnx2x_init_bp().
10476 u8 max_cos_est = 0;
10478 switch (ent->driver_data) {
10482 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10487 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10496 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10500 pr_err("Unknown board_type (%ld), aborting\n",
10505 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10508 * Do not allow the maximum SB count to grow above 16
10509 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10510 * We will use the FP_SB_MAX_E1x macro for this matter.
10512 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10514 WARN_ON(!max_non_def_sbs);
10516 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10517 rss_count = max_non_def_sbs - CNIC_PRESENT;
10519 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10520 rx_count = rss_count + FCOE_PRESENT;
10523 * Maximum number of netdev Tx queues:
10524 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10526 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10528 /* dev zeroed in init_etherdev */
10529 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10531 dev_err(&pdev->dev, "Cannot allocate net device\n");
10535 bp = netdev_priv(dev);
10537 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10538 tx_count, rx_count);
10540 bp->igu_sb_cnt = max_non_def_sbs;
10541 bp->msg_enable = debug;
10542 pci_set_drvdata(pdev, dev);
10544 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10550 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
10552 rc = bnx2x_init_bp(bp);
10554 goto init_one_exit;
10557 * Map doorbels here as we need the real value of bp->max_cos which
10558 * is initialized in bnx2x_init_bp().
10560 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10561 min_t(u64, BNX2X_DB_SIZE(bp),
10562 pci_resource_len(pdev, 2)));
10563 if (!bp->doorbells) {
10564 dev_err(&bp->pdev->dev,
10565 "Cannot map doorbell space, aborting\n");
10567 goto init_one_exit;
10570 /* calc qm_cid_count */
10571 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10574 /* disable FCOE L2 queue for E1x*/
10575 if (CHIP_IS_E1x(bp))
10576 bp->flags |= NO_FCOE_FLAG;
10580 /* Configure interrupt mode: try to enable MSI-X/MSI if
10581 * needed, set bp->num_queues appropriately.
10583 bnx2x_set_int_mode(bp);
10585 /* Add all NAPI objects */
10586 bnx2x_add_all_napi(bp);
10588 rc = register_netdev(dev);
10590 dev_err(&pdev->dev, "Cannot register net device\n");
10591 goto init_one_exit;
10595 if (!NO_FCOE(bp)) {
10596 /* Add storage MAC address */
10598 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10603 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10605 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10606 " IRQ %d, ", board_info[ent->driver_data].name,
10607 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10609 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10610 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10611 "5GHz (Gen2)" : "2.5GHz",
10612 dev->base_addr, bp->pdev->irq);
10613 pr_cont("node addr %pM\n", dev->dev_addr);
10619 iounmap(bp->regview);
10622 iounmap(bp->doorbells);
10626 if (atomic_read(&pdev->enable_cnt) == 1)
10627 pci_release_regions(pdev);
10629 pci_disable_device(pdev);
10630 pci_set_drvdata(pdev, NULL);
10635 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10637 struct net_device *dev = pci_get_drvdata(pdev);
10641 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10644 bp = netdev_priv(dev);
10647 /* Delete storage MAC address */
10648 if (!NO_FCOE(bp)) {
10650 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10656 /* Delete app tlvs from dcbnl */
10657 bnx2x_dcbnl_update_applist(bp, true);
10660 unregister_netdev(dev);
10662 /* Delete all NAPI objects */
10663 bnx2x_del_all_napi(bp);
10665 /* Power on: we can't let PCI layer write to us while we are in D3 */
10666 bnx2x_set_power_state(bp, PCI_D0);
10668 /* Disable MSI/MSI-X */
10669 bnx2x_disable_msi(bp);
10672 bnx2x_set_power_state(bp, PCI_D3hot);
10674 /* Make sure RESET task is not scheduled before continuing */
10675 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10678 iounmap(bp->regview);
10681 iounmap(bp->doorbells);
10683 bnx2x_free_mem_bp(bp);
10687 if (atomic_read(&pdev->enable_cnt) == 1)
10688 pci_release_regions(pdev);
10690 pci_disable_device(pdev);
10691 pci_set_drvdata(pdev, NULL);
10694 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10698 bp->state = BNX2X_STATE_ERROR;
10700 bp->rx_mode = BNX2X_RX_MODE_NONE;
10703 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10706 bnx2x_tx_disable(bp);
10708 bnx2x_netif_stop(bp, 0);
10710 del_timer_sync(&bp->timer);
10712 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10715 bnx2x_free_irq(bp);
10717 /* Free SKBs, SGEs, TPA pool and driver internals */
10718 bnx2x_free_skbs(bp);
10720 for_each_rx_queue(bp, i)
10721 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10723 bnx2x_free_mem(bp);
10725 bp->state = BNX2X_STATE_CLOSED;
10727 netif_carrier_off(bp->dev);
10732 static void bnx2x_eeh_recover(struct bnx2x *bp)
10736 mutex_init(&bp->port.phy_mutex);
10738 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10739 bp->link_params.shmem_base = bp->common.shmem_base;
10740 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10742 if (!bp->common.shmem_base ||
10743 (bp->common.shmem_base < 0xA0000) ||
10744 (bp->common.shmem_base >= 0xC0000)) {
10745 BNX2X_DEV_INFO("MCP not active\n");
10746 bp->flags |= NO_MCP_FLAG;
10750 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10751 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10752 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10753 BNX2X_ERR("BAD MCP validity signature\n");
10755 if (!BP_NOMCP(bp)) {
10757 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10758 DRV_MSG_SEQ_NUMBER_MASK);
10759 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10764 * bnx2x_io_error_detected - called when PCI error is detected
10765 * @pdev: Pointer to PCI device
10766 * @state: The current pci connection state
10768 * This function is called after a PCI bus error affecting
10769 * this device has been detected.
10771 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10772 pci_channel_state_t state)
10774 struct net_device *dev = pci_get_drvdata(pdev);
10775 struct bnx2x *bp = netdev_priv(dev);
10779 netif_device_detach(dev);
10781 if (state == pci_channel_io_perm_failure) {
10783 return PCI_ERS_RESULT_DISCONNECT;
10786 if (netif_running(dev))
10787 bnx2x_eeh_nic_unload(bp);
10789 pci_disable_device(pdev);
10793 /* Request a slot reset */
10794 return PCI_ERS_RESULT_NEED_RESET;
10798 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10799 * @pdev: Pointer to PCI device
10801 * Restart the card from scratch, as if from a cold-boot.
10803 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10805 struct net_device *dev = pci_get_drvdata(pdev);
10806 struct bnx2x *bp = netdev_priv(dev);
10810 if (pci_enable_device(pdev)) {
10811 dev_err(&pdev->dev,
10812 "Cannot re-enable PCI device after reset\n");
10814 return PCI_ERS_RESULT_DISCONNECT;
10817 pci_set_master(pdev);
10818 pci_restore_state(pdev);
10820 if (netif_running(dev))
10821 bnx2x_set_power_state(bp, PCI_D0);
10825 return PCI_ERS_RESULT_RECOVERED;
10829 * bnx2x_io_resume - called when traffic can start flowing again
10830 * @pdev: Pointer to PCI device
10832 * This callback is called when the error recovery driver tells us that
10833 * its OK to resume normal operation.
10835 static void bnx2x_io_resume(struct pci_dev *pdev)
10837 struct net_device *dev = pci_get_drvdata(pdev);
10838 struct bnx2x *bp = netdev_priv(dev);
10840 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10841 netdev_err(bp->dev, "Handling parity error recovery. "
10842 "Try again later\n");
10848 bnx2x_eeh_recover(bp);
10850 if (netif_running(dev))
10851 bnx2x_nic_load(bp, LOAD_NORMAL);
10853 netif_device_attach(dev);
10858 static struct pci_error_handlers bnx2x_err_handler = {
10859 .error_detected = bnx2x_io_error_detected,
10860 .slot_reset = bnx2x_io_slot_reset,
10861 .resume = bnx2x_io_resume,
10864 static struct pci_driver bnx2x_pci_driver = {
10865 .name = DRV_MODULE_NAME,
10866 .id_table = bnx2x_pci_tbl,
10867 .probe = bnx2x_init_one,
10868 .remove = __devexit_p(bnx2x_remove_one),
10869 .suspend = bnx2x_suspend,
10870 .resume = bnx2x_resume,
10871 .err_handler = &bnx2x_err_handler,
10874 static int __init bnx2x_init(void)
10878 pr_info("%s", version);
10880 bnx2x_wq = create_singlethread_workqueue("bnx2x");
10881 if (bnx2x_wq == NULL) {
10882 pr_err("Cannot create workqueue\n");
10886 ret = pci_register_driver(&bnx2x_pci_driver);
10888 pr_err("Cannot register driver\n");
10889 destroy_workqueue(bnx2x_wq);
10894 static void __exit bnx2x_cleanup(void)
10896 pci_unregister_driver(&bnx2x_pci_driver);
10898 destroy_workqueue(bnx2x_wq);
10901 void bnx2x_notify_link_changed(struct bnx2x *bp)
10903 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
10906 module_init(bnx2x_init);
10907 module_exit(bnx2x_cleanup);
10911 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
10913 * @bp: driver handle
10914 * @set: set or clear the CAM entry
10916 * This function will wait until the ramdord completion returns.
10917 * Return 0 if success, -ENODEV if ramrod doesn't return.
10919 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
10921 unsigned long ramrod_flags = 0;
10923 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
10924 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
10925 &bp->iscsi_l2_mac_obj, true,
10926 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
10929 /* count denotes the number of new completions we have seen */
10930 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
10932 struct eth_spe *spe;
10934 #ifdef BNX2X_STOP_ON_ERROR
10935 if (unlikely(bp->panic))
10939 spin_lock_bh(&bp->spq_lock);
10940 BUG_ON(bp->cnic_spq_pending < count);
10941 bp->cnic_spq_pending -= count;
10944 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
10945 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
10946 & SPE_HDR_CONN_TYPE) >>
10947 SPE_HDR_CONN_TYPE_SHIFT;
10948 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
10949 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
10951 /* Set validation for iSCSI L2 client before sending SETUP
10954 if (type == ETH_CONNECTION_TYPE) {
10955 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
10956 bnx2x_set_ctx_validation(bp, &bp->context.
10957 vcxt[BNX2X_ISCSI_ETH_CID].eth,
10958 BNX2X_ISCSI_ETH_CID);
10962 * There may be not more than 8 L2, not more than 8 L5 SPEs
10963 * and in the air. We also check that number of outstanding
10964 * COMMON ramrods is not more than the EQ and SPQ can
10967 if (type == ETH_CONNECTION_TYPE) {
10968 if (!atomic_read(&bp->cq_spq_left))
10971 atomic_dec(&bp->cq_spq_left);
10972 } else if (type == NONE_CONNECTION_TYPE) {
10973 if (!atomic_read(&bp->eq_spq_left))
10976 atomic_dec(&bp->eq_spq_left);
10977 } else if ((type == ISCSI_CONNECTION_TYPE) ||
10978 (type == FCOE_CONNECTION_TYPE)) {
10979 if (bp->cnic_spq_pending >=
10980 bp->cnic_eth_dev.max_kwqe_pending)
10983 bp->cnic_spq_pending++;
10985 BNX2X_ERR("Unknown SPE type: %d\n", type);
10990 spe = bnx2x_sp_get_next(bp);
10991 *spe = *bp->cnic_kwq_cons;
10993 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
10994 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
10996 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
10997 bp->cnic_kwq_cons = bp->cnic_kwq;
10999 bp->cnic_kwq_cons++;
11001 bnx2x_sp_prod_update(bp);
11002 spin_unlock_bh(&bp->spq_lock);
11005 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11006 struct kwqe_16 *kwqes[], u32 count)
11008 struct bnx2x *bp = netdev_priv(dev);
11011 #ifdef BNX2X_STOP_ON_ERROR
11012 if (unlikely(bp->panic))
11016 spin_lock_bh(&bp->spq_lock);
11018 for (i = 0; i < count; i++) {
11019 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11021 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11024 *bp->cnic_kwq_prod = *spe;
11026 bp->cnic_kwq_pending++;
11028 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11029 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11030 spe->data.update_data_addr.hi,
11031 spe->data.update_data_addr.lo,
11032 bp->cnic_kwq_pending);
11034 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11035 bp->cnic_kwq_prod = bp->cnic_kwq;
11037 bp->cnic_kwq_prod++;
11040 spin_unlock_bh(&bp->spq_lock);
11042 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11043 bnx2x_cnic_sp_post(bp, 0);
11048 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11050 struct cnic_ops *c_ops;
11053 mutex_lock(&bp->cnic_mutex);
11054 c_ops = rcu_dereference_protected(bp->cnic_ops,
11055 lockdep_is_held(&bp->cnic_mutex));
11057 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11058 mutex_unlock(&bp->cnic_mutex);
11063 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11065 struct cnic_ops *c_ops;
11069 c_ops = rcu_dereference(bp->cnic_ops);
11071 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11078 * for commands that have no data
11080 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11082 struct cnic_ctl_info ctl = {0};
11086 return bnx2x_cnic_ctl_send(bp, &ctl);
11089 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11091 struct cnic_ctl_info ctl = {0};
11093 /* first we tell CNIC and only then we count this as a completion */
11094 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11095 ctl.data.comp.cid = cid;
11096 ctl.data.comp.error = err;
11098 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11099 bnx2x_cnic_sp_post(bp, 0);
11103 /* Called with netif_addr_lock_bh() taken.
11104 * Sets an rx_mode config for an iSCSI ETH client.
11106 * Completion should be checked outside.
11108 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11110 unsigned long accept_flags = 0, ramrod_flags = 0;
11111 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11112 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11115 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11116 * because it's the only way for UIO Queue to accept
11117 * multicasts (in non-promiscuous mode only one Queue per
11118 * function will receive multicast packets (leading in our
11121 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11122 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11123 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11124 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11126 /* Clear STOP_PENDING bit if START is requested */
11127 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11129 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11131 /* Clear START_PENDING bit if STOP is requested */
11132 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11134 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11135 set_bit(sched_state, &bp->sp_state);
11137 __set_bit(RAMROD_RX, &ramrod_flags);
11138 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11144 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11146 struct bnx2x *bp = netdev_priv(dev);
11149 switch (ctl->cmd) {
11150 case DRV_CTL_CTXTBL_WR_CMD: {
11151 u32 index = ctl->data.io.offset;
11152 dma_addr_t addr = ctl->data.io.dma_addr;
11154 bnx2x_ilt_wr(bp, index, addr);
11158 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11159 int count = ctl->data.credit.credit_count;
11161 bnx2x_cnic_sp_post(bp, count);
11165 /* rtnl_lock is held. */
11166 case DRV_CTL_START_L2_CMD: {
11167 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11168 unsigned long sp_bits = 0;
11170 /* Configure the iSCSI classification object */
11171 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11172 cp->iscsi_l2_client_id,
11173 cp->iscsi_l2_cid, BP_FUNC(bp),
11174 bnx2x_sp(bp, mac_rdata),
11175 bnx2x_sp_mapping(bp, mac_rdata),
11176 BNX2X_FILTER_MAC_PENDING,
11177 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11180 /* Set iSCSI MAC address */
11181 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11188 /* Start accepting on iSCSI L2 ring */
11190 netif_addr_lock_bh(dev);
11191 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11192 netif_addr_unlock_bh(dev);
11194 /* bits to wait on */
11195 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11196 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11198 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11199 BNX2X_ERR("rx_mode completion timed out!\n");
11204 /* rtnl_lock is held. */
11205 case DRV_CTL_STOP_L2_CMD: {
11206 unsigned long sp_bits = 0;
11208 /* Stop accepting on iSCSI L2 ring */
11209 netif_addr_lock_bh(dev);
11210 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11211 netif_addr_unlock_bh(dev);
11213 /* bits to wait on */
11214 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11215 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11217 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11218 BNX2X_ERR("rx_mode completion timed out!\n");
11223 /* Unset iSCSI L2 MAC */
11224 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11225 BNX2X_ISCSI_ETH_MAC, true);
11228 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11229 int count = ctl->data.credit.credit_count;
11231 smp_mb__before_atomic_inc();
11232 atomic_add(count, &bp->cq_spq_left);
11233 smp_mb__after_atomic_inc();
11238 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11245 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11247 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11249 if (bp->flags & USING_MSIX_FLAG) {
11250 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11251 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11252 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11254 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11255 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11257 if (!CHIP_IS_E1x(bp))
11258 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11260 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11262 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11263 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11264 cp->irq_arr[1].status_blk = bp->def_status_blk;
11265 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11266 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11271 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11274 struct bnx2x *bp = netdev_priv(dev);
11275 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11280 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11284 bp->cnic_kwq_cons = bp->cnic_kwq;
11285 bp->cnic_kwq_prod = bp->cnic_kwq;
11286 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11288 bp->cnic_spq_pending = 0;
11289 bp->cnic_kwq_pending = 0;
11291 bp->cnic_data = data;
11294 cp->drv_state |= CNIC_DRV_STATE_REGD;
11295 cp->iro_arr = bp->iro_arr;
11297 bnx2x_setup_cnic_irq_info(bp);
11299 rcu_assign_pointer(bp->cnic_ops, ops);
11304 static int bnx2x_unregister_cnic(struct net_device *dev)
11306 struct bnx2x *bp = netdev_priv(dev);
11307 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11309 mutex_lock(&bp->cnic_mutex);
11311 rcu_assign_pointer(bp->cnic_ops, NULL);
11312 mutex_unlock(&bp->cnic_mutex);
11314 kfree(bp->cnic_kwq);
11315 bp->cnic_kwq = NULL;
11320 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11322 struct bnx2x *bp = netdev_priv(dev);
11323 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11325 /* If both iSCSI and FCoE are disabled - return NULL in
11326 * order to indicate CNIC that it should not try to work
11327 * with this device.
11329 if (NO_ISCSI(bp) && NO_FCOE(bp))
11332 cp->drv_owner = THIS_MODULE;
11333 cp->chip_id = CHIP_ID(bp);
11334 cp->pdev = bp->pdev;
11335 cp->io_base = bp->regview;
11336 cp->io_base2 = bp->doorbells;
11337 cp->max_kwqe_pending = 8;
11338 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11339 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11340 bnx2x_cid_ilt_lines(bp);
11341 cp->ctx_tbl_len = CNIC_ILT_LINES;
11342 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11343 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11344 cp->drv_ctl = bnx2x_drv_ctl;
11345 cp->drv_register_cnic = bnx2x_register_cnic;
11346 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11347 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11348 cp->iscsi_l2_client_id =
11349 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11350 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11352 if (NO_ISCSI_OOO(bp))
11353 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11356 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11359 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11361 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11362 "starting cid %d\n",
11364 cp->ctx_tbl_offset,
11369 EXPORT_SYMBOL(bnx2x_cnic_probe);
11371 #endif /* BCM_CNIC */