1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30 /* [RW 1] Initiate the ATC array - reset all the valid bits */
31 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32 /* [R 1] ATC initalization done */
33 #define ATC_REG_ATC_INIT_DONE 0x1100bc
34 /* [RC 6] Interrupt register #0 read clear */
35 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36 /* [RW 19] Interrupt mask register #0 read/write */
37 #define BRB1_REG_BRB1_INT_MASK 0x60128
38 /* [R 19] Interrupt register #0 read */
39 #define BRB1_REG_BRB1_INT_STS 0x6011c
40 /* [RW 4] Parity mask register #0 read/write */
41 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
42 /* [R 4] Parity register #0 read */
43 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
44 /* [RC 4] Parity register #0 read clear */
45 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
46 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
47 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
48 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
49 * following reset the first rbc access to this reg must be write; there can
50 * be no more rbc writes after the first one; there can be any number of rbc
51 * read following the first write; rbc access not following these rules will
52 * result in hang condition. */
53 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
54 /* [RW 10] The number of free blocks below which the full signal to class 0
56 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
57 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
58 /* [RW 11] The number of free blocks above which the full signal to class 0
60 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
61 #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
62 /* [RW 11] The number of free blocks below which the full signal to class 1
64 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
65 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
66 /* [RW 11] The number of free blocks above which the full signal to class 1
68 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
69 #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
70 /* [RW 11] The number of free blocks below which the full signal to the LB
72 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
73 /* [RW 10] The number of free blocks above which the full signal to the LB
74 * port is de-asserted */
75 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
76 /* [RW 10] The number of free blocks above which the High_llfc signal to
77 interface #n is de-asserted. */
78 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
79 /* [RW 10] The number of free blocks below which the High_llfc signal to
80 interface #n is asserted. */
81 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
82 /* [RW 11] The number of blocks guarantied for the LB port */
83 #define BRB1_REG_LB_GUARANTIED 0x601ec
84 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
85 * before signaling XON. */
86 #define BRB1_REG_LB_GUARANTIED_HYST 0x60264
87 /* [RW 24] LL RAM data. */
88 #define BRB1_REG_LL_RAM 0x61000
89 /* [RW 10] The number of free blocks above which the Low_llfc signal to
90 interface #n is de-asserted. */
91 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
92 /* [RW 10] The number of free blocks below which the Low_llfc signal to
93 interface #n is asserted. */
94 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
95 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
96 * register is applicable only when per_class_guaranty_mode is set. */
97 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
98 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
99 * 1 before signaling XON. The register is applicable only when
100 * per_class_guaranty_mode is set. */
101 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
102 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
103 * register is applicable only when per_class_guaranty_mode is set. */
104 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
105 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
106 * before signaling XON. The register is applicable only when
107 * per_class_guaranty_mode is set. */
108 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
109 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
110 * is applicable only when per_class_guaranty_mode is set. */
111 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
112 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
113 * 1 before signaling XON. The register is applicable only when
114 * per_class_guaranty_mode is set. */
115 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
116 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
117 * register is applicable only when per_class_guaranty_mode is set. */
118 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
119 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
120 * 1 before signaling XON. The register is applicable only when
121 * per_class_guaranty_mode is set. */
122 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
123 /* [RW 11] The number of blocks guarantied for the MAC port. The register is
124 * applicable only when per_class_guaranty_mode is reset. */
125 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
126 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
127 /* [R 24] The number of full blocks. */
128 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
129 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
131 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
132 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
133 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
134 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
136 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
137 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
138 /* [RW 10] The number of free blocks below which the pause signal to class 0
140 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
141 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
142 /* [RW 11] The number of free blocks above which the pause signal to class 0
144 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
145 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
146 /* [RW 11] The number of free blocks below which the pause signal to class 1
148 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
149 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
150 /* [RW 11] The number of free blocks above which the pause signal to class 1
152 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
153 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
154 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
155 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
156 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
157 /* [RW 10] Write client 0: Assert pause threshold. */
158 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
159 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
160 /* [R 24] The number of full blocks occupied by port. */
161 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
162 /* [RW 1] Reset the design by software. */
163 #define BRB1_REG_SOFT_RESET 0x600dc
164 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
165 #define CCM_REG_CAM_OCCUP 0xd0188
166 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
167 acknowledge output is deasserted; all other signals are treated as usual;
168 if 1 - normal activity. */
169 #define CCM_REG_CCM_CFC_IFEN 0xd003c
170 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
171 disregarded; valid is deasserted; all other signals are treated as usual;
172 if 1 - normal activity. */
173 #define CCM_REG_CCM_CQM_IFEN 0xd000c
174 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
175 Otherwise 0 is inserted. */
176 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
177 /* [RW 11] Interrupt mask register #0 read/write */
178 #define CCM_REG_CCM_INT_MASK 0xd01e4
179 /* [R 11] Interrupt register #0 read */
180 #define CCM_REG_CCM_INT_STS 0xd01d8
181 /* [RW 27] Parity mask register #0 read/write */
182 #define CCM_REG_CCM_PRTY_MASK 0xd01f4
183 /* [R 27] Parity register #0 read */
184 #define CCM_REG_CCM_PRTY_STS 0xd01e8
185 /* [RC 27] Parity register #0 read clear */
186 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
187 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
188 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
189 Is used to determine the number of the AG context REG-pairs written back;
190 when the input message Reg1WbFlg isn't set. */
191 #define CCM_REG_CCM_REG0_SZ 0xd00c4
192 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
193 disregarded; valid is deasserted; all other signals are treated as usual;
194 if 1 - normal activity. */
195 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
196 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
197 disregarded; valid is deasserted; all other signals are treated as usual;
198 if 1 - normal activity. */
199 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
200 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
201 disregarded; valid output is deasserted; all other signals are treated as
202 usual; if 1 - normal activity. */
203 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
204 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
205 are disregarded; all other signals are treated as usual; if 1 - normal
207 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
208 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
209 disregarded; valid output is deasserted; all other signals are treated as
210 usual; if 1 - normal activity. */
211 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
212 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
213 input is disregarded; all other signals are treated as usual; if 1 -
215 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
216 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
217 the initial credit value; read returns the current value of the credit
218 counter. Must be initialized to 1 at start-up. */
219 #define CCM_REG_CFC_INIT_CRD 0xd0204
220 /* [RW 2] Auxiliary counter flag Q number 1. */
221 #define CCM_REG_CNT_AUX1_Q 0xd00c8
222 /* [RW 2] Auxiliary counter flag Q number 2. */
223 #define CCM_REG_CNT_AUX2_Q 0xd00cc
224 /* [RW 28] The CM header value for QM request (primary). */
225 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
226 /* [RW 28] The CM header value for QM request (secondary). */
227 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
228 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
229 acknowledge output is deasserted; all other signals are treated as usual;
230 if 1 - normal activity. */
231 #define CCM_REG_CQM_CCM_IFEN 0xd0014
232 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
233 the initial credit value; read returns the current value of the credit
234 counter. Must be initialized to 32 at start-up. */
235 #define CCM_REG_CQM_INIT_CRD 0xd020c
236 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
237 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
238 prioritised); 2 stands for weight 2; tc. */
239 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
240 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
241 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
242 prioritised); 2 stands for weight 2; tc. */
243 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
244 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
245 acknowledge output is deasserted; all other signals are treated as usual;
246 if 1 - normal activity. */
247 #define CCM_REG_CSDM_IFEN 0xd0018
248 /* [RC 1] Set when the message length mismatch (relative to last indication)
249 at the SDM interface is detected. */
250 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
251 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
252 weight 8 (the most prioritised); 1 stands for weight 1(least
253 prioritised); 2 stands for weight 2; tc. */
254 #define CCM_REG_CSDM_WEIGHT 0xd00b4
255 /* [RW 28] The CM header for QM formatting in case of an error in the QM
257 #define CCM_REG_ERR_CCM_HDR 0xd0094
258 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
259 #define CCM_REG_ERR_EVNT_ID 0xd0098
260 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
261 writes the initial credit value; read returns the current value of the
262 credit counter. Must be initialized to 64 at start-up. */
263 #define CCM_REG_FIC0_INIT_CRD 0xd0210
264 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
265 writes the initial credit value; read returns the current value of the
266 credit counter. Must be initialized to 64 at start-up. */
267 #define CCM_REG_FIC1_INIT_CRD 0xd0214
268 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
269 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
270 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
271 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
272 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
273 #define CCM_REG_GR_ARB_TYPE 0xd015c
274 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
275 highest priority is 3. It is supposed; that the Store channel priority is
276 the compliment to 4 of the rest priorities - Aggregation channel; Load
277 (FIC0) channel and Load (FIC1). */
278 #define CCM_REG_GR_LD0_PR 0xd0164
279 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
280 highest priority is 3. It is supposed; that the Store channel priority is
281 the compliment to 4 of the rest priorities - Aggregation channel; Load
282 (FIC0) channel and Load (FIC1). */
283 #define CCM_REG_GR_LD1_PR 0xd0168
284 /* [RW 2] General flags index. */
285 #define CCM_REG_INV_DONE_Q 0xd0108
286 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
287 context and sent to STORM; for a specific connection type. The double
288 REG-pairs are used in order to align to STORM context row size of 128
289 bits. The offset of these data in the STORM context is always 0. Index
290 _(0..15) stands for the connection type (one of 16). */
291 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
292 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
293 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
294 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
295 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
296 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
297 acknowledge output is deasserted; all other signals are treated as usual;
298 if 1 - normal activity. */
299 #define CCM_REG_PBF_IFEN 0xd0028
300 /* [RC 1] Set when the message length mismatch (relative to last indication)
301 at the pbf interface is detected. */
302 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
303 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
304 weight 8 (the most prioritised); 1 stands for weight 1(least
305 prioritised); 2 stands for weight 2; tc. */
306 #define CCM_REG_PBF_WEIGHT 0xd00ac
307 #define CCM_REG_PHYS_QNUM1_0 0xd0134
308 #define CCM_REG_PHYS_QNUM1_1 0xd0138
309 #define CCM_REG_PHYS_QNUM2_0 0xd013c
310 #define CCM_REG_PHYS_QNUM2_1 0xd0140
311 #define CCM_REG_PHYS_QNUM3_0 0xd0144
312 #define CCM_REG_PHYS_QNUM3_1 0xd0148
313 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
314 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
315 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
316 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
317 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
318 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
319 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
320 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
321 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
322 disregarded; acknowledge output is deasserted; all other signals are
323 treated as usual; if 1 - normal activity. */
324 #define CCM_REG_STORM_CCM_IFEN 0xd0010
325 /* [RC 1] Set when the message length mismatch (relative to last indication)
326 at the STORM interface is detected. */
327 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
328 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
329 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
330 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
332 #define CCM_REG_STORM_WEIGHT 0xd009c
333 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
334 disregarded; acknowledge output is deasserted; all other signals are
335 treated as usual; if 1 - normal activity. */
336 #define CCM_REG_TSEM_IFEN 0xd001c
337 /* [RC 1] Set when the message length mismatch (relative to last indication)
338 at the tsem interface is detected. */
339 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
340 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
341 weight 8 (the most prioritised); 1 stands for weight 1(least
342 prioritised); 2 stands for weight 2; tc. */
343 #define CCM_REG_TSEM_WEIGHT 0xd00a0
344 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
345 disregarded; acknowledge output is deasserted; all other signals are
346 treated as usual; if 1 - normal activity. */
347 #define CCM_REG_USEM_IFEN 0xd0024
348 /* [RC 1] Set when message length mismatch (relative to last indication) at
349 the usem interface is detected. */
350 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
351 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
352 weight 8 (the most prioritised); 1 stands for weight 1(least
353 prioritised); 2 stands for weight 2; tc. */
354 #define CCM_REG_USEM_WEIGHT 0xd00a8
355 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
356 disregarded; acknowledge output is deasserted; all other signals are
357 treated as usual; if 1 - normal activity. */
358 #define CCM_REG_XSEM_IFEN 0xd0020
359 /* [RC 1] Set when the message length mismatch (relative to last indication)
360 at the xsem interface is detected. */
361 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
362 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
363 weight 8 (the most prioritised); 1 stands for weight 1(least
364 prioritised); 2 stands for weight 2; tc. */
365 #define CCM_REG_XSEM_WEIGHT 0xd00a4
366 /* [RW 19] Indirect access to the descriptor table of the XX protection
367 mechanism. The fields are: [5:0] - message length; [12:6] - message
368 pointer; 18:13] - next pointer. */
369 #define CCM_REG_XX_DESCR_TABLE 0xd0300
370 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
371 /* [R 7] Used to read the value of XX protection Free counter. */
372 #define CCM_REG_XX_FREE 0xd0184
373 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
374 of the Input Stage XX protection buffer by the XX protection pending
375 messages. Max credit available - 127. Write writes the initial credit
376 value; read returns the current value of the credit counter. Must be
377 initialized to maximum XX protected message size - 2 at start-up. */
378 #define CCM_REG_XX_INIT_CRD 0xd0220
379 /* [RW 7] The maximum number of pending messages; which may be stored in XX
380 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
381 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
383 #define CCM_REG_XX_MSG_NUM 0xd0224
384 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
385 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
386 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
387 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
389 #define CCM_REG_XX_TABLE 0xd0280
390 #define CDU_REG_CDU_CHK_MASK0 0x101000
391 #define CDU_REG_CDU_CHK_MASK1 0x101004
392 #define CDU_REG_CDU_CONTROL0 0x101008
393 #define CDU_REG_CDU_DEBUG 0x101010
394 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
395 /* [RW 7] Interrupt mask register #0 read/write */
396 #define CDU_REG_CDU_INT_MASK 0x10103c
397 /* [R 7] Interrupt register #0 read */
398 #define CDU_REG_CDU_INT_STS 0x101030
399 /* [RW 5] Parity mask register #0 read/write */
400 #define CDU_REG_CDU_PRTY_MASK 0x10104c
401 /* [R 5] Parity register #0 read */
402 #define CDU_REG_CDU_PRTY_STS 0x101040
403 /* [RC 5] Parity register #0 read clear */
404 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044
405 /* [RC 32] logging of error data in case of a CDU load error:
406 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
407 ype_error; ctual_active; ctual_compressed_context}; */
408 #define CDU_REG_ERROR_DATA 0x101014
409 /* [WB 216] L1TT ram access. each entry has the following format :
410 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
411 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
412 #define CDU_REG_L1TT 0x101800
413 /* [WB 24] MATT ram access. each entry has the following
414 format:{RegionLength[11:0]; egionOffset[11:0]} */
415 #define CDU_REG_MATT 0x101100
416 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
417 #define CDU_REG_MF_MODE 0x101050
418 /* [R 1] indication the initializing the activity counter by the hardware
420 #define CFC_REG_AC_INIT_DONE 0x104078
421 /* [RW 13] activity counter ram access */
422 #define CFC_REG_ACTIVITY_COUNTER 0x104400
423 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
424 /* [R 1] indication the initializing the cams by the hardware was done. */
425 #define CFC_REG_CAM_INIT_DONE 0x10407c
426 /* [RW 2] Interrupt mask register #0 read/write */
427 #define CFC_REG_CFC_INT_MASK 0x104108
428 /* [R 2] Interrupt register #0 read */
429 #define CFC_REG_CFC_INT_STS 0x1040fc
430 /* [RC 2] Interrupt register #0 read clear */
431 #define CFC_REG_CFC_INT_STS_CLR 0x104100
432 /* [RW 4] Parity mask register #0 read/write */
433 #define CFC_REG_CFC_PRTY_MASK 0x104118
434 /* [R 4] Parity register #0 read */
435 #define CFC_REG_CFC_PRTY_STS 0x10410c
436 /* [RC 4] Parity register #0 read clear */
437 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110
438 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
439 #define CFC_REG_CID_CAM 0x104800
440 #define CFC_REG_CONTROL0 0x104028
441 #define CFC_REG_DEBUG0 0x104050
442 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
443 vector) whether the cfc should be disabled upon it */
444 #define CFC_REG_DISABLE_ON_ERROR 0x104044
445 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
446 set one of these bits. the bit description can be found in CFC
448 #define CFC_REG_ERROR_VECTOR 0x10403c
449 /* [WB 93] LCID info ram access */
450 #define CFC_REG_INFO_RAM 0x105000
451 #define CFC_REG_INFO_RAM_SIZE 1024
452 #define CFC_REG_INIT_REG 0x10404c
453 #define CFC_REG_INTERFACES 0x104058
454 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
455 field allows changing the priorities of the weighted-round-robin arbiter
456 which selects which CFC load client should be served next */
457 #define CFC_REG_LCREQ_WEIGHTS 0x104084
458 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
459 #define CFC_REG_LINK_LIST 0x104c00
460 #define CFC_REG_LINK_LIST_SIZE 256
461 /* [R 1] indication the initializing the link list by the hardware was done. */
462 #define CFC_REG_LL_INIT_DONE 0x104074
463 /* [R 9] Number of allocated LCIDs which are at empty state */
464 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
465 /* [R 9] Number of Arriving LCIDs in Link List Block */
466 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
467 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
468 /* [R 9] Number of Leaving LCIDs in Link List Block */
469 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
470 #define CFC_REG_WEAK_ENABLE_PF 0x104124
471 /* [RW 8] The event id for aggregated interrupt 0 */
472 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
473 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
474 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
475 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
476 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
477 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
478 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
479 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
480 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
481 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
482 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
483 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
484 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
485 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
486 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
487 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
488 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
489 or auto-mask-mode (1) */
490 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
491 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
492 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
493 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
494 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
495 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
496 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
497 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
498 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
499 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
500 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
501 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
502 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
503 /* [RW 16] The maximum value of the completion counter #0 */
504 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
505 /* [RW 16] The maximum value of the completion counter #1 */
506 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
507 /* [RW 16] The maximum value of the completion counter #2 */
508 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
509 /* [RW 16] The maximum value of the completion counter #3 */
510 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
511 /* [RW 13] The start address in the internal RAM for the completion
513 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
514 /* [RW 32] Interrupt mask register #0 read/write */
515 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
516 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
517 /* [R 32] Interrupt register #0 read */
518 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
519 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
520 /* [RW 11] Parity mask register #0 read/write */
521 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
522 /* [R 11] Parity register #0 read */
523 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
524 /* [RC 11] Parity register #0 read clear */
525 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
526 #define CSDM_REG_ENABLE_IN1 0xc2238
527 #define CSDM_REG_ENABLE_IN2 0xc223c
528 #define CSDM_REG_ENABLE_OUT1 0xc2240
529 #define CSDM_REG_ENABLE_OUT2 0xc2244
530 /* [RW 4] The initial number of messages that can be sent to the pxp control
531 interface without receiving any ACK. */
532 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
533 /* [ST 32] The number of ACK after placement messages received */
534 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
535 /* [ST 32] The number of packet end messages received from the parser */
536 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
537 /* [ST 32] The number of requests received from the pxp async if */
538 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
539 /* [ST 32] The number of commands received in queue 0 */
540 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
541 /* [ST 32] The number of commands received in queue 10 */
542 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
543 /* [ST 32] The number of commands received in queue 11 */
544 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
545 /* [ST 32] The number of commands received in queue 1 */
546 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
547 /* [ST 32] The number of commands received in queue 3 */
548 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
549 /* [ST 32] The number of commands received in queue 4 */
550 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
551 /* [ST 32] The number of commands received in queue 5 */
552 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
553 /* [ST 32] The number of commands received in queue 6 */
554 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
555 /* [ST 32] The number of commands received in queue 7 */
556 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
557 /* [ST 32] The number of commands received in queue 8 */
558 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
559 /* [ST 32] The number of commands received in queue 9 */
560 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
561 /* [RW 13] The start address in the internal RAM for queue counters */
562 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
563 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
564 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
565 /* [R 1] parser fifo empty in sdm_sync block */
566 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
567 /* [R 1] parser serial fifo empty in sdm_sync block */
568 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
569 /* [RW 32] Tick for timer counter. Applicable only when
570 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
571 #define CSDM_REG_TIMER_TICK 0xc2000
572 /* [RW 5] The number of time_slots in the arbitration cycle */
573 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
574 /* [RW 3] The source that is associated with arbitration element 0. Source
575 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
576 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
577 #define CSEM_REG_ARB_ELEMENT0 0x200020
578 /* [RW 3] The source that is associated with arbitration element 1. Source
579 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
580 sleeping thread with priority 1; 4- sleeping thread with priority 2.
581 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
582 #define CSEM_REG_ARB_ELEMENT1 0x200024
583 /* [RW 3] The source that is associated with arbitration element 2. Source
584 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
585 sleeping thread with priority 1; 4- sleeping thread with priority 2.
586 Could not be equal to register ~csem_registers_arb_element0.arb_element0
587 and ~csem_registers_arb_element1.arb_element1 */
588 #define CSEM_REG_ARB_ELEMENT2 0x200028
589 /* [RW 3] The source that is associated with arbitration element 3. Source
590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
591 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
592 not be equal to register ~csem_registers_arb_element0.arb_element0 and
593 ~csem_registers_arb_element1.arb_element1 and
594 ~csem_registers_arb_element2.arb_element2 */
595 #define CSEM_REG_ARB_ELEMENT3 0x20002c
596 /* [RW 3] The source that is associated with arbitration element 4. Source
597 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
598 sleeping thread with priority 1; 4- sleeping thread with priority 2.
599 Could not be equal to register ~csem_registers_arb_element0.arb_element0
600 and ~csem_registers_arb_element1.arb_element1 and
601 ~csem_registers_arb_element2.arb_element2 and
602 ~csem_registers_arb_element3.arb_element3 */
603 #define CSEM_REG_ARB_ELEMENT4 0x200030
604 /* [RW 32] Interrupt mask register #0 read/write */
605 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
606 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
607 /* [R 32] Interrupt register #0 read */
608 #define CSEM_REG_CSEM_INT_STS_0 0x200104
609 #define CSEM_REG_CSEM_INT_STS_1 0x200114
610 /* [RW 32] Parity mask register #0 read/write */
611 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
612 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
613 /* [R 32] Parity register #0 read */
614 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
615 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
616 /* [RC 32] Parity register #0 read clear */
617 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
618 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
619 #define CSEM_REG_ENABLE_IN 0x2000a4
620 #define CSEM_REG_ENABLE_OUT 0x2000a8
621 /* [RW 32] This address space contains all registers and memories that are
622 placed in SEM_FAST block. The SEM_FAST registers are described in
623 appendix B. In order to access the sem_fast registers the base address
624 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
625 #define CSEM_REG_FAST_MEMORY 0x220000
626 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
628 #define CSEM_REG_FIC0_DISABLE 0x200224
629 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
631 #define CSEM_REG_FIC1_DISABLE 0x200234
632 /* [RW 15] Interrupt table Read and write access to it is not possible in
633 the middle of the work */
634 #define CSEM_REG_INT_TABLE 0x200400
635 /* [ST 24] Statistics register. The number of messages that entered through
637 #define CSEM_REG_MSG_NUM_FIC0 0x200000
638 /* [ST 24] Statistics register. The number of messages that entered through
640 #define CSEM_REG_MSG_NUM_FIC1 0x200004
641 /* [ST 24] Statistics register. The number of messages that were sent to
643 #define CSEM_REG_MSG_NUM_FOC0 0x200008
644 /* [ST 24] Statistics register. The number of messages that were sent to
646 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
647 /* [ST 24] Statistics register. The number of messages that were sent to
649 #define CSEM_REG_MSG_NUM_FOC2 0x200010
650 /* [ST 24] Statistics register. The number of messages that were sent to
652 #define CSEM_REG_MSG_NUM_FOC3 0x200014
653 /* [RW 1] Disables input messages from the passive buffer May be updated
654 during run_time by the microcode */
655 #define CSEM_REG_PAS_DISABLE 0x20024c
656 /* [WB 128] Debug only. Passive buffer memory */
657 #define CSEM_REG_PASSIVE_BUFFER 0x202000
658 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
659 #define CSEM_REG_PRAM 0x240000
660 /* [R 16] Valid sleeping threads indication have bit per thread */
661 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
662 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
663 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
664 /* [RW 16] List of free threads . There is a bit per thread. */
665 #define CSEM_REG_THREADS_LIST 0x2002e4
666 /* [RW 3] The arbitration scheme of time_slot 0 */
667 #define CSEM_REG_TS_0_AS 0x200038
668 /* [RW 3] The arbitration scheme of time_slot 10 */
669 #define CSEM_REG_TS_10_AS 0x200060
670 /* [RW 3] The arbitration scheme of time_slot 11 */
671 #define CSEM_REG_TS_11_AS 0x200064
672 /* [RW 3] The arbitration scheme of time_slot 12 */
673 #define CSEM_REG_TS_12_AS 0x200068
674 /* [RW 3] The arbitration scheme of time_slot 13 */
675 #define CSEM_REG_TS_13_AS 0x20006c
676 /* [RW 3] The arbitration scheme of time_slot 14 */
677 #define CSEM_REG_TS_14_AS 0x200070
678 /* [RW 3] The arbitration scheme of time_slot 15 */
679 #define CSEM_REG_TS_15_AS 0x200074
680 /* [RW 3] The arbitration scheme of time_slot 16 */
681 #define CSEM_REG_TS_16_AS 0x200078
682 /* [RW 3] The arbitration scheme of time_slot 17 */
683 #define CSEM_REG_TS_17_AS 0x20007c
684 /* [RW 3] The arbitration scheme of time_slot 18 */
685 #define CSEM_REG_TS_18_AS 0x200080
686 /* [RW 3] The arbitration scheme of time_slot 1 */
687 #define CSEM_REG_TS_1_AS 0x20003c
688 /* [RW 3] The arbitration scheme of time_slot 2 */
689 #define CSEM_REG_TS_2_AS 0x200040
690 /* [RW 3] The arbitration scheme of time_slot 3 */
691 #define CSEM_REG_TS_3_AS 0x200044
692 /* [RW 3] The arbitration scheme of time_slot 4 */
693 #define CSEM_REG_TS_4_AS 0x200048
694 /* [RW 3] The arbitration scheme of time_slot 5 */
695 #define CSEM_REG_TS_5_AS 0x20004c
696 /* [RW 3] The arbitration scheme of time_slot 6 */
697 #define CSEM_REG_TS_6_AS 0x200050
698 /* [RW 3] The arbitration scheme of time_slot 7 */
699 #define CSEM_REG_TS_7_AS 0x200054
700 /* [RW 3] The arbitration scheme of time_slot 8 */
701 #define CSEM_REG_TS_8_AS 0x200058
702 /* [RW 3] The arbitration scheme of time_slot 9 */
703 #define CSEM_REG_TS_9_AS 0x20005c
704 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
705 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
706 #define CSEM_REG_VFPF_ERR_NUM 0x200380
707 /* [RW 1] Parity mask register #0 read/write */
708 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
709 /* [R 1] Parity register #0 read */
710 #define DBG_REG_DBG_PRTY_STS 0xc09c
711 /* [RC 1] Parity register #0 read clear */
712 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
713 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
714 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
715 * 4.Completion function=0; 5.Error handling=0 */
716 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
717 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
719 #define DMAE_REG_CMD_MEM 0x102400
720 #define DMAE_REG_CMD_MEM_SIZE 224
721 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
722 initial value is all ones. */
723 #define DMAE_REG_CRC16C_INIT 0x10201c
724 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
725 CRC-16 T10 initial value is all ones. */
726 #define DMAE_REG_CRC16T10_INIT 0x102020
727 /* [RW 2] Interrupt mask register #0 read/write */
728 #define DMAE_REG_DMAE_INT_MASK 0x102054
729 /* [RW 4] Parity mask register #0 read/write */
730 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
731 /* [R 4] Parity register #0 read */
732 #define DMAE_REG_DMAE_PRTY_STS 0x102058
733 /* [RC 4] Parity register #0 read clear */
734 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
735 /* [RW 1] Command 0 go. */
736 #define DMAE_REG_GO_C0 0x102080
737 /* [RW 1] Command 1 go. */
738 #define DMAE_REG_GO_C1 0x102084
739 /* [RW 1] Command 10 go. */
740 #define DMAE_REG_GO_C10 0x102088
741 /* [RW 1] Command 11 go. */
742 #define DMAE_REG_GO_C11 0x10208c
743 /* [RW 1] Command 12 go. */
744 #define DMAE_REG_GO_C12 0x102090
745 /* [RW 1] Command 13 go. */
746 #define DMAE_REG_GO_C13 0x102094
747 /* [RW 1] Command 14 go. */
748 #define DMAE_REG_GO_C14 0x102098
749 /* [RW 1] Command 15 go. */
750 #define DMAE_REG_GO_C15 0x10209c
751 /* [RW 1] Command 2 go. */
752 #define DMAE_REG_GO_C2 0x1020a0
753 /* [RW 1] Command 3 go. */
754 #define DMAE_REG_GO_C3 0x1020a4
755 /* [RW 1] Command 4 go. */
756 #define DMAE_REG_GO_C4 0x1020a8
757 /* [RW 1] Command 5 go. */
758 #define DMAE_REG_GO_C5 0x1020ac
759 /* [RW 1] Command 6 go. */
760 #define DMAE_REG_GO_C6 0x1020b0
761 /* [RW 1] Command 7 go. */
762 #define DMAE_REG_GO_C7 0x1020b4
763 /* [RW 1] Command 8 go. */
764 #define DMAE_REG_GO_C8 0x1020b8
765 /* [RW 1] Command 9 go. */
766 #define DMAE_REG_GO_C9 0x1020bc
767 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
768 input is disregarded; valid is deasserted; all other signals are treated
769 as usual; if 1 - normal activity. */
770 #define DMAE_REG_GRC_IFEN 0x102008
771 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
772 acknowledge input is disregarded; valid is deasserted; full is asserted;
773 all other signals are treated as usual; if 1 - normal activity. */
774 #define DMAE_REG_PCI_IFEN 0x102004
775 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
776 initial value to the credit counter; related to the address. Read returns
777 the current value of the counter. */
778 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
779 /* [RW 8] Aggregation command. */
780 #define DORQ_REG_AGG_CMD0 0x170060
781 /* [RW 8] Aggregation command. */
782 #define DORQ_REG_AGG_CMD1 0x170064
783 /* [RW 8] Aggregation command. */
784 #define DORQ_REG_AGG_CMD2 0x170068
785 /* [RW 8] Aggregation command. */
786 #define DORQ_REG_AGG_CMD3 0x17006c
787 /* [RW 28] UCM Header. */
788 #define DORQ_REG_CMHEAD_RX 0x170050
789 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
790 #define DORQ_REG_DB_ADDR0 0x17008c
791 /* [RW 5] Interrupt mask register #0 read/write */
792 #define DORQ_REG_DORQ_INT_MASK 0x170180
793 /* [R 5] Interrupt register #0 read */
794 #define DORQ_REG_DORQ_INT_STS 0x170174
795 /* [RC 5] Interrupt register #0 read clear */
796 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
797 /* [RW 2] Parity mask register #0 read/write */
798 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
799 /* [R 2] Parity register #0 read */
800 #define DORQ_REG_DORQ_PRTY_STS 0x170184
801 /* [RC 2] Parity register #0 read clear */
802 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
803 /* [RW 8] The address to write the DPM CID to STORM. */
804 #define DORQ_REG_DPM_CID_ADDR 0x170044
805 /* [RW 5] The DPM mode CID extraction offset. */
806 #define DORQ_REG_DPM_CID_OFST 0x170030
807 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
808 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
809 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
810 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
811 /* [R 13] Current value of the DQ FIFO fill level according to following
812 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
814 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
815 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
816 equal to full threshold; reset on full clear. */
817 #define DORQ_REG_DQ_FULL_ST 0x1700c0
818 /* [RW 28] The value sent to CM header in the case of CFC load error. */
819 #define DORQ_REG_ERR_CMHEAD 0x170058
820 #define DORQ_REG_IF_EN 0x170004
821 #define DORQ_REG_MODE_ACT 0x170008
822 /* [RW 5] The normal mode CID extraction offset. */
823 #define DORQ_REG_NORM_CID_OFST 0x17002c
824 /* [RW 28] TCM Header when only TCP context is loaded. */
825 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
826 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
828 #define DORQ_REG_OUTST_REQ 0x17003c
829 #define DORQ_REG_PF_USAGE_CNT 0x1701d0
830 #define DORQ_REG_REGN 0x170038
831 /* [R 4] Current value of response A counter credit. Initial credit is
832 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
834 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
835 /* [R 4] Current value of response B counter credit. Initial credit is
836 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
838 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
839 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
840 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
841 read reads this written value. */
842 #define DORQ_REG_RSP_INIT_CRD 0x170048
843 /* [RW 4] Initial activity counter value on the load request; when the
845 #define DORQ_REG_SHRT_ACT_CNT 0x170070
846 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
847 #define DORQ_REG_SHRT_CMHEAD 0x170054
848 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
849 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
850 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
851 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
852 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
853 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
854 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
855 #define HC_REG_AGG_INT_0 0x108050
856 #define HC_REG_AGG_INT_1 0x108054
857 #define HC_REG_ATTN_BIT 0x108120
858 #define HC_REG_ATTN_IDX 0x108100
859 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
860 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
861 #define HC_REG_ATTN_NUM_P0 0x108038
862 #define HC_REG_ATTN_NUM_P1 0x10803c
863 #define HC_REG_COMMAND_REG 0x108180
864 #define HC_REG_CONFIG_0 0x108000
865 #define HC_REG_CONFIG_1 0x108004
866 #define HC_REG_FUNC_NUM_P0 0x1080ac
867 #define HC_REG_FUNC_NUM_P1 0x1080b0
868 /* [RW 3] Parity mask register #0 read/write */
869 #define HC_REG_HC_PRTY_MASK 0x1080a0
870 /* [R 3] Parity register #0 read */
871 #define HC_REG_HC_PRTY_STS 0x108094
872 /* [RC 3] Parity register #0 read clear */
873 #define HC_REG_HC_PRTY_STS_CLR 0x108098
874 #define HC_REG_INT_MASK 0x108108
875 #define HC_REG_LEADING_EDGE_0 0x108040
876 #define HC_REG_LEADING_EDGE_1 0x108048
877 #define HC_REG_MAIN_MEMORY 0x108800
878 #define HC_REG_MAIN_MEMORY_SIZE 152
879 #define HC_REG_P0_PROD_CONS 0x108200
880 #define HC_REG_P1_PROD_CONS 0x108400
881 #define HC_REG_PBA_COMMAND 0x108140
882 #define HC_REG_PCI_CONFIG_0 0x108010
883 #define HC_REG_PCI_CONFIG_1 0x108014
884 #define HC_REG_STATISTIC_COUNTERS 0x109000
885 #define HC_REG_TRAILING_EDGE_0 0x108044
886 #define HC_REG_TRAILING_EDGE_1 0x10804c
887 #define HC_REG_UC_RAM_ADDR_0 0x108028
888 #define HC_REG_UC_RAM_ADDR_1 0x108030
889 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
890 #define HC_REG_VQID_0 0x108008
891 #define HC_REG_VQID_1 0x10800c
892 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
893 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
894 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
895 /* [R 4] Debug: attn_fsm */
896 #define IGU_REG_ATTN_FSM 0x130054
897 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
898 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
899 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
900 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
901 * write done didn't receive. */
902 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
903 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
904 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
905 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
906 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
907 * is clear. The bits in this registers are set and clear via the producer
908 * command. Data valid only in addresses 0-4. all the rest are zero. */
909 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
910 /* [R 5] Debug: ctrl_fsm */
911 #define IGU_REG_CTRL_FSM 0x130064
912 /* [R 1] data available for error memory. If this bit is clear do not red
913 * from error_handling_memory. */
914 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
915 /* [RW 11] Parity mask register #0 read/write */
916 #define IGU_REG_IGU_PRTY_MASK 0x1300a8
917 /* [R 11] Parity register #0 read */
918 #define IGU_REG_IGU_PRTY_STS 0x13009c
919 /* [RC 11] Parity register #0 read clear */
920 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
921 /* [R 4] Debug: int_handle_fsm */
922 #define IGU_REG_INT_HANDLE_FSM 0x130050
923 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
924 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
925 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
926 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
927 #define IGU_REG_MAPPING_MEMORY 0x131000
928 #define IGU_REG_MAPPING_MEMORY_SIZE 136
929 #define IGU_REG_PBA_STATUS_LSB 0x130138
930 #define IGU_REG_PBA_STATUS_MSB 0x13013c
931 #define IGU_REG_PCI_PF_MSI_EN 0x130140
932 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
933 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
934 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
935 * pending; 1 = pending. Pendings means interrupt was asserted; and write
936 * done was not received. Data valid only in addresses 0-4. all the rest are
938 #define IGU_REG_PENDING_BITS_STATUS 0x130300
939 #define IGU_REG_PF_CONFIGURATION 0x130154
940 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
941 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
942 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
943 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
944 * - In backward compatible mode; for non default SB; each even line in the
945 * memory holds the U producer and each odd line hold the C producer. The
946 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
947 * last 20 producers are for the DSB for each PF. each PF has five segments
948 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
949 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
950 #define IGU_REG_PROD_CONS_MEMORY 0x132000
951 /* [R 3] Debug: pxp_arb_fsm */
952 #define IGU_REG_PXP_ARB_FSM 0x130068
953 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
954 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
955 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
956 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
957 #define IGU_REG_RESET_MEMORIES 0x130158
958 /* [R 4] Debug: sb_ctrl_fsm */
959 #define IGU_REG_SB_CTRL_FSM 0x13004c
960 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
961 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
962 #define IGU_REG_SB_MASK_LSB 0x130164
963 #define IGU_REG_SB_MASK_MSB 0x130168
964 /* [RW 16] Number of command that were dropped without causing an interrupt
965 * due to: read access for WO BAR address; or write access for RO BAR
966 * address or any access for reserved address or PCI function error is set
967 * and address is not MSIX; PBA or cleanup */
968 #define IGU_REG_SILENT_DROP 0x13016c
969 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
970 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
971 * PF; 68-71 number of ATTN messages per PF */
972 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
973 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
974 * timer mask command arrives. Value must be bigger than 100. */
975 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
976 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
977 #define IGU_REG_VF_CONFIGURATION 0x130170
978 /* [WB_R 32] Each bit represent write done pending bits status for that SB
979 * (MSI/MSIX message was sent and write done was not received yet). 0 =
980 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
981 #define IGU_REG_WRITE_DONE_PENDING 0x130480
982 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
983 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
984 #define MCP_REG_MCPR_GP_INPUTS 0x800c0
985 #define MCP_REG_MCPR_GP_OENABLE 0x800c8
986 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
987 #define MCP_REG_MCPR_IMC_COMMAND 0x85900
988 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920
989 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
990 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
991 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
992 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
993 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
994 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
995 #define MCP_REG_MCPR_NVM_READ 0x86410
996 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
997 #define MCP_REG_MCPR_NVM_WRITE 0x86408
998 #define MCP_REG_MCPR_SCRATCH 0xa0000
999 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1000 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
1001 /* [R 32] read first 32 bit after inversion of function 0. mapped as
1002 follows: [0] NIG attention for function0; [1] NIG attention for
1003 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1004 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1005 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1006 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1007 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1008 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1009 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1010 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1011 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1012 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1013 Parity error; [31] PBF Hw interrupt; */
1014 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1015 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1016 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1017 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1018 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1019 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1020 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1021 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1022 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1023 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1024 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1025 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1026 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1027 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1029 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1030 /* [R 32] read second 32 bit after inversion of function 0. mapped as
1031 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1032 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1033 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1034 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1035 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1036 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1037 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1038 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1039 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1040 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1041 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1043 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1044 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1045 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1046 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1047 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1048 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1049 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1050 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1051 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1052 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1053 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1054 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1055 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1056 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1057 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1058 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1059 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1060 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1061 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1062 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1063 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1064 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1065 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1066 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1067 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1068 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1069 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1071 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1072 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1073 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1074 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1075 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1076 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1077 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1078 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1079 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1080 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1081 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1082 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1083 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1084 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1085 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1086 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1087 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1088 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1089 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1090 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1091 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1092 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1093 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1094 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1095 Latched timeout attention; [27] GRC Latched reserved access attention;
1096 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1097 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1098 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1099 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1100 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1101 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1102 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1103 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1104 General attn13; [12] General attn14; [13] General attn15; [14] General
1105 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1106 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1107 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1108 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1109 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1110 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1111 ump_tx_parity; [31] MCP Latched scpad_parity; */
1112 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1113 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1114 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1115 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1116 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1117 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1118 /* [W 14] write to this register results with the clear of the latched
1119 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1120 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1121 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1122 GRC Latched reserved access attention; one in d7 clears Latched
1123 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1124 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1125 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1126 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1127 from this register return zero */
1128 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1129 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1130 as follows: [0] NIG attention for function0; [1] NIG attention for
1131 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1132 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1133 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1134 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1135 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1136 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1137 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1138 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1139 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1140 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1141 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1142 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1143 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1144 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1145 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1146 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1147 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1148 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1149 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1150 as follows: [0] NIG attention for function0; [1] NIG attention for
1151 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1152 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1153 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1154 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1155 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1156 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1157 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1158 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1159 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1160 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1161 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1162 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1163 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1164 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1165 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1166 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1167 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1168 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1169 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1170 as follows: [0] NIG attention for function0; [1] NIG attention for
1171 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1172 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1173 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1174 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1175 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1176 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1177 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1178 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1179 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1180 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1181 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1182 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1183 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1184 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1185 as follows: [0] NIG attention for function0; [1] NIG attention for
1186 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1187 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1188 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1189 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1190 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1191 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1192 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1193 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1194 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1195 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1196 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1197 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1198 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1199 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1200 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1201 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1202 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1203 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1204 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1205 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1206 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1207 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1208 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1209 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1210 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1212 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1213 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1214 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1215 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1216 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1217 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1218 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1219 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1220 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1221 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1222 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1223 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1224 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1225 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1227 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1228 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1229 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1230 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1231 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1232 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1233 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1234 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1235 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1236 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1237 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1238 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1239 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1240 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1242 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1243 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1244 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1245 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1246 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1247 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1248 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1249 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1250 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1251 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1252 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1253 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1254 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1255 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1257 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1258 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1259 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1260 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1261 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1262 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1263 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1264 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1265 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1266 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1267 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1268 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1269 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1270 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1272 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1273 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1274 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1275 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1276 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1277 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1278 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1279 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1280 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1281 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1282 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1283 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1284 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1285 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1287 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1288 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1289 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1290 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1291 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1292 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1293 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1294 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1295 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1296 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1297 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1298 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1299 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1300 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1302 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1303 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1304 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1305 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1306 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1307 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1308 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1309 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1310 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1311 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1312 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1313 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1314 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1315 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1317 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1318 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1319 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1320 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1321 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1322 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1323 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1324 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1325 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1326 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1327 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1328 Latched timeout attention; [27] GRC Latched reserved access attention;
1329 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1330 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1331 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1332 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1333 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1334 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1335 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1336 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1337 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1338 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1339 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1340 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1341 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1342 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1343 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1344 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1345 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1346 Latched timeout attention; [27] GRC Latched reserved access attention;
1347 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1348 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1349 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1350 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1351 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1352 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1353 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1354 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1355 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1356 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1357 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1358 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1359 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1360 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1361 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1362 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1363 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1364 Latched timeout attention; [27] GRC Latched reserved access attention;
1365 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1366 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1367 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1368 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1369 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1370 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1371 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1372 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1373 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1374 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1375 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1376 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1377 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1378 Latched timeout attention; [27] GRC Latched reserved access attention;
1379 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1380 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1381 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1382 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1383 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1385 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1386 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1387 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1388 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1389 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1390 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1391 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1392 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1393 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1394 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1395 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1396 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1397 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1398 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1399 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1400 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1401 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1402 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1403 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1404 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1405 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1406 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1407 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1408 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1409 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1410 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1411 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1412 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1413 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1414 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1415 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1416 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1417 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1418 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1419 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1420 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1421 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1422 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1423 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1424 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1425 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1426 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1427 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1428 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1429 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1430 [9:8] = raserved. Zero = mask; one = unmask */
1431 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1432 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1433 /* [RW 1] If set a system kill occurred */
1434 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1435 /* [RW 32] Represent the status of the input vector to the AEU when a system
1436 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1437 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1438 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1439 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1440 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1441 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1442 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1443 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1444 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1445 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1446 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1447 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1449 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1450 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1451 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1452 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1453 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1455 #define MISC_REG_BOND_ID 0xa400
1456 /* [R 8] These bits indicate the metal revision of the chip. This value
1457 starts at 0x00 for each all-layer tape-out and increments by one for each
1459 #define MISC_REG_CHIP_METAL 0xa404
1460 /* [R 16] These bits indicate the part number for the chip. */
1461 #define MISC_REG_CHIP_NUM 0xa408
1462 /* [R 4] These bits indicate the base revision of the chip. This value
1463 starts at 0x0 for the A0 tape-out and increments by one for each
1464 all-layer tape-out. */
1465 #define MISC_REG_CHIP_REV 0xa40c
1466 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1467 32 clients. Each client can be controlled by one driver only. One in each
1468 bit represent that this driver control the appropriate client (Ex: bit 5
1469 is set means this driver control client number 5). addr1 = set; addr0 =
1470 clear; read from both addresses will give the same result = status. write
1471 to address 1 will set a request to control all the clients that their
1472 appropriate bit (in the write command) is set. if the client is free (the
1473 appropriate bit in all the other drivers is clear) one will be written to
1474 that driver register; if the client isn't free the bit will remain zero.
1475 if the appropriate bit is set (the driver request to gain control on a
1476 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1477 interrupt will be asserted). write to address 0 will set a request to
1478 free all the clients that their appropriate bit (in the write command) is
1479 set. if the appropriate bit is clear (the driver request to free a client
1480 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1482 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1483 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1484 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1486 #define MISC_REG_E1HMF_MODE 0xa5f8
1487 /* [R 1] Status of four port mode path swap input pin. */
1488 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1489 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1490 the path_swap output is equal to 4 port mode path swap input pin; if it
1491 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1492 Overwrite value. If bit[0] of this register is 1 this is the value that
1493 receives the path_swap output. Reset on Hard reset. */
1494 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1495 /* [R 1] Status of 4 port mode port swap input pin. */
1496 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1497 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1498 the port_swap output is equal to 4 port mode port swap input pin; if it
1499 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1500 Overwrite value. If bit[0] of this register is 1 this is the value that
1501 receives the port_swap output. Reset on Hard reset. */
1502 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
1503 /* [RW 32] Debug only: spare RW register reset by core reset */
1504 #define MISC_REG_GENERIC_CR_0 0xa460
1505 #define MISC_REG_GENERIC_CR_1 0xa464
1506 /* [RW 32] Debug only: spare RW register reset by por reset */
1507 #define MISC_REG_GENERIC_POR_1 0xa474
1508 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1509 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1510 can not be configured as an output. Each output has its output enable in
1511 the MCP register space; but this bit needs to be set to make use of that.
1512 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1513 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1514 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1515 the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1516 spare. Global register. Reset by hard reset. */
1517 #define MISC_REG_GEN_PURP_HWG 0xa9a0
1518 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1519 these bits is written as a '1'; the corresponding SPIO bit will turn off
1520 it's drivers and become an input. This is the reset state of all GPIO
1521 pins. The read value of these bits will be a '1' if that last command
1522 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1523 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1524 as a '1'; the corresponding GPIO bit will drive low. The read value of
1525 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1526 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1527 SET When any of these bits is written as a '1'; the corresponding GPIO
1528 bit will drive high (if it has that capability). The read value of these
1529 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1530 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1531 RO; These bits indicate the read value of each of the eight GPIO pins.
1532 This is the result value of the pin; not the drive value. Writing these
1533 bits will have not effect. */
1534 #define MISC_REG_GPIO 0xa490
1535 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1536 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1537 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1539 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1540 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1541 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1542 This will acknowledge an interrupt on the falling edge of corresponding
1543 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1544 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1545 register. This will acknowledge an interrupt on the rising edge of
1546 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1547 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1548 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1549 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1550 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1551 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1552 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1553 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1554 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1555 set when the GPIO input does not match the current value in #OLD_VALUE
1557 #define MISC_REG_GPIO_INT 0xa494
1558 /* [R 28] this field hold the last information that caused reserved
1559 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1560 [27:24] the master that caused the attention - according to the following
1561 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1563 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1564 /* [R 28] this field hold the last information that caused timeout
1565 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1566 [27:24] the master that caused the attention - according to the following
1567 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1569 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1570 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1571 access that does not finish within
1572 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1573 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1574 assert it attention output. */
1575 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1576 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1577 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1578 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1579 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1580 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1581 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1582 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1583 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1584 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1585 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1586 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1587 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1588 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1589 connected to RESET input directly. [15] capRetry_en (reset value 0)
1590 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1591 value 0) bit to continuously monitor vco freq (inverted). [17]
1592 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1593 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1594 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1595 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1596 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1597 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1598 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1599 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1600 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1601 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1602 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1604 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1605 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1606 /* [RW 4] Interrupt mask register #0 read/write */
1607 #define MISC_REG_MISC_INT_MASK 0xa388
1608 /* [RW 1] Parity mask register #0 read/write */
1609 #define MISC_REG_MISC_PRTY_MASK 0xa398
1610 /* [R 1] Parity register #0 read */
1611 #define MISC_REG_MISC_PRTY_STS 0xa38c
1612 /* [RC 1] Parity register #0 read clear */
1613 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1614 #define MISC_REG_NIG_WOL_P0 0xa270
1615 #define MISC_REG_NIG_WOL_P1 0xa274
1616 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1618 #define MISC_REG_PCIE_HOT_RESET 0xa618
1619 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1620 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1621 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1622 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1623 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1624 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1625 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1626 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1627 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1628 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1629 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1630 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1631 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1632 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1633 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1634 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1635 testa_en (reset value 0); */
1636 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1637 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1638 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1639 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1640 /* [R 1] Status of 4 port mode enable input pin. */
1641 #define MISC_REG_PORT4MODE_EN 0xa750
1642 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1643 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1644 * the port4mode_en output is equal to bit[1] of this register; [1] -
1645 * Overwrite value. If bit[0] of this register is 1 this is the value that
1646 * receives the port4mode_en output . */
1647 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1648 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1649 write/read zero = the specific block is in reset; addr 0-wr- the write
1650 value will be written to the register; addr 1-set - one will be written
1651 to all the bits that have the value of one in the data written (bits that
1652 have the value of zero will not be change) ; addr 2-clear - zero will be
1653 written to all the bits that have the value of one in the data written
1654 (bits that have the value of zero will not be change); addr 3-ignore;
1655 read ignore from all addr except addr 00; inside order of the bits is:
1656 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1657 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1658 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1659 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1660 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1661 rst_pxp_rq_rd_wr; 31:17] reserved */
1662 #define MISC_REG_RESET_REG_2 0xa590
1663 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1664 shared with the driver resides */
1665 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1666 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1667 the corresponding SPIO bit will turn off it's drivers and become an
1668 input. This is the reset state of all SPIO pins. The read value of these
1669 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1670 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1671 is written as a '1'; the corresponding SPIO bit will drive low. The read
1672 value of these bits will be a '1' if that last command (#SET; #CLR; or
1673 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1674 these bits is written as a '1'; the corresponding SPIO bit will drive
1675 high (if it has that capability). The read value of these bits will be a
1676 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1677 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1678 each of the eight SPIO pins. This is the result value of the pin; not the
1679 drive value. Writing these bits will have not effect. Each 8 bits field
1680 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1681 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1682 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1683 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1684 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1685 select VAUX supply. (This is an output pin only; it is not controlled by
1686 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1687 field is not applicable for this pin; only the VALUE fields is relevant -
1688 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1689 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1690 device ID select; read by UMP firmware. */
1691 #define MISC_REG_SPIO 0xa4fc
1692 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1693 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1695 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1696 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1697 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1698 interrupt on the falling edge of corresponding SPIO input (reset value
1699 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1700 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1701 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1702 RO; These bits indicate the old value of the SPIO input value. When the
1703 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1704 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1705 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1706 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1707 RO; These bits indicate the current SPIO interrupt state for each SPIO
1708 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1709 command bit is written. This bit is set when the SPIO input does not
1710 match the current value in #OLD_VALUE (reset value 0). */
1711 #define MISC_REG_SPIO_INT 0xa500
1712 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1713 the counter reached zero and the reload bit
1714 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1715 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1716 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1717 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1719 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1720 /* [R 1] Status of two port mode path swap input pin. */
1721 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1722 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1723 path_swap output is equal to 2 port mode path swap input pin; if it is 1
1724 - the path_swap output is equal to bit[1] of this register; [1] -
1725 Overwrite value. If bit[0] of this register is 1 this is the value that
1726 receives the path_swap output. Reset on Hard reset. */
1727 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
1728 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1729 loaded; 0-prepare; -unprepare */
1730 #define MISC_REG_UNPREPARED 0xa424
1731 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1732 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1733 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1734 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1735 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1736 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1737 * not it is the recipient of the message on the MDIO interface. The value
1738 * is compared to the value on ctrl_md_devad. Drives output
1739 * misc_xgxs0_phy_addr. Global register. */
1740 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1741 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1742 side. This should be less than or equal to phy_port_mode; if some of the
1743 ports are not used. This enables reduction of frequency on the core side.
1744 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1745 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1746 input for the XMAC_MP core; and should be changed only while reset is
1747 held low. Reset on Hard reset. */
1748 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1749 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1750 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1751 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1752 XMAC_MP core; and should be changed only while reset is held low. Reset
1754 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1755 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1756 * Reads from this register will clear bits 31:0. */
1757 #define MSTAT_REG_RX_STAT_GR64_LO 0x200
1758 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1759 * 31:0. Reads from this register will clear bits 31:0. */
1760 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1761 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1762 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1763 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1764 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1765 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1766 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1767 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1768 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1769 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1770 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1771 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1772 /* [RW 1] Input enable for RX_BMAC0 IF */
1773 #define NIG_REG_BMAC0_IN_EN 0x100ac
1774 /* [RW 1] output enable for TX_BMAC0 IF */
1775 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1776 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1777 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1778 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1779 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1780 /* [RW 1] output enable for RX BRB1 port0 IF */
1781 #define NIG_REG_BRB0_OUT_EN 0x100f8
1782 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1783 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1784 /* [RW 1] output enable for RX BRB1 port1 IF */
1785 #define NIG_REG_BRB1_OUT_EN 0x100fc
1786 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1787 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1788 /* [RW 1] output enable for RX BRB1 LP IF */
1789 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1790 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1791 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1792 72:73]-vnic_num; 81:74]-sideband_info */
1793 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1794 /* [RW 1] Input enable for TX Debug packet */
1795 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1796 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1797 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1798 First packet may be deleted from the middle. And last packet will be
1799 always deleted till the end. */
1800 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1801 /* [RW 1] Output enable to EMAC0 */
1802 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1803 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1804 to emac for port0; other way to bmac for port0 */
1805 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1806 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1807 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1808 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1809 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1810 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1811 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1812 /* [RW 1] Input enable for RX_EMAC0 IF */
1813 #define NIG_REG_EMAC0_IN_EN 0x100a4
1814 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1815 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1816 /* [R 1] status from emac0. This bit is set when MDINT from either the
1817 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1818 be cleared in the attached PHY device that is driving the MINT pin. */
1819 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1820 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1821 are described in appendix A. In order to access the BMAC0 registers; the
1822 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1823 added to each BMAC register offset */
1824 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1825 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1826 are described in appendix A. In order to access the BMAC0 registers; the
1827 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1828 added to each BMAC register offset */
1829 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1830 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1831 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1832 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1833 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1834 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1835 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1836 logic for interrupts must be used. Enable per bit of interrupt of
1837 ~latch_status.latch_status */
1838 #define NIG_REG_LATCH_BC_0 0x16210
1839 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1840 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1841 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1842 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1843 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1844 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1845 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1846 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1847 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1848 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1849 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1850 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1851 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1852 #define NIG_REG_LATCH_STATUS_0 0x18000
1853 /* [RW 1] led 10g for port 0 */
1854 #define NIG_REG_LED_10G_P0 0x10320
1855 /* [RW 1] led 10g for port 1 */
1856 #define NIG_REG_LED_10G_P1 0x10324
1857 /* [RW 1] Port0: This bit is set to enable the use of the
1858 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1859 defined below. If this bit is cleared; then the blink rate will be about
1861 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1862 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1863 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1864 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1865 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1866 /* [RW 1] Port0: If set along with the
1867 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1868 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1869 bit; the Traffic LED will blink with the blink rate specified in
1870 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1871 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1873 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1874 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1875 Traffic LED will then be controlled via bit ~nig_registers_
1876 led_control_traffic_p0.led_control_traffic_p0 and bit
1877 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1878 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1879 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1880 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1881 set; the LED will blink with blink rate specified in
1882 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1883 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1885 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1886 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1887 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1888 #define NIG_REG_LED_MODE_P0 0x102f0
1889 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1890 tsdm enable; b2- usdm enable */
1891 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1892 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
1893 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1894 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1896 #define NIG_REG_LLFC_ENABLE_0 0x16208
1897 #define NIG_REG_LLFC_ENABLE_1 0x1620c
1898 /* [RW 16] classes are high-priority for port0 */
1899 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1900 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
1901 /* [RW 16] classes are low-priority for port0 */
1902 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1903 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
1904 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1905 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
1906 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
1907 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1908 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1909 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1910 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1911 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1912 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1913 /* [RW 2] Determine the classification participants. 0: no classification.1:
1914 classification upon VLAN id. 2: classification upon MAC address. 3:
1915 classification upon both VLAN id & MAC addr. */
1916 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1917 /* [RW 32] cm header for llh0 */
1918 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1919 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1920 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1921 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1922 all incoming packets. */
1923 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1924 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1925 all incoming packets. */
1926 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1927 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1928 /* [RW 8] event id for llh0 */
1929 #define NIG_REG_LLH0_EVENT_ID 0x10084
1930 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1931 #define NIG_REG_LLH0_FUNC_MEM 0x16180
1932 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
1933 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1934 /* [RW 1] Determine the IP version to look for in
1935 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1936 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1937 /* [RW 1] t bit for llh0 */
1938 #define NIG_REG_LLH0_T_BIT 0x10074
1939 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1940 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1941 /* [RW 8] init credit counter for port0 in LLH */
1942 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1943 #define NIG_REG_LLH0_XCM_MASK 0x10130
1944 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1945 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1946 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1947 /* [RW 2] Determine the classification participants. 0: no classification.1:
1948 classification upon VLAN id. 2: classification upon MAC address. 3:
1949 classification upon both VLAN id & MAC addr. */
1950 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1951 /* [RW 32] cm header for llh1 */
1952 #define NIG_REG_LLH1_CM_HEADER 0x10080
1953 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1954 /* [RW 8] event id for llh1 */
1955 #define NIG_REG_LLH1_EVENT_ID 0x10088
1956 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
1957 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1958 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16
1959 /* [RW 1] When this bit is set; the LLH will classify the packet before
1960 * sending it to the BRB or calculating WoL on it. This bit controls port 1
1961 * only. The legacy llh_multi_function_mode bit controls port 0. */
1962 #define NIG_REG_LLH1_MF_MODE 0x18614
1963 /* [RW 8] init credit counter for port1 in LLH */
1964 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1965 #define NIG_REG_LLH1_XCM_MASK 0x10134
1966 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1968 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1969 /* [RW 1] When this bit is set; the LLH will classify the packet before
1970 sending it to the BRB or calculating WoL on it. */
1971 #define NIG_REG_LLH_MF_MODE 0x16024
1972 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1973 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1974 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1975 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1976 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1977 #define NIG_REG_NIG_EMAC1_EN 0x10040
1978 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1979 EMAC0 to strip the CRC from the ingress packets. */
1980 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1981 /* [R 32] Interrupt register #0 read */
1982 #define NIG_REG_NIG_INT_STS_0 0x103b0
1983 #define NIG_REG_NIG_INT_STS_1 0x103c0
1984 /* [R 32] Legacy E1 and E1H location for parity error mask register. */
1985 #define NIG_REG_NIG_PRTY_MASK 0x103dc
1986 /* [RW 32] Parity mask register #0 read/write */
1987 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8
1988 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8
1989 /* [R 32] Legacy E1 and E1H location for parity error status register. */
1990 #define NIG_REG_NIG_PRTY_STS 0x103d0
1991 /* [R 32] Parity register #0 read */
1992 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
1993 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
1994 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */
1995 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
1996 /* [RC 32] Parity register #0 read clear */
1997 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
1998 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
1999 #define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2000 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2001 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2002 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
2003 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2004 * Ethernet header. */
2005 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2006 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2007 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2008 * disabled when this bit is set. */
2009 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
2010 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2011 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
2012 /* [RW 1] Input enable for RX MAC interface. */
2013 #define NIG_REG_P0_MAC_IN_EN 0x185ac
2014 /* [RW 1] Output enable for TX MAC interface */
2015 #define NIG_REG_P0_MAC_OUT_EN 0x185b0
2016 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2017 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
2018 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2019 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2020 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2021 * priority field is extracted from the outer-most VLAN in receive packet.
2022 * Only COS 0 and COS 1 are supported in E2. */
2023 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2024 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2025 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2026 * than one bit may be set; allowing multiple priorities to be mapped to one
2028 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2029 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2030 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2031 * than one bit may be set; allowing multiple priorities to be mapped to one
2033 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
2034 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2035 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2036 * than one bit may be set; allowing multiple priorities to be mapped to one
2038 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2039 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2040 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2041 * than one bit may be set; allowing multiple priorities to be mapped to one
2043 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2044 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2045 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2046 * than one bit may be set; allowing multiple priorities to be mapped to one
2048 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2049 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2050 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2051 * than one bit may be set; allowing multiple priorities to be mapped to one
2053 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2054 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2055 /* [RW 15] Specify which of the credit registers the client is to be mapped
2056 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2057 * clients that are not subject to WFQ credit blocking - their
2058 * specifications here are not used. */
2059 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
2060 /* [RW 5] Specify whether the client competes directly in the strict
2061 * priority arbiter. The bits are mapped according to client ID (client IDs
2062 * are defined in tx_arb_priority_client). Default value is set to enable
2063 * strict priorities for clients 0-2 -- management and debug traffic. */
2064 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2065 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2066 * bits are mapped according to client ID (client IDs are defined in
2067 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2069 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2070 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2072 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2073 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
2074 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2075 * when it is time to increment. */
2076 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2077 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
2078 /* [RW 12] Specify the number of strict priority arbitration slots between
2079 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2080 * no strict priority cycles - the strict priority with anti-starvation
2081 * arbiter becomes a round-robin arbiter. */
2082 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2083 /* [RW 15] Specify the client number to be assigned to each priority of the
2084 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2085 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2086 * clients are assigned the following IDs: 0-management; 1-debug traffic
2087 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2088 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2089 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2090 * traffic at priority 3; and COS1 traffic at priority 4. */
2091 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
2092 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2093 * Ethernet header. */
2094 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
2095 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2096 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
2097 #define NIG_REG_P1_MAC_IN_EN 0x185c0
2098 /* [RW 1] Output enable for TX MAC interface */
2099 #define NIG_REG_P1_MAC_OUT_EN 0x185c4
2100 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2101 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
2102 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2103 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2104 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2105 * priority field is extracted from the outer-most VLAN in receive packet.
2106 * Only COS 0 and COS 1 are supported in E2. */
2107 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2108 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2109 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2110 * than one bit may be set; allowing multiple priorities to be mapped to one
2112 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2113 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2114 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2115 * than one bit may be set; allowing multiple priorities to be mapped to one
2117 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
2118 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2119 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2120 * than one bit may be set; allowing multiple priorities to be mapped to one
2122 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2123 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2124 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2125 /* [R 1] TLLH FIFO is empty. */
2126 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2127 /* [RW 32] Specify which of the credit registers the client is to be mapped
2128 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2129 * for client 0; bits [35:32] are for client 8. For clients that are not
2130 * subject to WFQ credit blocking - their specifications here are not used.
2131 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2132 * input clients to ETS arbiter. The reset default is set for management and
2133 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2134 * use credit registers 0-5 respectively (0x543210876). Note that credit
2135 * registers can not be shared between clients. Note also that there are
2136 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2137 * credit registers 0-5 are valid. This register should be configured
2138 * appropriately before enabling WFQ. */
2139 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2140 /* [RW 4] Specify which of the credit registers the client is to be mapped
2141 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2142 * for client 0; bits [35:32] are for client 8. For clients that are not
2143 * subject to WFQ credit blocking - their specifications here are not used.
2144 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2145 * input clients to ETS arbiter. The reset default is set for management and
2146 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2147 * use credit registers 0-5 respectively (0x543210876). Note that credit
2148 * registers can not be shared between clients. Note also that there are
2149 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2150 * credit registers 0-5 are valid. This register should be configured
2151 * appropriately before enabling WFQ. */
2152 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2153 /* [RW 9] Specify whether the client competes directly in the strict
2154 * priority arbiter. The bits are mapped according to client ID (client IDs
2155 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2156 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2157 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2158 * Default value is set to enable strict priorities for all clients. */
2159 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2160 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2161 * bits are mapped according to client ID (client IDs are defined in
2162 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2163 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2164 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2165 * 0 for not using WFQ credit blocking. */
2166 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2167 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2169 /* [RW 1] Pause enable for port0. This register may get 1 only when
2170 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2172 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
2173 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
2174 /* [RW 1] Input enable for RX PBF LP IF */
2175 #define NIG_REG_PBF_LB_IN_EN 0x100b4
2176 /* [RW 1] Value of this register will be transmitted to port swap when
2177 ~nig_registers_strap_override.strap_override =1 */
2178 #define NIG_REG_PORT_SWAP 0x10394
2179 /* [RW 1] PPP enable for port0. This register may get 1 only when
2180 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2182 #define NIG_REG_PPP_ENABLE_0 0x160b0
2183 #define NIG_REG_PPP_ENABLE_1 0x160b4
2184 /* [RW 1] output enable for RX parser descriptor IF */
2185 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
2186 /* [RW 1] Input enable for RX parser request IF */
2187 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
2188 /* [RW 5] control to serdes - CL45 DEVAD */
2189 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2190 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2191 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
2192 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2193 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2194 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2195 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2196 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2198 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
2199 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2201 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
2202 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2203 between 1024 and 1522 bytes for port0 */
2204 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2205 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2206 between 1523 bytes and above for port0 */
2207 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
2208 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2210 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
2211 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2212 between 1024 and 1522 bytes for port1 */
2213 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2214 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2215 between 1523 bytes and above for port1 */
2216 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
2217 /* [WB_R 64] Rx statistics : User octets received for LP */
2218 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
2219 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2220 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
2221 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2222 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2223 ort swap is equal to ~nig_registers_port_swap.port_swap */
2224 #define NIG_REG_STRAP_OVERRIDE 0x10398
2225 /* [RW 1] output enable for RX_XCM0 IF */
2226 #define NIG_REG_XCM0_OUT_EN 0x100f0
2227 /* [RW 1] output enable for RX_XCM1 IF */
2228 #define NIG_REG_XCM1_OUT_EN 0x100f4
2229 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2230 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2231 /* [RW 5] control to xgxs - CL45 DEVAD */
2232 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2233 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2234 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2235 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2236 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2237 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2238 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2239 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2240 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2241 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2242 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2243 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2244 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2245 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2246 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2247 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2248 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2249 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2250 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2251 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2252 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2253 #define PBF_REG_COS0_WEIGHT 0x15c054
2254 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2255 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2256 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2257 #define PBF_REG_COS1_WEIGHT 0x15c058
2258 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2260 #define PBF_REG_CREDIT_LB_Q 0x140338
2261 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2263 #define PBF_REG_CREDIT_Q0 0x14033c
2264 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2266 #define PBF_REG_CREDIT_Q1 0x140340
2267 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2268 current task in process). */
2269 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2270 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2271 current task in process). */
2272 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2273 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2274 current task in process). */
2275 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2276 #define PBF_REG_DISABLE_PF 0x1402e8
2277 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2278 * arbiter. If reset strict priority w/ anti-starvation will be performed
2280 #define PBF_REG_ETS_ENABLED 0x15c050
2281 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2282 * Ethernet header. */
2283 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2284 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2285 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2286 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2287 * priority in the command arbiter. */
2288 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2289 #define PBF_REG_IF_ENABLE_REG 0x140044
2290 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2291 registers (except the port credits). Should be set and then reset after
2292 the configuration of the block has ended. */
2293 #define PBF_REG_INIT 0x140000
2294 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2296 #define PBF_REG_INIT_CRD_LB_Q 0x15c248
2297 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2299 #define PBF_REG_INIT_CRD_Q0 0x15c230
2300 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2302 #define PBF_REG_INIT_CRD_Q1 0x15c234
2303 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2304 copied to the credit register. Should be set and then reset after the
2305 configuration of the port has ended. */
2306 #define PBF_REG_INIT_P0 0x140004
2307 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2308 copied to the credit register. Should be set and then reset after the
2309 configuration of the port has ended. */
2310 #define PBF_REG_INIT_P1 0x140008
2311 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2312 copied to the credit register. Should be set and then reset after the
2313 configuration of the port has ended. */
2314 #define PBF_REG_INIT_P4 0x14000c
2315 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2316 * the LB queue. Reset upon init. */
2317 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2318 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2319 * queue 0. Reset upon init. */
2320 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2321 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2322 * queue 1. Reset upon init. */
2323 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2324 /* [RW 1] Enable for mac interface 0. */
2325 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2326 /* [RW 1] Enable for mac interface 1. */
2327 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2328 /* [RW 1] Enable for the loopback interface. */
2329 #define PBF_REG_MAC_LB_ENABLE 0x140040
2330 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2331 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2332 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2333 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2334 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2335 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2336 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2338 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2339 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2340 #define PBF_REG_P0_CREDIT 0x140200
2341 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2343 #define PBF_REG_P0_INIT_CRD 0x1400d0
2344 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2345 * port 0. Reset upon init. */
2346 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2347 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2348 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2349 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2350 #define PBF_REG_P0_TASK_CNT 0x140204
2351 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2352 * freed from the task queue of port 0. Reset upon init. */
2353 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2354 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2355 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2356 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2357 * buffers in 16 byte lines. */
2358 #define PBF_REG_P1_CREDIT 0x140208
2359 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2360 * buffers in 16 byte lines. */
2361 #define PBF_REG_P1_INIT_CRD 0x1400d4
2362 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2363 * port 1. Reset upon init. */
2364 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2365 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2366 #define PBF_REG_P1_TASK_CNT 0x14020c
2367 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2368 * freed from the task queue of port 1. Reset upon init. */
2369 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2370 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2371 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2372 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2373 #define PBF_REG_P4_CREDIT 0x140210
2374 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2376 #define PBF_REG_P4_INIT_CRD 0x1400e0
2377 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2378 * port 4. Reset upon init. */
2379 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2380 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2381 #define PBF_REG_P4_TASK_CNT 0x140214
2382 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2383 * freed from the task queue of port 4. Reset upon init. */
2384 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2385 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2386 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2387 /* [RW 5] Interrupt mask register #0 read/write */
2388 #define PBF_REG_PBF_INT_MASK 0x1401d4
2389 /* [R 5] Interrupt register #0 read */
2390 #define PBF_REG_PBF_INT_STS 0x1401c8
2391 /* [RW 20] Parity mask register #0 read/write */
2392 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
2393 /* [RC 20] Parity register #0 read clear */
2394 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2395 /* [RW 16] The Ethernet type value for L2 tag 0 */
2396 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2397 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2398 * 2B and 14B; in 2B granularity */
2399 #define PBF_REG_TAG_LEN_0 0x15c09c
2400 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2401 * queue. Reset upon init. */
2402 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2403 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2404 * queue 0. Reset upon init. */
2405 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2406 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2407 * Reset upon init. */
2408 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2409 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2411 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2412 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2413 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2414 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2415 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2416 #define PB_REG_CONTROL 0
2417 /* [RW 2] Interrupt mask register #0 read/write */
2418 #define PB_REG_PB_INT_MASK 0x28
2419 /* [R 2] Interrupt register #0 read */
2420 #define PB_REG_PB_INT_STS 0x1c
2421 /* [RW 4] Parity mask register #0 read/write */
2422 #define PB_REG_PB_PRTY_MASK 0x38
2423 /* [R 4] Parity register #0 read */
2424 #define PB_REG_PB_PRTY_STS 0x2c
2425 /* [RC 4] Parity register #0 read clear */
2426 #define PB_REG_PB_PRTY_STS_CLR 0x30
2427 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2428 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2429 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2430 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2431 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2432 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2433 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2434 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2435 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2436 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2437 * corresponding PF generates config space A attention. Set by PXP. Reset by
2438 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2439 * from both paths. */
2440 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2441 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2442 * corresponding PF generates config space B attention. Set by PXP. Reset by
2443 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2444 * from both paths. */
2445 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2446 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2448 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2449 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2450 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2451 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2452 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2454 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2455 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2456 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2457 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2458 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2459 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2460 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2461 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2462 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2463 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2464 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2465 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2466 * from both paths. */
2467 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2468 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2469 * to a bit in this register in order to clear the corresponding bit in
2470 * flr_request_pf_7_0 register. Note: register contains bits from both
2472 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2473 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2474 * indicates that the FLR register of the corresponding VF was set. Set by
2475 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2476 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2477 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2478 * indicates that the FLR register of the corresponding VF was set. Set by
2479 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2480 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2481 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2482 * indicates that the FLR register of the corresponding VF was set. Set by
2483 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2484 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2485 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2486 * indicates that the FLR register of the corresponding VF was set. Set by
2487 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2488 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2489 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2490 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2491 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2492 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2493 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2494 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2495 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2496 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2497 * and pcie_rx_last not asserted. */
2498 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2499 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2500 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2501 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2502 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2503 /* [R 9] Interrupt register #0 read */
2504 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2505 /* [RC 9] Interrupt register #0 read clear */
2506 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2507 /* [R 2] Parity register #0 read */
2508 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2509 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2510 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2511 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2512 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2513 * if there was a completion error since the last time this register was
2515 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2516 /* [R 18] Details of first ATS Translation Completion request received with
2517 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2518 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2519 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2520 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2521 * completion error since the last time this register was cleared. */
2522 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2523 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2524 * a bit in this register in order to clear the corresponding bit in
2525 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2526 * work-around is needed. Note: register contains bits from both paths. */
2527 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2528 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2529 * VF enable register of the corresponding PF is written to 0 and was
2530 * previously 1. Set by PXP. Reset by MCP writing 1 to
2531 * sr_iov_disabled_request_clr. Note: register contains bits from both
2533 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2534 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2535 * completion did not return yet. 1 - tag is unused. Same functionality as
2536 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2537 #define PGLUE_B_REG_TAGS_63_32 0x9244
2538 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2540 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2541 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2542 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2543 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2544 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2545 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2546 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2547 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2548 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2549 /* [R 32] Address [31:0] of first read request not submitted due to error */
2550 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2551 /* [R 32] Address [63:32] of first read request not submitted due to error */
2552 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2553 /* [R 31] Details of first read request not submitted due to error. [4:0]
2554 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2555 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2557 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2558 /* [R 26] Details of first read request not submitted due to error. [15:0]
2559 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2560 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2561 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2562 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2563 * indicates if there was a request not submitted due to error since the
2564 * last time this register was cleared. */
2565 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2566 /* [R 32] Address [31:0] of first write request not submitted due to error */
2567 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2568 /* [R 32] Address [63:32] of first write request not submitted due to error */
2569 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2570 /* [R 31] Details of first write request not submitted due to error. [4:0]
2571 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2573 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2574 /* [R 26] Details of first write request not submitted due to error. [15:0]
2575 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2576 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2577 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2578 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2579 * indicates if there was a request not submitted due to error since the
2580 * last time this register was cleared. */
2581 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2582 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2583 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2584 * value (Byte resolution address). */
2585 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2586 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2587 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2588 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2589 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2590 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2591 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2592 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2594 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2595 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2597 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2598 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2600 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2601 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2602 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2603 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2604 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2605 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2606 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2607 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2608 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2609 /* [R 26] Details of first target VF request accessing VF GRC space that
2610 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2611 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2612 * request accessing VF GRC space that failed permission check since the
2613 * last time this register was cleared. Permission checks are: function
2614 * permission; R/W permission; address range permission. */
2615 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2616 /* [R 31] Details of first target VF request with length violation (too many
2617 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2618 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2619 * valid - indicates if there was a request with length violation since the
2620 * last time this register was cleared. Length violations: length of more
2621 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2622 * length is more than 1 DW. */
2623 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2624 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2625 * that there was a completion with uncorrectable error for the
2626 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2627 * was_error_pf_7_0_clr. */
2628 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2629 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2630 * to a bit in this register in order to clear the corresponding bit in
2631 * flr_request_pf_7_0 register. */
2632 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2633 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2634 * indicates that there was a completion with uncorrectable error for the
2635 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2636 * was_error_vf_127_96_clr. */
2637 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2638 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2639 * writes 1 to a bit in this register in order to clear the corresponding
2640 * bit in was_error_vf_127_96 register. */
2641 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2642 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2643 * indicates that there was a completion with uncorrectable error for the
2644 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2645 * was_error_vf_31_0_clr. */
2646 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2647 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2648 * 1 to a bit in this register in order to clear the corresponding bit in
2649 * was_error_vf_31_0 register. */
2650 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2651 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2652 * indicates that there was a completion with uncorrectable error for the
2653 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2654 * was_error_vf_63_32_clr. */
2655 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2656 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2657 * 1 to a bit in this register in order to clear the corresponding bit in
2658 * was_error_vf_63_32 register. */
2659 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2660 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2661 * indicates that there was a completion with uncorrectable error for the
2662 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2663 * was_error_vf_95_64_clr. */
2664 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2665 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2666 * 1 to a bit in this register in order to clear the corresponding bit in
2667 * was_error_vf_95_64 register. */
2668 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
2669 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2671 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
2672 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2673 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
2674 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2675 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
2676 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2677 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
2678 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2679 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
2680 #define PRS_REG_A_PRSU_20 0x40134
2681 /* [R 8] debug only: CFC load request current credit. Transaction based. */
2682 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
2683 /* [R 8] debug only: CFC search request current credit. Transaction based. */
2684 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
2685 /* [RW 6] The initial credit for the search message to the CFC interface.
2686 Credit is transaction based. */
2687 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
2688 /* [RW 24] CID for port 0 if no match */
2689 #define PRS_REG_CID_PORT_0 0x400fc
2690 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2691 load response is reset and packet type is 0. Used in packet start message
2693 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
2694 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
2695 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
2696 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
2697 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
2698 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
2699 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2700 load response is set and packet type is 0. Used in packet start message
2702 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
2703 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
2704 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
2705 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
2706 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
2707 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
2708 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
2709 Used in packet start message to TCM. */
2710 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
2711 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2712 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2713 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2714 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
2716 #define PRS_REG_CM_HDR_TYPE_0 0x40078
2717 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
2718 #define PRS_REG_CM_HDR_TYPE_2 0x40080
2719 #define PRS_REG_CM_HDR_TYPE_3 0x40084
2720 #define PRS_REG_CM_HDR_TYPE_4 0x40088
2721 /* [RW 32] The CM header in case there was not a match on the connection */
2722 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
2723 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2724 #define PRS_REG_E1HOV_MODE 0x401c8
2725 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2726 start message to TCM. */
2727 #define PRS_REG_EVENT_ID_1 0x40054
2728 #define PRS_REG_EVENT_ID_2 0x40058
2729 #define PRS_REG_EVENT_ID_3 0x4005c
2730 /* [RW 16] The Ethernet type value for FCoE */
2731 #define PRS_REG_FCOE_TYPE 0x401d0
2732 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2733 load request message. */
2734 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2735 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2736 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2737 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2738 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2739 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2740 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2741 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
2742 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2743 * Ethernet header. */
2744 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
2745 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2746 * Ethernet header for port 0 packets. */
2747 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
2748 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
2749 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2750 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248
2751 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
2753 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
2754 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
2755 /* [RW 4] The increment value to send in the CFC load request message */
2756 #define PRS_REG_INC_VALUE 0x40048
2757 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2758 #define PRS_REG_MUST_HAVE_HDRS 0x40254
2759 /* [RW 6] Bit-map indicating which headers must appear in the packet for
2761 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
2762 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
2763 #define PRS_REG_NIC_MODE 0x40138
2764 /* [RW 8] The 8-bit event ID for cases where there is no match on the
2765 connection. Used in packet start message to TCM. */
2766 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2767 /* [ST 24] The number of input CFC flush packets */
2768 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2769 /* [ST 32] The number of cycles the Parser halted its operation since it
2770 could not allocate the next serial number */
2771 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2772 /* [ST 24] The number of input packets */
2773 #define PRS_REG_NUM_OF_PACKETS 0x40124
2774 /* [ST 24] The number of input transparent flush packets */
2775 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2776 /* [RW 8] Context region for received Ethernet packet with a match and
2777 packet type 0. Used in CFC load request message */
2778 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2779 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2780 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2781 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2782 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2783 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2784 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2785 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2786 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
2787 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2788 /* [R 2] debug only: Number of pending requests for header parsing. */
2789 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2790 /* [R 1] Interrupt register #0 read */
2791 #define PRS_REG_PRS_INT_STS 0x40188
2792 /* [RW 8] Parity mask register #0 read/write */
2793 #define PRS_REG_PRS_PRTY_MASK 0x401a4
2794 /* [R 8] Parity register #0 read */
2795 #define PRS_REG_PRS_PRTY_STS 0x40198
2796 /* [RC 8] Parity register #0 read clear */
2797 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
2798 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2800 #define PRS_REG_PURE_REGIONS 0x40024
2801 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2802 serail number was released by SDM but cannot be used because a previous
2803 serial number was not released. */
2804 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2805 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2806 serail number was released by SDM but cannot be used because a previous
2807 serial number was not released. */
2808 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2809 /* [R 4] debug only: SRC current credit. Transaction based. */
2810 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2811 /* [RW 16] The Ethernet type value for L2 tag 0 */
2812 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4
2813 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2814 * 2B and 14B; in 2B granularity */
2815 #define PRS_REG_TAG_LEN_0 0x4022c
2816 /* [R 8] debug only: TCM current credit. Cycle based. */
2817 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2818 /* [R 8] debug only: TSDM current credit. Transaction based. */
2819 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2820 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
2821 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
2822 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
2823 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
2824 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
2825 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2826 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2827 /* [R 6] Debug only: Number of used entries in the data FIFO */
2828 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2829 /* [R 7] Debug only: Number of used entries in the header FIFO */
2830 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
2831 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
2832 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2833 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2834 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
2835 #define PXP2_REG_PGL_CONTROL0 0x120490
2836 #define PXP2_REG_PGL_CONTROL1 0x120514
2837 #define PXP2_REG_PGL_DEBUG 0x120520
2838 /* [RW 32] third dword data of expansion rom request. this register is
2839 special. reading from it provides a vector outstanding read requests. if
2840 a bit is zero it means that a read request on the corresponding tag did
2841 not finish yet (not all completions have arrived for it) */
2842 #define PXP2_REG_PGL_EXP_ROM2 0x120808
2843 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2844 its[15:0]-address */
2845 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2846 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2847 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2848 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
2849 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
2850 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
2851 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2852 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
2853 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2854 its[15:0]-address */
2855 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
2856 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
2857 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2858 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2859 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2860 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2861 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2862 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2863 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2864 its[15:0]-address */
2865 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2866 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2867 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2868 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2869 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2870 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2871 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2872 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2873 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2874 its[15:0]-address */
2875 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2876 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2877 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2878 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2879 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2880 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2881 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2882 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2883 /* [RW 3] this field allows one function to pretend being another function
2884 when accessing any BAR mapped resource within the device. the value of
2885 the field is the number of the function that will be accessed
2886 effectively. after software write to this bit it must read it in order to
2887 know that the new value is updated */
2888 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
2889 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
2890 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
2891 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
2892 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
2893 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
2894 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
2895 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
2896 /* [R 1] this bit indicates that a read request was blocked because of
2897 bus_master_en was deasserted */
2898 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
2899 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
2900 /* [R 18] debug only */
2901 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
2902 /* [R 1] this bit indicates that a write request was blocked because of
2903 bus_master_en was deasserted */
2904 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2905 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2906 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2907 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2908 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2909 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2910 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2911 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2912 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2913 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2914 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2915 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2916 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2917 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2918 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2919 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2920 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2921 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2922 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2923 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2924 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2925 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2926 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2927 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2928 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2929 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2930 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2931 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2932 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2933 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2934 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2935 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2936 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2937 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2938 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2939 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2940 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2941 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2942 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2943 /* [RW 32] Interrupt mask register #0 read/write */
2944 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2945 /* [R 32] Interrupt register #0 read */
2946 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2947 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2948 /* [RC 32] Interrupt register #0 read clear */
2949 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2950 /* [RW 32] Parity mask register #0 read/write */
2951 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2952 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2953 /* [R 32] Parity register #0 read */
2954 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2955 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2956 /* [RC 32] Parity register #0 read clear */
2957 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
2958 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
2959 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2960 indication about backpressure) */
2961 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2962 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2963 #define PXP2_REG_RD_BLK_CNT 0x120418
2964 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2965 Must be bigger than 6. Normally should not be changed. */
2966 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2967 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2968 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2969 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2970 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2971 /* [R 1] PSWRD internal memories initialization is done */
2972 #define PXP2_REG_RD_INIT_DONE 0x120370
2973 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2974 allocated for vq10 */
2975 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2976 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2977 allocated for vq11 */
2978 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2979 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2980 allocated for vq17 */
2981 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2982 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2983 allocated for vq18 */
2984 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2985 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2986 allocated for vq19 */
2987 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2988 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2989 allocated for vq22 */
2990 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2991 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2992 allocated for vq25 */
2993 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
2994 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2995 allocated for vq6 */
2996 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2997 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2998 allocated for vq9 */
2999 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3000 /* [RW 2] PBF byte swapping mode configuration for master read requests */
3001 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3002 /* [R 1] Debug only: Indication if delivery ports are idle */
3003 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3004 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3005 /* [RW 2] QM byte swapping mode configuration for master read requests */
3006 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3007 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
3008 #define PXP2_REG_RD_SR_CNT 0x120414
3009 /* [RW 2] SRC byte swapping mode configuration for master read requests */
3010 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3011 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3012 be bigger than 1. Normally should not be changed. */
3013 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
3014 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
3015 #define PXP2_REG_RD_START_INIT 0x12036c
3016 /* [RW 2] TM byte swapping mode configuration for master read requests */
3017 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3018 /* [RW 10] Bandwidth addition to VQ0 write requests */
3019 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3020 /* [RW 10] Bandwidth addition to VQ12 read requests */
3021 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3022 /* [RW 10] Bandwidth addition to VQ13 read requests */
3023 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3024 /* [RW 10] Bandwidth addition to VQ14 read requests */
3025 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3026 /* [RW 10] Bandwidth addition to VQ15 read requests */
3027 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3028 /* [RW 10] Bandwidth addition to VQ16 read requests */
3029 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3030 /* [RW 10] Bandwidth addition to VQ17 read requests */
3031 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3032 /* [RW 10] Bandwidth addition to VQ18 read requests */
3033 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3034 /* [RW 10] Bandwidth addition to VQ19 read requests */
3035 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3036 /* [RW 10] Bandwidth addition to VQ20 read requests */
3037 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3038 /* [RW 10] Bandwidth addition to VQ22 read requests */
3039 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3040 /* [RW 10] Bandwidth addition to VQ23 read requests */
3041 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3042 /* [RW 10] Bandwidth addition to VQ24 read requests */
3043 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3044 /* [RW 10] Bandwidth addition to VQ25 read requests */
3045 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3046 /* [RW 10] Bandwidth addition to VQ26 read requests */
3047 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3048 /* [RW 10] Bandwidth addition to VQ27 read requests */
3049 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3050 /* [RW 10] Bandwidth addition to VQ4 read requests */
3051 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3052 /* [RW 10] Bandwidth addition to VQ5 read requests */
3053 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3054 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3055 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3056 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3057 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3058 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3059 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3060 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3061 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3062 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3063 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3064 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3065 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3066 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3067 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3068 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3069 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3070 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3071 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3072 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3073 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3074 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3075 #define PXP2_REG_RQ_BW_RD_L22 0x120300
3076 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3077 #define PXP2_REG_RQ_BW_RD_L23 0x120304
3078 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3079 #define PXP2_REG_RQ_BW_RD_L24 0x120308
3080 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3081 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
3082 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3083 #define PXP2_REG_RQ_BW_RD_L26 0x120310
3084 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3085 #define PXP2_REG_RQ_BW_RD_L27 0x120314
3086 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3087 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3088 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3089 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3090 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
3091 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3092 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
3093 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3094 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
3095 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3096 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
3097 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3098 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
3099 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3100 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
3101 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3102 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
3103 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3104 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
3105 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3106 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
3107 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3108 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
3109 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3110 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
3111 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3112 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
3113 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3114 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
3115 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3116 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
3117 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3118 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
3119 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3120 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
3121 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3122 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
3123 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3124 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
3125 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3126 /* [RW 10] Bandwidth addition to VQ29 write requests */
3127 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3128 /* [RW 10] Bandwidth addition to VQ30 write requests */
3129 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3130 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3131 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
3132 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3133 #define PXP2_REG_RQ_BW_WR_L30 0x120320
3134 /* [RW 7] Bandwidth upper bound for VQ29 */
3135 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3136 /* [RW 7] Bandwidth upper bound for VQ30 */
3137 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
3138 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3139 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
3140 /* [RW 2] Endian mode for cdu */
3141 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
3142 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3143 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
3144 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3146 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3147 /* [R 1] 1' indicates that the requester has finished its internal
3149 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
3150 /* [RW 2] Endian mode for debug */
3151 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3152 /* [RW 1] When '1'; requests will enter input buffers but wont get out
3154 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
3155 /* [RW 4] Determines alignment of write SRs when a request is split into
3156 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3157 * aligned. 4 - 512B aligned. */
3158 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
3159 /* [RW 4] Determines alignment of read SRs when a request is split into
3160 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3161 * aligned. 4 - 512B aligned. */
3162 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3163 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
3164 * the original alignment method (E1 E1H) will be applied */
3165 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
3166 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3168 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
3169 /* [RW 2] Endian mode for hc */
3170 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
3171 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3172 compatibility needs; Note that different registers are used per mode */
3173 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
3174 /* [WB 53] Onchip address table */
3175 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
3176 /* [WB 53] Onchip address table - B0 */
3177 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
3178 /* [RW 13] Pending read limiter threshold; in Dwords */
3179 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
3180 /* [RW 2] Endian mode for qm */
3181 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
3182 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3183 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
3184 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3186 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
3187 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3188 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
3189 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3190 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3191 #define PXP2_REG_RQ_RD_MBS0 0x120160
3192 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3193 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3194 #define PXP2_REG_RQ_RD_MBS1 0x120168
3195 /* [RW 2] Endian mode for src */
3196 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
3197 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3198 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
3199 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3201 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3202 /* [RW 2] Endian mode for tm */
3203 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
3204 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3205 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
3206 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3208 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
3209 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3210 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
3211 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3212 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
3213 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3214 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3215 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3216 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3217 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3218 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3219 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3220 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3221 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3222 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3223 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3224 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3225 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3226 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3227 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3228 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3229 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3230 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3231 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3232 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3233 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3234 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3235 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3236 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3237 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3238 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3239 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3240 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3241 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3242 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3243 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3244 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3245 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3246 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3247 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3248 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3249 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3250 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3251 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3252 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3253 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3254 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3255 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3256 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3257 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3258 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3259 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3260 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3261 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3262 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3263 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3264 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3265 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3266 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3267 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3268 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3269 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3270 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3271 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3272 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3273 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3274 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3275 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3276 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3277 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3278 001:256B; 010: 512B; */
3279 #define PXP2_REG_RQ_WR_MBS0 0x12015c
3280 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3281 001:256B; 010: 512B; */
3282 #define PXP2_REG_RQ_WR_MBS1 0x120164
3283 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3284 buffer reaches this number has_payload will be asserted */
3285 #define PXP2_REG_WR_CDU_MPS 0x1205f0
3286 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3287 buffer reaches this number has_payload will be asserted */
3288 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
3289 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3290 buffer reaches this number has_payload will be asserted */
3291 #define PXP2_REG_WR_DBG_MPS 0x1205e8
3292 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3293 buffer reaches this number has_payload will be asserted */
3294 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
3295 /* [RW 10] if Number of entries in dmae fifo will be higher than this
3296 threshold then has_payload indication will be asserted; the default value
3297 should be equal to > write MBS size! */
3298 #define PXP2_REG_WR_DMAE_TH 0x120368
3299 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3300 buffer reaches this number has_payload will be asserted */
3301 #define PXP2_REG_WR_HC_MPS 0x1205c8
3302 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3303 buffer reaches this number has_payload will be asserted */
3304 #define PXP2_REG_WR_QM_MPS 0x1205dc
3305 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3306 #define PXP2_REG_WR_REV_MODE 0x120670
3307 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3308 buffer reaches this number has_payload will be asserted */
3309 #define PXP2_REG_WR_SRC_MPS 0x1205e4
3310 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3311 buffer reaches this number has_payload will be asserted */
3312 #define PXP2_REG_WR_TM_MPS 0x1205e0
3313 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3314 buffer reaches this number has_payload will be asserted */
3315 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
3316 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3317 threshold then has_payload indication will be asserted; the default value
3318 should be equal to > write MBS size! */
3319 #define PXP2_REG_WR_USDMDP_TH 0x120348
3320 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3321 buffer reaches this number has_payload will be asserted */
3322 #define PXP2_REG_WR_USDM_MPS 0x1205cc
3323 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3324 buffer reaches this number has_payload will be asserted */
3325 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
3326 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
3327 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
3328 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3329 this client is waiting for the arbiter. */
3330 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3331 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3332 block. Should be used for close the gates. */
3333 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3334 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3335 should update according to 'hst_discard_doorbells' register when the state
3337 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3338 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3339 Should be used for close the gates. */
3340 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3341 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3342 means this PSWHST is discarding inputs from this client. Each bit should
3343 update according to 'hst_discard_internal_writes' register when the state
3345 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3346 /* [WB 160] Used for initialization of the inbound interrupts memory */
3347 #define PXP_REG_HST_INBOUND_INT 0x103800
3348 /* [RW 32] Interrupt mask register #0 read/write */
3349 #define PXP_REG_PXP_INT_MASK_0 0x103074
3350 #define PXP_REG_PXP_INT_MASK_1 0x103084
3351 /* [R 32] Interrupt register #0 read */
3352 #define PXP_REG_PXP_INT_STS_0 0x103068
3353 #define PXP_REG_PXP_INT_STS_1 0x103078
3354 /* [RC 32] Interrupt register #0 read clear */
3355 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3356 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3357 /* [RW 27] Parity mask register #0 read/write */
3358 #define PXP_REG_PXP_PRTY_MASK 0x103094
3359 /* [R 26] Parity register #0 read */
3360 #define PXP_REG_PXP_PRTY_STS 0x103088
3361 /* [RC 27] Parity register #0 read clear */
3362 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3363 /* [RW 4] The activity counter initial increment value sent in the load
3365 #define QM_REG_ACTCTRINITVAL_0 0x168040
3366 #define QM_REG_ACTCTRINITVAL_1 0x168044
3367 #define QM_REG_ACTCTRINITVAL_2 0x168048
3368 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3369 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3370 index I represents the physical queue number. The 12 lsbs are ignore and
3371 considered zero so practically there are only 20 bits in this register;
3373 #define QM_REG_BASEADDR 0x168900
3374 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3375 index I represents the physical queue number. The 12 lsbs are ignore and
3376 considered zero so practically there are only 20 bits in this register;
3378 #define QM_REG_BASEADDR_EXT_A 0x16e100
3379 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3380 #define QM_REG_BYTECRDCOST 0x168234
3381 /* [RW 16] The initial byte credit value for both ports. */
3382 #define QM_REG_BYTECRDINITVAL 0x168238
3383 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3384 queue uses port 0 else it uses port 1; queues 31-0 */
3385 #define QM_REG_BYTECRDPORT_LSB 0x168228
3386 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3387 queue uses port 0 else it uses port 1; queues 95-64 */
3388 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3389 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3390 queue uses port 0 else it uses port 1; queues 63-32 */
3391 #define QM_REG_BYTECRDPORT_MSB 0x168224
3392 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3393 queue uses port 0 else it uses port 1; queues 127-96 */
3394 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3395 /* [RW 16] The byte credit value that if above the QM is considered almost
3397 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3398 /* [RW 4] The initial credit for interface */
3399 #define QM_REG_CMINITCRD_0 0x1680cc
3400 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3401 #define QM_REG_CMINITCRD_1 0x1680d0
3402 #define QM_REG_CMINITCRD_2 0x1680d4
3403 #define QM_REG_CMINITCRD_3 0x1680d8
3404 #define QM_REG_CMINITCRD_4 0x1680dc
3405 #define QM_REG_CMINITCRD_5 0x1680e0
3406 #define QM_REG_CMINITCRD_6 0x1680e4
3407 #define QM_REG_CMINITCRD_7 0x1680e8
3408 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3410 #define QM_REG_CMINTEN 0x1680ec
3411 /* [RW 12] A bit vector which indicates which one of the queues are tied to
3413 #define QM_REG_CMINTVOQMASK_0 0x1681f4
3414 #define QM_REG_CMINTVOQMASK_1 0x1681f8
3415 #define QM_REG_CMINTVOQMASK_2 0x1681fc
3416 #define QM_REG_CMINTVOQMASK_3 0x168200
3417 #define QM_REG_CMINTVOQMASK_4 0x168204
3418 #define QM_REG_CMINTVOQMASK_5 0x168208
3419 #define QM_REG_CMINTVOQMASK_6 0x16820c
3420 #define QM_REG_CMINTVOQMASK_7 0x168210
3421 /* [RW 20] The number of connections divided by 16 which dictates the size
3422 of each queue which belongs to even function number. */
3423 #define QM_REG_CONNNUM_0 0x168020
3424 /* [R 6] Keep the fill level of the fifo from write client 4 */
3425 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
3426 /* [RW 8] The context regions sent in the CFC load request */
3427 #define QM_REG_CTXREG_0 0x168030
3428 #define QM_REG_CTXREG_1 0x168034
3429 #define QM_REG_CTXREG_2 0x168038
3430 #define QM_REG_CTXREG_3 0x16803c
3431 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3433 #define QM_REG_ENBYPVOQMASK 0x16823c
3434 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3435 physical queue uses the byte credit; queues 31-0 */
3436 #define QM_REG_ENBYTECRD_LSB 0x168220
3437 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3438 physical queue uses the byte credit; queues 95-64 */
3439 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3440 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3441 physical queue uses the byte credit; queues 63-32 */
3442 #define QM_REG_ENBYTECRD_MSB 0x16821c
3443 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3444 physical queue uses the byte credit; queues 127-96 */
3445 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
3446 /* [RW 4] If cleared then the secondary interface will not be served by the
3448 #define QM_REG_ENSEC 0x1680f0
3450 #define QM_REG_FUNCNUMSEL_LSB 0x168230
3452 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
3453 /* [RW 32] A mask register to mask the Almost empty signals which will not
3454 be use for the almost empty indication to the HW block; queues 31:0 */
3455 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
3456 /* [RW 32] A mask register to mask the Almost empty signals which will not
3457 be use for the almost empty indication to the HW block; queues 95-64 */
3458 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3459 /* [RW 32] A mask register to mask the Almost empty signals which will not
3460 be use for the almost empty indication to the HW block; queues 63:32 */
3461 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
3462 /* [RW 32] A mask register to mask the Almost empty signals which will not
3463 be use for the almost empty indication to the HW block; queues 127-96 */
3464 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
3465 /* [RW 4] The number of outstanding request to CFC */
3466 #define QM_REG_OUTLDREQ 0x168804
3467 /* [RC 1] A flag to indicate that overflow error occurred in one of the
3469 #define QM_REG_OVFERROR 0x16805c
3470 /* [RC 7] the Q where the overflow occurs */
3471 #define QM_REG_OVFQNUM 0x168058
3472 /* [R 16] Pause state for physical queues 15-0 */
3473 #define QM_REG_PAUSESTATE0 0x168410
3474 /* [R 16] Pause state for physical queues 31-16 */
3475 #define QM_REG_PAUSESTATE1 0x168414
3476 /* [R 16] Pause state for physical queues 47-32 */
3477 #define QM_REG_PAUSESTATE2 0x16e684
3478 /* [R 16] Pause state for physical queues 63-48 */
3479 #define QM_REG_PAUSESTATE3 0x16e688
3480 /* [R 16] Pause state for physical queues 79-64 */
3481 #define QM_REG_PAUSESTATE4 0x16e68c
3482 /* [R 16] Pause state for physical queues 95-80 */
3483 #define QM_REG_PAUSESTATE5 0x16e690
3484 /* [R 16] Pause state for physical queues 111-96 */
3485 #define QM_REG_PAUSESTATE6 0x16e694
3486 /* [R 16] Pause state for physical queues 127-112 */
3487 #define QM_REG_PAUSESTATE7 0x16e698
3488 /* [RW 2] The PCI attributes field used in the PCI request. */
3489 #define QM_REG_PCIREQAT 0x168054
3490 #define QM_REG_PF_EN 0x16e70c
3491 /* [R 24] The number of tasks stored in the QM for the PF. only even
3492 * functions are valid in E2 (odd I registers will be hard wired to 0) */
3493 #define QM_REG_PF_USG_CNT_0 0x16e040
3494 /* [R 16] NOT USED */
3495 #define QM_REG_PORT0BYTECRD 0x168300
3496 /* [R 16] The byte credit of port 1 */
3497 #define QM_REG_PORT1BYTECRD 0x168304
3498 /* [RW 3] pci function number of queues 15-0 */
3499 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3500 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3501 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3502 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3503 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3504 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3505 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3506 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3507 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3508 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3509 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3510 #define QM_REG_PTRTBL 0x168a00
3511 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3512 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3513 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3514 #define QM_REG_PTRTBL_EXT_A 0x16e200
3515 /* [RW 2] Interrupt mask register #0 read/write */
3516 #define QM_REG_QM_INT_MASK 0x168444
3517 /* [R 2] Interrupt register #0 read */
3518 #define QM_REG_QM_INT_STS 0x168438
3519 /* [RW 12] Parity mask register #0 read/write */
3520 #define QM_REG_QM_PRTY_MASK 0x168454
3521 /* [R 12] Parity register #0 read */
3522 #define QM_REG_QM_PRTY_STS 0x168448
3523 /* [RC 12] Parity register #0 read clear */
3524 #define QM_REG_QM_PRTY_STS_CLR 0x16844c
3525 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3526 #define QM_REG_QSTATUS_HIGH 0x16802c
3527 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3528 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
3529 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3530 #define QM_REG_QSTATUS_LOW 0x168028
3531 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3532 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3533 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
3534 #define QM_REG_QTASKCTR_0 0x168308
3535 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
3536 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
3537 /* [RW 4] Queue tied to VOQ */
3538 #define QM_REG_QVOQIDX_0 0x1680f4
3539 #define QM_REG_QVOQIDX_10 0x16811c
3540 #define QM_REG_QVOQIDX_100 0x16e49c
3541 #define QM_REG_QVOQIDX_101 0x16e4a0
3542 #define QM_REG_QVOQIDX_102 0x16e4a4
3543 #define QM_REG_QVOQIDX_103 0x16e4a8
3544 #define QM_REG_QVOQIDX_104 0x16e4ac
3545 #define QM_REG_QVOQIDX_105 0x16e4b0
3546 #define QM_REG_QVOQIDX_106 0x16e4b4
3547 #define QM_REG_QVOQIDX_107 0x16e4b8
3548 #define QM_REG_QVOQIDX_108 0x16e4bc
3549 #define QM_REG_QVOQIDX_109 0x16e4c0
3550 #define QM_REG_QVOQIDX_11 0x168120
3551 #define QM_REG_QVOQIDX_110 0x16e4c4
3552 #define QM_REG_QVOQIDX_111 0x16e4c8
3553 #define QM_REG_QVOQIDX_112 0x16e4cc
3554 #define QM_REG_QVOQIDX_113 0x16e4d0
3555 #define QM_REG_QVOQIDX_114 0x16e4d4
3556 #define QM_REG_QVOQIDX_115 0x16e4d8
3557 #define QM_REG_QVOQIDX_116 0x16e4dc
3558 #define QM_REG_QVOQIDX_117 0x16e4e0
3559 #define QM_REG_QVOQIDX_118 0x16e4e4
3560 #define QM_REG_QVOQIDX_119 0x16e4e8
3561 #define QM_REG_QVOQIDX_12 0x168124
3562 #define QM_REG_QVOQIDX_120 0x16e4ec
3563 #define QM_REG_QVOQIDX_121 0x16e4f0
3564 #define QM_REG_QVOQIDX_122 0x16e4f4
3565 #define QM_REG_QVOQIDX_123 0x16e4f8
3566 #define QM_REG_QVOQIDX_124 0x16e4fc
3567 #define QM_REG_QVOQIDX_125 0x16e500
3568 #define QM_REG_QVOQIDX_126 0x16e504
3569 #define QM_REG_QVOQIDX_127 0x16e508
3570 #define QM_REG_QVOQIDX_13 0x168128
3571 #define QM_REG_QVOQIDX_14 0x16812c
3572 #define QM_REG_QVOQIDX_15 0x168130
3573 #define QM_REG_QVOQIDX_16 0x168134
3574 #define QM_REG_QVOQIDX_17 0x168138
3575 #define QM_REG_QVOQIDX_21 0x168148
3576 #define QM_REG_QVOQIDX_22 0x16814c
3577 #define QM_REG_QVOQIDX_23 0x168150
3578 #define QM_REG_QVOQIDX_24 0x168154
3579 #define QM_REG_QVOQIDX_25 0x168158
3580 #define QM_REG_QVOQIDX_26 0x16815c
3581 #define QM_REG_QVOQIDX_27 0x168160
3582 #define QM_REG_QVOQIDX_28 0x168164
3583 #define QM_REG_QVOQIDX_29 0x168168
3584 #define QM_REG_QVOQIDX_30 0x16816c
3585 #define QM_REG_QVOQIDX_31 0x168170
3586 #define QM_REG_QVOQIDX_32 0x168174
3587 #define QM_REG_QVOQIDX_33 0x168178
3588 #define QM_REG_QVOQIDX_34 0x16817c
3589 #define QM_REG_QVOQIDX_35 0x168180
3590 #define QM_REG_QVOQIDX_36 0x168184
3591 #define QM_REG_QVOQIDX_37 0x168188
3592 #define QM_REG_QVOQIDX_38 0x16818c
3593 #define QM_REG_QVOQIDX_39 0x168190
3594 #define QM_REG_QVOQIDX_40 0x168194
3595 #define QM_REG_QVOQIDX_41 0x168198
3596 #define QM_REG_QVOQIDX_42 0x16819c
3597 #define QM_REG_QVOQIDX_43 0x1681a0
3598 #define QM_REG_QVOQIDX_44 0x1681a4
3599 #define QM_REG_QVOQIDX_45 0x1681a8
3600 #define QM_REG_QVOQIDX_46 0x1681ac
3601 #define QM_REG_QVOQIDX_47 0x1681b0
3602 #define QM_REG_QVOQIDX_48 0x1681b4
3603 #define QM_REG_QVOQIDX_49 0x1681b8
3604 #define QM_REG_QVOQIDX_5 0x168108
3605 #define QM_REG_QVOQIDX_50 0x1681bc
3606 #define QM_REG_QVOQIDX_51 0x1681c0
3607 #define QM_REG_QVOQIDX_52 0x1681c4
3608 #define QM_REG_QVOQIDX_53 0x1681c8
3609 #define QM_REG_QVOQIDX_54 0x1681cc
3610 #define QM_REG_QVOQIDX_55 0x1681d0
3611 #define QM_REG_QVOQIDX_56 0x1681d4
3612 #define QM_REG_QVOQIDX_57 0x1681d8
3613 #define QM_REG_QVOQIDX_58 0x1681dc
3614 #define QM_REG_QVOQIDX_59 0x1681e0
3615 #define QM_REG_QVOQIDX_6 0x16810c
3616 #define QM_REG_QVOQIDX_60 0x1681e4
3617 #define QM_REG_QVOQIDX_61 0x1681e8
3618 #define QM_REG_QVOQIDX_62 0x1681ec
3619 #define QM_REG_QVOQIDX_63 0x1681f0
3620 #define QM_REG_QVOQIDX_64 0x16e40c
3621 #define QM_REG_QVOQIDX_65 0x16e410
3622 #define QM_REG_QVOQIDX_69 0x16e420
3623 #define QM_REG_QVOQIDX_7 0x168110
3624 #define QM_REG_QVOQIDX_70 0x16e424
3625 #define QM_REG_QVOQIDX_71 0x16e428
3626 #define QM_REG_QVOQIDX_72 0x16e42c
3627 #define QM_REG_QVOQIDX_73 0x16e430
3628 #define QM_REG_QVOQIDX_74 0x16e434
3629 #define QM_REG_QVOQIDX_75 0x16e438
3630 #define QM_REG_QVOQIDX_76 0x16e43c
3631 #define QM_REG_QVOQIDX_77 0x16e440
3632 #define QM_REG_QVOQIDX_78 0x16e444
3633 #define QM_REG_QVOQIDX_79 0x16e448
3634 #define QM_REG_QVOQIDX_8 0x168114
3635 #define QM_REG_QVOQIDX_80 0x16e44c
3636 #define QM_REG_QVOQIDX_81 0x16e450
3637 #define QM_REG_QVOQIDX_85 0x16e460
3638 #define QM_REG_QVOQIDX_86 0x16e464
3639 #define QM_REG_QVOQIDX_87 0x16e468
3640 #define QM_REG_QVOQIDX_88 0x16e46c
3641 #define QM_REG_QVOQIDX_89 0x16e470
3642 #define QM_REG_QVOQIDX_9 0x168118
3643 #define QM_REG_QVOQIDX_90 0x16e474
3644 #define QM_REG_QVOQIDX_91 0x16e478
3645 #define QM_REG_QVOQIDX_92 0x16e47c
3646 #define QM_REG_QVOQIDX_93 0x16e480
3647 #define QM_REG_QVOQIDX_94 0x16e484
3648 #define QM_REG_QVOQIDX_95 0x16e488
3649 #define QM_REG_QVOQIDX_96 0x16e48c
3650 #define QM_REG_QVOQIDX_97 0x16e490
3651 #define QM_REG_QVOQIDX_98 0x16e494
3652 #define QM_REG_QVOQIDX_99 0x16e498
3653 /* [RW 1] Initialization bit command */
3654 #define QM_REG_SOFT_RESET 0x168428
3655 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3656 #define QM_REG_TASKCRDCOST_0 0x16809c
3657 #define QM_REG_TASKCRDCOST_1 0x1680a0
3658 #define QM_REG_TASKCRDCOST_2 0x1680a4
3659 #define QM_REG_TASKCRDCOST_4 0x1680ac
3660 #define QM_REG_TASKCRDCOST_5 0x1680b0
3661 /* [R 6] Keep the fill level of the fifo from write client 3 */
3662 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
3663 /* [R 6] Keep the fill level of the fifo from write client 2 */
3664 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
3665 /* [RC 32] Credit update error register */
3666 #define QM_REG_VOQCRDERRREG 0x168408
3667 /* [R 16] The credit value for each VOQ */
3668 #define QM_REG_VOQCREDIT_0 0x1682d0
3669 #define QM_REG_VOQCREDIT_1 0x1682d4
3670 #define QM_REG_VOQCREDIT_4 0x1682e0
3671 /* [RW 16] The credit value that if above the QM is considered almost full */
3672 #define QM_REG_VOQCREDITAFULLTHR 0x168090
3673 /* [RW 16] The init and maximum credit for each VoQ */
3674 #define QM_REG_VOQINITCREDIT_0 0x168060
3675 #define QM_REG_VOQINITCREDIT_1 0x168064
3676 #define QM_REG_VOQINITCREDIT_2 0x168068
3677 #define QM_REG_VOQINITCREDIT_4 0x168070
3678 #define QM_REG_VOQINITCREDIT_5 0x168074
3679 /* [RW 1] The port of which VOQ belongs */
3680 #define QM_REG_VOQPORT_0 0x1682a0
3681 #define QM_REG_VOQPORT_1 0x1682a4
3682 #define QM_REG_VOQPORT_2 0x1682a8
3683 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3684 #define QM_REG_VOQQMASK_0_LSB 0x168240
3685 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3686 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3687 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3688 #define QM_REG_VOQQMASK_0_MSB 0x168244
3689 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3690 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3691 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3692 #define QM_REG_VOQQMASK_10_LSB 0x168290
3693 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3694 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3695 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3696 #define QM_REG_VOQQMASK_10_MSB 0x168294
3697 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3698 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3699 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3700 #define QM_REG_VOQQMASK_11_LSB 0x168298
3701 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3702 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3703 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3704 #define QM_REG_VOQQMASK_11_MSB 0x16829c
3705 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3706 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3707 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3708 #define QM_REG_VOQQMASK_1_LSB 0x168248
3709 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3710 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3711 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3712 #define QM_REG_VOQQMASK_1_MSB 0x16824c
3713 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3714 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3715 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3716 #define QM_REG_VOQQMASK_2_LSB 0x168250
3717 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3718 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3719 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3720 #define QM_REG_VOQQMASK_2_MSB 0x168254
3721 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3722 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3723 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3724 #define QM_REG_VOQQMASK_3_LSB 0x168258
3725 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3726 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3727 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3728 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3729 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3730 #define QM_REG_VOQQMASK_4_LSB 0x168260
3731 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3732 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3733 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3734 #define QM_REG_VOQQMASK_4_MSB 0x168264
3735 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3736 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3737 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3738 #define QM_REG_VOQQMASK_5_LSB 0x168268
3739 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3740 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3741 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3742 #define QM_REG_VOQQMASK_5_MSB 0x16826c
3743 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3744 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3745 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3746 #define QM_REG_VOQQMASK_6_LSB 0x168270
3747 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3748 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3749 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3750 #define QM_REG_VOQQMASK_6_MSB 0x168274
3751 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3752 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3753 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3754 #define QM_REG_VOQQMASK_7_LSB 0x168278
3755 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3756 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3757 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3758 #define QM_REG_VOQQMASK_7_MSB 0x16827c
3759 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3760 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3761 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3762 #define QM_REG_VOQQMASK_8_LSB 0x168280
3763 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3764 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3765 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3766 #define QM_REG_VOQQMASK_8_MSB 0x168284
3767 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3768 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3769 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3770 #define QM_REG_VOQQMASK_9_LSB 0x168288
3771 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3772 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3773 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3774 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3775 /* [RW 32] Wrr weights */
3776 #define QM_REG_WRRWEIGHTS_0 0x16880c
3777 #define QM_REG_WRRWEIGHTS_1 0x168810
3778 #define QM_REG_WRRWEIGHTS_10 0x168814
3779 #define QM_REG_WRRWEIGHTS_11 0x168818
3780 #define QM_REG_WRRWEIGHTS_12 0x16881c
3781 #define QM_REG_WRRWEIGHTS_13 0x168820
3782 #define QM_REG_WRRWEIGHTS_14 0x168824
3783 #define QM_REG_WRRWEIGHTS_15 0x168828
3784 #define QM_REG_WRRWEIGHTS_16 0x16e000
3785 #define QM_REG_WRRWEIGHTS_17 0x16e004
3786 #define QM_REG_WRRWEIGHTS_18 0x16e008
3787 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3788 #define QM_REG_WRRWEIGHTS_2 0x16882c
3789 #define QM_REG_WRRWEIGHTS_20 0x16e010
3790 #define QM_REG_WRRWEIGHTS_21 0x16e014
3791 #define QM_REG_WRRWEIGHTS_22 0x16e018
3792 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3793 #define QM_REG_WRRWEIGHTS_24 0x16e020
3794 #define QM_REG_WRRWEIGHTS_25 0x16e024
3795 #define QM_REG_WRRWEIGHTS_26 0x16e028
3796 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3797 #define QM_REG_WRRWEIGHTS_28 0x16e030
3798 #define QM_REG_WRRWEIGHTS_29 0x16e034
3799 #define QM_REG_WRRWEIGHTS_3 0x168830
3800 #define QM_REG_WRRWEIGHTS_30 0x16e038
3801 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3802 #define QM_REG_WRRWEIGHTS_4 0x168834
3803 #define QM_REG_WRRWEIGHTS_5 0x168838
3804 #define QM_REG_WRRWEIGHTS_6 0x16883c
3805 #define QM_REG_WRRWEIGHTS_7 0x168840
3806 #define QM_REG_WRRWEIGHTS_8 0x168844
3807 #define QM_REG_WRRWEIGHTS_9 0x168848
3808 /* [R 6] Keep the fill level of the fifo from write client 1 */
3809 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
3810 /* [W 1] reset to parity interrupt */
3811 #define SEM_FAST_REG_PARITY_RST 0x18840
3812 #define SRC_REG_COUNTFREE0 0x40500
3813 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3814 ports. If set the searcher support 8 functions. */
3815 #define SRC_REG_E1HMF_ENABLE 0x404cc
3816 #define SRC_REG_FIRSTFREE0 0x40510
3817 #define SRC_REG_KEYRSS0_0 0x40408
3818 #define SRC_REG_KEYRSS0_7 0x40424
3819 #define SRC_REG_KEYRSS1_9 0x40454
3820 #define SRC_REG_KEYSEARCH_0 0x40458
3821 #define SRC_REG_KEYSEARCH_1 0x4045c
3822 #define SRC_REG_KEYSEARCH_2 0x40460
3823 #define SRC_REG_KEYSEARCH_3 0x40464
3824 #define SRC_REG_KEYSEARCH_4 0x40468
3825 #define SRC_REG_KEYSEARCH_5 0x4046c
3826 #define SRC_REG_KEYSEARCH_6 0x40470
3827 #define SRC_REG_KEYSEARCH_7 0x40474
3828 #define SRC_REG_KEYSEARCH_8 0x40478
3829 #define SRC_REG_KEYSEARCH_9 0x4047c
3830 #define SRC_REG_LASTFREE0 0x40530
3831 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
3832 /* [RW 1] Reset internal state machines. */
3833 #define SRC_REG_SOFT_RST 0x4049c
3834 /* [R 3] Interrupt register #0 read */
3835 #define SRC_REG_SRC_INT_STS 0x404ac
3836 /* [RW 3] Parity mask register #0 read/write */
3837 #define SRC_REG_SRC_PRTY_MASK 0x404c8
3838 /* [R 3] Parity register #0 read */
3839 #define SRC_REG_SRC_PRTY_STS 0x404bc
3840 /* [RC 3] Parity register #0 read clear */
3841 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
3842 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3843 #define TCM_REG_CAM_OCCUP 0x5017c
3844 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3845 disregarded; valid output is deasserted; all other signals are treated as
3846 usual; if 1 - normal activity. */
3847 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
3848 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3849 are disregarded; all other signals are treated as usual; if 1 - normal
3851 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
3852 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3853 disregarded; valid output is deasserted; all other signals are treated as
3854 usual; if 1 - normal activity. */
3855 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3856 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3857 input is disregarded; all other signals are treated as usual; if 1 -
3859 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
3860 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3861 the initial credit value; read returns the current value of the credit
3862 counter. Must be initialized to 1 at start-up. */
3863 #define TCM_REG_CFC_INIT_CRD 0x50204
3864 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3865 weight 8 (the most prioritised); 1 stands for weight 1(least
3866 prioritised); 2 stands for weight 2; tc. */
3867 #define TCM_REG_CP_WEIGHT 0x500c0
3868 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3869 disregarded; acknowledge output is deasserted; all other signals are
3870 treated as usual; if 1 - normal activity. */
3871 #define TCM_REG_CSEM_IFEN 0x5002c
3872 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
3874 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
3875 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3876 weight 8 (the most prioritised); 1 stands for weight 1(least
3877 prioritised); 2 stands for weight 2; tc. */
3878 #define TCM_REG_CSEM_WEIGHT 0x500bc
3879 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3880 #define TCM_REG_ERR_EVNT_ID 0x500a0
3881 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3882 #define TCM_REG_ERR_TCM_HDR 0x5009c
3883 /* [RW 8] The Event ID for Timers expiration. */
3884 #define TCM_REG_EXPR_EVNT_ID 0x500a4
3885 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3886 writes the initial credit value; read returns the current value of the
3887 credit counter. Must be initialized to 64 at start-up. */
3888 #define TCM_REG_FIC0_INIT_CRD 0x5020c
3889 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3890 writes the initial credit value; read returns the current value of the
3891 credit counter. Must be initialized to 64 at start-up. */
3892 #define TCM_REG_FIC1_INIT_CRD 0x50210
3893 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3894 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3895 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3896 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3897 #define TCM_REG_GR_ARB_TYPE 0x50114
3898 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3899 highest priority is 3. It is supposed that the Store channel is the
3900 compliment of the other 3 groups. */
3901 #define TCM_REG_GR_LD0_PR 0x5011c
3902 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3903 highest priority is 3. It is supposed that the Store channel is the
3904 compliment of the other 3 groups. */
3905 #define TCM_REG_GR_LD1_PR 0x50120
3906 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3907 sent to STORM; for a specific connection type. The double REG-pairs are
3908 used to align to STORM context row size of 128 bits. The offset of these
3909 data in the STORM context is always 0. Index _i stands for the connection
3910 type (one of 16). */
3911 #define TCM_REG_N_SM_CTX_LD_0 0x50050
3912 #define TCM_REG_N_SM_CTX_LD_1 0x50054
3913 #define TCM_REG_N_SM_CTX_LD_2 0x50058
3914 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
3915 #define TCM_REG_N_SM_CTX_LD_4 0x50060
3916 #define TCM_REG_N_SM_CTX_LD_5 0x50064
3917 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3918 acknowledge output is deasserted; all other signals are treated as usual;
3919 if 1 - normal activity. */
3920 #define TCM_REG_PBF_IFEN 0x50024
3921 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
3923 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
3924 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3925 weight 8 (the most prioritised); 1 stands for weight 1(least
3926 prioritised); 2 stands for weight 2; tc. */
3927 #define TCM_REG_PBF_WEIGHT 0x500b4
3928 #define TCM_REG_PHYS_QNUM0_0 0x500e0
3929 #define TCM_REG_PHYS_QNUM0_1 0x500e4
3930 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3931 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3932 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3933 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3934 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3935 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3936 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3937 acknowledge output is deasserted; all other signals are treated as usual;
3938 if 1 - normal activity. */
3939 #define TCM_REG_PRS_IFEN 0x50020
3940 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3942 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3943 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3944 weight 8 (the most prioritised); 1 stands for weight 1(least
3945 prioritised); 2 stands for weight 2; tc. */
3946 #define TCM_REG_PRS_WEIGHT 0x500b0
3947 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3948 #define TCM_REG_STOP_EVNT_ID 0x500a8
3949 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3951 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3952 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3953 disregarded; acknowledge output is deasserted; all other signals are
3954 treated as usual; if 1 - normal activity. */
3955 #define TCM_REG_STORM_TCM_IFEN 0x50010
3956 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3957 weight 8 (the most prioritised); 1 stands for weight 1(least
3958 prioritised); 2 stands for weight 2; tc. */
3959 #define TCM_REG_STORM_WEIGHT 0x500ac
3960 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3961 acknowledge output is deasserted; all other signals are treated as usual;
3962 if 1 - normal activity. */
3963 #define TCM_REG_TCM_CFC_IFEN 0x50040
3964 /* [RW 11] Interrupt mask register #0 read/write */
3965 #define TCM_REG_TCM_INT_MASK 0x501dc
3966 /* [R 11] Interrupt register #0 read */
3967 #define TCM_REG_TCM_INT_STS 0x501d0
3968 /* [RW 27] Parity mask register #0 read/write */
3969 #define TCM_REG_TCM_PRTY_MASK 0x501ec
3970 /* [R 27] Parity register #0 read */
3971 #define TCM_REG_TCM_PRTY_STS 0x501e0
3972 /* [RC 27] Parity register #0 read clear */
3973 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
3974 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3975 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3976 Is used to determine the number of the AG context REG-pairs written back;
3977 when the input message Reg1WbFlg isn't set. */
3978 #define TCM_REG_TCM_REG0_SZ 0x500d8
3979 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3980 disregarded; valid is deasserted; all other signals are treated as usual;
3981 if 1 - normal activity. */
3982 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3983 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3984 disregarded; valid is deasserted; all other signals are treated as usual;
3985 if 1 - normal activity. */
3986 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3987 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3988 disregarded; valid is deasserted; all other signals are treated as usual;
3989 if 1 - normal activity. */
3990 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3991 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3992 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3993 /* [RW 28] The CM header for Timers expiration command. */
3994 #define TCM_REG_TM_TCM_HDR 0x50098
3995 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3996 disregarded; acknowledge output is deasserted; all other signals are
3997 treated as usual; if 1 - normal activity. */
3998 #define TCM_REG_TM_TCM_IFEN 0x5001c
3999 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4000 weight 8 (the most prioritised); 1 stands for weight 1(least
4001 prioritised); 2 stands for weight 2; tc. */
4002 #define TCM_REG_TM_WEIGHT 0x500d0
4003 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4004 the initial credit value; read returns the current value of the credit
4005 counter. Must be initialized to 32 at start-up. */
4006 #define TCM_REG_TQM_INIT_CRD 0x5021c
4007 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4008 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4009 prioritised); 2 stands for weight 2; tc. */
4010 #define TCM_REG_TQM_P_WEIGHT 0x500c8
4011 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4012 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4013 prioritised); 2 stands for weight 2; tc. */
4014 #define TCM_REG_TQM_S_WEIGHT 0x500cc
4015 /* [RW 28] The CM header value for QM request (primary). */
4016 #define TCM_REG_TQM_TCM_HDR_P 0x50090
4017 /* [RW 28] The CM header value for QM request (secondary). */
4018 #define TCM_REG_TQM_TCM_HDR_S 0x50094
4019 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4020 acknowledge output is deasserted; all other signals are treated as usual;
4021 if 1 - normal activity. */
4022 #define TCM_REG_TQM_TCM_IFEN 0x50014
4023 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4024 acknowledge output is deasserted; all other signals are treated as usual;
4025 if 1 - normal activity. */
4026 #define TCM_REG_TSDM_IFEN 0x50018
4027 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
4029 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
4030 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4031 weight 8 (the most prioritised); 1 stands for weight 1(least
4032 prioritised); 2 stands for weight 2; tc. */
4033 #define TCM_REG_TSDM_WEIGHT 0x500c4
4034 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4035 disregarded; acknowledge output is deasserted; all other signals are
4036 treated as usual; if 1 - normal activity. */
4037 #define TCM_REG_USEM_IFEN 0x50028
4038 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
4040 #define TCM_REG_USEM_LENGTH_MIS 0x50170
4041 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4042 weight 8 (the most prioritised); 1 stands for weight 1(least
4043 prioritised); 2 stands for weight 2; tc. */
4044 #define TCM_REG_USEM_WEIGHT 0x500b8
4045 /* [RW 21] Indirect access to the descriptor table of the XX protection
4046 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4047 pointer; 20:16] - next pointer. */
4048 #define TCM_REG_XX_DESCR_TABLE 0x50280
4049 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
4050 /* [R 6] Use to read the value of XX protection Free counter. */
4051 #define TCM_REG_XX_FREE 0x50178
4052 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4053 of the Input Stage XX protection buffer by the XX protection pending
4054 messages. Max credit available - 127.Write writes the initial credit
4055 value; read returns the current value of the credit counter. Must be
4056 initialized to 19 at start-up. */
4057 #define TCM_REG_XX_INIT_CRD 0x50220
4058 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
4060 #define TCM_REG_XX_MAX_LL_SZ 0x50044
4061 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4062 protection. ~tcm_registers_xx_free.xx_free is read on read. */
4063 #define TCM_REG_XX_MSG_NUM 0x50224
4064 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4065 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4066 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4067 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4069 #define TCM_REG_XX_TABLE 0x50240
4070 /* [RW 4] Load value for cfc ac credit cnt. */
4071 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4072 /* [RW 4] Load value for cfc cld credit cnt. */
4073 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4074 /* [RW 8] Client0 context region. */
4075 #define TM_REG_CL0_CONT_REGION 0x164030
4076 /* [RW 8] Client1 context region. */
4077 #define TM_REG_CL1_CONT_REGION 0x164034
4078 /* [RW 8] Client2 context region. */
4079 #define TM_REG_CL2_CONT_REGION 0x164038
4080 /* [RW 2] Client in High priority client number. */
4081 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4082 /* [RW 4] Load value for clout0 cred cnt. */
4083 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4084 /* [RW 4] Load value for clout1 cred cnt. */
4085 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4086 /* [RW 4] Load value for clout2 cred cnt. */
4087 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4088 /* [RW 1] Enable client0 input. */
4089 #define TM_REG_EN_CL0_INPUT 0x164008
4090 /* [RW 1] Enable client1 input. */
4091 #define TM_REG_EN_CL1_INPUT 0x16400c
4092 /* [RW 1] Enable client2 input. */
4093 #define TM_REG_EN_CL2_INPUT 0x164010
4094 #define TM_REG_EN_LINEAR0_TIMER 0x164014
4095 /* [RW 1] Enable real time counter. */
4096 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4097 /* [RW 1] Enable for Timers state machines. */
4098 #define TM_REG_EN_TIMERS 0x164000
4099 /* [RW 4] Load value for expiration credit cnt. CFC max number of
4100 outstanding load requests for timers (expiration) context loading. */
4101 #define TM_REG_EXP_CRDCNT_VAL 0x164238
4102 /* [RW 32] Linear0 logic address. */
4103 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
4104 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4105 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
4106 /* [ST 16] Linear0 Number of scans counter. */
4107 #define TM_REG_LIN0_NUM_SCANS 0x1640a0
4108 /* [WB 64] Linear0 phy address. */
4109 #define TM_REG_LIN0_PHY_ADDR 0x164270
4110 /* [RW 1] Linear0 physical address valid. */
4111 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
4112 #define TM_REG_LIN0_SCAN_ON 0x1640d0
4113 /* [RW 24] Linear0 array scan timeout. */
4114 #define TM_REG_LIN0_SCAN_TIME 0x16403c
4115 #define TM_REG_LIN0_VNIC_UC 0x164128
4116 /* [RW 32] Linear1 logic address. */
4117 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
4118 /* [WB 64] Linear1 phy address. */
4119 #define TM_REG_LIN1_PHY_ADDR 0x164280
4120 /* [RW 1] Linear1 physical address valid. */
4121 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
4122 /* [RW 6] Linear timer set_clear fifo threshold. */
4123 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4124 /* [RW 2] Load value for pci arbiter credit cnt. */
4125 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
4126 /* [RW 20] The amount of hardware cycles for each timer tick. */
4127 #define TM_REG_TIMER_TICK_SIZE 0x16401c
4128 /* [RW 8] Timers Context region. */
4129 #define TM_REG_TM_CONTEXT_REGION 0x164044
4130 /* [RW 1] Interrupt mask register #0 read/write */
4131 #define TM_REG_TM_INT_MASK 0x1640fc
4132 /* [R 1] Interrupt register #0 read */
4133 #define TM_REG_TM_INT_STS 0x1640f0
4134 /* [RW 7] Parity mask register #0 read/write */
4135 #define TM_REG_TM_PRTY_MASK 0x16410c
4136 /* [RC 7] Parity register #0 read clear */
4137 #define TM_REG_TM_PRTY_STS_CLR 0x164104
4138 /* [RW 8] The event id for aggregated interrupt 0 */
4139 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
4140 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
4141 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
4142 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
4143 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
4144 /* [RW 1] The T bit for aggregated interrupt 0 */
4145 #define TSDM_REG_AGG_INT_T_0 0x420b8
4146 #define TSDM_REG_AGG_INT_T_1 0x420bc
4147 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4148 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
4149 /* [RW 16] The maximum value of the completion counter #0 */
4150 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
4151 /* [RW 16] The maximum value of the completion counter #1 */
4152 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
4153 /* [RW 16] The maximum value of the completion counter #2 */
4154 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
4155 /* [RW 16] The maximum value of the completion counter #3 */
4156 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4157 /* [RW 13] The start address in the internal RAM for the completion
4159 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4160 #define TSDM_REG_ENABLE_IN1 0x42238
4161 #define TSDM_REG_ENABLE_IN2 0x4223c
4162 #define TSDM_REG_ENABLE_OUT1 0x42240
4163 #define TSDM_REG_ENABLE_OUT2 0x42244
4164 /* [RW 4] The initial number of messages that can be sent to the pxp control
4165 interface without receiving any ACK. */
4166 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4167 /* [ST 32] The number of ACK after placement messages received */
4168 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4169 /* [ST 32] The number of packet end messages received from the parser */
4170 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4171 /* [ST 32] The number of requests received from the pxp async if */
4172 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4173 /* [ST 32] The number of commands received in queue 0 */
4174 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4175 /* [ST 32] The number of commands received in queue 10 */
4176 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4177 /* [ST 32] The number of commands received in queue 11 */
4178 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4179 /* [ST 32] The number of commands received in queue 1 */
4180 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4181 /* [ST 32] The number of commands received in queue 3 */
4182 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4183 /* [ST 32] The number of commands received in queue 4 */
4184 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4185 /* [ST 32] The number of commands received in queue 5 */
4186 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4187 /* [ST 32] The number of commands received in queue 6 */
4188 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4189 /* [ST 32] The number of commands received in queue 7 */
4190 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4191 /* [ST 32] The number of commands received in queue 8 */
4192 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4193 /* [ST 32] The number of commands received in queue 9 */
4194 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4195 /* [RW 13] The start address in the internal RAM for the packet end message */
4196 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4197 /* [RW 13] The start address in the internal RAM for queue counters */
4198 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4199 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4200 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4201 /* [R 1] parser fifo empty in sdm_sync block */
4202 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4203 /* [R 1] parser serial fifo empty in sdm_sync block */
4204 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4205 /* [RW 32] Tick for timer counter. Applicable only when
4206 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4207 #define TSDM_REG_TIMER_TICK 0x42000
4208 /* [RW 32] Interrupt mask register #0 read/write */
4209 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4210 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
4211 /* [R 32] Interrupt register #0 read */
4212 #define TSDM_REG_TSDM_INT_STS_0 0x42290
4213 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
4214 /* [RW 11] Parity mask register #0 read/write */
4215 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
4216 /* [R 11] Parity register #0 read */
4217 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
4218 /* [RC 11] Parity register #0 read clear */
4219 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
4220 /* [RW 5] The number of time_slots in the arbitration cycle */
4221 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4222 /* [RW 3] The source that is associated with arbitration element 0. Source
4223 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4224 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4225 #define TSEM_REG_ARB_ELEMENT0 0x180020
4226 /* [RW 3] The source that is associated with arbitration element 1. Source
4227 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4228 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4229 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4230 #define TSEM_REG_ARB_ELEMENT1 0x180024
4231 /* [RW 3] The source that is associated with arbitration element 2. Source
4232 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4233 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4234 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4235 and ~tsem_registers_arb_element1.arb_element1 */
4236 #define TSEM_REG_ARB_ELEMENT2 0x180028
4237 /* [RW 3] The source that is associated with arbitration element 3. Source
4238 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4239 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4240 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4241 ~tsem_registers_arb_element1.arb_element1 and
4242 ~tsem_registers_arb_element2.arb_element2 */
4243 #define TSEM_REG_ARB_ELEMENT3 0x18002c
4244 /* [RW 3] The source that is associated with arbitration element 4. Source
4245 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4246 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4247 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4248 and ~tsem_registers_arb_element1.arb_element1 and
4249 ~tsem_registers_arb_element2.arb_element2 and
4250 ~tsem_registers_arb_element3.arb_element3 */
4251 #define TSEM_REG_ARB_ELEMENT4 0x180030
4252 #define TSEM_REG_ENABLE_IN 0x1800a4
4253 #define TSEM_REG_ENABLE_OUT 0x1800a8
4254 /* [RW 32] This address space contains all registers and memories that are
4255 placed in SEM_FAST block. The SEM_FAST registers are described in
4256 appendix B. In order to access the sem_fast registers the base address
4257 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4258 #define TSEM_REG_FAST_MEMORY 0x1a0000
4259 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4261 #define TSEM_REG_FIC0_DISABLE 0x180224
4262 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4264 #define TSEM_REG_FIC1_DISABLE 0x180234
4265 /* [RW 15] Interrupt table Read and write access to it is not possible in
4266 the middle of the work */
4267 #define TSEM_REG_INT_TABLE 0x180400
4268 /* [ST 24] Statistics register. The number of messages that entered through
4270 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4271 /* [ST 24] Statistics register. The number of messages that entered through
4273 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4274 /* [ST 24] Statistics register. The number of messages that were sent to
4276 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4277 /* [ST 24] Statistics register. The number of messages that were sent to
4279 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4280 /* [ST 24] Statistics register. The number of messages that were sent to
4282 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4283 /* [ST 24] Statistics register. The number of messages that were sent to
4285 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4286 /* [RW 1] Disables input messages from the passive buffer May be updated
4287 during run_time by the microcode */
4288 #define TSEM_REG_PAS_DISABLE 0x18024c
4289 /* [WB 128] Debug only. Passive buffer memory */
4290 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4291 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4292 #define TSEM_REG_PRAM 0x1c0000
4293 /* [R 8] Valid sleeping threads indication have bit per thread */
4294 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4295 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4296 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4297 /* [RW 8] List of free threads . There is a bit per thread. */
4298 #define TSEM_REG_THREADS_LIST 0x1802e4
4299 /* [RC 32] Parity register #0 read clear */
4300 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4301 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
4302 /* [RW 3] The arbitration scheme of time_slot 0 */
4303 #define TSEM_REG_TS_0_AS 0x180038
4304 /* [RW 3] The arbitration scheme of time_slot 10 */
4305 #define TSEM_REG_TS_10_AS 0x180060
4306 /* [RW 3] The arbitration scheme of time_slot 11 */
4307 #define TSEM_REG_TS_11_AS 0x180064
4308 /* [RW 3] The arbitration scheme of time_slot 12 */
4309 #define TSEM_REG_TS_12_AS 0x180068
4310 /* [RW 3] The arbitration scheme of time_slot 13 */
4311 #define TSEM_REG_TS_13_AS 0x18006c
4312 /* [RW 3] The arbitration scheme of time_slot 14 */
4313 #define TSEM_REG_TS_14_AS 0x180070
4314 /* [RW 3] The arbitration scheme of time_slot 15 */
4315 #define TSEM_REG_TS_15_AS 0x180074
4316 /* [RW 3] The arbitration scheme of time_slot 16 */
4317 #define TSEM_REG_TS_16_AS 0x180078
4318 /* [RW 3] The arbitration scheme of time_slot 17 */
4319 #define TSEM_REG_TS_17_AS 0x18007c
4320 /* [RW 3] The arbitration scheme of time_slot 18 */
4321 #define TSEM_REG_TS_18_AS 0x180080
4322 /* [RW 3] The arbitration scheme of time_slot 1 */
4323 #define TSEM_REG_TS_1_AS 0x18003c
4324 /* [RW 3] The arbitration scheme of time_slot 2 */
4325 #define TSEM_REG_TS_2_AS 0x180040
4326 /* [RW 3] The arbitration scheme of time_slot 3 */
4327 #define TSEM_REG_TS_3_AS 0x180044
4328 /* [RW 3] The arbitration scheme of time_slot 4 */
4329 #define TSEM_REG_TS_4_AS 0x180048
4330 /* [RW 3] The arbitration scheme of time_slot 5 */
4331 #define TSEM_REG_TS_5_AS 0x18004c
4332 /* [RW 3] The arbitration scheme of time_slot 6 */
4333 #define TSEM_REG_TS_6_AS 0x180050
4334 /* [RW 3] The arbitration scheme of time_slot 7 */
4335 #define TSEM_REG_TS_7_AS 0x180054
4336 /* [RW 3] The arbitration scheme of time_slot 8 */
4337 #define TSEM_REG_TS_8_AS 0x180058
4338 /* [RW 3] The arbitration scheme of time_slot 9 */
4339 #define TSEM_REG_TS_9_AS 0x18005c
4340 /* [RW 32] Interrupt mask register #0 read/write */
4341 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4342 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4343 /* [R 32] Interrupt register #0 read */
4344 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4345 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4346 /* [RW 32] Parity mask register #0 read/write */
4347 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4348 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4349 /* [R 32] Parity register #0 read */
4350 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4351 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4352 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4353 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4354 #define TSEM_REG_VFPF_ERR_NUM 0x180380
4355 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4356 * [10:8] of the address should be the offset within the accessed LCID
4357 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4358 * LCID100. The RBC address should be 12'ha64. */
4359 #define UCM_REG_AG_CTX 0xe2000
4360 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4361 #define UCM_REG_CAM_OCCUP 0xe0170
4362 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4363 disregarded; valid output is deasserted; all other signals are treated as
4364 usual; if 1 - normal activity. */
4365 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4366 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4367 are disregarded; all other signals are treated as usual; if 1 - normal
4369 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4370 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4371 disregarded; valid output is deasserted; all other signals are treated as
4372 usual; if 1 - normal activity. */
4373 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4374 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4375 input is disregarded; all other signals are treated as usual; if 1 -
4377 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4378 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4379 the initial credit value; read returns the current value of the credit
4380 counter. Must be initialized to 1 at start-up. */
4381 #define UCM_REG_CFC_INIT_CRD 0xe0204
4382 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4383 weight 8 (the most prioritised); 1 stands for weight 1(least
4384 prioritised); 2 stands for weight 2; tc. */
4385 #define UCM_REG_CP_WEIGHT 0xe00c4
4386 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4387 disregarded; acknowledge output is deasserted; all other signals are
4388 treated as usual; if 1 - normal activity. */
4389 #define UCM_REG_CSEM_IFEN 0xe0028
4390 /* [RC 1] Set when the message length mismatch (relative to last indication)
4391 at the csem interface is detected. */
4392 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4393 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4394 weight 8 (the most prioritised); 1 stands for weight 1(least
4395 prioritised); 2 stands for weight 2; tc. */
4396 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4397 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4398 disregarded; acknowledge output is deasserted; all other signals are
4399 treated as usual; if 1 - normal activity. */
4400 #define UCM_REG_DORQ_IFEN 0xe0030
4401 /* [RC 1] Set when the message length mismatch (relative to last indication)
4402 at the dorq interface is detected. */
4403 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4404 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4405 weight 8 (the most prioritised); 1 stands for weight 1(least
4406 prioritised); 2 stands for weight 2; tc. */
4407 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4408 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4409 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4410 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4411 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4412 /* [RW 8] The Event ID for Timers expiration. */
4413 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4414 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4415 writes the initial credit value; read returns the current value of the
4416 credit counter. Must be initialized to 64 at start-up. */
4417 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4418 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4419 writes the initial credit value; read returns the current value of the
4420 credit counter. Must be initialized to 64 at start-up. */
4421 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4422 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4423 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4424 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4425 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4426 #define UCM_REG_GR_ARB_TYPE 0xe0144
4427 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4428 highest priority is 3. It is supposed that the Store channel group is
4429 compliment to the others. */
4430 #define UCM_REG_GR_LD0_PR 0xe014c
4431 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4432 highest priority is 3. It is supposed that the Store channel group is
4433 compliment to the others. */
4434 #define UCM_REG_GR_LD1_PR 0xe0150
4435 /* [RW 2] The queue index for invalidate counter flag decision. */
4436 #define UCM_REG_INV_CFLG_Q 0xe00e4
4437 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4438 sent to STORM; for a specific connection type. the double REG-pairs are
4439 used in order to align to STORM context row size of 128 bits. The offset
4440 of these data in the STORM context is always 0. Index _i stands for the
4441 connection type (one of 16). */
4442 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4443 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4444 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4445 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4446 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4447 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4448 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4449 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4450 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4451 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4452 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4453 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4454 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4455 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4456 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4457 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4458 /* [RC 1] Set when the message length mismatch (relative to last indication)
4459 at the STORM interface is detected. */
4460 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4461 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4462 disregarded; acknowledge output is deasserted; all other signals are
4463 treated as usual; if 1 - normal activity. */
4464 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4465 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4466 weight 8 (the most prioritised); 1 stands for weight 1(least
4467 prioritised); 2 stands for weight 2; tc. */
4468 #define UCM_REG_STORM_WEIGHT 0xe00b0
4469 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4470 writes the initial credit value; read returns the current value of the
4471 credit counter. Must be initialized to 4 at start-up. */
4472 #define UCM_REG_TM_INIT_CRD 0xe021c
4473 /* [RW 28] The CM header for Timers expiration command. */
4474 #define UCM_REG_TM_UCM_HDR 0xe009c
4475 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4476 disregarded; acknowledge output is deasserted; all other signals are
4477 treated as usual; if 1 - normal activity. */
4478 #define UCM_REG_TM_UCM_IFEN 0xe001c
4479 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4480 weight 8 (the most prioritised); 1 stands for weight 1(least
4481 prioritised); 2 stands for weight 2; tc. */
4482 #define UCM_REG_TM_WEIGHT 0xe00d4
4483 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4484 disregarded; acknowledge output is deasserted; all other signals are
4485 treated as usual; if 1 - normal activity. */
4486 #define UCM_REG_TSEM_IFEN 0xe0024
4487 /* [RC 1] Set when the message length mismatch (relative to last indication)
4488 at the tsem interface is detected. */
4489 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4490 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4491 weight 8 (the most prioritised); 1 stands for weight 1(least
4492 prioritised); 2 stands for weight 2; tc. */
4493 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4494 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4495 acknowledge output is deasserted; all other signals are treated as usual;
4496 if 1 - normal activity. */
4497 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4498 /* [RW 11] Interrupt mask register #0 read/write */
4499 #define UCM_REG_UCM_INT_MASK 0xe01d4
4500 /* [R 11] Interrupt register #0 read */
4501 #define UCM_REG_UCM_INT_STS 0xe01c8
4502 /* [RW 27] Parity mask register #0 read/write */
4503 #define UCM_REG_UCM_PRTY_MASK 0xe01e4
4504 /* [R 27] Parity register #0 read */
4505 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4506 /* [RC 27] Parity register #0 read clear */
4507 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
4508 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4509 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4510 Is used to determine the number of the AG context REG-pairs written back;
4511 when the Reg1WbFlg isn't set. */
4512 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4513 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4514 disregarded; valid is deasserted; all other signals are treated as usual;
4515 if 1 - normal activity. */
4516 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4517 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4518 disregarded; valid is deasserted; all other signals are treated as usual;
4519 if 1 - normal activity. */
4520 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4521 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4522 disregarded; acknowledge output is deasserted; all other signals are
4523 treated as usual; if 1 - normal activity. */
4524 #define UCM_REG_UCM_TM_IFEN 0xe0020
4525 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4526 disregarded; valid is deasserted; all other signals are treated as usual;
4527 if 1 - normal activity. */
4528 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4529 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4530 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4531 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4532 the initial credit value; read returns the current value of the credit
4533 counter. Must be initialized to 32 at start-up. */
4534 #define UCM_REG_UQM_INIT_CRD 0xe0220
4535 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4536 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4537 prioritised); 2 stands for weight 2; tc. */
4538 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4539 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4540 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4541 prioritised); 2 stands for weight 2; tc. */
4542 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4543 /* [RW 28] The CM header value for QM request (primary). */
4544 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4545 /* [RW 28] The CM header value for QM request (secondary). */
4546 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4547 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4548 acknowledge output is deasserted; all other signals are treated as usual;
4549 if 1 - normal activity. */
4550 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4551 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4552 acknowledge output is deasserted; all other signals are treated as usual;
4553 if 1 - normal activity. */
4554 #define UCM_REG_USDM_IFEN 0xe0018
4555 /* [RC 1] Set when the message length mismatch (relative to last indication)
4556 at the SDM interface is detected. */
4557 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4558 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4559 weight 8 (the most prioritised); 1 stands for weight 1(least
4560 prioritised); 2 stands for weight 2; tc. */
4561 #define UCM_REG_USDM_WEIGHT 0xe00c8
4562 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4563 disregarded; acknowledge output is deasserted; all other signals are
4564 treated as usual; if 1 - normal activity. */
4565 #define UCM_REG_XSEM_IFEN 0xe002c
4566 /* [RC 1] Set when the message length mismatch (relative to last indication)
4567 at the xsem interface isdetected. */
4568 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4569 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4570 weight 8 (the most prioritised); 1 stands for weight 1(least
4571 prioritised); 2 stands for weight 2; tc. */
4572 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4573 /* [RW 20] Indirect access to the descriptor table of the XX protection
4574 mechanism. The fields are:[5:0] - message length; 14:6] - message
4575 pointer; 19:15] - next pointer. */
4576 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4577 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
4578 /* [R 6] Use to read the XX protection Free counter. */
4579 #define UCM_REG_XX_FREE 0xe016c
4580 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4581 of the Input Stage XX protection buffer by the XX protection pending
4582 messages. Write writes the initial credit value; read returns the current
4583 value of the credit counter. Must be initialized to 12 at start-up. */
4584 #define UCM_REG_XX_INIT_CRD 0xe0224
4585 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4586 protection. ~ucm_registers_xx_free.xx_free read on read. */
4587 #define UCM_REG_XX_MSG_NUM 0xe0228
4588 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4589 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4590 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4591 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4593 #define UCM_REG_XX_TABLE 0xe0300
4594 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
4595 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
4596 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
4597 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
4598 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
4599 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
4600 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
4601 #define UMAC_REG_COMMAND_CONFIG 0x8
4602 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
4603 * logic to check frames. */
4604 #define UMAC_REG_MAXFR 0x14
4605 /* [RW 8] The event id for aggregated interrupt 0 */
4606 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
4607 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
4608 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
4609 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
4610 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
4611 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
4612 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4613 or auto-mask-mode (1) */
4614 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
4615 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
4616 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
4617 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
4618 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
4619 /* [RW 1] The T bit for aggregated interrupt 5 */
4620 #define USDM_REG_AGG_INT_T_5 0xc40cc
4621 #define USDM_REG_AGG_INT_T_6 0xc40d0
4622 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4623 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4624 /* [RW 16] The maximum value of the completion counter #0 */
4625 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4626 /* [RW 16] The maximum value of the completion counter #1 */
4627 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4628 /* [RW 16] The maximum value of the completion counter #2 */
4629 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4630 /* [RW 16] The maximum value of the completion counter #3 */
4631 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4632 /* [RW 13] The start address in the internal RAM for the completion
4634 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4635 #define USDM_REG_ENABLE_IN1 0xc4238
4636 #define USDM_REG_ENABLE_IN2 0xc423c
4637 #define USDM_REG_ENABLE_OUT1 0xc4240
4638 #define USDM_REG_ENABLE_OUT2 0xc4244
4639 /* [RW 4] The initial number of messages that can be sent to the pxp control
4640 interface without receiving any ACK. */
4641 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4642 /* [ST 32] The number of ACK after placement messages received */
4643 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4644 /* [ST 32] The number of packet end messages received from the parser */
4645 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4646 /* [ST 32] The number of requests received from the pxp async if */
4647 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4648 /* [ST 32] The number of commands received in queue 0 */
4649 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4650 /* [ST 32] The number of commands received in queue 10 */
4651 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4652 /* [ST 32] The number of commands received in queue 11 */
4653 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4654 /* [ST 32] The number of commands received in queue 1 */
4655 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4656 /* [ST 32] The number of commands received in queue 2 */
4657 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4658 /* [ST 32] The number of commands received in queue 3 */
4659 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4660 /* [ST 32] The number of commands received in queue 4 */
4661 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4662 /* [ST 32] The number of commands received in queue 5 */
4663 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4664 /* [ST 32] The number of commands received in queue 6 */
4665 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4666 /* [ST 32] The number of commands received in queue 7 */
4667 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4668 /* [ST 32] The number of commands received in queue 8 */
4669 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4670 /* [ST 32] The number of commands received in queue 9 */
4671 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4672 /* [RW 13] The start address in the internal RAM for the packet end message */
4673 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4674 /* [RW 13] The start address in the internal RAM for queue counters */
4675 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4676 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4677 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4678 /* [R 1] parser fifo empty in sdm_sync block */
4679 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4680 /* [R 1] parser serial fifo empty in sdm_sync block */
4681 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4682 /* [RW 32] Tick for timer counter. Applicable only when
4683 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4684 #define USDM_REG_TIMER_TICK 0xc4000
4685 /* [RW 32] Interrupt mask register #0 read/write */
4686 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
4687 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
4688 /* [R 32] Interrupt register #0 read */
4689 #define USDM_REG_USDM_INT_STS_0 0xc4294
4690 #define USDM_REG_USDM_INT_STS_1 0xc42a4
4691 /* [RW 11] Parity mask register #0 read/write */
4692 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
4693 /* [R 11] Parity register #0 read */
4694 #define USDM_REG_USDM_PRTY_STS 0xc42b4
4695 /* [RC 11] Parity register #0 read clear */
4696 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
4697 /* [RW 5] The number of time_slots in the arbitration cycle */
4698 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
4699 /* [RW 3] The source that is associated with arbitration element 0. Source
4700 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4701 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4702 #define USEM_REG_ARB_ELEMENT0 0x300020
4703 /* [RW 3] The source that is associated with arbitration element 1. Source
4704 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4705 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4706 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4707 #define USEM_REG_ARB_ELEMENT1 0x300024
4708 /* [RW 3] The source that is associated with arbitration element 2. Source
4709 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4710 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4711 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4712 and ~usem_registers_arb_element1.arb_element1 */
4713 #define USEM_REG_ARB_ELEMENT2 0x300028
4714 /* [RW 3] The source that is associated with arbitration element 3. Source
4715 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4716 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4717 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4718 ~usem_registers_arb_element1.arb_element1 and
4719 ~usem_registers_arb_element2.arb_element2 */
4720 #define USEM_REG_ARB_ELEMENT3 0x30002c
4721 /* [RW 3] The source that is associated with arbitration element 4. Source
4722 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4723 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4724 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4725 and ~usem_registers_arb_element1.arb_element1 and
4726 ~usem_registers_arb_element2.arb_element2 and
4727 ~usem_registers_arb_element3.arb_element3 */
4728 #define USEM_REG_ARB_ELEMENT4 0x300030
4729 #define USEM_REG_ENABLE_IN 0x3000a4
4730 #define USEM_REG_ENABLE_OUT 0x3000a8
4731 /* [RW 32] This address space contains all registers and memories that are
4732 placed in SEM_FAST block. The SEM_FAST registers are described in
4733 appendix B. In order to access the sem_fast registers the base address
4734 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4735 #define USEM_REG_FAST_MEMORY 0x320000
4736 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4738 #define USEM_REG_FIC0_DISABLE 0x300224
4739 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4741 #define USEM_REG_FIC1_DISABLE 0x300234
4742 /* [RW 15] Interrupt table Read and write access to it is not possible in
4743 the middle of the work */
4744 #define USEM_REG_INT_TABLE 0x300400
4745 /* [ST 24] Statistics register. The number of messages that entered through
4747 #define USEM_REG_MSG_NUM_FIC0 0x300000
4748 /* [ST 24] Statistics register. The number of messages that entered through
4750 #define USEM_REG_MSG_NUM_FIC1 0x300004
4751 /* [ST 24] Statistics register. The number of messages that were sent to
4753 #define USEM_REG_MSG_NUM_FOC0 0x300008
4754 /* [ST 24] Statistics register. The number of messages that were sent to
4756 #define USEM_REG_MSG_NUM_FOC1 0x30000c
4757 /* [ST 24] Statistics register. The number of messages that were sent to
4759 #define USEM_REG_MSG_NUM_FOC2 0x300010
4760 /* [ST 24] Statistics register. The number of messages that were sent to
4762 #define USEM_REG_MSG_NUM_FOC3 0x300014
4763 /* [RW 1] Disables input messages from the passive buffer May be updated
4764 during run_time by the microcode */
4765 #define USEM_REG_PAS_DISABLE 0x30024c
4766 /* [WB 128] Debug only. Passive buffer memory */
4767 #define USEM_REG_PASSIVE_BUFFER 0x302000
4768 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4769 #define USEM_REG_PRAM 0x340000
4770 /* [R 16] Valid sleeping threads indication have bit per thread */
4771 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4772 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4773 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4774 /* [RW 16] List of free threads . There is a bit per thread. */
4775 #define USEM_REG_THREADS_LIST 0x3002e4
4776 /* [RW 3] The arbitration scheme of time_slot 0 */
4777 #define USEM_REG_TS_0_AS 0x300038
4778 /* [RW 3] The arbitration scheme of time_slot 10 */
4779 #define USEM_REG_TS_10_AS 0x300060
4780 /* [RW 3] The arbitration scheme of time_slot 11 */
4781 #define USEM_REG_TS_11_AS 0x300064
4782 /* [RW 3] The arbitration scheme of time_slot 12 */
4783 #define USEM_REG_TS_12_AS 0x300068
4784 /* [RW 3] The arbitration scheme of time_slot 13 */
4785 #define USEM_REG_TS_13_AS 0x30006c
4786 /* [RW 3] The arbitration scheme of time_slot 14 */
4787 #define USEM_REG_TS_14_AS 0x300070
4788 /* [RW 3] The arbitration scheme of time_slot 15 */
4789 #define USEM_REG_TS_15_AS 0x300074
4790 /* [RW 3] The arbitration scheme of time_slot 16 */
4791 #define USEM_REG_TS_16_AS 0x300078
4792 /* [RW 3] The arbitration scheme of time_slot 17 */
4793 #define USEM_REG_TS_17_AS 0x30007c
4794 /* [RW 3] The arbitration scheme of time_slot 18 */
4795 #define USEM_REG_TS_18_AS 0x300080
4796 /* [RW 3] The arbitration scheme of time_slot 1 */
4797 #define USEM_REG_TS_1_AS 0x30003c
4798 /* [RW 3] The arbitration scheme of time_slot 2 */
4799 #define USEM_REG_TS_2_AS 0x300040
4800 /* [RW 3] The arbitration scheme of time_slot 3 */
4801 #define USEM_REG_TS_3_AS 0x300044
4802 /* [RW 3] The arbitration scheme of time_slot 4 */
4803 #define USEM_REG_TS_4_AS 0x300048
4804 /* [RW 3] The arbitration scheme of time_slot 5 */
4805 #define USEM_REG_TS_5_AS 0x30004c
4806 /* [RW 3] The arbitration scheme of time_slot 6 */
4807 #define USEM_REG_TS_6_AS 0x300050
4808 /* [RW 3] The arbitration scheme of time_slot 7 */
4809 #define USEM_REG_TS_7_AS 0x300054
4810 /* [RW 3] The arbitration scheme of time_slot 8 */
4811 #define USEM_REG_TS_8_AS 0x300058
4812 /* [RW 3] The arbitration scheme of time_slot 9 */
4813 #define USEM_REG_TS_9_AS 0x30005c
4814 /* [RW 32] Interrupt mask register #0 read/write */
4815 #define USEM_REG_USEM_INT_MASK_0 0x300110
4816 #define USEM_REG_USEM_INT_MASK_1 0x300120
4817 /* [R 32] Interrupt register #0 read */
4818 #define USEM_REG_USEM_INT_STS_0 0x300104
4819 #define USEM_REG_USEM_INT_STS_1 0x300114
4820 /* [RW 32] Parity mask register #0 read/write */
4821 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
4822 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
4823 /* [R 32] Parity register #0 read */
4824 #define USEM_REG_USEM_PRTY_STS_0 0x300124
4825 #define USEM_REG_USEM_PRTY_STS_1 0x300134
4826 /* [RC 32] Parity register #0 read clear */
4827 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
4828 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
4829 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4830 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4831 #define USEM_REG_VFPF_ERR_NUM 0x300380
4832 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
4833 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
4834 #define VFC_REG_MEMORIES_RST 0x1943c
4835 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4836 * [12:8] of the address should be the offset within the accessed LCID
4837 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4838 * LCID100. The RBC address should be 13'ha64. */
4839 #define XCM_REG_AG_CTX 0x28000
4840 /* [RW 2] The queue index for registration on Aux1 counter flag. */
4841 #define XCM_REG_AUX1_Q 0x20134
4842 /* [RW 2] Per each decision rule the queue index to register to. */
4843 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4844 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4845 #define XCM_REG_CAM_OCCUP 0x20244
4846 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4847 disregarded; valid output is deasserted; all other signals are treated as
4848 usual; if 1 - normal activity. */
4849 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
4850 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4851 are disregarded; all other signals are treated as usual; if 1 - normal
4853 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
4854 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4855 disregarded; valid output is deasserted; all other signals are treated as
4856 usual; if 1 - normal activity. */
4857 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4858 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4859 input is disregarded; all other signals are treated as usual; if 1 -
4861 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
4862 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4863 the initial credit value; read returns the current value of the credit
4864 counter. Must be initialized to 1 at start-up. */
4865 #define XCM_REG_CFC_INIT_CRD 0x20404
4866 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4867 weight 8 (the most prioritised); 1 stands for weight 1(least
4868 prioritised); 2 stands for weight 2; tc. */
4869 #define XCM_REG_CP_WEIGHT 0x200dc
4870 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4871 disregarded; acknowledge output is deasserted; all other signals are
4872 treated as usual; if 1 - normal activity. */
4873 #define XCM_REG_CSEM_IFEN 0x20028
4874 /* [RC 1] Set at message length mismatch (relative to last indication) at
4875 the csem interface. */
4876 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
4877 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4878 weight 8 (the most prioritised); 1 stands for weight 1(least
4879 prioritised); 2 stands for weight 2; tc. */
4880 #define XCM_REG_CSEM_WEIGHT 0x200c4
4881 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4882 disregarded; acknowledge output is deasserted; all other signals are
4883 treated as usual; if 1 - normal activity. */
4884 #define XCM_REG_DORQ_IFEN 0x20030
4885 /* [RC 1] Set at message length mismatch (relative to last indication) at
4886 the dorq interface. */
4887 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
4888 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4889 weight 8 (the most prioritised); 1 stands for weight 1(least
4890 prioritised); 2 stands for weight 2; tc. */
4891 #define XCM_REG_DORQ_WEIGHT 0x200cc
4892 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4893 #define XCM_REG_ERR_EVNT_ID 0x200b0
4894 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4895 #define XCM_REG_ERR_XCM_HDR 0x200ac
4896 /* [RW 8] The Event ID for Timers expiration. */
4897 #define XCM_REG_EXPR_EVNT_ID 0x200b4
4898 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4899 writes the initial credit value; read returns the current value of the
4900 credit counter. Must be initialized to 64 at start-up. */
4901 #define XCM_REG_FIC0_INIT_CRD 0x2040c
4902 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4903 writes the initial credit value; read returns the current value of the
4904 credit counter. Must be initialized to 64 at start-up. */
4905 #define XCM_REG_FIC1_INIT_CRD 0x20410
4906 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4907 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
4908 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4909 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4910 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4911 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4912 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4913 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4914 #define XCM_REG_GR_ARB_TYPE 0x2020c
4915 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4916 highest priority is 3. It is supposed that the Channel group is the
4917 compliment of the other 3 groups. */
4918 #define XCM_REG_GR_LD0_PR 0x20214
4919 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4920 highest priority is 3. It is supposed that the Channel group is the
4921 compliment of the other 3 groups. */
4922 #define XCM_REG_GR_LD1_PR 0x20218
4923 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4924 disregarded; acknowledge output is deasserted; all other signals are
4925 treated as usual; if 1 - normal activity. */
4926 #define XCM_REG_NIG0_IFEN 0x20038
4927 /* [RC 1] Set at message length mismatch (relative to last indication) at
4928 the nig0 interface. */
4929 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
4930 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4931 weight 8 (the most prioritised); 1 stands for weight 1(least
4932 prioritised); 2 stands for weight 2; tc. */
4933 #define XCM_REG_NIG0_WEIGHT 0x200d4
4934 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4935 disregarded; acknowledge output is deasserted; all other signals are
4936 treated as usual; if 1 - normal activity. */
4937 #define XCM_REG_NIG1_IFEN 0x2003c
4938 /* [RC 1] Set at message length mismatch (relative to last indication) at
4939 the nig1 interface. */
4940 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4941 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4942 sent to STORM; for a specific connection type. The double REG-pairs are
4943 used in order to align to STORM context row size of 128 bits. The offset
4944 of these data in the STORM context is always 0. Index _i stands for the
4945 connection type (one of 16). */
4946 #define XCM_REG_N_SM_CTX_LD_0 0x20060
4947 #define XCM_REG_N_SM_CTX_LD_1 0x20064
4948 #define XCM_REG_N_SM_CTX_LD_2 0x20068
4949 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
4950 #define XCM_REG_N_SM_CTX_LD_4 0x20070
4951 #define XCM_REG_N_SM_CTX_LD_5 0x20074
4952 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4953 acknowledge output is deasserted; all other signals are treated as usual;
4954 if 1 - normal activity. */
4955 #define XCM_REG_PBF_IFEN 0x20034
4956 /* [RC 1] Set at message length mismatch (relative to last indication) at
4957 the pbf interface. */
4958 #define XCM_REG_PBF_LENGTH_MIS 0x20234
4959 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4960 weight 8 (the most prioritised); 1 stands for weight 1(least
4961 prioritised); 2 stands for weight 2; tc. */
4962 #define XCM_REG_PBF_WEIGHT 0x200d0
4963 #define XCM_REG_PHYS_QNUM3_0 0x20100
4964 #define XCM_REG_PHYS_QNUM3_1 0x20104
4965 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4966 #define XCM_REG_STOP_EVNT_ID 0x200b8
4967 /* [RC 1] Set at message length mismatch (relative to last indication) at
4968 the STORM interface. */
4969 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
4970 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4971 weight 8 (the most prioritised); 1 stands for weight 1(least
4972 prioritised); 2 stands for weight 2; tc. */
4973 #define XCM_REG_STORM_WEIGHT 0x200bc
4974 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4975 disregarded; acknowledge output is deasserted; all other signals are
4976 treated as usual; if 1 - normal activity. */
4977 #define XCM_REG_STORM_XCM_IFEN 0x20010
4978 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4979 writes the initial credit value; read returns the current value of the
4980 credit counter. Must be initialized to 4 at start-up. */
4981 #define XCM_REG_TM_INIT_CRD 0x2041c
4982 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4983 weight 8 (the most prioritised); 1 stands for weight 1(least
4984 prioritised); 2 stands for weight 2; tc. */
4985 #define XCM_REG_TM_WEIGHT 0x200ec
4986 /* [RW 28] The CM header for Timers expiration command. */
4987 #define XCM_REG_TM_XCM_HDR 0x200a8
4988 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4989 disregarded; acknowledge output is deasserted; all other signals are
4990 treated as usual; if 1 - normal activity. */
4991 #define XCM_REG_TM_XCM_IFEN 0x2001c
4992 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4993 disregarded; acknowledge output is deasserted; all other signals are
4994 treated as usual; if 1 - normal activity. */
4995 #define XCM_REG_TSEM_IFEN 0x20024
4996 /* [RC 1] Set at message length mismatch (relative to last indication) at
4997 the tsem interface. */
4998 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4999 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5000 weight 8 (the most prioritised); 1 stands for weight 1(least
5001 prioritised); 2 stands for weight 2; tc. */
5002 #define XCM_REG_TSEM_WEIGHT 0x200c0
5003 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5004 #define XCM_REG_UNA_GT_NXT_Q 0x20120
5005 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5006 disregarded; acknowledge output is deasserted; all other signals are
5007 treated as usual; if 1 - normal activity. */
5008 #define XCM_REG_USEM_IFEN 0x2002c
5009 /* [RC 1] Message length mismatch (relative to last indication) at the usem
5011 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
5012 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5013 weight 8 (the most prioritised); 1 stands for weight 1(least
5014 prioritised); 2 stands for weight 2; tc. */
5015 #define XCM_REG_USEM_WEIGHT 0x200c8
5016 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
5017 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
5018 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
5019 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
5020 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
5021 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
5022 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
5023 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
5024 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
5025 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
5026 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
5027 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
5028 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5029 acknowledge output is deasserted; all other signals are treated as usual;
5030 if 1 - normal activity. */
5031 #define XCM_REG_XCM_CFC_IFEN 0x20050
5032 /* [RW 14] Interrupt mask register #0 read/write */
5033 #define XCM_REG_XCM_INT_MASK 0x202b4
5034 /* [R 14] Interrupt register #0 read */
5035 #define XCM_REG_XCM_INT_STS 0x202a8
5036 /* [RW 30] Parity mask register #0 read/write */
5037 #define XCM_REG_XCM_PRTY_MASK 0x202c4
5038 /* [R 30] Parity register #0 read */
5039 #define XCM_REG_XCM_PRTY_STS 0x202b8
5040 /* [RC 30] Parity register #0 read clear */
5041 #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5043 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5044 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5045 Is used to determine the number of the AG context REG-pairs written back;
5046 when the Reg1WbFlg isn't set. */
5047 #define XCM_REG_XCM_REG0_SZ 0x200f4
5048 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5049 disregarded; valid is deasserted; all other signals are treated as usual;
5050 if 1 - normal activity. */
5051 #define XCM_REG_XCM_STORM0_IFEN 0x20004
5052 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5053 disregarded; valid is deasserted; all other signals are treated as usual;
5054 if 1 - normal activity. */
5055 #define XCM_REG_XCM_STORM1_IFEN 0x20008
5056 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5057 disregarded; acknowledge output is deasserted; all other signals are
5058 treated as usual; if 1 - normal activity. */
5059 #define XCM_REG_XCM_TM_IFEN 0x20020
5060 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5061 disregarded; valid is deasserted; all other signals are treated as usual;
5062 if 1 - normal activity. */
5063 #define XCM_REG_XCM_XQM_IFEN 0x2000c
5064 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5065 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
5066 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5067 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
5068 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5069 the initial credit value; read returns the current value of the credit
5070 counter. Must be initialized to 32 at start-up. */
5071 #define XCM_REG_XQM_INIT_CRD 0x20420
5072 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5073 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5074 prioritised); 2 stands for weight 2; tc. */
5075 #define XCM_REG_XQM_P_WEIGHT 0x200e4
5076 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5077 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5078 prioritised); 2 stands for weight 2; tc. */
5079 #define XCM_REG_XQM_S_WEIGHT 0x200e8
5080 /* [RW 28] The CM header value for QM request (primary). */
5081 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
5082 /* [RW 28] The CM header value for QM request (secondary). */
5083 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
5084 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5085 acknowledge output is deasserted; all other signals are treated as usual;
5086 if 1 - normal activity. */
5087 #define XCM_REG_XQM_XCM_IFEN 0x20014
5088 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5089 acknowledge output is deasserted; all other signals are treated as usual;
5090 if 1 - normal activity. */
5091 #define XCM_REG_XSDM_IFEN 0x20018
5092 /* [RC 1] Set at message length mismatch (relative to last indication) at
5093 the SDM interface. */
5094 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
5095 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5096 weight 8 (the most prioritised); 1 stands for weight 1(least
5097 prioritised); 2 stands for weight 2; tc. */
5098 #define XCM_REG_XSDM_WEIGHT 0x200e0
5099 /* [RW 17] Indirect access to the descriptor table of the XX protection
5100 mechanism. The fields are: [5:0] - message length; 11:6] - message
5101 pointer; 16:12] - next pointer. */
5102 #define XCM_REG_XX_DESCR_TABLE 0x20480
5103 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
5104 /* [R 6] Used to read the XX protection Free counter. */
5105 #define XCM_REG_XX_FREE 0x20240
5106 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
5107 of the Input Stage XX protection buffer by the XX protection pending
5108 messages. Max credit available - 3.Write writes the initial credit value;
5109 read returns the current value of the credit counter. Must be initialized
5110 to 2 at start-up. */
5111 #define XCM_REG_XX_INIT_CRD 0x20424
5112 /* [RW 6] The maximum number of pending messages; which may be stored in XX
5113 protection. ~xcm_registers_xx_free.xx_free read on read. */
5114 #define XCM_REG_XX_MSG_NUM 0x20428
5115 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5116 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
5117 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5118 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5119 #define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3)
5120 #define XMAC_CTRL_REG_RX_EN (0x1<<1)
5121 #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5122 #define XMAC_CTRL_REG_TX_EN (0x1<<0)
5123 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5124 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5125 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5126 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5127 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5128 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5129 #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5130 #define XMAC_REG_CTRL 0
5131 #define XMAC_REG_PAUSE_CTRL 0x68
5132 #define XMAC_REG_PFC_CTRL 0x70
5133 #define XMAC_REG_PFC_CTRL_HI 0x74
5134 #define XMAC_REG_RX_LSS_STATUS 0x58
5135 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5136 * CRC in strip mode */
5137 #define XMAC_REG_RX_MAX_SIZE 0x40
5138 #define XMAC_REG_TX_CTRL 0x20
5139 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5140 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5142 #define XCM_REG_XX_TABLE 0x20500
5143 /* [RW 8] The event id for aggregated interrupt 0 */
5144 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
5145 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
5146 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
5147 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
5148 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
5149 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
5150 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
5151 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
5152 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
5153 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
5154 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
5155 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
5156 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
5157 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
5158 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
5159 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5160 or auto-mask-mode (1) */
5161 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
5162 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
5163 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5164 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
5165 /* [RW 16] The maximum value of the completion counter #0 */
5166 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
5167 /* [RW 16] The maximum value of the completion counter #1 */
5168 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
5169 /* [RW 16] The maximum value of the completion counter #2 */
5170 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
5171 /* [RW 16] The maximum value of the completion counter #3 */
5172 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
5173 /* [RW 13] The start address in the internal RAM for the completion
5175 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
5176 #define XSDM_REG_ENABLE_IN1 0x166238
5177 #define XSDM_REG_ENABLE_IN2 0x16623c
5178 #define XSDM_REG_ENABLE_OUT1 0x166240
5179 #define XSDM_REG_ENABLE_OUT2 0x166244
5180 /* [RW 4] The initial number of messages that can be sent to the pxp control
5181 interface without receiving any ACK. */
5182 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
5183 /* [ST 32] The number of ACK after placement messages received */
5184 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
5185 /* [ST 32] The number of packet end messages received from the parser */
5186 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
5187 /* [ST 32] The number of requests received from the pxp async if */
5188 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
5189 /* [ST 32] The number of commands received in queue 0 */
5190 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
5191 /* [ST 32] The number of commands received in queue 10 */
5192 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
5193 /* [ST 32] The number of commands received in queue 11 */
5194 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
5195 /* [ST 32] The number of commands received in queue 1 */
5196 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
5197 /* [ST 32] The number of commands received in queue 3 */
5198 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
5199 /* [ST 32] The number of commands received in queue 4 */
5200 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
5201 /* [ST 32] The number of commands received in queue 5 */
5202 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
5203 /* [ST 32] The number of commands received in queue 6 */
5204 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
5205 /* [ST 32] The number of commands received in queue 7 */
5206 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
5207 /* [ST 32] The number of commands received in queue 8 */
5208 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5209 /* [ST 32] The number of commands received in queue 9 */
5210 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
5211 /* [RW 13] The start address in the internal RAM for queue counters */
5212 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
5213 /* [W 17] Generate an operation after completion; bit-16 is
5214 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5215 * bits 4:0 are the T124Param[4:0] */
5216 #define XSDM_REG_OPERATION_GEN 0x1664c4
5217 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5218 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5219 /* [R 1] parser fifo empty in sdm_sync block */
5220 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5221 /* [R 1] parser serial fifo empty in sdm_sync block */
5222 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5223 /* [RW 32] Tick for timer counter. Applicable only when
5224 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5225 #define XSDM_REG_TIMER_TICK 0x166000
5226 /* [RW 32] Interrupt mask register #0 read/write */
5227 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5228 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
5229 /* [R 32] Interrupt register #0 read */
5230 #define XSDM_REG_XSDM_INT_STS_0 0x166290
5231 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
5232 /* [RW 11] Parity mask register #0 read/write */
5233 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
5234 /* [R 11] Parity register #0 read */
5235 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
5236 /* [RC 11] Parity register #0 read clear */
5237 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
5238 /* [RW 5] The number of time_slots in the arbitration cycle */
5239 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5240 /* [RW 3] The source that is associated with arbitration element 0. Source
5241 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5242 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5243 #define XSEM_REG_ARB_ELEMENT0 0x280020
5244 /* [RW 3] The source that is associated with arbitration element 1. Source
5245 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5246 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5247 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5248 #define XSEM_REG_ARB_ELEMENT1 0x280024
5249 /* [RW 3] The source that is associated with arbitration element 2. Source
5250 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5251 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5252 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5253 and ~xsem_registers_arb_element1.arb_element1 */
5254 #define XSEM_REG_ARB_ELEMENT2 0x280028
5255 /* [RW 3] The source that is associated with arbitration element 3. Source
5256 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5257 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5258 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5259 ~xsem_registers_arb_element1.arb_element1 and
5260 ~xsem_registers_arb_element2.arb_element2 */
5261 #define XSEM_REG_ARB_ELEMENT3 0x28002c
5262 /* [RW 3] The source that is associated with arbitration element 4. Source
5263 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5264 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5265 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5266 and ~xsem_registers_arb_element1.arb_element1 and
5267 ~xsem_registers_arb_element2.arb_element2 and
5268 ~xsem_registers_arb_element3.arb_element3 */
5269 #define XSEM_REG_ARB_ELEMENT4 0x280030
5270 #define XSEM_REG_ENABLE_IN 0x2800a4
5271 #define XSEM_REG_ENABLE_OUT 0x2800a8
5272 /* [RW 32] This address space contains all registers and memories that are
5273 placed in SEM_FAST block. The SEM_FAST registers are described in
5274 appendix B. In order to access the sem_fast registers the base address
5275 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5276 #define XSEM_REG_FAST_MEMORY 0x2a0000
5277 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5279 #define XSEM_REG_FIC0_DISABLE 0x280224
5280 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5282 #define XSEM_REG_FIC1_DISABLE 0x280234
5283 /* [RW 15] Interrupt table Read and write access to it is not possible in
5284 the middle of the work */
5285 #define XSEM_REG_INT_TABLE 0x280400
5286 /* [ST 24] Statistics register. The number of messages that entered through
5288 #define XSEM_REG_MSG_NUM_FIC0 0x280000
5289 /* [ST 24] Statistics register. The number of messages that entered through
5291 #define XSEM_REG_MSG_NUM_FIC1 0x280004
5292 /* [ST 24] Statistics register. The number of messages that were sent to
5294 #define XSEM_REG_MSG_NUM_FOC0 0x280008
5295 /* [ST 24] Statistics register. The number of messages that were sent to
5297 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
5298 /* [ST 24] Statistics register. The number of messages that were sent to
5300 #define XSEM_REG_MSG_NUM_FOC2 0x280010
5301 /* [ST 24] Statistics register. The number of messages that were sent to
5303 #define XSEM_REG_MSG_NUM_FOC3 0x280014
5304 /* [RW 1] Disables input messages from the passive buffer May be updated
5305 during run_time by the microcode */
5306 #define XSEM_REG_PAS_DISABLE 0x28024c
5307 /* [WB 128] Debug only. Passive buffer memory */
5308 #define XSEM_REG_PASSIVE_BUFFER 0x282000
5309 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5310 #define XSEM_REG_PRAM 0x2c0000
5311 /* [R 16] Valid sleeping threads indication have bit per thread */
5312 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5313 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5314 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5315 /* [RW 16] List of free threads . There is a bit per thread. */
5316 #define XSEM_REG_THREADS_LIST 0x2802e4
5317 /* [RW 3] The arbitration scheme of time_slot 0 */
5318 #define XSEM_REG_TS_0_AS 0x280038
5319 /* [RW 3] The arbitration scheme of time_slot 10 */
5320 #define XSEM_REG_TS_10_AS 0x280060
5321 /* [RW 3] The arbitration scheme of time_slot 11 */
5322 #define XSEM_REG_TS_11_AS 0x280064
5323 /* [RW 3] The arbitration scheme of time_slot 12 */
5324 #define XSEM_REG_TS_12_AS 0x280068
5325 /* [RW 3] The arbitration scheme of time_slot 13 */
5326 #define XSEM_REG_TS_13_AS 0x28006c
5327 /* [RW 3] The arbitration scheme of time_slot 14 */
5328 #define XSEM_REG_TS_14_AS 0x280070
5329 /* [RW 3] The arbitration scheme of time_slot 15 */
5330 #define XSEM_REG_TS_15_AS 0x280074
5331 /* [RW 3] The arbitration scheme of time_slot 16 */
5332 #define XSEM_REG_TS_16_AS 0x280078
5333 /* [RW 3] The arbitration scheme of time_slot 17 */
5334 #define XSEM_REG_TS_17_AS 0x28007c
5335 /* [RW 3] The arbitration scheme of time_slot 18 */
5336 #define XSEM_REG_TS_18_AS 0x280080
5337 /* [RW 3] The arbitration scheme of time_slot 1 */
5338 #define XSEM_REG_TS_1_AS 0x28003c
5339 /* [RW 3] The arbitration scheme of time_slot 2 */
5340 #define XSEM_REG_TS_2_AS 0x280040
5341 /* [RW 3] The arbitration scheme of time_slot 3 */
5342 #define XSEM_REG_TS_3_AS 0x280044
5343 /* [RW 3] The arbitration scheme of time_slot 4 */
5344 #define XSEM_REG_TS_4_AS 0x280048
5345 /* [RW 3] The arbitration scheme of time_slot 5 */
5346 #define XSEM_REG_TS_5_AS 0x28004c
5347 /* [RW 3] The arbitration scheme of time_slot 6 */
5348 #define XSEM_REG_TS_6_AS 0x280050
5349 /* [RW 3] The arbitration scheme of time_slot 7 */
5350 #define XSEM_REG_TS_7_AS 0x280054
5351 /* [RW 3] The arbitration scheme of time_slot 8 */
5352 #define XSEM_REG_TS_8_AS 0x280058
5353 /* [RW 3] The arbitration scheme of time_slot 9 */
5354 #define XSEM_REG_TS_9_AS 0x28005c
5355 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5356 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5357 #define XSEM_REG_VFPF_ERR_NUM 0x280380
5358 /* [RW 32] Interrupt mask register #0 read/write */
5359 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5360 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5361 /* [R 32] Interrupt register #0 read */
5362 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5363 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5364 /* [RW 32] Parity mask register #0 read/write */
5365 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5366 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5367 /* [R 32] Parity register #0 read */
5368 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5369 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5370 /* [RC 32] Parity register #0 read clear */
5371 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5372 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5373 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5374 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5375 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5376 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5377 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
5378 #define MCPR_NVM_COMMAND_DONE (1L<<3)
5379 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
5380 #define MCPR_NVM_COMMAND_LAST (1L<<8)
5381 #define MCPR_NVM_COMMAND_WR (1L<<5)
5382 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5383 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5384 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5385 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5386 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5387 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5388 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5389 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5390 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5391 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5392 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5393 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5394 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5395 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5396 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5397 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5398 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5399 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
5400 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5401 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
5402 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5403 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5404 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
5405 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5406 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5407 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
5408 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
5409 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
5410 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
5411 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
5412 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
5413 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
5414 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
5415 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
5416 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5417 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
5418 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
5419 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5420 #define EMAC_LED_OVERRIDE (1L<<0)
5421 #define EMAC_LED_TRAFFIC (1L<<6)
5422 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5423 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
5424 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5425 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
5426 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5427 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5428 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5429 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5430 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5431 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5432 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5433 #define EMAC_MODE_25G_MODE (1L<<5)
5434 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
5435 #define EMAC_MODE_PORT_GMII (2L<<2)
5436 #define EMAC_MODE_PORT_MII (1L<<2)
5437 #define EMAC_MODE_PORT_MII_10M (3L<<2)
5438 #define EMAC_MODE_RESET (1L<<0)
5439 #define EMAC_REG_EMAC_LED 0xc
5440 #define EMAC_REG_EMAC_MAC_MATCH 0x10
5441 #define EMAC_REG_EMAC_MDIO_COMM 0xac
5442 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5443 #define EMAC_REG_EMAC_MODE 0x0
5444 #define EMAC_REG_EMAC_RX_MODE 0xc8
5445 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5446 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5447 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5448 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5449 #define EMAC_REG_EMAC_TX_MODE 0xbc
5450 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5451 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5452 #define EMAC_REG_RX_PFC_MODE 0x320
5453 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5454 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5455 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5456 #define EMAC_REG_RX_PFC_PARAM 0x324
5457 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5458 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5459 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5460 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5461 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5462 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5463 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5464 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5465 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5466 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
5467 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5468 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
5469 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5470 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5471 #define EMAC_RX_MODE_RESET (1L<<0)
5472 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5473 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5474 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5475 #define EMAC_TX_MODE_RESET (1L<<0)
5476 #define MISC_REGISTERS_GPIO_0 0
5477 #define MISC_REGISTERS_GPIO_1 1
5478 #define MISC_REGISTERS_GPIO_2 2
5479 #define MISC_REGISTERS_GPIO_3 3
5480 #define MISC_REGISTERS_GPIO_CLR_POS 16
5481 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5482 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5483 #define MISC_REGISTERS_GPIO_HIGH 1
5484 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5485 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5486 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5487 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5488 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
5489 #define MISC_REGISTERS_GPIO_LOW 0
5490 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5491 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5492 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5493 #define MISC_REGISTERS_GPIO_SET_POS 8
5494 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5495 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
5496 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5497 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5498 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
5499 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5500 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5501 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
5502 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
5503 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5504 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5505 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5506 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5507 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5508 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
5509 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
5510 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5511 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5512 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5513 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
5514 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5515 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5516 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
5517 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
5518 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
5519 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5520 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5521 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5522 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5523 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5524 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5525 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5526 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5527 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5528 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5529 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5530 #define MISC_REGISTERS_SPIO_4 4
5531 #define MISC_REGISTERS_SPIO_5 5
5532 #define MISC_REGISTERS_SPIO_7 7
5533 #define MISC_REGISTERS_SPIO_CLR_POS 16
5534 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5535 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5536 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5537 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5538 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5539 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5540 #define MISC_REGISTERS_SPIO_SET_POS 8
5541 #define HW_LOCK_DRV_FLAGS 10
5542 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5543 #define HW_LOCK_RESOURCE_GPIO 1
5544 #define HW_LOCK_RESOURCE_MDIO 0
5545 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5546 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
5547 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
5548 #define HW_LOCK_RESOURCE_SPIO 2
5549 #define HW_LOCK_RESOURCE_UNDI 5
5550 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5551 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5552 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
5553 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
5554 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
5555 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
5556 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
5557 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
5558 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
5559 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
5560 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
5561 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
5562 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
5563 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
5564 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
5565 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
5566 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
5567 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
5568 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
5569 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
5570 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
5571 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
5572 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
5573 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
5574 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
5575 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
5576 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
5577 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
5578 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
5579 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
5580 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
5581 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5582 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5583 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
5584 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
5585 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
5586 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
5587 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
5588 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
5589 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
5590 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
5591 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
5592 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
5593 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
5594 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
5595 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
5596 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
5597 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
5598 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
5599 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
5600 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
5601 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
5602 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
5603 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
5604 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
5605 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
5606 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
5607 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
5608 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
5609 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
5610 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
5611 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
5612 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
5613 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
5615 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
5616 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
5618 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
5620 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
5621 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5623 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
5624 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
5625 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
5626 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
5627 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
5628 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
5629 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
5630 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
5631 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
5632 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
5633 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
5634 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
5635 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
5636 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
5637 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
5638 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
5640 /* storm asserts attention bits */
5641 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5642 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5643 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5644 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5646 /* mcp error attention bit */
5647 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5649 /*E1H NIG status sync attention mapped to group 4-7*/
5650 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5651 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5652 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5653 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5654 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5655 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5656 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5657 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5660 #define LATCHED_ATTN_RBCR 23
5661 #define LATCHED_ATTN_RBCT 24
5662 #define LATCHED_ATTN_RBCN 25
5663 #define LATCHED_ATTN_RBCU 26
5664 #define LATCHED_ATTN_RBCP 27
5665 #define LATCHED_ATTN_TIMEOUT_GRC 28
5666 #define LATCHED_ATTN_RSVD_GRC 29
5667 #define LATCHED_ATTN_ROM_PARITY_MCP 30
5668 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5669 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5670 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5672 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5673 #define GENERAL_ATTEN_OFFSET(atten_name)\
5674 (1UL << ((94 + atten_name) % 32))
5676 * This file defines GRC base address for every block.
5677 * This file is included by chipsim, asm microcode and cpp microcode.
5678 * These values are used in Design.xml on regBase attribute
5679 * Use the base with the generated offsets of specific registers.
5682 #define GRCBASE_PXPCS 0x000000
5683 #define GRCBASE_PCICONFIG 0x002000
5684 #define GRCBASE_PCIREG 0x002400
5685 #define GRCBASE_EMAC0 0x008000
5686 #define GRCBASE_EMAC1 0x008400
5687 #define GRCBASE_DBU 0x008800
5688 #define GRCBASE_MISC 0x00A000
5689 #define GRCBASE_DBG 0x00C000
5690 #define GRCBASE_NIG 0x010000
5691 #define GRCBASE_XCM 0x020000
5692 #define GRCBASE_PRS 0x040000
5693 #define GRCBASE_SRCH 0x040400
5694 #define GRCBASE_TSDM 0x042000
5695 #define GRCBASE_TCM 0x050000
5696 #define GRCBASE_BRB1 0x060000
5697 #define GRCBASE_MCP 0x080000
5698 #define GRCBASE_UPB 0x0C1000
5699 #define GRCBASE_CSDM 0x0C2000
5700 #define GRCBASE_USDM 0x0C4000
5701 #define GRCBASE_CCM 0x0D0000
5702 #define GRCBASE_UCM 0x0E0000
5703 #define GRCBASE_CDU 0x101000
5704 #define GRCBASE_DMAE 0x102000
5705 #define GRCBASE_PXP 0x103000
5706 #define GRCBASE_CFC 0x104000
5707 #define GRCBASE_HC 0x108000
5708 #define GRCBASE_PXP2 0x120000
5709 #define GRCBASE_PBF 0x140000
5710 #define GRCBASE_UMAC0 0x160000
5711 #define GRCBASE_UMAC1 0x160400
5712 #define GRCBASE_XPB 0x161000
5713 #define GRCBASE_MSTAT0 0x162000
5714 #define GRCBASE_MSTAT1 0x162800
5715 #define GRCBASE_XMAC0 0x163000
5716 #define GRCBASE_XMAC1 0x163800
5717 #define GRCBASE_TIMERS 0x164000
5718 #define GRCBASE_XSDM 0x166000
5719 #define GRCBASE_QM 0x168000
5720 #define GRCBASE_DQ 0x170000
5721 #define GRCBASE_TSEM 0x180000
5722 #define GRCBASE_CSEM 0x200000
5723 #define GRCBASE_XSEM 0x280000
5724 #define GRCBASE_USEM 0x300000
5725 #define GRCBASE_MISC_AEU GRCBASE_MISC
5728 /* offset of configuration space in the pci core register */
5729 #define PCICFG_OFFSET 0x2000
5730 #define PCICFG_VENDOR_ID_OFFSET 0x00
5731 #define PCICFG_DEVICE_ID_OFFSET 0x02
5732 #define PCICFG_COMMAND_OFFSET 0x04
5733 #define PCICFG_COMMAND_IO_SPACE (1<<0)
5734 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
5735 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
5736 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5737 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5738 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5739 #define PCICFG_COMMAND_PERR_ENA (1<<6)
5740 #define PCICFG_COMMAND_STEPPING (1<<7)
5741 #define PCICFG_COMMAND_SERR_ENA (1<<8)
5742 #define PCICFG_COMMAND_FAST_B2B (1<<9)
5743 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
5744 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
5745 #define PCICFG_STATUS_OFFSET 0x06
5746 #define PCICFG_REVESION_ID_OFFSET 0x08
5747 #define PCICFG_CACHE_LINE_SIZE 0x0c
5748 #define PCICFG_LATENCY_TIMER 0x0d
5749 #define PCICFG_BAR_1_LOW 0x10
5750 #define PCICFG_BAR_1_HIGH 0x14
5751 #define PCICFG_BAR_2_LOW 0x18
5752 #define PCICFG_BAR_2_HIGH 0x1c
5753 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5754 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5755 #define PCICFG_INT_LINE 0x3c
5756 #define PCICFG_INT_PIN 0x3d
5757 #define PCICFG_PM_CAPABILITY 0x48
5758 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5759 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5760 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5761 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
5762 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5763 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5764 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5765 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5766 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5767 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5768 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5769 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5770 #define PCICFG_PM_CSR_OFFSET 0x4c
5771 #define PCICFG_PM_CSR_STATE (0x3<<0)
5772 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5773 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
5774 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
5775 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5776 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5777 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5778 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5779 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5780 #define PCICFG_GRC_ADDRESS 0x78
5781 #define PCICFG_GRC_DATA 0x80
5782 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
5783 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5784 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5785 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5786 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5788 #define PCICFG_DEVICE_CONTROL 0xb4
5789 #define PCICFG_DEVICE_STATUS 0xb6
5790 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5791 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5792 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5793 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5794 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5795 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
5796 #define PCICFG_LINK_CONTROL 0xbc
5799 #define BAR_USTRORM_INTMEM 0x400000
5800 #define BAR_CSTRORM_INTMEM 0x410000
5801 #define BAR_XSTRORM_INTMEM 0x420000
5802 #define BAR_TSTRORM_INTMEM 0x430000
5804 /* for accessing the IGU in case of status block ACK */
5805 #define BAR_IGU_INTMEM 0x440000
5807 #define BAR_DOORBELL_OFFSET 0x800000
5809 #define BAR_ME_REGISTER 0x450000
5811 /* config_2 offset */
5812 #define GRC_CONFIG_2_SIZE_REG 0x408
5813 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5814 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5815 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5816 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5817 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5818 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5819 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5820 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5821 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5822 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5823 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5824 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5825 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5826 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5827 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5828 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5829 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5830 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5831 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5832 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5833 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5834 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5835 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5836 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5837 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5838 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5839 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5840 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5841 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5842 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5843 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5844 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5845 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5846 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5847 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5848 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5849 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5850 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5851 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5852 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5854 /* config_3 offset */
5855 #define GRC_CONFIG_3_SIZE_REG 0x40c
5856 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5857 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
5858 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
5859 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5860 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5861 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5862 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
5864 #define GRC_BAR2_CONFIG 0x4e0
5865 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5866 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5867 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5868 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5869 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5870 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5871 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5872 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5873 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5874 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5875 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5876 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5877 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5878 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5879 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5880 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5881 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5882 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5884 #define PCI_PM_DATA_A 0x410
5885 #define PCI_PM_DATA_B 0x414
5886 #define PCI_ID_VAL1 0x434
5887 #define PCI_ID_VAL2 0x438
5889 #define PXPCS_TL_CONTROL_5 0x814
5890 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
5891 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
5892 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
5893 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
5894 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
5895 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
5896 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
5897 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
5898 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
5899 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
5900 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
5901 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
5902 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
5903 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
5904 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
5905 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
5906 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
5907 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
5908 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
5909 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
5910 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
5911 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
5912 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
5913 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
5914 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
5915 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
5916 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
5917 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
5918 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
5919 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
5922 #define PXPCS_TL_FUNC345_STAT 0x854
5923 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
5924 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
5925 (1 << 28) /* Unsupported Request Error Status in function4, if \
5926 set, generate pcie_err_attn output when this error is seen. WC */
5927 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
5928 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
5929 generate pcie_err_attn output when this error is seen.. WC */
5930 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
5931 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
5932 generate pcie_err_attn output when this error is seen.. WC */
5933 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
5934 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
5935 set, generate pcie_err_attn output when this error is seen.. WC \
5937 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
5938 (1 << 24) /* Unexpected Completion Status Status in function 4, \
5939 if set, generate pcie_err_attn output when this error is seen. WC \
5941 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
5942 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
5943 pcie_err_attn output when this error is seen. WC */
5944 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
5945 (1 << 22) /* Completer Timeout Status Status in function 4, if \
5946 set, generate pcie_err_attn output when this error is seen. WC */
5947 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
5948 (1 << 21) /* Flow Control Protocol Error Status Status in \
5949 function 4, if set, generate pcie_err_attn output when this error \
5951 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
5952 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
5953 generate pcie_err_attn output when this error is seen.. WC */
5954 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
5955 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
5956 (1 << 18) /* Unsupported Request Error Status in function3, if \
5957 set, generate pcie_err_attn output when this error is seen. WC */
5958 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
5959 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
5960 generate pcie_err_attn output when this error is seen.. WC */
5961 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
5962 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
5963 generate pcie_err_attn output when this error is seen.. WC */
5964 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
5965 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
5966 set, generate pcie_err_attn output when this error is seen.. WC \
5968 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
5969 (1 << 14) /* Unexpected Completion Status Status in function 3, \
5970 if set, generate pcie_err_attn output when this error is seen. WC \
5972 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
5973 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
5974 pcie_err_attn output when this error is seen. WC */
5975 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
5976 (1 << 12) /* Completer Timeout Status Status in function 3, if \
5977 set, generate pcie_err_attn output when this error is seen. WC */
5978 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
5979 (1 << 11) /* Flow Control Protocol Error Status Status in \
5980 function 3, if set, generate pcie_err_attn output when this error \
5982 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
5983 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
5984 generate pcie_err_attn output when this error is seen.. WC */
5985 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
5986 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
5987 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
5988 set, generate pcie_err_attn output when this error is seen. WC */
5989 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
5990 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
5991 generate pcie_err_attn output when this error is seen.. WC */
5992 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
5993 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
5994 generate pcie_err_attn output when this error is seen.. WC */
5995 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
5996 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
5997 set, generate pcie_err_attn output when this error is seen.. WC \
5999 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
6000 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
6001 if set, generate pcie_err_attn output when this error is seen. WC \
6003 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
6004 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6005 pcie_err_attn output when this error is seen. WC */
6006 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
6007 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
6008 set, generate pcie_err_attn output when this error is seen. WC */
6009 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
6010 (1 << 1) /* Flow Control Protocol Error Status Status for \
6011 Function 2, if set, generate pcie_err_attn output when this error \
6013 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
6014 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6015 generate pcie_err_attn output when this error is seen.. WC */
6018 #define PXPCS_TL_FUNC678_STAT 0x85C
6019 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
6020 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
6021 (1 << 28) /* Unsupported Request Error Status in function7, if \
6022 set, generate pcie_err_attn output when this error is seen. WC */
6023 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
6024 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
6025 generate pcie_err_attn output when this error is seen.. WC */
6026 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
6027 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
6028 generate pcie_err_attn output when this error is seen.. WC */
6029 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
6030 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
6031 set, generate pcie_err_attn output when this error is seen.. WC \
6033 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
6034 (1 << 24) /* Unexpected Completion Status Status in function 7, \
6035 if set, generate pcie_err_attn output when this error is seen. WC \
6037 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
6038 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
6039 pcie_err_attn output when this error is seen. WC */
6040 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
6041 (1 << 22) /* Completer Timeout Status Status in function 7, if \
6042 set, generate pcie_err_attn output when this error is seen. WC */
6043 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
6044 (1 << 21) /* Flow Control Protocol Error Status Status in \
6045 function 7, if set, generate pcie_err_attn output when this error \
6047 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
6048 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
6049 generate pcie_err_attn output when this error is seen.. WC */
6050 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
6051 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
6052 (1 << 18) /* Unsupported Request Error Status in function6, if \
6053 set, generate pcie_err_attn output when this error is seen. WC */
6054 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
6055 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
6056 generate pcie_err_attn output when this error is seen.. WC */
6057 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
6058 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
6059 generate pcie_err_attn output when this error is seen.. WC */
6060 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
6061 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
6062 set, generate pcie_err_attn output when this error is seen.. WC \
6064 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
6065 (1 << 14) /* Unexpected Completion Status Status in function 6, \
6066 if set, generate pcie_err_attn output when this error is seen. WC \
6068 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
6069 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
6070 pcie_err_attn output when this error is seen. WC */
6071 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
6072 (1 << 12) /* Completer Timeout Status Status in function 6, if \
6073 set, generate pcie_err_attn output when this error is seen. WC */
6074 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
6075 (1 << 11) /* Flow Control Protocol Error Status Status in \
6076 function 6, if set, generate pcie_err_attn output when this error \
6078 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
6079 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
6080 generate pcie_err_attn output when this error is seen.. WC */
6081 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
6082 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
6083 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
6084 set, generate pcie_err_attn output when this error is seen. WC */
6085 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
6086 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
6087 generate pcie_err_attn output when this error is seen.. WC */
6088 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
6089 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
6090 generate pcie_err_attn output when this error is seen.. WC */
6091 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
6092 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
6093 set, generate pcie_err_attn output when this error is seen.. WC \
6095 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
6096 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
6097 if set, generate pcie_err_attn output when this error is seen. WC \
6099 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
6100 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6101 pcie_err_attn output when this error is seen. WC */
6102 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
6103 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
6104 set, generate pcie_err_attn output when this error is seen. WC */
6105 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
6106 (1 << 1) /* Flow Control Protocol Error Status Status for \
6107 Function 5, if set, generate pcie_err_attn output when this error \
6109 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
6110 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6111 generate pcie_err_attn output when this error is seen.. WC */
6114 #define BAR_USTRORM_INTMEM 0x400000
6115 #define BAR_CSTRORM_INTMEM 0x410000
6116 #define BAR_XSTRORM_INTMEM 0x420000
6117 #define BAR_TSTRORM_INTMEM 0x430000
6119 /* for accessing the IGU in case of status block ACK */
6120 #define BAR_IGU_INTMEM 0x440000
6122 #define BAR_DOORBELL_OFFSET 0x800000
6124 #define BAR_ME_REGISTER 0x450000
6125 #define ME_REG_PF_NUM_SHIFT 0
6126 #define ME_REG_PF_NUM\
6127 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
6128 #define ME_REG_VF_VALID (1<<8)
6129 #define ME_REG_VF_NUM_SHIFT 9
6130 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
6131 #define ME_REG_VF_ERR (0x1<<3)
6132 #define ME_REG_ABS_PF_NUM_SHIFT 16
6133 #define ME_REG_ABS_PF_NUM\
6134 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
6137 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
6138 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
6139 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
6140 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6141 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
6143 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
6144 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
6145 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
6146 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
6147 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
6148 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
6149 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
6150 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
6151 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
6152 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
6153 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
6154 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
6155 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
6156 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
6157 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
6158 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
6160 #define MDIO_REG_BANK_RX0 0x80b0
6161 #define MDIO_RX0_RX_STATUS 0x10
6162 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
6163 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
6164 #define MDIO_RX0_RX_EQ_BOOST 0x1c
6165 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6166 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
6168 #define MDIO_REG_BANK_RX1 0x80c0
6169 #define MDIO_RX1_RX_EQ_BOOST 0x1c
6170 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6171 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
6173 #define MDIO_REG_BANK_RX2 0x80d0
6174 #define MDIO_RX2_RX_EQ_BOOST 0x1c
6175 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6176 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
6178 #define MDIO_REG_BANK_RX3 0x80e0
6179 #define MDIO_RX3_RX_EQ_BOOST 0x1c
6180 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6181 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
6183 #define MDIO_REG_BANK_RX_ALL 0x80f0
6184 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
6185 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6186 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
6188 #define MDIO_REG_BANK_TX0 0x8060
6189 #define MDIO_TX0_TX_DRIVER 0x17
6190 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6191 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6192 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6193 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6194 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6195 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6196 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6197 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6198 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6200 #define MDIO_REG_BANK_TX1 0x8070
6201 #define MDIO_TX1_TX_DRIVER 0x17
6202 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6203 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6204 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6205 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6206 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6207 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6208 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6209 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6210 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6212 #define MDIO_REG_BANK_TX2 0x8080
6213 #define MDIO_TX2_TX_DRIVER 0x17
6214 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6215 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6216 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6217 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6218 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6219 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6220 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6221 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6222 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6224 #define MDIO_REG_BANK_TX3 0x8090
6225 #define MDIO_TX3_TX_DRIVER 0x17
6226 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6227 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6228 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6229 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6230 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6231 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6232 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6233 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6234 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6236 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
6237 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
6239 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
6240 #define MDIO_BLOCK1_LANE_CTRL0 0x15
6241 #define MDIO_BLOCK1_LANE_CTRL1 0x16
6242 #define MDIO_BLOCK1_LANE_CTRL2 0x17
6243 #define MDIO_BLOCK1_LANE_PRBS 0x19
6245 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6246 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6247 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6248 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
6249 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
6250 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
6251 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
6252 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6253 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
6254 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
6256 #define MDIO_REG_BANK_GP_STATUS 0x8120
6257 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6258 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6259 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6260 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6261 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6262 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6263 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6264 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6265 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6266 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6267 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6268 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6269 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6270 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6271 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6272 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6273 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6274 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6275 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6276 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6277 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6278 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6279 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6280 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6281 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
6282 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6283 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6284 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6285 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
6288 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
6289 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6290 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
6291 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6292 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6293 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6294 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
6296 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
6297 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6298 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6299 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6300 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6301 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6302 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6303 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6304 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6305 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6306 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6307 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
6308 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6309 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
6310 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6311 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
6312 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
6313 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
6314 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
6315 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
6316 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
6317 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
6318 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
6319 #define MDIO_SERDES_DIGITAL_MISC1 0x18
6320 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
6321 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
6322 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
6323 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
6324 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
6325 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
6326 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
6327 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
6328 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
6329 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
6330 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
6331 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
6332 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
6333 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
6334 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
6335 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
6336 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
6337 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
6339 #define MDIO_REG_BANK_OVER_1G 0x8320
6340 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
6341 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
6342 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
6343 #define MDIO_OVER_1G_UP1 0x19
6344 #define MDIO_OVER_1G_UP1_2_5G 0x0001
6345 #define MDIO_OVER_1G_UP1_5G 0x0002
6346 #define MDIO_OVER_1G_UP1_6G 0x0004
6347 #define MDIO_OVER_1G_UP1_10G 0x0010
6348 #define MDIO_OVER_1G_UP1_10GH 0x0008
6349 #define MDIO_OVER_1G_UP1_12G 0x0020
6350 #define MDIO_OVER_1G_UP1_12_5G 0x0040
6351 #define MDIO_OVER_1G_UP1_13G 0x0080
6352 #define MDIO_OVER_1G_UP1_15G 0x0100
6353 #define MDIO_OVER_1G_UP1_16G 0x0200
6354 #define MDIO_OVER_1G_UP2 0x1A
6355 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
6356 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
6357 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
6358 #define MDIO_OVER_1G_UP3 0x1B
6359 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
6360 #define MDIO_OVER_1G_LP_UP1 0x1C
6361 #define MDIO_OVER_1G_LP_UP2 0x1D
6362 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
6363 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
6364 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
6365 #define MDIO_OVER_1G_LP_UP3 0x1E
6367 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
6368 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
6369 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
6370 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
6372 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
6373 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
6374 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
6375 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
6377 #define MDIO_REG_BANK_CL73_USERB0 0x8370
6378 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
6379 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
6380 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
6381 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
6382 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
6383 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
6384 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
6385 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
6386 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
6387 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
6388 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
6390 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
6391 #define MDIO_AER_BLOCK_AER_REG 0x1E
6393 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
6394 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
6395 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
6396 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
6397 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
6398 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
6399 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
6400 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
6401 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
6402 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
6403 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
6404 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
6405 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
6406 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
6407 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
6408 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
6409 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
6410 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
6411 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
6412 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
6413 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
6414 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
6415 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
6416 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
6417 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
6418 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
6419 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
6420 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
6421 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
6422 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
6423 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
6424 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6425 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6426 Theotherbitsarereservedandshouldbezero*/
6427 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
6430 #define MDIO_PMA_DEVAD 0x1
6432 #define MDIO_PMA_REG_CTRL 0x0
6433 #define MDIO_PMA_REG_STATUS 0x1
6434 #define MDIO_PMA_REG_10G_CTRL2 0x7
6435 #define MDIO_PMA_REG_RX_SD 0xa
6437 #define MDIO_PMA_REG_BCM_CTRL 0x0096
6438 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
6439 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
6440 #define MDIO_PMA_REG_TX_ALARM_CTRL 0x9001
6441 #define MDIO_PMA_REG_LASI_CTRL 0x9002
6442 #define MDIO_PMA_REG_RX_ALARM 0x9003
6443 #define MDIO_PMA_REG_TX_ALARM 0x9004
6444 #define MDIO_PMA_REG_LASI_STATUS 0x9005
6445 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6446 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6447 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
6448 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
6449 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
6450 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
6451 #define MDIO_PMA_REG_GEN_CTRL 0xca10
6452 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
6453 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
6454 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
6455 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
6456 #define MDIO_PMA_REG_ROM_VER1 0xca19
6457 #define MDIO_PMA_REG_ROM_VER2 0xca1a
6458 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
6459 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
6460 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
6461 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
6462 #define MDIO_PMA_REG_LRM_MODE 0xca3f
6463 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
6464 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
6466 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
6467 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
6468 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
6469 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
6470 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
6471 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
6472 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
6473 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
6474 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6475 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6476 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6477 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6479 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6480 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6481 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
6482 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6483 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6484 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6485 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
6486 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
6487 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
6489 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
6491 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6492 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6493 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
6494 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
6496 #define MDIO_PMA_REG_7101_RESET 0xc000
6497 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
6498 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
6499 #define MDIO_PMA_REG_7101_VER1 0xc026
6500 #define MDIO_PMA_REG_7101_VER2 0xc027
6502 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6503 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6504 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6505 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6506 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6507 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6508 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6509 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6510 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6511 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
6514 #define MDIO_WIS_DEVAD 0x2
6516 #define MDIO_WIS_REG_LASI_CNTL 0x9002
6517 #define MDIO_WIS_REG_LASI_STATUS 0x9005
6519 #define MDIO_PCS_DEVAD 0x3
6520 #define MDIO_PCS_REG_STATUS 0x0020
6521 #define MDIO_PCS_REG_LASI_STATUS 0x9005
6522 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6523 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6524 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6525 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6526 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6527 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6528 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
6529 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6530 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6533 #define MDIO_XS_DEVAD 0x4
6534 #define MDIO_XS_PLL_SEQUENCER 0x8000
6535 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
6537 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
6538 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
6539 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
6540 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
6541 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
6543 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
6545 #define MDIO_AN_DEVAD 0x7
6547 #define MDIO_AN_REG_CTRL 0x0000
6548 #define MDIO_AN_REG_STATUS 0x0001
6549 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
6550 #define MDIO_AN_REG_ADV_PAUSE 0x0010
6551 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
6552 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
6553 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
6554 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
6555 #define MDIO_AN_REG_ADV 0x0011
6556 #define MDIO_AN_REG_ADV2 0x0012
6557 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
6558 #define MDIO_AN_REG_MASTER_STATUS 0x0021
6560 #define MDIO_AN_REG_LINK_STATUS 0x8304
6561 #define MDIO_AN_REG_CL37_CL73 0x8370
6562 #define MDIO_AN_REG_CL37_AN 0xffe0
6563 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
6564 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
6566 #define MDIO_AN_REG_8073_2_5G 0x8329
6567 #define MDIO_AN_REG_8073_BAM 0x8350
6569 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
6570 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
6571 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
6572 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
6573 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
6574 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6575 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6576 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
6577 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
6578 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
6581 #define MDIO_CTL_DEVAD 0x1e
6582 #define MDIO_CTL_REG_84823_MEDIA 0x401a
6583 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
6584 /* These pins configure the BCM84823 interface to MAC after reset. */
6585 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
6586 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
6587 /* These pins configure the BCM84823 interface to Line after reset. */
6588 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
6589 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
6590 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
6591 /* When this pin is active high during reset, 10GBASE-T core is power
6592 * down, When it is active low the 10GBASE-T is power up
6594 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
6595 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
6596 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
6597 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
6598 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
6599 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
6600 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
6602 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6603 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
6606 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
6607 #define MDIO_84833_SUPER_ISOLATE 0x8000
6608 /* These are mailbox register set used by 84833. */
6609 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
6610 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
6611 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
6612 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
6613 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
6615 /* Mailbox command set used by 84833. */
6616 #define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2
6617 /* Mailbox status set used by 84833. */
6618 #define PHY84833_CMD_RECEIVED 0x0001
6619 #define PHY84833_CMD_IN_PROGRESS 0x0002
6620 #define PHY84833_CMD_COMPLETE_PASS 0x0004
6621 #define PHY84833_CMD_COMPLETE_ERROR 0x0008
6622 #define PHY84833_CMD_OPEN_FOR_CMDS 0x0010
6623 #define PHY84833_CMD_SYSTEM_BOOT 0x0020
6624 #define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040
6625 #define PHY84833_CMD_CLEAR_COMPLETE 0x0080
6626 #define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5
6628 /* Warpcore clause 45 addressing */
6629 #define MDIO_WC_DEVAD 0x3
6630 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
6631 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
6632 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
6633 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
6634 #define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96
6635 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
6636 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
6637 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
6638 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
6639 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
6640 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
6641 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
6642 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
6643 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
6644 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
6645 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
6646 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
6647 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
6648 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
6649 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6650 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
6651 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
6652 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
6653 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
6654 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
6655 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
6656 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
6657 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
6658 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
6659 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
6660 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
6661 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
6662 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
6663 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
6664 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
6665 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
6666 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
6667 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
6668 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
6669 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
6670 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
6671 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
6672 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
6673 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
6674 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
6675 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
6676 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
6677 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
6678 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
6679 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
6680 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
6681 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
6682 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
6683 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
6684 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
6685 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
6686 #define MDIO_WC_REG_DSC_SMC 0x8213
6687 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
6688 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
6689 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
6690 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
6691 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
6692 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
6693 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
6694 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
6695 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
6696 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
6697 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
6698 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
6699 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
6700 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
6701 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
6702 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
6703 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
6704 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
6705 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
6706 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
6707 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
6708 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
6709 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
6710 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
6711 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
6712 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
6713 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
6714 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
6715 #define MDIO_WC_REG_RX66_SCW0 0x83c2
6716 #define MDIO_WC_REG_RX66_SCW1 0x83c3
6717 #define MDIO_WC_REG_RX66_SCW2 0x83c4
6718 #define MDIO_WC_REG_RX66_SCW3 0x83c5
6719 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
6720 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
6721 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
6722 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
6723 #define MDIO_WC_REG_FX100_CTRL1 0x8400
6724 #define MDIO_WC_REG_FX100_CTRL3 0x8402
6726 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
6727 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
6728 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
6730 #define MDIO_WC_REG_AERBLK_AER 0xffde
6731 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
6732 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
6734 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
6735 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
6736 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
6738 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
6740 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
6743 #define MDIO_REG_INTR_STATUS 0x1a
6744 #define MDIO_REG_INTR_MASK 0x1b
6745 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
6746 #define MDIO_REG_GPHY_SHADOW 0x1c
6747 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
6748 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
6749 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
6750 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
6752 #define IGU_FUNC_BASE 0x0400
6754 #define IGU_ADDR_MSIX 0x0000
6755 #define IGU_ADDR_INT_ACK 0x0200
6756 #define IGU_ADDR_PROD_UPD 0x0201
6757 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
6758 #define IGU_ADDR_ATTN_BITS_SET 0x0203
6759 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
6760 #define IGU_ADDR_COALESCE_NOW 0x0205
6761 #define IGU_ADDR_SIMD_MASK 0x0206
6762 #define IGU_ADDR_SIMD_NOMASK 0x0207
6763 #define IGU_ADDR_MSI_CTL 0x0210
6764 #define IGU_ADDR_MSI_ADDR_LO 0x0211
6765 #define IGU_ADDR_MSI_ADDR_HI 0x0212
6766 #define IGU_ADDR_MSI_DATA 0x0213
6768 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
6769 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
6770 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
6771 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
6773 #define COMMAND_REG_INT_ACK 0x0
6774 #define COMMAND_REG_PROD_UPD 0x4
6775 #define COMMAND_REG_ATTN_BITS_UPD 0x8
6776 #define COMMAND_REG_ATTN_BITS_SET 0xc
6777 #define COMMAND_REG_ATTN_BITS_CLR 0x10
6778 #define COMMAND_REG_COALESCE_NOW 0x14
6779 #define COMMAND_REG_SIMD_MASK 0x18
6780 #define COMMAND_REG_SIMD_NOMASK 0x1c
6783 #define IGU_MEM_BASE 0x0000
6785 #define IGU_MEM_MSIX_BASE 0x0000
6786 #define IGU_MEM_MSIX_UPPER 0x007f
6787 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
6789 #define IGU_MEM_PBA_MSIX_BASE 0x0200
6790 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
6792 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
6793 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
6795 #define IGU_CMD_INT_ACK_BASE 0x0400
6796 #define IGU_CMD_INT_ACK_UPPER\
6797 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6798 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
6800 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
6801 #define IGU_CMD_E2_PROD_UPD_UPPER\
6802 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6803 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
6805 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
6806 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
6807 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
6809 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
6810 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
6811 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
6812 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
6814 #define IGU_REG_RESERVED_UPPER 0x05ff
6815 /* Fields of IGU PF CONFIGRATION REGISTER */
6816 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
6817 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6818 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
6819 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
6820 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6821 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
6823 /* Fields of IGU VF CONFIGRATION REGISTER */
6824 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
6825 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6826 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
6827 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
6828 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6831 #define IGU_BC_DSB_NUM_SEGS 5
6832 #define IGU_BC_NDSB_NUM_SEGS 2
6833 #define IGU_NORM_DSB_NUM_SEGS 2
6834 #define IGU_NORM_NDSB_NUM_SEGS 1
6835 #define IGU_BC_BASE_DSB_PROD 128
6836 #define IGU_NORM_BASE_DSB_PROD 136
6838 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
6839 [5:2] = 0; [1:0] = PF number) */
6840 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
6841 #define IGU_FID_ENCODE_IS_PF_SHIFT 6
6842 #define IGU_FID_VF_NUM_MASK (0x3f)
6843 #define IGU_FID_PF_NUM_MASK (0x7)
6845 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
6846 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
6847 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
6848 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
6849 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
6852 #define CDU_REGION_NUMBER_XCM_AG 2
6853 #define CDU_REGION_NUMBER_UCM_AG 4
6857 * String-to-compress [31:8] = CID (all 24 bits)
6858 * String-to-compress [7:4] = Region
6859 * String-to-compress [3:0] = Type
6861 #define CDU_VALID_DATA(_cid, _region, _type)\
6862 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
6863 #define CDU_CRC8(_cid, _region, _type)\
6864 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
6865 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
6866 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
6867 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
6868 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
6869 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
6871 /******************************************************************************
6873 * Calculates crc 8 on a word value: polynomial 0-1-2-8
6874 * Code was translated from Verilog.
6876 *****************************************************************************/
6877 static inline u8 calc_crc8(u32 data, u8 crc)
6885 /* split the data into 31 bits */
6886 for (i = 0; i < 32; i++) {
6887 D[i] = (u8)(data & 1);
6891 /* split the crc into 8 bits */
6892 for (i = 0; i < 8; i++) {
6897 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
6898 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
6900 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
6901 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
6902 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
6904 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
6905 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
6906 C[0] ^ C[1] ^ C[4] ^ C[5];
6907 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
6908 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
6909 C[1] ^ C[2] ^ C[5] ^ C[6];
6910 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
6911 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
6912 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
6913 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
6914 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
6916 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
6917 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
6919 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
6920 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
6924 for (i = 0; i < 8; i++)
6925 crc_res |= (NewCRC[i] << i);
6931 #endif /* BNX2X_REG_H */