1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
23 /* [R 19] Interrupt register #0 read */
24 #define BRB1_REG_BRB1_INT_STS 0x6011c
25 /* [RW 4] Parity mask register #0 read/write */
26 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
27 /* [R 4] Parity register #0 read */
28 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
29 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
32 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
33 /* [RW 23] LL RAM data. */
34 #define BRB1_REG_LL_RAM 0x61000
35 /* [R 24] The number of full blocks. */
36 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
37 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
39 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
40 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
41 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
42 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
44 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
45 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
46 /* [RW 10] Write client 0: De-assert pause threshold. */
47 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
48 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
49 /* [RW 10] Write client 0: Assert pause threshold. */
50 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
51 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
52 /* [R 24] The number of full blocks occupied by port. */
53 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
54 /* [RW 1] Reset the design by software. */
55 #define BRB1_REG_SOFT_RESET 0x600dc
56 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
57 #define CCM_REG_CAM_OCCUP 0xd0188
58 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
59 acknowledge output is deasserted; all other signals are treated as usual;
60 if 1 - normal activity. */
61 #define CCM_REG_CCM_CFC_IFEN 0xd003c
62 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
63 disregarded; valid is deasserted; all other signals are treated as usual;
64 if 1 - normal activity. */
65 #define CCM_REG_CCM_CQM_IFEN 0xd000c
66 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
67 Otherwise 0 is inserted. */
68 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
69 /* [RW 11] Interrupt mask register #0 read/write */
70 #define CCM_REG_CCM_INT_MASK 0xd01e4
71 /* [R 11] Interrupt register #0 read */
72 #define CCM_REG_CCM_INT_STS 0xd01d8
73 /* [R 27] Parity register #0 read */
74 #define CCM_REG_CCM_PRTY_STS 0xd01e8
75 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
76 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
77 Is used to determine the number of the AG context REG-pairs written back;
78 when the input message Reg1WbFlg isn't set. */
79 #define CCM_REG_CCM_REG0_SZ 0xd00c4
80 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
81 disregarded; valid is deasserted; all other signals are treated as usual;
82 if 1 - normal activity. */
83 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
84 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
85 disregarded; valid is deasserted; all other signals are treated as usual;
86 if 1 - normal activity. */
87 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
88 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
89 disregarded; valid output is deasserted; all other signals are treated as
90 usual; if 1 - normal activity. */
91 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
92 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
93 are disregarded; all other signals are treated as usual; if 1 - normal
95 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
96 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
97 disregarded; valid output is deasserted; all other signals are treated as
98 usual; if 1 - normal activity. */
99 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
100 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
101 input is disregarded; all other signals are treated as usual; if 1 -
103 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
104 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
105 the initial credit value; read returns the current value of the credit
106 counter. Must be initialized to 1 at start-up. */
107 #define CCM_REG_CFC_INIT_CRD 0xd0204
108 /* [RW 2] Auxillary counter flag Q number 1. */
109 #define CCM_REG_CNT_AUX1_Q 0xd00c8
110 /* [RW 2] Auxillary counter flag Q number 2. */
111 #define CCM_REG_CNT_AUX2_Q 0xd00cc
112 /* [RW 28] The CM header value for QM request (primary). */
113 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
114 /* [RW 28] The CM header value for QM request (secondary). */
115 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
116 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
117 acknowledge output is deasserted; all other signals are treated as usual;
118 if 1 - normal activity. */
119 #define CCM_REG_CQM_CCM_IFEN 0xd0014
120 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
121 the initial credit value; read returns the current value of the credit
122 counter. Must be initialized to 32 at start-up. */
123 #define CCM_REG_CQM_INIT_CRD 0xd020c
124 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
125 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
126 prioritised); 2 stands for weight 2; tc. */
127 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
128 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
129 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
130 prioritised); 2 stands for weight 2; tc. */
131 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
132 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
133 acknowledge output is deasserted; all other signals are treated as usual;
134 if 1 - normal activity. */
135 #define CCM_REG_CSDM_IFEN 0xd0018
136 /* [RC 1] Set when the message length mismatch (relative to last indication)
137 at the SDM interface is detected. */
138 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
139 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
140 weight 8 (the most prioritised); 1 stands for weight 1(least
141 prioritised); 2 stands for weight 2; tc. */
142 #define CCM_REG_CSDM_WEIGHT 0xd00b4
143 /* [RW 28] The CM header for QM formatting in case of an error in the QM
145 #define CCM_REG_ERR_CCM_HDR 0xd0094
146 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
147 #define CCM_REG_ERR_EVNT_ID 0xd0098
148 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
149 writes the initial credit value; read returns the current value of the
150 credit counter. Must be initialized to 64 at start-up. */
151 #define CCM_REG_FIC0_INIT_CRD 0xd0210
152 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
153 writes the initial credit value; read returns the current value of the
154 credit counter. Must be initialized to 64 at start-up. */
155 #define CCM_REG_FIC1_INIT_CRD 0xd0214
156 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
157 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
158 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
159 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
160 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
161 #define CCM_REG_GR_ARB_TYPE 0xd015c
162 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
163 highest priority is 3. It is supposed; that the Store channel priority is
164 the compliment to 4 of the rest priorities - Aggregation channel; Load
165 (FIC0) channel and Load (FIC1). */
166 #define CCM_REG_GR_LD0_PR 0xd0164
167 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
168 highest priority is 3. It is supposed; that the Store channel priority is
169 the compliment to 4 of the rest priorities - Aggregation channel; Load
170 (FIC0) channel and Load (FIC1). */
171 #define CCM_REG_GR_LD1_PR 0xd0168
172 /* [RW 2] General flags index. */
173 #define CCM_REG_INV_DONE_Q 0xd0108
174 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
175 context and sent to STORM; for a specific connection type. The double
176 REG-pairs are used in order to align to STORM context row size of 128
177 bits. The offset of these data in the STORM context is always 0. Index
178 _(0..15) stands for the connection type (one of 16). */
179 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
180 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
181 #define CCM_REG_N_SM_CTX_LD_10 0xd0074
182 #define CCM_REG_N_SM_CTX_LD_11 0xd0078
183 #define CCM_REG_N_SM_CTX_LD_12 0xd007c
184 #define CCM_REG_N_SM_CTX_LD_13 0xd0080
185 #define CCM_REG_N_SM_CTX_LD_14 0xd0084
186 #define CCM_REG_N_SM_CTX_LD_15 0xd0088
187 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
188 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
189 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
190 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
191 acknowledge output is deasserted; all other signals are treated as usual;
192 if 1 - normal activity. */
193 #define CCM_REG_PBF_IFEN 0xd0028
194 /* [RC 1] Set when the message length mismatch (relative to last indication)
195 at the pbf interface is detected. */
196 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
197 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
198 weight 8 (the most prioritised); 1 stands for weight 1(least
199 prioritised); 2 stands for weight 2; tc. */
200 #define CCM_REG_PBF_WEIGHT 0xd00ac
201 #define CCM_REG_PHYS_QNUM1_0 0xd0134
202 #define CCM_REG_PHYS_QNUM1_1 0xd0138
203 #define CCM_REG_PHYS_QNUM2_0 0xd013c
204 #define CCM_REG_PHYS_QNUM2_1 0xd0140
205 #define CCM_REG_PHYS_QNUM3_0 0xd0144
206 #define CCM_REG_PHYS_QNUM3_1 0xd0148
207 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
208 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
209 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
210 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
211 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
212 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
213 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
214 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
215 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
216 disregarded; acknowledge output is deasserted; all other signals are
217 treated as usual; if 1 - normal activity. */
218 #define CCM_REG_STORM_CCM_IFEN 0xd0010
219 /* [RC 1] Set when the message length mismatch (relative to last indication)
220 at the STORM interface is detected. */
221 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
222 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
223 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
224 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
226 #define CCM_REG_STORM_WEIGHT 0xd009c
227 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
228 disregarded; acknowledge output is deasserted; all other signals are
229 treated as usual; if 1 - normal activity. */
230 #define CCM_REG_TSEM_IFEN 0xd001c
231 /* [RC 1] Set when the message length mismatch (relative to last indication)
232 at the tsem interface is detected. */
233 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
234 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
235 weight 8 (the most prioritised); 1 stands for weight 1(least
236 prioritised); 2 stands for weight 2; tc. */
237 #define CCM_REG_TSEM_WEIGHT 0xd00a0
238 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
239 disregarded; acknowledge output is deasserted; all other signals are
240 treated as usual; if 1 - normal activity. */
241 #define CCM_REG_USEM_IFEN 0xd0024
242 /* [RC 1] Set when message length mismatch (relative to last indication) at
243 the usem interface is detected. */
244 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
245 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
246 weight 8 (the most prioritised); 1 stands for weight 1(least
247 prioritised); 2 stands for weight 2; tc. */
248 #define CCM_REG_USEM_WEIGHT 0xd00a8
249 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
250 disregarded; acknowledge output is deasserted; all other signals are
251 treated as usual; if 1 - normal activity. */
252 #define CCM_REG_XSEM_IFEN 0xd0020
253 /* [RC 1] Set when the message length mismatch (relative to last indication)
254 at the xsem interface is detected. */
255 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
256 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
257 weight 8 (the most prioritised); 1 stands for weight 1(least
258 prioritised); 2 stands for weight 2; tc. */
259 #define CCM_REG_XSEM_WEIGHT 0xd00a4
260 /* [RW 19] Indirect access to the descriptor table of the XX protection
261 mechanism. The fields are: [5:0] - message length; [12:6] - message
262 pointer; 18:13] - next pointer. */
263 #define CCM_REG_XX_DESCR_TABLE 0xd0300
264 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
265 /* [R 7] Used to read the value of XX protection Free counter. */
266 #define CCM_REG_XX_FREE 0xd0184
267 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
268 of the Input Stage XX protection buffer by the XX protection pending
269 messages. Max credit available - 127. Write writes the initial credit
270 value; read returns the current value of the credit counter. Must be
271 initialized to maximum XX protected message size - 2 at start-up. */
272 #define CCM_REG_XX_INIT_CRD 0xd0220
273 /* [RW 7] The maximum number of pending messages; which may be stored in XX
274 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
275 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
277 #define CCM_REG_XX_MSG_NUM 0xd0224
278 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
279 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
280 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
281 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
283 #define CCM_REG_XX_TABLE 0xd0280
284 #define CDU_REG_CDU_CHK_MASK0 0x101000
285 #define CDU_REG_CDU_CHK_MASK1 0x101004
286 #define CDU_REG_CDU_CONTROL0 0x101008
287 #define CDU_REG_CDU_DEBUG 0x101010
288 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
289 /* [RW 7] Interrupt mask register #0 read/write */
290 #define CDU_REG_CDU_INT_MASK 0x10103c
291 /* [R 7] Interrupt register #0 read */
292 #define CDU_REG_CDU_INT_STS 0x101030
293 /* [RW 5] Parity mask register #0 read/write */
294 #define CDU_REG_CDU_PRTY_MASK 0x10104c
295 /* [R 5] Parity register #0 read */
296 #define CDU_REG_CDU_PRTY_STS 0x101040
297 /* [RC 32] logging of error data in case of a CDU load error:
298 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
299 ype_error; ctual_active; ctual_compressed_context}; */
300 #define CDU_REG_ERROR_DATA 0x101014
301 /* [WB 216] L1TT ram access. each entry has the following format :
302 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
303 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
304 #define CDU_REG_L1TT 0x101800
305 /* [WB 24] MATT ram access. each entry has the following
306 format:{RegionLength[11:0]; egionOffset[11:0]} */
307 #define CDU_REG_MATT 0x101100
308 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
309 #define CDU_REG_MF_MODE 0x101050
310 /* [R 1] indication the initializing the activity counter by the hardware
312 #define CFC_REG_AC_INIT_DONE 0x104078
313 /* [RW 13] activity counter ram access */
314 #define CFC_REG_ACTIVITY_COUNTER 0x104400
315 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
316 /* [R 1] indication the initializing the cams by the hardware was done. */
317 #define CFC_REG_CAM_INIT_DONE 0x10407c
318 /* [RW 2] Interrupt mask register #0 read/write */
319 #define CFC_REG_CFC_INT_MASK 0x104108
320 /* [R 2] Interrupt register #0 read */
321 #define CFC_REG_CFC_INT_STS 0x1040fc
322 /* [RC 2] Interrupt register #0 read clear */
323 #define CFC_REG_CFC_INT_STS_CLR 0x104100
324 /* [RW 4] Parity mask register #0 read/write */
325 #define CFC_REG_CFC_PRTY_MASK 0x104118
326 /* [R 4] Parity register #0 read */
327 #define CFC_REG_CFC_PRTY_STS 0x10410c
328 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
329 #define CFC_REG_CID_CAM 0x104800
330 #define CFC_REG_CONTROL0 0x104028
331 #define CFC_REG_DEBUG0 0x104050
332 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
333 vector) whether the cfc should be disabled upon it */
334 #define CFC_REG_DISABLE_ON_ERROR 0x104044
335 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
336 set one of these bits. the bit description can be found in CFC
338 #define CFC_REG_ERROR_VECTOR 0x10403c
339 /* [WB 93] LCID info ram access */
340 #define CFC_REG_INFO_RAM 0x105000
341 #define CFC_REG_INFO_RAM_SIZE 1024
342 #define CFC_REG_INIT_REG 0x10404c
343 #define CFC_REG_INTERFACES 0x104058
344 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
345 field allows changing the priorities of the weighted-round-robin arbiter
346 which selects which CFC load client should be served next */
347 #define CFC_REG_LCREQ_WEIGHTS 0x104084
348 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
349 #define CFC_REG_LINK_LIST 0x104c00
350 #define CFC_REG_LINK_LIST_SIZE 256
351 /* [R 1] indication the initializing the link list by the hardware was done. */
352 #define CFC_REG_LL_INIT_DONE 0x104074
353 /* [R 9] Number of allocated LCIDs which are at empty state */
354 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
355 /* [R 9] Number of Arriving LCIDs in Link List Block */
356 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
357 /* [R 9] Number of Leaving LCIDs in Link List Block */
358 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
359 /* [RW 8] The event id for aggregated interrupt 0 */
360 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
361 #define CSDM_REG_AGG_INT_EVENT_1 0xc203c
362 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
363 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
364 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
365 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
366 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
367 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
368 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
369 #define CSDM_REG_AGG_INT_EVENT_17 0xc207c
370 #define CSDM_REG_AGG_INT_EVENT_18 0xc2080
371 #define CSDM_REG_AGG_INT_EVENT_19 0xc2084
372 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
373 #define CSDM_REG_AGG_INT_EVENT_20 0xc2088
374 #define CSDM_REG_AGG_INT_EVENT_21 0xc208c
375 #define CSDM_REG_AGG_INT_EVENT_22 0xc2090
376 #define CSDM_REG_AGG_INT_EVENT_23 0xc2094
377 #define CSDM_REG_AGG_INT_EVENT_24 0xc2098
378 #define CSDM_REG_AGG_INT_EVENT_25 0xc209c
379 #define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
380 #define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
381 #define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
382 #define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
383 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
384 #define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
385 #define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
386 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
387 /* [RW 1] The T bit for aggregated interrupt 0 */
388 #define CSDM_REG_AGG_INT_T_0 0xc20b8
389 #define CSDM_REG_AGG_INT_T_1 0xc20bc
390 #define CSDM_REG_AGG_INT_T_10 0xc20e0
391 #define CSDM_REG_AGG_INT_T_11 0xc20e4
392 #define CSDM_REG_AGG_INT_T_12 0xc20e8
393 #define CSDM_REG_AGG_INT_T_13 0xc20ec
394 #define CSDM_REG_AGG_INT_T_14 0xc20f0
395 #define CSDM_REG_AGG_INT_T_15 0xc20f4
396 #define CSDM_REG_AGG_INT_T_16 0xc20f8
397 #define CSDM_REG_AGG_INT_T_17 0xc20fc
398 #define CSDM_REG_AGG_INT_T_18 0xc2100
399 #define CSDM_REG_AGG_INT_T_19 0xc2104
400 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
401 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
402 /* [RW 16] The maximum value of the competion counter #0 */
403 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
404 /* [RW 16] The maximum value of the competion counter #1 */
405 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
406 /* [RW 16] The maximum value of the competion counter #2 */
407 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
408 /* [RW 16] The maximum value of the competion counter #3 */
409 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
410 /* [RW 13] The start address in the internal RAM for the completion
412 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
413 /* [RW 32] Interrupt mask register #0 read/write */
414 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
415 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
416 /* [R 32] Interrupt register #0 read */
417 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
418 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
419 /* [RW 11] Parity mask register #0 read/write */
420 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
421 /* [R 11] Parity register #0 read */
422 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
423 #define CSDM_REG_ENABLE_IN1 0xc2238
424 #define CSDM_REG_ENABLE_IN2 0xc223c
425 #define CSDM_REG_ENABLE_OUT1 0xc2240
426 #define CSDM_REG_ENABLE_OUT2 0xc2244
427 /* [RW 4] The initial number of messages that can be sent to the pxp control
428 interface without receiving any ACK. */
429 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
430 /* [ST 32] The number of ACK after placement messages received */
431 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
432 /* [ST 32] The number of packet end messages received from the parser */
433 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
434 /* [ST 32] The number of requests received from the pxp async if */
435 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
436 /* [ST 32] The number of commands received in queue 0 */
437 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
438 /* [ST 32] The number of commands received in queue 10 */
439 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
440 /* [ST 32] The number of commands received in queue 11 */
441 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
442 /* [ST 32] The number of commands received in queue 1 */
443 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
444 /* [ST 32] The number of commands received in queue 3 */
445 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
446 /* [ST 32] The number of commands received in queue 4 */
447 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
448 /* [ST 32] The number of commands received in queue 5 */
449 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
450 /* [ST 32] The number of commands received in queue 6 */
451 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
452 /* [ST 32] The number of commands received in queue 7 */
453 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
454 /* [ST 32] The number of commands received in queue 8 */
455 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
456 /* [ST 32] The number of commands received in queue 9 */
457 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
458 /* [RW 13] The start address in the internal RAM for queue counters */
459 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
460 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
461 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
462 /* [R 1] parser fifo empty in sdm_sync block */
463 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
464 /* [R 1] parser serial fifo empty in sdm_sync block */
465 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
466 /* [RW 32] Tick for timer counter. Applicable only when
467 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
468 #define CSDM_REG_TIMER_TICK 0xc2000
469 /* [RW 5] The number of time_slots in the arbitration cycle */
470 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
471 /* [RW 3] The source that is associated with arbitration element 0. Source
472 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
473 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
474 #define CSEM_REG_ARB_ELEMENT0 0x200020
475 /* [RW 3] The source that is associated with arbitration element 1. Source
476 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
477 sleeping thread with priority 1; 4- sleeping thread with priority 2.
478 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
479 #define CSEM_REG_ARB_ELEMENT1 0x200024
480 /* [RW 3] The source that is associated with arbitration element 2. Source
481 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
482 sleeping thread with priority 1; 4- sleeping thread with priority 2.
483 Could not be equal to register ~csem_registers_arb_element0.arb_element0
484 and ~csem_registers_arb_element1.arb_element1 */
485 #define CSEM_REG_ARB_ELEMENT2 0x200028
486 /* [RW 3] The source that is associated with arbitration element 3. Source
487 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
488 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
489 not be equal to register ~csem_registers_arb_element0.arb_element0 and
490 ~csem_registers_arb_element1.arb_element1 and
491 ~csem_registers_arb_element2.arb_element2 */
492 #define CSEM_REG_ARB_ELEMENT3 0x20002c
493 /* [RW 3] The source that is associated with arbitration element 4. Source
494 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
495 sleeping thread with priority 1; 4- sleeping thread with priority 2.
496 Could not be equal to register ~csem_registers_arb_element0.arb_element0
497 and ~csem_registers_arb_element1.arb_element1 and
498 ~csem_registers_arb_element2.arb_element2 and
499 ~csem_registers_arb_element3.arb_element3 */
500 #define CSEM_REG_ARB_ELEMENT4 0x200030
501 /* [RW 32] Interrupt mask register #0 read/write */
502 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
503 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
504 /* [R 32] Interrupt register #0 read */
505 #define CSEM_REG_CSEM_INT_STS_0 0x200104
506 #define CSEM_REG_CSEM_INT_STS_1 0x200114
507 /* [RW 32] Parity mask register #0 read/write */
508 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
509 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
510 /* [R 32] Parity register #0 read */
511 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
512 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
513 #define CSEM_REG_ENABLE_IN 0x2000a4
514 #define CSEM_REG_ENABLE_OUT 0x2000a8
515 /* [RW 32] This address space contains all registers and memories that are
516 placed in SEM_FAST block. The SEM_FAST registers are described in
517 appendix B. In order to access the sem_fast registers the base address
518 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
519 #define CSEM_REG_FAST_MEMORY 0x220000
520 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
522 #define CSEM_REG_FIC0_DISABLE 0x200224
523 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
525 #define CSEM_REG_FIC1_DISABLE 0x200234
526 /* [RW 15] Interrupt table Read and write access to it is not possible in
527 the middle of the work */
528 #define CSEM_REG_INT_TABLE 0x200400
529 /* [ST 24] Statistics register. The number of messages that entered through
531 #define CSEM_REG_MSG_NUM_FIC0 0x200000
532 /* [ST 24] Statistics register. The number of messages that entered through
534 #define CSEM_REG_MSG_NUM_FIC1 0x200004
535 /* [ST 24] Statistics register. The number of messages that were sent to
537 #define CSEM_REG_MSG_NUM_FOC0 0x200008
538 /* [ST 24] Statistics register. The number of messages that were sent to
540 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
541 /* [ST 24] Statistics register. The number of messages that were sent to
543 #define CSEM_REG_MSG_NUM_FOC2 0x200010
544 /* [ST 24] Statistics register. The number of messages that were sent to
546 #define CSEM_REG_MSG_NUM_FOC3 0x200014
547 /* [RW 1] Disables input messages from the passive buffer May be updated
548 during run_time by the microcode */
549 #define CSEM_REG_PAS_DISABLE 0x20024c
550 /* [WB 128] Debug only. Passive buffer memory */
551 #define CSEM_REG_PASSIVE_BUFFER 0x202000
552 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
553 #define CSEM_REG_PRAM 0x240000
554 /* [R 16] Valid sleeping threads indication have bit per thread */
555 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
556 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
557 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
558 /* [RW 16] List of free threads . There is a bit per thread. */
559 #define CSEM_REG_THREADS_LIST 0x2002e4
560 /* [RW 3] The arbitration scheme of time_slot 0 */
561 #define CSEM_REG_TS_0_AS 0x200038
562 /* [RW 3] The arbitration scheme of time_slot 10 */
563 #define CSEM_REG_TS_10_AS 0x200060
564 /* [RW 3] The arbitration scheme of time_slot 11 */
565 #define CSEM_REG_TS_11_AS 0x200064
566 /* [RW 3] The arbitration scheme of time_slot 12 */
567 #define CSEM_REG_TS_12_AS 0x200068
568 /* [RW 3] The arbitration scheme of time_slot 13 */
569 #define CSEM_REG_TS_13_AS 0x20006c
570 /* [RW 3] The arbitration scheme of time_slot 14 */
571 #define CSEM_REG_TS_14_AS 0x200070
572 /* [RW 3] The arbitration scheme of time_slot 15 */
573 #define CSEM_REG_TS_15_AS 0x200074
574 /* [RW 3] The arbitration scheme of time_slot 16 */
575 #define CSEM_REG_TS_16_AS 0x200078
576 /* [RW 3] The arbitration scheme of time_slot 17 */
577 #define CSEM_REG_TS_17_AS 0x20007c
578 /* [RW 3] The arbitration scheme of time_slot 18 */
579 #define CSEM_REG_TS_18_AS 0x200080
580 /* [RW 3] The arbitration scheme of time_slot 1 */
581 #define CSEM_REG_TS_1_AS 0x20003c
582 /* [RW 3] The arbitration scheme of time_slot 2 */
583 #define CSEM_REG_TS_2_AS 0x200040
584 /* [RW 3] The arbitration scheme of time_slot 3 */
585 #define CSEM_REG_TS_3_AS 0x200044
586 /* [RW 3] The arbitration scheme of time_slot 4 */
587 #define CSEM_REG_TS_4_AS 0x200048
588 /* [RW 3] The arbitration scheme of time_slot 5 */
589 #define CSEM_REG_TS_5_AS 0x20004c
590 /* [RW 3] The arbitration scheme of time_slot 6 */
591 #define CSEM_REG_TS_6_AS 0x200050
592 /* [RW 3] The arbitration scheme of time_slot 7 */
593 #define CSEM_REG_TS_7_AS 0x200054
594 /* [RW 3] The arbitration scheme of time_slot 8 */
595 #define CSEM_REG_TS_8_AS 0x200058
596 /* [RW 3] The arbitration scheme of time_slot 9 */
597 #define CSEM_REG_TS_9_AS 0x20005c
598 /* [RW 1] Parity mask register #0 read/write */
599 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
600 /* [R 1] Parity register #0 read */
601 #define DBG_REG_DBG_PRTY_STS 0xc09c
602 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
604 #define DMAE_REG_CMD_MEM 0x102400
605 #define DMAE_REG_CMD_MEM_SIZE 224
606 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
607 initial value is all ones. */
608 #define DMAE_REG_CRC16C_INIT 0x10201c
609 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
610 CRC-16 T10 initial value is all ones. */
611 #define DMAE_REG_CRC16T10_INIT 0x102020
612 /* [RW 2] Interrupt mask register #0 read/write */
613 #define DMAE_REG_DMAE_INT_MASK 0x102054
614 /* [RW 4] Parity mask register #0 read/write */
615 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
616 /* [R 4] Parity register #0 read */
617 #define DMAE_REG_DMAE_PRTY_STS 0x102058
618 /* [RW 1] Command 0 go. */
619 #define DMAE_REG_GO_C0 0x102080
620 /* [RW 1] Command 1 go. */
621 #define DMAE_REG_GO_C1 0x102084
622 /* [RW 1] Command 10 go. */
623 #define DMAE_REG_GO_C10 0x102088
624 #define DMAE_REG_GO_C10_SIZE 1
625 /* [RW 1] Command 11 go. */
626 #define DMAE_REG_GO_C11 0x10208c
627 #define DMAE_REG_GO_C11_SIZE 1
628 /* [RW 1] Command 12 go. */
629 #define DMAE_REG_GO_C12 0x102090
630 #define DMAE_REG_GO_C12_SIZE 1
631 /* [RW 1] Command 13 go. */
632 #define DMAE_REG_GO_C13 0x102094
633 #define DMAE_REG_GO_C13_SIZE 1
634 /* [RW 1] Command 14 go. */
635 #define DMAE_REG_GO_C14 0x102098
636 #define DMAE_REG_GO_C14_SIZE 1
637 /* [RW 1] Command 15 go. */
638 #define DMAE_REG_GO_C15 0x10209c
639 #define DMAE_REG_GO_C15_SIZE 1
640 /* [RW 1] Command 10 go. */
641 #define DMAE_REG_GO_C10 0x102088
642 /* [RW 1] Command 11 go. */
643 #define DMAE_REG_GO_C11 0x10208c
644 /* [RW 1] Command 12 go. */
645 #define DMAE_REG_GO_C12 0x102090
646 /* [RW 1] Command 13 go. */
647 #define DMAE_REG_GO_C13 0x102094
648 /* [RW 1] Command 14 go. */
649 #define DMAE_REG_GO_C14 0x102098
650 /* [RW 1] Command 15 go. */
651 #define DMAE_REG_GO_C15 0x10209c
652 /* [RW 1] Command 2 go. */
653 #define DMAE_REG_GO_C2 0x1020a0
654 /* [RW 1] Command 3 go. */
655 #define DMAE_REG_GO_C3 0x1020a4
656 /* [RW 1] Command 4 go. */
657 #define DMAE_REG_GO_C4 0x1020a8
658 /* [RW 1] Command 5 go. */
659 #define DMAE_REG_GO_C5 0x1020ac
660 /* [RW 1] Command 6 go. */
661 #define DMAE_REG_GO_C6 0x1020b0
662 /* [RW 1] Command 7 go. */
663 #define DMAE_REG_GO_C7 0x1020b4
664 /* [RW 1] Command 8 go. */
665 #define DMAE_REG_GO_C8 0x1020b8
666 /* [RW 1] Command 9 go. */
667 #define DMAE_REG_GO_C9 0x1020bc
668 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
669 input is disregarded; valid is deasserted; all other signals are treated
670 as usual; if 1 - normal activity. */
671 #define DMAE_REG_GRC_IFEN 0x102008
672 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
673 acknowledge input is disregarded; valid is deasserted; full is asserted;
674 all other signals are treated as usual; if 1 - normal activity. */
675 #define DMAE_REG_PCI_IFEN 0x102004
676 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
677 initial value to the credit counter; related to the address. Read returns
678 the current value of the counter. */
679 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
680 /* [RW 8] Aggregation command. */
681 #define DORQ_REG_AGG_CMD0 0x170060
682 /* [RW 8] Aggregation command. */
683 #define DORQ_REG_AGG_CMD1 0x170064
684 /* [RW 8] Aggregation command. */
685 #define DORQ_REG_AGG_CMD2 0x170068
686 /* [RW 8] Aggregation command. */
687 #define DORQ_REG_AGG_CMD3 0x17006c
688 /* [RW 28] UCM Header. */
689 #define DORQ_REG_CMHEAD_RX 0x170050
690 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
691 #define DORQ_REG_DB_ADDR0 0x17008c
692 /* [RW 5] Interrupt mask register #0 read/write */
693 #define DORQ_REG_DORQ_INT_MASK 0x170180
694 /* [R 5] Interrupt register #0 read */
695 #define DORQ_REG_DORQ_INT_STS 0x170174
696 /* [RC 5] Interrupt register #0 read clear */
697 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
698 /* [RW 2] Parity mask register #0 read/write */
699 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
700 /* [R 2] Parity register #0 read */
701 #define DORQ_REG_DORQ_PRTY_STS 0x170184
702 /* [RW 8] The address to write the DPM CID to STORM. */
703 #define DORQ_REG_DPM_CID_ADDR 0x170044
704 /* [RW 5] The DPM mode CID extraction offset. */
705 #define DORQ_REG_DPM_CID_OFST 0x170030
706 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
707 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
708 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
709 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
710 /* [R 13] Current value of the DQ FIFO fill level according to following
711 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
713 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
714 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
715 equal to full threshold; reset on full clear. */
716 #define DORQ_REG_DQ_FULL_ST 0x1700c0
717 /* [RW 28] The value sent to CM header in the case of CFC load error. */
718 #define DORQ_REG_ERR_CMHEAD 0x170058
719 #define DORQ_REG_IF_EN 0x170004
720 #define DORQ_REG_MODE_ACT 0x170008
721 /* [RW 5] The normal mode CID extraction offset. */
722 #define DORQ_REG_NORM_CID_OFST 0x17002c
723 /* [RW 28] TCM Header when only TCP context is loaded. */
724 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
725 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
727 #define DORQ_REG_OUTST_REQ 0x17003c
728 #define DORQ_REG_REGN 0x170038
729 /* [R 4] Current value of response A counter credit. Initial credit is
730 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
732 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
733 /* [R 4] Current value of response B counter credit. Initial credit is
734 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
736 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
737 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
738 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
739 read reads this written value. */
740 #define DORQ_REG_RSP_INIT_CRD 0x170048
741 /* [RW 4] Initial activity counter value on the load request; when the
743 #define DORQ_REG_SHRT_ACT_CNT 0x170070
744 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
745 #define DORQ_REG_SHRT_CMHEAD 0x170054
746 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
747 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
748 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
749 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
750 #define HC_REG_AGG_INT_0 0x108050
751 #define HC_REG_AGG_INT_1 0x108054
752 #define HC_REG_ATTN_BIT 0x108120
753 #define HC_REG_ATTN_IDX 0x108100
754 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
755 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
756 #define HC_REG_ATTN_NUM_P0 0x108038
757 #define HC_REG_ATTN_NUM_P1 0x10803c
758 #define HC_REG_COMMAND_REG 0x108180
759 #define HC_REG_CONFIG_0 0x108000
760 #define HC_REG_CONFIG_1 0x108004
761 #define HC_REG_FUNC_NUM_P0 0x1080ac
762 #define HC_REG_FUNC_NUM_P1 0x1080b0
763 /* [RW 3] Parity mask register #0 read/write */
764 #define HC_REG_HC_PRTY_MASK 0x1080a0
765 /* [R 3] Parity register #0 read */
766 #define HC_REG_HC_PRTY_STS 0x108094
767 #define HC_REG_INT_MASK 0x108108
768 #define HC_REG_LEADING_EDGE_0 0x108040
769 #define HC_REG_LEADING_EDGE_1 0x108048
770 #define HC_REG_P0_PROD_CONS 0x108200
771 #define HC_REG_P1_PROD_CONS 0x108400
772 #define HC_REG_PBA_COMMAND 0x108140
773 #define HC_REG_PCI_CONFIG_0 0x108010
774 #define HC_REG_PCI_CONFIG_1 0x108014
775 #define HC_REG_STATISTIC_COUNTERS 0x109000
776 #define HC_REG_TRAILING_EDGE_0 0x108044
777 #define HC_REG_TRAILING_EDGE_1 0x10804c
778 #define HC_REG_UC_RAM_ADDR_0 0x108028
779 #define HC_REG_UC_RAM_ADDR_1 0x108030
780 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
781 #define HC_REG_VQID_0 0x108008
782 #define HC_REG_VQID_1 0x10800c
783 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
784 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
785 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
786 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
787 #define MCP_REG_MCPR_NVM_READ 0x86410
788 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
789 #define MCP_REG_MCPR_NVM_WRITE 0x86408
790 #define MCP_REG_MCPR_NVM_WRITE1 0x86428
791 #define MCP_REG_MCPR_SCRATCH 0xa0000
792 /* [R 32] read first 32 bit after inversion of function 0. mapped as
793 follows: [0] NIG attention for function0; [1] NIG attention for
794 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
795 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
796 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
797 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
798 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
799 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
800 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
801 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
802 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
803 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
804 Parity error; [31] PBF Hw interrupt; */
805 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
806 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
807 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
808 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
809 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
810 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
811 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
812 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
813 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
814 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
815 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
816 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
817 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
818 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
820 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
821 /* [R 32] read second 32 bit after inversion of function 0. mapped as
822 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
823 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
824 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
825 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
826 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
827 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
828 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
829 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
830 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
831 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
832 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
834 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
835 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
836 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
837 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
838 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
839 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
840 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
841 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
842 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
843 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
844 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
845 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
846 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
847 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
848 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
849 /* [R 32] read third 32 bit after inversion of function 0. mapped as
850 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
851 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
852 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
853 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
854 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
855 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
856 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
857 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
858 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
859 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
860 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
862 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
863 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
864 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
865 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
866 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
867 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
868 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
869 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
870 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
871 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
872 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
873 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
874 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
875 timers attn_4 func1; [30] General attn0; [31] General attn1; */
876 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
877 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
878 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
879 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
880 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
881 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
882 [14] General attn16; [15] General attn17; [16] General attn18; [17]
883 General attn19; [18] General attn20; [19] General attn21; [20] Main power
884 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
885 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
886 Latched timeout attention; [27] GRC Latched reserved access attention;
887 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
888 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
889 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
890 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
891 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
892 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
893 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
894 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
895 General attn13; [12] General attn14; [13] General attn15; [14] General
896 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
897 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
898 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
899 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
900 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
901 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
902 ump_tx_parity; [31] MCP Latched scpad_parity; */
903 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
904 /* [W 14] write to this register results with the clear of the latched
905 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
906 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
907 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
908 GRC Latched reserved access attention; one in d7 clears Latched
909 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
910 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
911 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
912 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
913 from this register return zero */
914 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
915 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
916 as follows: [0] NIG attention for function0; [1] NIG attention for
917 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
918 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
919 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
920 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
921 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
922 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
923 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
924 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
925 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
926 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
927 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
928 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
929 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
930 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
931 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
932 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
933 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
934 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
935 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
936 as follows: [0] NIG attention for function0; [1] NIG attention for
937 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
938 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
939 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
940 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
941 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
942 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
943 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
944 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
945 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
946 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
947 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
948 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
949 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
950 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
951 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
952 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
953 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
954 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
955 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
956 as follows: [0] NIG attention for function0; [1] NIG attention for
957 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
958 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
959 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
960 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
961 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
962 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
963 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
964 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
965 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
966 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
967 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
968 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
969 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
970 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
971 as follows: [0] NIG attention for function0; [1] NIG attention for
972 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
973 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
974 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
975 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
976 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
977 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
978 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
979 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
980 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
981 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
982 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
983 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
984 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
985 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
986 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
987 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
988 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
989 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
990 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
991 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
992 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
993 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
994 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
995 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
996 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
998 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
999 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1000 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1001 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1002 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1003 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1004 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1005 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1006 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1007 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1008 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1009 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1010 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1011 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1013 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1014 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1015 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1016 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1017 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1018 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1019 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1020 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1021 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1022 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1023 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1024 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1025 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1026 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1028 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1029 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1030 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1031 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1032 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1033 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1034 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1035 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1036 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1037 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1038 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1039 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1040 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1041 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1043 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1044 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1045 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1046 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1047 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1048 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1049 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1050 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1051 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1052 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1053 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1054 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1055 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1056 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1058 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1059 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1060 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1061 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1062 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1063 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1064 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1065 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1066 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1067 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1068 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1069 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1070 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1071 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1073 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1074 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1075 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1076 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1077 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1078 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1079 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1080 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1081 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1082 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1083 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1084 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1085 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1086 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1088 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1089 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1090 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1091 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1092 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1093 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1094 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1095 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1096 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1097 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1098 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1099 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1100 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1101 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1103 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1104 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1105 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1106 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1107 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1108 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1109 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1110 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1111 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1112 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1113 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1114 Latched timeout attention; [27] GRC Latched reserved access attention;
1115 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1116 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1117 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1118 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1119 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1120 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1121 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1122 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1123 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1124 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1125 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1126 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1127 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1128 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1129 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1130 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1131 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1132 Latched timeout attention; [27] GRC Latched reserved access attention;
1133 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1134 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1135 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1136 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1137 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1138 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1139 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1140 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1141 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1142 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1143 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1144 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1145 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1146 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1147 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1148 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1149 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1150 Latched timeout attention; [27] GRC Latched reserved access attention;
1151 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1152 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1153 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1154 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1155 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1156 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1157 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1158 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1159 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1160 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1161 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1162 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1163 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1164 Latched timeout attention; [27] GRC Latched reserved access attention;
1165 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1166 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1167 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1168 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1169 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1171 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1172 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1173 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1174 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1175 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1176 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1177 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1178 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1179 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1180 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1181 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1182 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1183 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1184 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1185 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1186 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1187 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1188 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1189 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1190 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1191 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1192 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1193 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1194 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1195 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1196 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1197 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1198 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1199 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1200 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1201 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1202 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1203 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1204 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1205 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1206 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1207 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1208 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1209 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1210 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1211 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1212 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1213 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1214 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1215 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1216 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1217 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1218 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1219 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1220 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1221 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1222 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1223 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1224 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1225 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1226 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1227 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1228 [9:8] = raserved. Zero = mask; one = unmask */
1229 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1230 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1231 /* [RW 1] If set a system kill occurred */
1232 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1233 /* [RW 32] Represent the status of the input vector to the AEU when a system
1234 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1235 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1236 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1237 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1238 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1239 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1240 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1241 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1242 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1243 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1244 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1245 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1247 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1248 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1249 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1250 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1251 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1253 #define MISC_REG_BOND_ID 0xa400
1254 /* [R 8] These bits indicate the metal revision of the chip. This value
1255 starts at 0x00 for each all-layer tape-out and increments by one for each
1257 #define MISC_REG_CHIP_METAL 0xa404
1258 /* [R 16] These bits indicate the part number for the chip. */
1259 #define MISC_REG_CHIP_NUM 0xa408
1260 /* [R 4] These bits indicate the base revision of the chip. This value
1261 starts at 0x0 for the A0 tape-out and increments by one for each
1262 all-layer tape-out. */
1263 #define MISC_REG_CHIP_REV 0xa40c
1264 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1265 32 clients. Each client can be controlled by one driver only. One in each
1266 bit represent that this driver control the appropriate client (Ex: bit 5
1267 is set means this driver control client number 5). addr1 = set; addr0 =
1268 clear; read from both addresses will give the same result = status. write
1269 to address 1 will set a request to control all the clients that their
1270 appropriate bit (in the write command) is set. if the client is free (the
1271 appropriate bit in all the other drivers is clear) one will be written to
1272 that driver register; if the client isn't free the bit will remain zero.
1273 if the appropriate bit is set (the driver request to gain control on a
1274 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1275 interrupt will be asserted). write to address 0 will set a request to
1276 free all the clients that their appropriate bit (in the write command) is
1277 set. if the appropriate bit is clear (the driver request to free a client
1278 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1280 #define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1281 #define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1282 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1283 32 clients. Each client can be controlled by one driver only. One in each
1284 bit represent that this driver control the appropriate client (Ex: bit 5
1285 is set means this driver control client number 5). addr1 = set; addr0 =
1286 clear; read from both addresses will give the same result = status. write
1287 to address 1 will set a request to control all the clients that their
1288 appropriate bit (in the write command) is set. if the client is free (the
1289 appropriate bit in all the other drivers is clear) one will be written to
1290 that driver register; if the client isn't free the bit will remain zero.
1291 if the appropriate bit is set (the driver request to gain control on a
1292 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1293 interrupt will be asserted). write to address 0 will set a request to
1294 free all the clients that their appropriate bit (in the write command) is
1295 set. if the appropriate bit is clear (the driver request to free a client
1296 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1298 #define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1299 #define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1300 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1301 32 clients. Each client can be controlled by one driver only. One in each
1302 bit represent that this driver control the appropriate client (Ex: bit 5
1303 is set means this driver control client number 5). addr1 = set; addr0 =
1304 clear; read from both addresses will give the same result = status. write
1305 to address 1 will set a request to control all the clients that their
1306 appropriate bit (in the write command) is set. if the client is free (the
1307 appropriate bit in all the other drivers is clear) one will be written to
1308 that driver register; if the client isn't free the bit will remain zero.
1309 if the appropriate bit is set (the driver request to gain control on a
1310 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1311 interrupt will be asserted). write to address 0 will set a request to
1312 free all the clients that their appropriate bit (in the write command) is
1313 set. if the appropriate bit is clear (the driver request to free a client
1314 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1316 #define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1317 #define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1318 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1319 32 clients. Each client can be controlled by one driver only. One in each
1320 bit represent that this driver control the appropriate client (Ex: bit 5
1321 is set means this driver control client number 5). addr1 = set; addr0 =
1322 clear; read from both addresses will give the same result = status. write
1323 to address 1 will set a request to control all the clients that their
1324 appropriate bit (in the write command) is set. if the client is free (the
1325 appropriate bit in all the other drivers is clear) one will be written to
1326 that driver register; if the client isn't free the bit will remain zero.
1327 if the appropriate bit is set (the driver request to gain control on a
1328 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1329 interrupt will be asserted). write to address 0 will set a request to
1330 free all the clients that their appropriate bit (in the write command) is
1331 set. if the appropriate bit is clear (the driver request to free a client
1332 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1334 #define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1335 #define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1336 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1337 32 clients. Each client can be controlled by one driver only. One in each
1338 bit represent that this driver control the appropriate client (Ex: bit 5
1339 is set means this driver control client number 5). addr1 = set; addr0 =
1340 clear; read from both addresses will give the same result = status. write
1341 to address 1 will set a request to control all the clients that their
1342 appropriate bit (in the write command) is set. if the client is free (the
1343 appropriate bit in all the other drivers is clear) one will be written to
1344 that driver register; if the client isn't free the bit will remain zero.
1345 if the appropriate bit is set (the driver request to gain control on a
1346 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1347 interrupt will be asserted). write to address 0 will set a request to
1348 free all the clients that their appropriate bit (in the write command) is
1349 set. if the appropriate bit is clear (the driver request to free a client
1350 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1352 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1353 #define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1354 #define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1355 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1356 32 clients. Each client can be controlled by one driver only. One in each
1357 bit represent that this driver control the appropriate client (Ex: bit 5
1358 is set means this driver control client number 5). addr1 = set; addr0 =
1359 clear; read from both addresses will give the same result = status. write
1360 to address 1 will set a request to control all the clients that their
1361 appropriate bit (in the write command) is set. if the client is free (the
1362 appropriate bit in all the other drivers is clear) one will be written to
1363 that driver register; if the client isn't free the bit will remain zero.
1364 if the appropriate bit is set (the driver request to gain control on a
1365 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1366 interrupt will be asserted). write to address 0 will set a request to
1367 free all the clients that their appropriate bit (in the write command) is
1368 set. if the appropriate bit is clear (the driver request to free a client
1369 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1371 #define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1372 #define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1373 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1374 32 clients. Each client can be controlled by one driver only. One in each
1375 bit represent that this driver control the appropriate client (Ex: bit 5
1376 is set means this driver control client number 5). addr1 = set; addr0 =
1377 clear; read from both addresses will give the same result = status. write
1378 to address 1 will set a request to control all the clients that their
1379 appropriate bit (in the write command) is set. if the client is free (the
1380 appropriate bit in all the other drivers is clear) one will be written to
1381 that driver register; if the client isn't free the bit will remain zero.
1382 if the appropriate bit is set (the driver request to gain control on a
1383 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1384 interrupt will be asserted). write to address 0 will set a request to
1385 free all the clients that their appropriate bit (in the write command) is
1386 set. if the appropriate bit is clear (the driver request to free a client
1387 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1389 #define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1390 #define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1391 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1392 32 clients. Each client can be controlled by one driver only. One in each
1393 bit represent that this driver control the appropriate client (Ex: bit 5
1394 is set means this driver control client number 5). addr1 = set; addr0 =
1395 clear; read from both addresses will give the same result = status. write
1396 to address 1 will set a request to control all the clients that their
1397 appropriate bit (in the write command) is set. if the client is free (the
1398 appropriate bit in all the other drivers is clear) one will be written to
1399 that driver register; if the client isn't free the bit will remain zero.
1400 if the appropriate bit is set (the driver request to gain control on a
1401 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1402 interrupt will be asserted). write to address 0 will set a request to
1403 free all the clients that their appropriate bit (in the write command) is
1404 set. if the appropriate bit is clear (the driver request to free a client
1405 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1407 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1408 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1410 #define MISC_REG_E1HMF_MODE 0xa5f8
1411 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1412 these bits is written as a '1'; the corresponding SPIO bit will turn off
1413 it's drivers and become an input. This is the reset state of all GPIO
1414 pins. The read value of these bits will be a '1' if that last command
1415 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1416 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1417 as a '1'; the corresponding GPIO bit will drive low. The read value of
1418 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1419 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1420 SET When any of these bits is written as a '1'; the corresponding GPIO
1421 bit will drive high (if it has that capability). The read value of these
1422 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1423 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1424 RO; These bits indicate the read value of each of the eight GPIO pins.
1425 This is the result value of the pin; not the drive value. Writing these
1426 bits will have not effect. */
1427 #define MISC_REG_GPIO 0xa490
1428 /* [R 28] this field hold the last information that caused reserved
1429 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1430 [27:24] the master that caused the attention - according to the following
1431 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1433 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1434 /* [R 28] this field hold the last information that caused timeout
1435 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1436 [27:24] the master that caused the attention - according to the following
1437 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1439 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1440 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1441 access that does not finish within
1442 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1443 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1444 assert it attention output. */
1445 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1446 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1447 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1448 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1449 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1450 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1451 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1452 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1453 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1454 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1455 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1456 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1457 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1458 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1459 connected to RESET input directly. [15] capRetry_en (reset value 0)
1460 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1461 value 0) bit to continuously monitor vco freq (inverted). [17]
1462 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1463 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1464 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1465 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1466 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1467 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1468 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1469 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1470 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1471 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1472 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1474 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1475 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1476 /* [RW 4] Interrupt mask register #0 read/write */
1477 #define MISC_REG_MISC_INT_MASK 0xa388
1478 /* [RW 1] Parity mask register #0 read/write */
1479 #define MISC_REG_MISC_PRTY_MASK 0xa398
1480 /* [R 1] Parity register #0 read */
1481 #define MISC_REG_MISC_PRTY_STS 0xa38c
1482 #define MISC_REG_NIG_WOL_P0 0xa270
1483 #define MISC_REG_NIG_WOL_P1 0xa274
1484 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1486 #define MISC_REG_PCIE_HOT_RESET 0xa618
1487 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1488 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1489 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1490 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1491 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1492 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1493 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1494 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1495 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1496 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1497 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1498 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1499 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1500 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1501 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1502 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1503 testa_en (reset value 0); */
1504 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1505 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1506 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1507 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1508 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1509 write/read zero = the specific block is in reset; addr 0-wr- the write
1510 value will be written to the register; addr 1-set - one will be written
1511 to all the bits that have the value of one in the data written (bits that
1512 have the value of zero will not be change) ; addr 2-clear - zero will be
1513 written to all the bits that have the value of one in the data written
1514 (bits that have the value of zero will not be change); addr 3-ignore;
1515 read ignore from all addr except addr 00; inside order of the bits is:
1516 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1517 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1518 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1519 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1520 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1521 rst_pxp_rq_rd_wr; 31:17] reserved */
1522 #define MISC_REG_RESET_REG_2 0xa590
1523 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1524 shared with the driver resides */
1525 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1526 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1527 the corresponding SPIO bit will turn off it's drivers and become an
1528 input. This is the reset state of all SPIO pins. The read value of these
1529 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1530 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1531 is written as a '1'; the corresponding SPIO bit will drive low. The read
1532 value of these bits will be a '1' if that last command (#SET; #CLR; or
1533 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1534 these bits is written as a '1'; the corresponding SPIO bit will drive
1535 high (if it has that capability). The read value of these bits will be a
1536 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1537 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1538 each of the eight SPIO pins. This is the result value of the pin; not the
1539 drive value. Writing these bits will have not effect. Each 8 bits field
1540 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1541 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1542 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1543 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1544 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1545 select VAUX supply. (This is an output pin only; it is not controlled by
1546 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1547 field is not applicable for this pin; only the VALUE fields is relevant -
1548 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1549 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1550 device ID select; read by UMP firmware. */
1551 #define MISC_REG_SPIO 0xa4fc
1552 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1553 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1555 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1556 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1557 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1558 interrupt on the falling edge of corresponding SPIO input (reset value
1559 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1560 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1561 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1562 RO; These bits indicate the old value of the SPIO input value. When the
1563 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1564 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1565 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1566 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1567 RO; These bits indicate the current SPIO interrupt state for each SPIO
1568 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1569 command bit is written. This bit is set when the SPIO input does not
1570 match the current value in #OLD_VALUE (reset value 0). */
1571 #define MISC_REG_SPIO_INT 0xa500
1572 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1573 the counter reached zero and the reload bit
1574 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1575 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1576 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1577 in this register. addres 0 - timer 1; address - timer 2�address 7 -
1579 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1580 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1581 loaded; 0-prepare; -unprepare */
1582 #define MISC_REG_UNPREPARED 0xa424
1583 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1584 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1585 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1586 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1587 /* [RW 1] Input enable for RX_BMAC0 IF */
1588 #define NIG_REG_BMAC0_IN_EN 0x100ac
1589 /* [RW 1] output enable for TX_BMAC0 IF */
1590 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1591 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1592 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1593 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1594 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1595 /* [RW 1] output enable for RX BRB1 port0 IF */
1596 #define NIG_REG_BRB0_OUT_EN 0x100f8
1597 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1598 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1599 /* [RW 1] output enable for RX BRB1 port1 IF */
1600 #define NIG_REG_BRB1_OUT_EN 0x100fc
1601 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1602 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1603 /* [RW 1] output enable for RX BRB1 LP IF */
1604 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1605 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1606 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1607 72:73]-vnic_num; 81:74]-sideband_info */
1608 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1609 /* [RW 1] Input enable for TX Debug packet */
1610 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1611 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1612 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1613 First packet may be deleted from the middle. And last packet will be
1614 always deleted till the end. */
1615 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1616 /* [RW 1] Output enable to EMAC0 */
1617 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1618 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1619 to emac for port0; other way to bmac for port0 */
1620 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1621 /* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1622 #define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
1623 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1624 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1625 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1626 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1627 /* [RW 1] Input enable for RX_EMAC0 IF */
1628 #define NIG_REG_EMAC0_IN_EN 0x100a4
1629 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1630 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1631 /* [R 1] status from emac0. This bit is set when MDINT from either the
1632 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1633 be cleared in the attached PHY device that is driving the MINT pin. */
1634 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1635 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1636 are described in appendix A. In order to access the BMAC0 registers; the
1637 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1638 added to each BMAC register offset */
1639 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1640 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1641 are described in appendix A. In order to access the BMAC0 registers; the
1642 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1643 added to each BMAC register offset */
1644 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1645 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1646 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1647 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1648 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1649 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1650 /* [RW 1] led 10g for port 0 */
1651 #define NIG_REG_LED_10G_P0 0x10320
1652 /* [RW 1] led 10g for port 1 */
1653 #define NIG_REG_LED_10G_P1 0x10324
1654 /* [RW 1] Port0: This bit is set to enable the use of the
1655 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1656 defined below. If this bit is cleared; then the blink rate will be about
1658 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1659 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1660 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1661 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1662 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1663 /* [RW 1] Port0: If set along with the
1664 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1665 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1666 bit; the Traffic LED will blink with the blink rate specified in
1667 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1668 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1670 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1671 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1672 Traffic LED will then be controlled via bit ~nig_registers_
1673 led_control_traffic_p0.led_control_traffic_p0 and bit
1674 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1675 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1676 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1677 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1678 set; the LED will blink with blink rate specified in
1679 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1680 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1682 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1683 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1684 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1685 #define NIG_REG_LED_MODE_P0 0x102f0
1686 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1687 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1688 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1689 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1690 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1691 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1692 /* [RW 2] Determine the classification participants. 0: no classification.1:
1693 classification upon VLAN id. 2: classification upon MAC address. 3:
1694 classification upon both VLAN id & MAC addr. */
1695 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1696 /* [RW 32] cm header for llh0 */
1697 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1698 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1699 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1700 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1701 all incoming packets. */
1702 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1703 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1704 all incoming packets. */
1705 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1706 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1707 /* [RW 8] event id for llh0 */
1708 #define NIG_REG_LLH0_EVENT_ID 0x10084
1709 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1710 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1711 /* [RW 1] Determine the IP version to look for in
1712 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1713 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1714 /* [RW 1] t bit for llh0 */
1715 #define NIG_REG_LLH0_T_BIT 0x10074
1716 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1717 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1718 /* [RW 8] init credit counter for port0 in LLH */
1719 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1720 #define NIG_REG_LLH0_XCM_MASK 0x10130
1721 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1722 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1723 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1724 /* [RW 2] Determine the classification participants. 0: no classification.1:
1725 classification upon VLAN id. 2: classification upon MAC address. 3:
1726 classification upon both VLAN id & MAC addr. */
1727 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1728 /* [RW 32] cm header for llh1 */
1729 #define NIG_REG_LLH1_CM_HEADER 0x10080
1730 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1731 /* [RW 8] event id for llh1 */
1732 #define NIG_REG_LLH1_EVENT_ID 0x10088
1733 /* [RW 8] init credit counter for port1 in LLH */
1734 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1735 #define NIG_REG_LLH1_XCM_MASK 0x10134
1736 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1738 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1739 /* [RW 1] When this bit is set; the LLH will classify the packet before
1740 sending it to the BRB or calculating WoL on it. */
1741 #define NIG_REG_LLH_MF_MODE 0x16024
1742 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1743 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1744 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1745 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1746 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1747 #define NIG_REG_NIG_EMAC1_EN 0x10040
1748 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1749 EMAC0 to strip the CRC from the ingress packets. */
1750 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1751 /* [R 32] Interrupt register #0 read */
1752 #define NIG_REG_NIG_INT_STS_0 0x103b0
1753 #define NIG_REG_NIG_INT_STS_1 0x103c0
1754 /* [R 32] Parity register #0 read */
1755 #define NIG_REG_NIG_PRTY_STS 0x103d0
1756 /* [RW 1] Input enable for RX PBF LP IF */
1757 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1758 /* [RW 1] Value of this register will be transmitted to port swap when
1759 ~nig_registers_strap_override.strap_override =1 */
1760 #define NIG_REG_PORT_SWAP 0x10394
1761 /* [RW 1] output enable for RX parser descriptor IF */
1762 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1763 /* [RW 1] Input enable for RX parser request IF */
1764 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1765 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1766 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1767 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1768 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1769 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1771 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1772 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1774 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1775 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1776 between 1024 and 1522 bytes for port0 */
1777 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1778 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1779 between 1523 bytes and above for port0 */
1780 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1781 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1783 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1784 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1785 between 1024 and 1522 bytes for port1 */
1786 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1787 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1788 between 1523 bytes and above for port1 */
1789 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1790 /* [WB_R 64] Rx statistics : User octets received for LP */
1791 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1792 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1793 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1794 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1795 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1796 ort swap is equal to ~nig_registers_port_swap.port_swap */
1797 #define NIG_REG_STRAP_OVERRIDE 0x10398
1798 /* [RW 1] output enable for RX_XCM0 IF */
1799 #define NIG_REG_XCM0_OUT_EN 0x100f0
1800 /* [RW 1] output enable for RX_XCM1 IF */
1801 #define NIG_REG_XCM1_OUT_EN 0x100f4
1802 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
1803 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
1804 /* [RW 5] control to xgxs - CL45 DEVAD */
1805 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1806 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1807 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
1808 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1809 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1810 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1811 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1812 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1813 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1814 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1815 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1816 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1817 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1818 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1819 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1820 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1821 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1822 /* [RW 1] Disable processing further tasks from port 0 (after ending the
1823 current task in process). */
1824 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1825 /* [RW 1] Disable processing further tasks from port 1 (after ending the
1826 current task in process). */
1827 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1828 /* [RW 1] Disable processing further tasks from port 4 (after ending the
1829 current task in process). */
1830 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1831 #define PBF_REG_IF_ENABLE_REG 0x140044
1832 /* [RW 1] Init bit. When set the initial credits are copied to the credit
1833 registers (except the port credits). Should be set and then reset after
1834 the configuration of the block has ended. */
1835 #define PBF_REG_INIT 0x140000
1836 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1837 copied to the credit register. Should be set and then reset after the
1838 configuration of the port has ended. */
1839 #define PBF_REG_INIT_P0 0x140004
1840 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1841 copied to the credit register. Should be set and then reset after the
1842 configuration of the port has ended. */
1843 #define PBF_REG_INIT_P1 0x140008
1844 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1845 copied to the credit register. Should be set and then reset after the
1846 configuration of the port has ended. */
1847 #define PBF_REG_INIT_P4 0x14000c
1848 /* [RW 1] Enable for mac interface 0. */
1849 #define PBF_REG_MAC_IF0_ENABLE 0x140030
1850 /* [RW 1] Enable for mac interface 1. */
1851 #define PBF_REG_MAC_IF1_ENABLE 0x140034
1852 /* [RW 1] Enable for the loopback interface. */
1853 #define PBF_REG_MAC_LB_ENABLE 0x140040
1854 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1856 #define PBF_REG_P0_ARB_THRSH 0x1400e4
1857 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1858 #define PBF_REG_P0_CREDIT 0x140200
1859 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1861 #define PBF_REG_P0_INIT_CRD 0x1400d0
1862 /* [RW 1] Indication that pause is enabled for port 0. */
1863 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
1864 /* [R 8] Number of tasks in port 0 task queue. */
1865 #define PBF_REG_P0_TASK_CNT 0x140204
1866 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1867 #define PBF_REG_P1_CREDIT 0x140208
1868 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1870 #define PBF_REG_P1_INIT_CRD 0x1400d4
1871 /* [R 8] Number of tasks in port 1 task queue. */
1872 #define PBF_REG_P1_TASK_CNT 0x14020c
1873 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1874 #define PBF_REG_P4_CREDIT 0x140210
1875 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1877 #define PBF_REG_P4_INIT_CRD 0x1400e0
1878 /* [R 8] Number of tasks in port 4 task queue. */
1879 #define PBF_REG_P4_TASK_CNT 0x140214
1880 /* [RW 5] Interrupt mask register #0 read/write */
1881 #define PBF_REG_PBF_INT_MASK 0x1401d4
1882 /* [R 5] Interrupt register #0 read */
1883 #define PBF_REG_PBF_INT_STS 0x1401c8
1884 #define PB_REG_CONTROL 0
1885 /* [RW 2] Interrupt mask register #0 read/write */
1886 #define PB_REG_PB_INT_MASK 0x28
1887 /* [R 2] Interrupt register #0 read */
1888 #define PB_REG_PB_INT_STS 0x1c
1889 /* [RW 4] Parity mask register #0 read/write */
1890 #define PB_REG_PB_PRTY_MASK 0x38
1891 /* [R 4] Parity register #0 read */
1892 #define PB_REG_PB_PRTY_STS 0x2c
1893 #define PRS_REG_A_PRSU_20 0x40134
1894 /* [R 8] debug only: CFC load request current credit. Transaction based. */
1895 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1896 /* [R 8] debug only: CFC search request current credit. Transaction based. */
1897 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1898 /* [RW 6] The initial credit for the search message to the CFC interface.
1899 Credit is transaction based. */
1900 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1901 /* [RW 24] CID for port 0 if no match */
1902 #define PRS_REG_CID_PORT_0 0x400fc
1903 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1904 load response is reset and packet type is 0. Used in packet start message
1906 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1907 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1908 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1909 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1910 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1911 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
1912 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1913 load response is set and packet type is 0. Used in packet start message
1915 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1916 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1917 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1918 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1919 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1920 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
1921 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
1922 Used in packet start message to TCM. */
1923 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1924 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1925 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1926 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1927 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
1929 #define PRS_REG_CM_HDR_TYPE_0 0x40078
1930 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
1931 #define PRS_REG_CM_HDR_TYPE_2 0x40080
1932 #define PRS_REG_CM_HDR_TYPE_3 0x40084
1933 #define PRS_REG_CM_HDR_TYPE_4 0x40088
1934 /* [RW 32] The CM header in case there was not a match on the connection */
1935 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1936 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
1937 #define PRS_REG_E1HOV_MODE 0x401c8
1938 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1939 start message to TCM. */
1940 #define PRS_REG_EVENT_ID_1 0x40054
1941 #define PRS_REG_EVENT_ID_2 0x40058
1942 #define PRS_REG_EVENT_ID_3 0x4005c
1943 /* [RW 16] The Ethernet type value for FCoE */
1944 #define PRS_REG_FCOE_TYPE 0x401d0
1945 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1946 load request message. */
1947 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1948 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1949 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1950 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1951 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1952 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1953 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1954 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1955 /* [RW 4] The increment value to send in the CFC load request message */
1956 #define PRS_REG_INC_VALUE 0x40048
1957 /* [RW 1] If set indicates not to send messages to CFC on received packets */
1958 #define PRS_REG_NIC_MODE 0x40138
1959 /* [RW 8] The 8-bit event ID for cases where there is no match on the
1960 connection. Used in packet start message to TCM. */
1961 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1962 /* [ST 24] The number of input CFC flush packets */
1963 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1964 /* [ST 32] The number of cycles the Parser halted its operation since it
1965 could not allocate the next serial number */
1966 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1967 /* [ST 24] The number of input packets */
1968 #define PRS_REG_NUM_OF_PACKETS 0x40124
1969 /* [ST 24] The number of input transparent flush packets */
1970 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
1971 /* [RW 8] Context region for received Ethernet packet with a match and
1972 packet type 0. Used in CFC load request message */
1973 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
1974 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
1975 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
1976 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
1977 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
1978 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
1979 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
1980 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
1981 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
1982 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
1983 /* [R 2] debug only: Number of pending requests for header parsing. */
1984 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
1985 /* [R 1] Interrupt register #0 read */
1986 #define PRS_REG_PRS_INT_STS 0x40188
1987 /* [RW 8] Parity mask register #0 read/write */
1988 #define PRS_REG_PRS_PRTY_MASK 0x401a4
1989 /* [R 8] Parity register #0 read */
1990 #define PRS_REG_PRS_PRTY_STS 0x40198
1991 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
1993 #define PRS_REG_PURE_REGIONS 0x40024
1994 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
1995 serail number was released by SDM but cannot be used because a previous
1996 serial number was not released. */
1997 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
1998 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
1999 serail number was released by SDM but cannot be used because a previous
2000 serial number was not released. */
2001 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2002 /* [R 4] debug only: SRC current credit. Transaction based. */
2003 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2004 /* [R 8] debug only: TCM current credit. Cycle based. */
2005 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2006 /* [R 8] debug only: TSDM current credit. Transaction based. */
2007 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2008 /* [R 6] Debug only: Number of used entries in the data FIFO */
2009 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2010 /* [R 7] Debug only: Number of used entries in the header FIFO */
2011 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
2012 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
2013 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2014 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2015 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
2016 #define PXP2_REG_PGL_CONTROL0 0x120490
2017 #define PXP2_REG_PGL_CONTROL1 0x120514
2018 /* [RW 32] third dword data of expansion rom request. this register is
2019 special. reading from it provides a vector outstanding read requests. if
2020 a bit is zero it means that a read request on the corresponding tag did
2021 not finish yet (not all completions have arrived for it) */
2022 #define PXP2_REG_PGL_EXP_ROM2 0x120808
2023 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2024 its[15:0]-address */
2025 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2026 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2027 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2028 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
2029 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
2030 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
2031 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2032 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
2033 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2034 its[15:0]-address */
2035 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
2036 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
2037 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2038 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2039 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2040 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2041 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2042 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2043 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2044 its[15:0]-address */
2045 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2046 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2047 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2048 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2049 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2050 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2051 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2052 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2053 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2054 its[15:0]-address */
2055 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2056 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2057 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2058 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2059 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2060 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2061 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2062 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2063 /* [R 1] this bit indicates that a read request was blocked because of
2064 bus_master_en was deasserted */
2065 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
2066 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
2067 /* [R 18] debug only */
2068 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
2069 /* [R 1] this bit indicates that a write request was blocked because of
2070 bus_master_en was deasserted */
2071 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2072 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2073 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2074 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2075 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2076 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2077 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2078 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2079 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2080 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2081 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2082 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2083 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2084 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2085 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2086 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2087 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2088 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2089 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2090 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2091 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2092 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2093 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2094 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2095 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2096 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2097 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2098 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2099 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2100 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2101 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2102 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2103 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2104 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2105 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2106 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2107 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2108 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2109 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2110 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2111 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2112 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2113 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2114 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2115 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2116 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2117 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2118 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2119 /* [RW 32] Interrupt mask register #0 read/write */
2120 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2121 /* [R 32] Interrupt register #0 read */
2122 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2123 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2124 /* [RC 32] Interrupt register #0 read clear */
2125 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2126 /* [RW 32] Parity mask register #0 read/write */
2127 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2128 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2129 /* [R 32] Parity register #0 read */
2130 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2131 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2132 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2133 indication about backpressure) */
2134 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2135 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2136 #define PXP2_REG_RD_BLK_CNT 0x120418
2137 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2138 Must be bigger than 6. Normally should not be changed. */
2139 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2140 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2141 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2142 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2143 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2144 /* [R 1] PSWRD internal memories initialization is done */
2145 #define PXP2_REG_RD_INIT_DONE 0x120370
2146 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2147 allocated for vq10 */
2148 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2149 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2150 allocated for vq11 */
2151 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2152 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2153 allocated for vq17 */
2154 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2155 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2156 allocated for vq18 */
2157 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2158 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2159 allocated for vq19 */
2160 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2161 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2162 allocated for vq22 */
2163 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2164 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2165 allocated for vq6 */
2166 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2167 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2168 allocated for vq9 */
2169 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2170 /* [RW 2] PBF byte swapping mode configuration for master read requests */
2171 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2172 /* [R 1] Debug only: Indication if delivery ports are idle */
2173 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2174 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2175 /* [RW 2] QM byte swapping mode configuration for master read requests */
2176 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2177 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
2178 #define PXP2_REG_RD_SR_CNT 0x120414
2179 /* [RW 2] SRC byte swapping mode configuration for master read requests */
2180 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2181 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2182 be bigger than 1. Normally should not be changed. */
2183 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
2184 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
2185 #define PXP2_REG_RD_START_INIT 0x12036c
2186 /* [RW 2] TM byte swapping mode configuration for master read requests */
2187 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2188 /* [RW 10] Bandwidth addition to VQ0 write requests */
2189 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2190 /* [RW 10] Bandwidth addition to VQ12 read requests */
2191 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2192 /* [RW 10] Bandwidth addition to VQ13 read requests */
2193 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2194 /* [RW 10] Bandwidth addition to VQ14 read requests */
2195 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2196 /* [RW 10] Bandwidth addition to VQ15 read requests */
2197 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2198 /* [RW 10] Bandwidth addition to VQ16 read requests */
2199 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2200 /* [RW 10] Bandwidth addition to VQ17 read requests */
2201 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2202 /* [RW 10] Bandwidth addition to VQ18 read requests */
2203 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2204 /* [RW 10] Bandwidth addition to VQ19 read requests */
2205 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2206 /* [RW 10] Bandwidth addition to VQ20 read requests */
2207 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2208 /* [RW 10] Bandwidth addition to VQ22 read requests */
2209 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2210 /* [RW 10] Bandwidth addition to VQ23 read requests */
2211 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2212 /* [RW 10] Bandwidth addition to VQ24 read requests */
2213 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2214 /* [RW 10] Bandwidth addition to VQ25 read requests */
2215 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2216 /* [RW 10] Bandwidth addition to VQ26 read requests */
2217 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2218 /* [RW 10] Bandwidth addition to VQ27 read requests */
2219 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2220 /* [RW 10] Bandwidth addition to VQ4 read requests */
2221 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2222 /* [RW 10] Bandwidth addition to VQ5 read requests */
2223 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2224 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2225 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2226 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2227 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2228 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2229 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2230 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2231 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2232 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2233 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2234 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2235 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2236 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2237 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2238 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2239 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2240 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2241 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2242 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2243 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2244 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2245 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2246 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2247 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2248 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2249 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2250 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2251 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2252 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2253 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2254 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2255 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2256 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2257 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2258 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2259 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2260 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2261 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2262 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2263 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2264 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2265 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2266 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2267 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2268 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2269 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2270 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2271 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2272 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2273 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2274 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2275 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2276 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2277 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2278 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2279 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2280 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2281 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2282 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2283 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2284 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2285 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2286 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2287 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2288 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2289 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2290 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2291 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2292 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2293 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2294 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2295 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2296 /* [RW 10] Bandwidth addition to VQ29 write requests */
2297 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2298 /* [RW 10] Bandwidth addition to VQ30 write requests */
2299 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2300 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2301 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2302 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2303 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2304 /* [RW 7] Bandwidth upper bound for VQ29 */
2305 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2306 /* [RW 7] Bandwidth upper bound for VQ30 */
2307 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2308 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2309 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2310 /* [RW 2] Endian mode for cdu */
2311 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2312 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2313 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2314 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2316 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2317 /* [R 1] 1' indicates that the requester has finished its internal
2319 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2320 /* [RW 2] Endian mode for debug */
2321 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2322 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2324 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2325 /* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2326 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2327 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2329 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2330 /* [RW 2] Endian mode for hc */
2331 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2332 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2333 compatibility needs; Note that different registers are used per mode */
2334 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
2335 /* [WB 53] Onchip address table */
2336 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2337 /* [WB 53] Onchip address table - B0 */
2338 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2339 /* [RW 13] Pending read limiter threshold; in Dwords */
2340 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2341 /* [RW 2] Endian mode for qm */
2342 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2343 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2344 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2345 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2347 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2348 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2349 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2350 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2351 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2352 #define PXP2_REG_RQ_RD_MBS0 0x120160
2353 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2354 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2355 #define PXP2_REG_RQ_RD_MBS1 0x120168
2356 /* [RW 2] Endian mode for src */
2357 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2358 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2359 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2360 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2362 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2363 /* [RW 2] Endian mode for tm */
2364 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2365 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2366 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2367 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2369 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2370 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2371 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2372 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2373 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2374 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2375 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2376 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2377 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2378 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2379 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2380 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2381 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2382 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2383 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2384 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2385 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2386 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2387 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2388 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2389 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2390 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2391 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2392 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2393 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2394 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2395 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2396 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2397 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2398 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2399 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2400 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2401 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2402 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2403 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2404 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2405 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2406 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2407 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2408 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2409 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2410 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2411 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2412 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2413 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2414 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2415 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2416 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2417 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2418 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2419 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2420 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2421 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2422 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2423 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2424 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2425 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2426 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2427 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2428 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2429 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2430 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2431 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2432 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2433 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2434 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2435 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2436 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2437 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2438 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2439 001:256B; 010: 512B; */
2440 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2441 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2442 001:256B; 010: 512B; */
2443 #define PXP2_REG_RQ_WR_MBS1 0x120164
2444 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2445 buffer reaches this number has_payload will be asserted */
2446 #define PXP2_REG_WR_CDU_MPS 0x1205f0
2447 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2448 buffer reaches this number has_payload will be asserted */
2449 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
2450 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2451 buffer reaches this number has_payload will be asserted */
2452 #define PXP2_REG_WR_DBG_MPS 0x1205e8
2453 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2454 buffer reaches this number has_payload will be asserted */
2455 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
2456 /* [RW 10] if Number of entries in dmae fifo will be higher than this
2457 threshold then has_payload indication will be asserted; the default value
2458 should be equal to > write MBS size! */
2459 #define PXP2_REG_WR_DMAE_TH 0x120368
2460 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2461 buffer reaches this number has_payload will be asserted */
2462 #define PXP2_REG_WR_HC_MPS 0x1205c8
2463 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2464 buffer reaches this number has_payload will be asserted */
2465 #define PXP2_REG_WR_QM_MPS 0x1205dc
2466 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2467 #define PXP2_REG_WR_REV_MODE 0x120670
2468 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2469 buffer reaches this number has_payload will be asserted */
2470 #define PXP2_REG_WR_SRC_MPS 0x1205e4
2471 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2472 buffer reaches this number has_payload will be asserted */
2473 #define PXP2_REG_WR_TM_MPS 0x1205e0
2474 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2475 buffer reaches this number has_payload will be asserted */
2476 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
2477 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
2478 threshold then has_payload indication will be asserted; the default value
2479 should be equal to > write MBS size! */
2480 #define PXP2_REG_WR_USDMDP_TH 0x120348
2481 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2482 buffer reaches this number has_payload will be asserted */
2483 #define PXP2_REG_WR_USDM_MPS 0x1205cc
2484 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2485 buffer reaches this number has_payload will be asserted */
2486 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
2487 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2488 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2489 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2490 this client is waiting for the arbiter. */
2491 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2492 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2493 should update accoring to 'hst_discard_doorbells' register when the state
2495 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2496 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2497 means this PSWHST is discarding inputs from this client. Each bit should
2498 update accoring to 'hst_discard_internal_writes' register when the state
2500 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
2501 /* [WB 160] Used for initialization of the inbound interrupts memory */
2502 #define PXP_REG_HST_INBOUND_INT 0x103800
2503 /* [RW 32] Interrupt mask register #0 read/write */
2504 #define PXP_REG_PXP_INT_MASK_0 0x103074
2505 #define PXP_REG_PXP_INT_MASK_1 0x103084
2506 /* [R 32] Interrupt register #0 read */
2507 #define PXP_REG_PXP_INT_STS_0 0x103068
2508 #define PXP_REG_PXP_INT_STS_1 0x103078
2509 /* [RC 32] Interrupt register #0 read clear */
2510 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2511 /* [RW 26] Parity mask register #0 read/write */
2512 #define PXP_REG_PXP_PRTY_MASK 0x103094
2513 /* [R 26] Parity register #0 read */
2514 #define PXP_REG_PXP_PRTY_STS 0x103088
2515 /* [RW 4] The activity counter initial increment value sent in the load
2517 #define QM_REG_ACTCTRINITVAL_0 0x168040
2518 #define QM_REG_ACTCTRINITVAL_1 0x168044
2519 #define QM_REG_ACTCTRINITVAL_2 0x168048
2520 #define QM_REG_ACTCTRINITVAL_3 0x16804c
2521 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2522 index I represents the physical queue number. The 12 lsbs are ignore and
2523 considered zero so practically there are only 20 bits in this register;
2525 #define QM_REG_BASEADDR 0x168900
2526 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2527 index I represents the physical queue number. The 12 lsbs are ignore and
2528 considered zero so practically there are only 20 bits in this register;
2530 #define QM_REG_BASEADDR_EXT_A 0x16e100
2531 /* [RW 16] The byte credit cost for each task. This value is for both ports */
2532 #define QM_REG_BYTECRDCOST 0x168234
2533 /* [RW 16] The initial byte credit value for both ports. */
2534 #define QM_REG_BYTECRDINITVAL 0x168238
2535 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2536 queue uses port 0 else it uses port 1; queues 31-0 */
2537 #define QM_REG_BYTECRDPORT_LSB 0x168228
2538 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2539 queue uses port 0 else it uses port 1; queues 95-64 */
2540 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2541 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2542 queue uses port 0 else it uses port 1; queues 63-32 */
2543 #define QM_REG_BYTECRDPORT_MSB 0x168224
2544 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2545 queue uses port 0 else it uses port 1; queues 127-96 */
2546 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
2547 /* [RW 16] The byte credit value that if above the QM is considered almost
2549 #define QM_REG_BYTECREDITAFULLTHR 0x168094
2550 /* [RW 4] The initial credit for interface */
2551 #define QM_REG_CMINITCRD_0 0x1680cc
2552 #define QM_REG_CMINITCRD_1 0x1680d0
2553 #define QM_REG_CMINITCRD_2 0x1680d4
2554 #define QM_REG_CMINITCRD_3 0x1680d8
2555 #define QM_REG_CMINITCRD_4 0x1680dc
2556 #define QM_REG_CMINITCRD_5 0x1680e0
2557 #define QM_REG_CMINITCRD_6 0x1680e4
2558 #define QM_REG_CMINITCRD_7 0x1680e8
2559 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2561 #define QM_REG_CMINTEN 0x1680ec
2562 /* [RW 12] A bit vector which indicates which one of the queues are tied to
2564 #define QM_REG_CMINTVOQMASK_0 0x1681f4
2565 #define QM_REG_CMINTVOQMASK_1 0x1681f8
2566 #define QM_REG_CMINTVOQMASK_2 0x1681fc
2567 #define QM_REG_CMINTVOQMASK_3 0x168200
2568 #define QM_REG_CMINTVOQMASK_4 0x168204
2569 #define QM_REG_CMINTVOQMASK_5 0x168208
2570 #define QM_REG_CMINTVOQMASK_6 0x16820c
2571 #define QM_REG_CMINTVOQMASK_7 0x168210
2572 /* [RW 20] The number of connections divided by 16 which dictates the size
2573 of each queue which belongs to even function number. */
2574 #define QM_REG_CONNNUM_0 0x168020
2575 /* [R 6] Keep the fill level of the fifo from write client 4 */
2576 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
2577 /* [RW 8] The context regions sent in the CFC load request */
2578 #define QM_REG_CTXREG_0 0x168030
2579 #define QM_REG_CTXREG_1 0x168034
2580 #define QM_REG_CTXREG_2 0x168038
2581 #define QM_REG_CTXREG_3 0x16803c
2582 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2584 #define QM_REG_ENBYPVOQMASK 0x16823c
2585 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2586 physical queue uses the byte credit; queues 31-0 */
2587 #define QM_REG_ENBYTECRD_LSB 0x168220
2588 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2589 physical queue uses the byte credit; queues 95-64 */
2590 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2591 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2592 physical queue uses the byte credit; queues 63-32 */
2593 #define QM_REG_ENBYTECRD_MSB 0x16821c
2594 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2595 physical queue uses the byte credit; queues 127-96 */
2596 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
2597 /* [RW 4] If cleared then the secondary interface will not be served by the
2599 #define QM_REG_ENSEC 0x1680f0
2601 #define QM_REG_FUNCNUMSEL_LSB 0x168230
2603 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
2604 /* [RW 32] A mask register to mask the Almost empty signals which will not
2605 be use for the almost empty indication to the HW block; queues 31:0 */
2606 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
2607 /* [RW 32] A mask register to mask the Almost empty signals which will not
2608 be use for the almost empty indication to the HW block; queues 95-64 */
2609 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2610 /* [RW 32] A mask register to mask the Almost empty signals which will not
2611 be use for the almost empty indication to the HW block; queues 63:32 */
2612 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
2613 /* [RW 32] A mask register to mask the Almost empty signals which will not
2614 be use for the almost empty indication to the HW block; queues 127-96 */
2615 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
2616 /* [RW 4] The number of outstanding request to CFC */
2617 #define QM_REG_OUTLDREQ 0x168804
2618 /* [RC 1] A flag to indicate that overflow error occurred in one of the
2620 #define QM_REG_OVFERROR 0x16805c
2621 /* [RC 7] the Q were the qverflow occurs */
2622 #define QM_REG_OVFQNUM 0x168058
2623 /* [R 16] Pause state for physical queues 15-0 */
2624 #define QM_REG_PAUSESTATE0 0x168410
2625 /* [R 16] Pause state for physical queues 31-16 */
2626 #define QM_REG_PAUSESTATE1 0x168414
2627 /* [R 16] Pause state for physical queues 47-32 */
2628 #define QM_REG_PAUSESTATE2 0x16e684
2629 /* [R 16] Pause state for physical queues 63-48 */
2630 #define QM_REG_PAUSESTATE3 0x16e688
2631 /* [R 16] Pause state for physical queues 79-64 */
2632 #define QM_REG_PAUSESTATE4 0x16e68c
2633 /* [R 16] Pause state for physical queues 95-80 */
2634 #define QM_REG_PAUSESTATE5 0x16e690
2635 /* [R 16] Pause state for physical queues 111-96 */
2636 #define QM_REG_PAUSESTATE6 0x16e694
2637 /* [R 16] Pause state for physical queues 127-112 */
2638 #define QM_REG_PAUSESTATE7 0x16e698
2639 /* [RW 2] The PCI attributes field used in the PCI request. */
2640 #define QM_REG_PCIREQAT 0x168054
2641 /* [R 16] The byte credit of port 0 */
2642 #define QM_REG_PORT0BYTECRD 0x168300
2643 /* [R 16] The byte credit of port 1 */
2644 #define QM_REG_PORT1BYTECRD 0x168304
2645 /* [RW 3] pci function number of queues 15-0 */
2646 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2647 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2648 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2649 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2650 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2651 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2652 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2653 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2654 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2655 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2656 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2657 #define QM_REG_PTRTBL 0x168a00
2658 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2659 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2660 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2661 #define QM_REG_PTRTBL_EXT_A 0x16e200
2662 /* [RW 2] Interrupt mask register #0 read/write */
2663 #define QM_REG_QM_INT_MASK 0x168444
2664 /* [R 2] Interrupt register #0 read */
2665 #define QM_REG_QM_INT_STS 0x168438
2666 /* [RW 12] Parity mask register #0 read/write */
2667 #define QM_REG_QM_PRTY_MASK 0x168454
2668 /* [R 12] Parity register #0 read */
2669 #define QM_REG_QM_PRTY_STS 0x168448
2670 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2671 #define QM_REG_QSTATUS_HIGH 0x16802c
2672 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2673 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
2674 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2675 #define QM_REG_QSTATUS_LOW 0x168028
2676 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2677 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2678 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
2679 #define QM_REG_QTASKCTR_0 0x168308
2680 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
2681 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
2682 /* [RW 4] Queue tied to VOQ */
2683 #define QM_REG_QVOQIDX_0 0x1680f4
2684 #define QM_REG_QVOQIDX_10 0x16811c
2685 #define QM_REG_QVOQIDX_100 0x16e49c
2686 #define QM_REG_QVOQIDX_101 0x16e4a0
2687 #define QM_REG_QVOQIDX_102 0x16e4a4
2688 #define QM_REG_QVOQIDX_103 0x16e4a8
2689 #define QM_REG_QVOQIDX_104 0x16e4ac
2690 #define QM_REG_QVOQIDX_105 0x16e4b0
2691 #define QM_REG_QVOQIDX_106 0x16e4b4
2692 #define QM_REG_QVOQIDX_107 0x16e4b8
2693 #define QM_REG_QVOQIDX_108 0x16e4bc
2694 #define QM_REG_QVOQIDX_109 0x16e4c0
2695 #define QM_REG_QVOQIDX_100 0x16e49c
2696 #define QM_REG_QVOQIDX_101 0x16e4a0
2697 #define QM_REG_QVOQIDX_102 0x16e4a4
2698 #define QM_REG_QVOQIDX_103 0x16e4a8
2699 #define QM_REG_QVOQIDX_104 0x16e4ac
2700 #define QM_REG_QVOQIDX_105 0x16e4b0
2701 #define QM_REG_QVOQIDX_106 0x16e4b4
2702 #define QM_REG_QVOQIDX_107 0x16e4b8
2703 #define QM_REG_QVOQIDX_108 0x16e4bc
2704 #define QM_REG_QVOQIDX_109 0x16e4c0
2705 #define QM_REG_QVOQIDX_11 0x168120
2706 #define QM_REG_QVOQIDX_110 0x16e4c4
2707 #define QM_REG_QVOQIDX_111 0x16e4c8
2708 #define QM_REG_QVOQIDX_112 0x16e4cc
2709 #define QM_REG_QVOQIDX_113 0x16e4d0
2710 #define QM_REG_QVOQIDX_114 0x16e4d4
2711 #define QM_REG_QVOQIDX_115 0x16e4d8
2712 #define QM_REG_QVOQIDX_116 0x16e4dc
2713 #define QM_REG_QVOQIDX_117 0x16e4e0
2714 #define QM_REG_QVOQIDX_118 0x16e4e4
2715 #define QM_REG_QVOQIDX_119 0x16e4e8
2716 #define QM_REG_QVOQIDX_110 0x16e4c4
2717 #define QM_REG_QVOQIDX_111 0x16e4c8
2718 #define QM_REG_QVOQIDX_112 0x16e4cc
2719 #define QM_REG_QVOQIDX_113 0x16e4d0
2720 #define QM_REG_QVOQIDX_114 0x16e4d4
2721 #define QM_REG_QVOQIDX_115 0x16e4d8
2722 #define QM_REG_QVOQIDX_116 0x16e4dc
2723 #define QM_REG_QVOQIDX_117 0x16e4e0
2724 #define QM_REG_QVOQIDX_118 0x16e4e4
2725 #define QM_REG_QVOQIDX_119 0x16e4e8
2726 #define QM_REG_QVOQIDX_12 0x168124
2727 #define QM_REG_QVOQIDX_120 0x16e4ec
2728 #define QM_REG_QVOQIDX_121 0x16e4f0
2729 #define QM_REG_QVOQIDX_122 0x16e4f4
2730 #define QM_REG_QVOQIDX_123 0x16e4f8
2731 #define QM_REG_QVOQIDX_124 0x16e4fc
2732 #define QM_REG_QVOQIDX_125 0x16e500
2733 #define QM_REG_QVOQIDX_126 0x16e504
2734 #define QM_REG_QVOQIDX_127 0x16e508
2735 #define QM_REG_QVOQIDX_120 0x16e4ec
2736 #define QM_REG_QVOQIDX_121 0x16e4f0
2737 #define QM_REG_QVOQIDX_122 0x16e4f4
2738 #define QM_REG_QVOQIDX_123 0x16e4f8
2739 #define QM_REG_QVOQIDX_124 0x16e4fc
2740 #define QM_REG_QVOQIDX_125 0x16e500
2741 #define QM_REG_QVOQIDX_126 0x16e504
2742 #define QM_REG_QVOQIDX_127 0x16e508
2743 #define QM_REG_QVOQIDX_13 0x168128
2744 #define QM_REG_QVOQIDX_14 0x16812c
2745 #define QM_REG_QVOQIDX_15 0x168130
2746 #define QM_REG_QVOQIDX_16 0x168134
2747 #define QM_REG_QVOQIDX_17 0x168138
2748 #define QM_REG_QVOQIDX_21 0x168148
2749 #define QM_REG_QVOQIDX_22 0x16814c
2750 #define QM_REG_QVOQIDX_23 0x168150
2751 #define QM_REG_QVOQIDX_24 0x168154
2752 #define QM_REG_QVOQIDX_25 0x168158
2753 #define QM_REG_QVOQIDX_26 0x16815c
2754 #define QM_REG_QVOQIDX_27 0x168160
2755 #define QM_REG_QVOQIDX_28 0x168164
2756 #define QM_REG_QVOQIDX_29 0x168168
2757 #define QM_REG_QVOQIDX_30 0x16816c
2758 #define QM_REG_QVOQIDX_31 0x168170
2759 #define QM_REG_QVOQIDX_32 0x168174
2760 #define QM_REG_QVOQIDX_33 0x168178
2761 #define QM_REG_QVOQIDX_34 0x16817c
2762 #define QM_REG_QVOQIDX_35 0x168180
2763 #define QM_REG_QVOQIDX_36 0x168184
2764 #define QM_REG_QVOQIDX_37 0x168188
2765 #define QM_REG_QVOQIDX_38 0x16818c
2766 #define QM_REG_QVOQIDX_39 0x168190
2767 #define QM_REG_QVOQIDX_40 0x168194
2768 #define QM_REG_QVOQIDX_41 0x168198
2769 #define QM_REG_QVOQIDX_42 0x16819c
2770 #define QM_REG_QVOQIDX_43 0x1681a0
2771 #define QM_REG_QVOQIDX_44 0x1681a4
2772 #define QM_REG_QVOQIDX_45 0x1681a8
2773 #define QM_REG_QVOQIDX_46 0x1681ac
2774 #define QM_REG_QVOQIDX_47 0x1681b0
2775 #define QM_REG_QVOQIDX_48 0x1681b4
2776 #define QM_REG_QVOQIDX_49 0x1681b8
2777 #define QM_REG_QVOQIDX_5 0x168108
2778 #define QM_REG_QVOQIDX_50 0x1681bc
2779 #define QM_REG_QVOQIDX_51 0x1681c0
2780 #define QM_REG_QVOQIDX_52 0x1681c4
2781 #define QM_REG_QVOQIDX_53 0x1681c8
2782 #define QM_REG_QVOQIDX_54 0x1681cc
2783 #define QM_REG_QVOQIDX_55 0x1681d0
2784 #define QM_REG_QVOQIDX_56 0x1681d4
2785 #define QM_REG_QVOQIDX_57 0x1681d8
2786 #define QM_REG_QVOQIDX_58 0x1681dc
2787 #define QM_REG_QVOQIDX_59 0x1681e0
2788 #define QM_REG_QVOQIDX_50 0x1681bc
2789 #define QM_REG_QVOQIDX_51 0x1681c0
2790 #define QM_REG_QVOQIDX_52 0x1681c4
2791 #define QM_REG_QVOQIDX_53 0x1681c8
2792 #define QM_REG_QVOQIDX_54 0x1681cc
2793 #define QM_REG_QVOQIDX_55 0x1681d0
2794 #define QM_REG_QVOQIDX_56 0x1681d4
2795 #define QM_REG_QVOQIDX_57 0x1681d8
2796 #define QM_REG_QVOQIDX_58 0x1681dc
2797 #define QM_REG_QVOQIDX_59 0x1681e0
2798 #define QM_REG_QVOQIDX_6 0x16810c
2799 #define QM_REG_QVOQIDX_60 0x1681e4
2800 #define QM_REG_QVOQIDX_61 0x1681e8
2801 #define QM_REG_QVOQIDX_62 0x1681ec
2802 #define QM_REG_QVOQIDX_63 0x1681f0
2803 #define QM_REG_QVOQIDX_64 0x16e40c
2804 #define QM_REG_QVOQIDX_65 0x16e410
2805 #define QM_REG_QVOQIDX_66 0x16e414
2806 #define QM_REG_QVOQIDX_67 0x16e418
2807 #define QM_REG_QVOQIDX_68 0x16e41c
2808 #define QM_REG_QVOQIDX_69 0x16e420
2809 #define QM_REG_QVOQIDX_60 0x1681e4
2810 #define QM_REG_QVOQIDX_61 0x1681e8
2811 #define QM_REG_QVOQIDX_62 0x1681ec
2812 #define QM_REG_QVOQIDX_63 0x1681f0
2813 #define QM_REG_QVOQIDX_64 0x16e40c
2814 #define QM_REG_QVOQIDX_65 0x16e410
2815 #define QM_REG_QVOQIDX_69 0x16e420
2816 #define QM_REG_QVOQIDX_7 0x168110
2817 #define QM_REG_QVOQIDX_70 0x16e424
2818 #define QM_REG_QVOQIDX_71 0x16e428
2819 #define QM_REG_QVOQIDX_72 0x16e42c
2820 #define QM_REG_QVOQIDX_73 0x16e430
2821 #define QM_REG_QVOQIDX_74 0x16e434
2822 #define QM_REG_QVOQIDX_75 0x16e438
2823 #define QM_REG_QVOQIDX_76 0x16e43c
2824 #define QM_REG_QVOQIDX_77 0x16e440
2825 #define QM_REG_QVOQIDX_78 0x16e444
2826 #define QM_REG_QVOQIDX_79 0x16e448
2827 #define QM_REG_QVOQIDX_70 0x16e424
2828 #define QM_REG_QVOQIDX_71 0x16e428
2829 #define QM_REG_QVOQIDX_72 0x16e42c
2830 #define QM_REG_QVOQIDX_73 0x16e430
2831 #define QM_REG_QVOQIDX_74 0x16e434
2832 #define QM_REG_QVOQIDX_75 0x16e438
2833 #define QM_REG_QVOQIDX_76 0x16e43c
2834 #define QM_REG_QVOQIDX_77 0x16e440
2835 #define QM_REG_QVOQIDX_78 0x16e444
2836 #define QM_REG_QVOQIDX_79 0x16e448
2837 #define QM_REG_QVOQIDX_8 0x168114
2838 #define QM_REG_QVOQIDX_80 0x16e44c
2839 #define QM_REG_QVOQIDX_81 0x16e450
2840 #define QM_REG_QVOQIDX_82 0x16e454
2841 #define QM_REG_QVOQIDX_83 0x16e458
2842 #define QM_REG_QVOQIDX_84 0x16e45c
2843 #define QM_REG_QVOQIDX_85 0x16e460
2844 #define QM_REG_QVOQIDX_86 0x16e464
2845 #define QM_REG_QVOQIDX_87 0x16e468
2846 #define QM_REG_QVOQIDX_88 0x16e46c
2847 #define QM_REG_QVOQIDX_89 0x16e470
2848 #define QM_REG_QVOQIDX_80 0x16e44c
2849 #define QM_REG_QVOQIDX_81 0x16e450
2850 #define QM_REG_QVOQIDX_85 0x16e460
2851 #define QM_REG_QVOQIDX_86 0x16e464
2852 #define QM_REG_QVOQIDX_87 0x16e468
2853 #define QM_REG_QVOQIDX_88 0x16e46c
2854 #define QM_REG_QVOQIDX_89 0x16e470
2855 #define QM_REG_QVOQIDX_9 0x168118
2856 #define QM_REG_QVOQIDX_90 0x16e474
2857 #define QM_REG_QVOQIDX_91 0x16e478
2858 #define QM_REG_QVOQIDX_92 0x16e47c
2859 #define QM_REG_QVOQIDX_93 0x16e480
2860 #define QM_REG_QVOQIDX_94 0x16e484
2861 #define QM_REG_QVOQIDX_95 0x16e488
2862 #define QM_REG_QVOQIDX_96 0x16e48c
2863 #define QM_REG_QVOQIDX_97 0x16e490
2864 #define QM_REG_QVOQIDX_98 0x16e494
2865 #define QM_REG_QVOQIDX_99 0x16e498
2866 #define QM_REG_QVOQIDX_90 0x16e474
2867 #define QM_REG_QVOQIDX_91 0x16e478
2868 #define QM_REG_QVOQIDX_92 0x16e47c
2869 #define QM_REG_QVOQIDX_93 0x16e480
2870 #define QM_REG_QVOQIDX_94 0x16e484
2871 #define QM_REG_QVOQIDX_95 0x16e488
2872 #define QM_REG_QVOQIDX_96 0x16e48c
2873 #define QM_REG_QVOQIDX_97 0x16e490
2874 #define QM_REG_QVOQIDX_98 0x16e494
2875 #define QM_REG_QVOQIDX_99 0x16e498
2876 /* [RW 1] Initialization bit command */
2877 #define QM_REG_SOFT_RESET 0x168428
2878 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2879 #define QM_REG_TASKCRDCOST_0 0x16809c
2880 #define QM_REG_TASKCRDCOST_1 0x1680a0
2881 #define QM_REG_TASKCRDCOST_10 0x1680c4
2882 #define QM_REG_TASKCRDCOST_11 0x1680c8
2883 #define QM_REG_TASKCRDCOST_2 0x1680a4
2884 #define QM_REG_TASKCRDCOST_4 0x1680ac
2885 #define QM_REG_TASKCRDCOST_5 0x1680b0
2886 /* [R 6] Keep the fill level of the fifo from write client 3 */
2887 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
2888 /* [R 6] Keep the fill level of the fifo from write client 2 */
2889 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
2890 /* [RC 32] Credit update error register */
2891 #define QM_REG_VOQCRDERRREG 0x168408
2892 /* [R 16] The credit value for each VOQ */
2893 #define QM_REG_VOQCREDIT_0 0x1682d0
2894 #define QM_REG_VOQCREDIT_1 0x1682d4
2895 #define QM_REG_VOQCREDIT_10 0x1682f8
2896 #define QM_REG_VOQCREDIT_11 0x1682fc
2897 #define QM_REG_VOQCREDIT_4 0x1682e0
2898 /* [RW 16] The credit value that if above the QM is considered almost full */
2899 #define QM_REG_VOQCREDITAFULLTHR 0x168090
2900 /* [RW 16] The init and maximum credit for each VoQ */
2901 #define QM_REG_VOQINITCREDIT_0 0x168060
2902 #define QM_REG_VOQINITCREDIT_1 0x168064
2903 #define QM_REG_VOQINITCREDIT_10 0x168088
2904 #define QM_REG_VOQINITCREDIT_11 0x16808c
2905 #define QM_REG_VOQINITCREDIT_2 0x168068
2906 #define QM_REG_VOQINITCREDIT_4 0x168070
2907 #define QM_REG_VOQINITCREDIT_5 0x168074
2908 /* [RW 1] The port of which VOQ belongs */
2909 #define QM_REG_VOQPORT_0 0x1682a0
2910 #define QM_REG_VOQPORT_1 0x1682a4
2911 #define QM_REG_VOQPORT_10 0x1682c8
2912 #define QM_REG_VOQPORT_11 0x1682cc
2913 #define QM_REG_VOQPORT_2 0x1682a8
2914 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2915 #define QM_REG_VOQQMASK_0_LSB 0x168240
2916 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2917 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
2918 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2919 #define QM_REG_VOQQMASK_0_MSB 0x168244
2920 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2921 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
2922 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2923 #define QM_REG_VOQQMASK_10_LSB 0x168290
2924 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2925 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
2926 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2927 #define QM_REG_VOQQMASK_10_MSB 0x168294
2928 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2929 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
2930 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2931 #define QM_REG_VOQQMASK_11_LSB 0x168298
2932 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2933 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
2934 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2935 #define QM_REG_VOQQMASK_11_MSB 0x16829c
2936 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2937 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
2938 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2939 #define QM_REG_VOQQMASK_1_LSB 0x168248
2940 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2941 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
2942 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2943 #define QM_REG_VOQQMASK_1_MSB 0x16824c
2944 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2945 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
2946 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2947 #define QM_REG_VOQQMASK_2_LSB 0x168250
2948 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2949 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
2950 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2951 #define QM_REG_VOQQMASK_2_MSB 0x168254
2952 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2953 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
2954 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2955 #define QM_REG_VOQQMASK_3_LSB 0x168258
2956 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2957 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
2958 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2959 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
2960 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2961 #define QM_REG_VOQQMASK_4_LSB 0x168260
2962 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2963 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
2964 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2965 #define QM_REG_VOQQMASK_4_MSB 0x168264
2966 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2967 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
2968 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2969 #define QM_REG_VOQQMASK_5_LSB 0x168268
2970 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2971 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
2972 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2973 #define QM_REG_VOQQMASK_5_MSB 0x16826c
2974 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2975 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
2976 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2977 #define QM_REG_VOQQMASK_6_LSB 0x168270
2978 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2979 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
2980 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2981 #define QM_REG_VOQQMASK_6_MSB 0x168274
2982 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2983 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
2984 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2985 #define QM_REG_VOQQMASK_7_LSB 0x168278
2986 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2987 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
2988 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2989 #define QM_REG_VOQQMASK_7_MSB 0x16827c
2990 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2991 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
2992 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2993 #define QM_REG_VOQQMASK_8_LSB 0x168280
2994 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2995 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
2996 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2997 #define QM_REG_VOQQMASK_8_MSB 0x168284
2998 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2999 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3000 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3001 #define QM_REG_VOQQMASK_9_LSB 0x168288
3002 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3003 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3004 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3005 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3006 /* [RW 32] Wrr weights */
3007 #define QM_REG_WRRWEIGHTS_0 0x16880c
3008 #define QM_REG_WRRWEIGHTS_1 0x168810
3009 #define QM_REG_WRRWEIGHTS_10 0x168814
3010 #define QM_REG_WRRWEIGHTS_10_SIZE 1
3011 /* [RW 32] Wrr weights */
3012 #define QM_REG_WRRWEIGHTS_11 0x168818
3013 #define QM_REG_WRRWEIGHTS_11_SIZE 1
3014 /* [RW 32] Wrr weights */
3015 #define QM_REG_WRRWEIGHTS_12 0x16881c
3016 #define QM_REG_WRRWEIGHTS_12_SIZE 1
3017 /* [RW 32] Wrr weights */
3018 #define QM_REG_WRRWEIGHTS_13 0x168820
3019 #define QM_REG_WRRWEIGHTS_13_SIZE 1
3020 /* [RW 32] Wrr weights */
3021 #define QM_REG_WRRWEIGHTS_14 0x168824
3022 #define QM_REG_WRRWEIGHTS_14_SIZE 1
3023 /* [RW 32] Wrr weights */
3024 #define QM_REG_WRRWEIGHTS_15 0x168828
3025 #define QM_REG_WRRWEIGHTS_15_SIZE 1
3026 /* [RW 32] Wrr weights */
3027 #define QM_REG_WRRWEIGHTS_16 0x16e000
3028 #define QM_REG_WRRWEIGHTS_16_SIZE 1
3029 /* [RW 32] Wrr weights */
3030 #define QM_REG_WRRWEIGHTS_17 0x16e004
3031 #define QM_REG_WRRWEIGHTS_17_SIZE 1
3032 /* [RW 32] Wrr weights */
3033 #define QM_REG_WRRWEIGHTS_18 0x16e008
3034 #define QM_REG_WRRWEIGHTS_18_SIZE 1
3035 /* [RW 32] Wrr weights */
3036 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3037 #define QM_REG_WRRWEIGHTS_19_SIZE 1
3038 /* [RW 32] Wrr weights */
3039 #define QM_REG_WRRWEIGHTS_10 0x168814
3040 #define QM_REG_WRRWEIGHTS_11 0x168818
3041 #define QM_REG_WRRWEIGHTS_12 0x16881c
3042 #define QM_REG_WRRWEIGHTS_13 0x168820
3043 #define QM_REG_WRRWEIGHTS_14 0x168824
3044 #define QM_REG_WRRWEIGHTS_15 0x168828
3045 #define QM_REG_WRRWEIGHTS_16 0x16e000
3046 #define QM_REG_WRRWEIGHTS_17 0x16e004
3047 #define QM_REG_WRRWEIGHTS_18 0x16e008
3048 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3049 #define QM_REG_WRRWEIGHTS_2 0x16882c
3050 #define QM_REG_WRRWEIGHTS_20 0x16e010
3051 #define QM_REG_WRRWEIGHTS_20_SIZE 1
3052 /* [RW 32] Wrr weights */
3053 #define QM_REG_WRRWEIGHTS_21 0x16e014
3054 #define QM_REG_WRRWEIGHTS_21_SIZE 1
3055 /* [RW 32] Wrr weights */
3056 #define QM_REG_WRRWEIGHTS_22 0x16e018
3057 #define QM_REG_WRRWEIGHTS_22_SIZE 1
3058 /* [RW 32] Wrr weights */
3059 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3060 #define QM_REG_WRRWEIGHTS_23_SIZE 1
3061 /* [RW 32] Wrr weights */
3062 #define QM_REG_WRRWEIGHTS_24 0x16e020
3063 #define QM_REG_WRRWEIGHTS_24_SIZE 1
3064 /* [RW 32] Wrr weights */
3065 #define QM_REG_WRRWEIGHTS_25 0x16e024
3066 #define QM_REG_WRRWEIGHTS_25_SIZE 1
3067 /* [RW 32] Wrr weights */
3068 #define QM_REG_WRRWEIGHTS_26 0x16e028
3069 #define QM_REG_WRRWEIGHTS_26_SIZE 1
3070 /* [RW 32] Wrr weights */
3071 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3072 #define QM_REG_WRRWEIGHTS_27_SIZE 1
3073 /* [RW 32] Wrr weights */
3074 #define QM_REG_WRRWEIGHTS_28 0x16e030
3075 #define QM_REG_WRRWEIGHTS_28_SIZE 1
3076 /* [RW 32] Wrr weights */
3077 #define QM_REG_WRRWEIGHTS_29 0x16e034
3078 #define QM_REG_WRRWEIGHTS_29_SIZE 1
3079 /* [RW 32] Wrr weights */
3080 #define QM_REG_WRRWEIGHTS_20 0x16e010
3081 #define QM_REG_WRRWEIGHTS_21 0x16e014
3082 #define QM_REG_WRRWEIGHTS_22 0x16e018
3083 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3084 #define QM_REG_WRRWEIGHTS_24 0x16e020
3085 #define QM_REG_WRRWEIGHTS_25 0x16e024
3086 #define QM_REG_WRRWEIGHTS_26 0x16e028
3087 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3088 #define QM_REG_WRRWEIGHTS_28 0x16e030
3089 #define QM_REG_WRRWEIGHTS_29 0x16e034
3090 #define QM_REG_WRRWEIGHTS_3 0x168830
3091 #define QM_REG_WRRWEIGHTS_30 0x16e038
3092 #define QM_REG_WRRWEIGHTS_30_SIZE 1
3093 /* [RW 32] Wrr weights */
3094 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3095 #define QM_REG_WRRWEIGHTS_31_SIZE 1
3096 /* [RW 32] Wrr weights */
3097 #define QM_REG_WRRWEIGHTS_30 0x16e038
3098 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3099 #define QM_REG_WRRWEIGHTS_4 0x168834
3100 #define QM_REG_WRRWEIGHTS_5 0x168838
3101 #define QM_REG_WRRWEIGHTS_6 0x16883c
3102 #define QM_REG_WRRWEIGHTS_7 0x168840
3103 #define QM_REG_WRRWEIGHTS_8 0x168844
3104 #define QM_REG_WRRWEIGHTS_9 0x168848
3105 /* [R 6] Keep the fill level of the fifo from write client 1 */
3106 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
3107 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3108 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3109 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3110 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3111 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3112 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3113 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3114 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3115 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3116 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3117 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3118 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3119 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3120 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3121 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3122 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3123 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3124 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3125 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3126 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3127 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3128 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3129 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3130 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3131 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3132 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3133 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3134 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3135 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3136 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3137 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3138 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3139 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3140 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3141 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3142 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3143 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3144 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3145 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3146 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3147 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3148 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3149 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3150 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3151 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3152 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3153 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3154 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3155 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3156 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3157 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3158 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3159 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3160 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3161 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3162 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3163 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3164 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3165 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3166 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3167 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3168 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3169 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3170 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3171 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3172 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3173 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3174 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3175 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3176 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3177 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3178 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3179 #define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3180 #define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3181 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3182 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3183 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3184 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3185 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3186 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3187 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3188 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3189 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3190 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3191 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3192 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3193 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3194 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3195 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3196 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3197 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3198 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3199 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3200 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3201 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3202 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3203 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3204 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3205 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3206 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3207 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3208 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3209 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3210 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3211 #define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3212 #define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3213 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3214 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3215 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3216 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3217 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3218 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3219 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3220 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3221 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3222 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3223 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3224 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3225 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3226 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3227 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3228 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3229 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3230 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3231 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3232 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3233 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3234 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3235 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3236 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3237 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3238 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3239 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3240 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3241 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3242 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3243 #define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3244 #define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3245 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3246 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3247 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3248 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3249 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3250 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3251 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3252 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3253 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3254 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3255 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3256 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3257 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3258 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3259 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3260 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3261 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3262 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3263 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3264 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3265 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3266 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3267 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3268 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3269 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3270 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3271 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3272 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3273 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3274 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3275 #define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3276 #define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3277 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3278 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3279 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3280 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3281 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3282 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3283 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3284 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3285 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3286 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3287 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3288 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3289 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3290 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3291 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3292 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3293 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3294 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3295 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3296 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3297 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3298 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3299 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3300 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3301 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3302 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3303 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3304 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3305 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3306 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3307 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3308 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3309 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3310 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3311 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3312 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3313 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3314 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3315 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3316 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3317 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3318 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3319 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3320 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3321 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3322 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3323 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3324 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3325 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3326 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3327 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3328 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3329 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3330 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3331 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3332 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3333 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3334 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3335 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3336 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3337 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3338 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3339 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3340 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3341 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3342 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3343 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3344 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3345 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3346 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3347 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3348 #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
3349 /* [R 1] debug only: This bit indicates whether indicates that external
3350 buffer was wrapped (oldest data was thrown); Relevant only when
3351 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3352 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3353 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
3354 /* [R 1] debug only: This bit indicates whether the internal buffer was
3355 wrapped (oldest data was thrown) Relevant only when
3356 ~dbg_registers_debug_target=0 (internal buffer) */
3357 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
3358 #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
3359 #define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3360 #define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3361 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3362 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3363 #define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3364 #define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3365 #define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3366 #define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
3367 /* [RW 32] Wrr weights */
3368 #define QM_REG_WRRWEIGHTS_0 0x16880c
3369 #define QM_REG_WRRWEIGHTS_0_SIZE 1
3370 /* [RW 32] Wrr weights */
3371 #define QM_REG_WRRWEIGHTS_1 0x168810
3372 #define QM_REG_WRRWEIGHTS_1_SIZE 1
3373 /* [RW 32] Wrr weights */
3374 #define QM_REG_WRRWEIGHTS_10 0x168814
3375 #define QM_REG_WRRWEIGHTS_10_SIZE 1
3376 /* [RW 32] Wrr weights */
3377 #define QM_REG_WRRWEIGHTS_11 0x168818
3378 #define QM_REG_WRRWEIGHTS_11_SIZE 1
3379 /* [RW 32] Wrr weights */
3380 #define QM_REG_WRRWEIGHTS_12 0x16881c
3381 #define QM_REG_WRRWEIGHTS_12_SIZE 1
3382 /* [RW 32] Wrr weights */
3383 #define QM_REG_WRRWEIGHTS_13 0x168820
3384 #define QM_REG_WRRWEIGHTS_13_SIZE 1
3385 /* [RW 32] Wrr weights */
3386 #define QM_REG_WRRWEIGHTS_14 0x168824
3387 #define QM_REG_WRRWEIGHTS_14_SIZE 1
3388 /* [RW 32] Wrr weights */
3389 #define QM_REG_WRRWEIGHTS_15 0x168828
3390 #define QM_REG_WRRWEIGHTS_15_SIZE 1
3391 /* [RW 32] Wrr weights */
3392 #define QM_REG_WRRWEIGHTS_2 0x16882c
3393 #define QM_REG_WRRWEIGHTS_2_SIZE 1
3394 /* [RW 32] Wrr weights */
3395 #define QM_REG_WRRWEIGHTS_3 0x168830
3396 #define QM_REG_WRRWEIGHTS_3_SIZE 1
3397 /* [RW 32] Wrr weights */
3398 #define QM_REG_WRRWEIGHTS_4 0x168834
3399 #define QM_REG_WRRWEIGHTS_4_SIZE 1
3400 /* [RW 32] Wrr weights */
3401 #define QM_REG_WRRWEIGHTS_5 0x168838
3402 #define QM_REG_WRRWEIGHTS_5_SIZE 1
3403 /* [RW 32] Wrr weights */
3404 #define QM_REG_WRRWEIGHTS_6 0x16883c
3405 #define QM_REG_WRRWEIGHTS_6_SIZE 1
3406 /* [RW 32] Wrr weights */
3407 #define QM_REG_WRRWEIGHTS_7 0x168840
3408 #define QM_REG_WRRWEIGHTS_7_SIZE 1
3409 /* [RW 32] Wrr weights */
3410 #define QM_REG_WRRWEIGHTS_8 0x168844
3411 #define QM_REG_WRRWEIGHTS_8_SIZE 1
3412 /* [RW 32] Wrr weights */
3413 #define QM_REG_WRRWEIGHTS_9 0x168848
3414 #define QM_REG_WRRWEIGHTS_9_SIZE 1
3415 /* [RW 32] Wrr weights */
3416 #define QM_REG_WRRWEIGHTS_16 0x16e000
3417 #define QM_REG_WRRWEIGHTS_16_SIZE 1
3418 /* [RW 32] Wrr weights */
3419 #define QM_REG_WRRWEIGHTS_17 0x16e004
3420 #define QM_REG_WRRWEIGHTS_17_SIZE 1
3421 /* [RW 32] Wrr weights */
3422 #define QM_REG_WRRWEIGHTS_18 0x16e008
3423 #define QM_REG_WRRWEIGHTS_18_SIZE 1
3424 /* [RW 32] Wrr weights */
3425 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3426 #define QM_REG_WRRWEIGHTS_19_SIZE 1
3427 /* [RW 32] Wrr weights */
3428 #define QM_REG_WRRWEIGHTS_20 0x16e010
3429 #define QM_REG_WRRWEIGHTS_20_SIZE 1
3430 /* [RW 32] Wrr weights */
3431 #define QM_REG_WRRWEIGHTS_21 0x16e014
3432 #define QM_REG_WRRWEIGHTS_21_SIZE 1
3433 /* [RW 32] Wrr weights */
3434 #define QM_REG_WRRWEIGHTS_22 0x16e018
3435 #define QM_REG_WRRWEIGHTS_22_SIZE 1
3436 /* [RW 32] Wrr weights */
3437 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3438 #define QM_REG_WRRWEIGHTS_23_SIZE 1
3439 /* [RW 32] Wrr weights */
3440 #define QM_REG_WRRWEIGHTS_24 0x16e020
3441 #define QM_REG_WRRWEIGHTS_24_SIZE 1
3442 /* [RW 32] Wrr weights */
3443 #define QM_REG_WRRWEIGHTS_25 0x16e024
3444 #define QM_REG_WRRWEIGHTS_25_SIZE 1
3445 /* [RW 32] Wrr weights */
3446 #define QM_REG_WRRWEIGHTS_26 0x16e028
3447 #define QM_REG_WRRWEIGHTS_26_SIZE 1
3448 /* [RW 32] Wrr weights */
3449 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3450 #define QM_REG_WRRWEIGHTS_27_SIZE 1
3451 /* [RW 32] Wrr weights */
3452 #define QM_REG_WRRWEIGHTS_28 0x16e030
3453 #define QM_REG_WRRWEIGHTS_28_SIZE 1
3454 /* [RW 32] Wrr weights */
3455 #define QM_REG_WRRWEIGHTS_29 0x16e034
3456 #define QM_REG_WRRWEIGHTS_29_SIZE 1
3457 /* [RW 32] Wrr weights */
3458 #define QM_REG_WRRWEIGHTS_30 0x16e038
3459 #define QM_REG_WRRWEIGHTS_30_SIZE 1
3460 /* [RW 32] Wrr weights */
3461 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3462 #define QM_REG_WRRWEIGHTS_31_SIZE 1
3463 #define SRC_REG_COUNTFREE0 0x40500
3464 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3465 ports. If set the searcher support 8 functions. */
3466 #define SRC_REG_E1HMF_ENABLE 0x404cc
3467 #define SRC_REG_FIRSTFREE0 0x40510
3468 #define SRC_REG_KEYRSS0_0 0x40408
3469 #define SRC_REG_KEYRSS0_7 0x40424
3470 #define SRC_REG_KEYRSS1_9 0x40454
3471 #define SRC_REG_KEYSEARCH_0 0x40458
3472 #define SRC_REG_KEYSEARCH_1 0x4045c
3473 #define SRC_REG_KEYSEARCH_2 0x40460
3474 #define SRC_REG_KEYSEARCH_3 0x40464
3475 #define SRC_REG_KEYSEARCH_4 0x40468
3476 #define SRC_REG_KEYSEARCH_5 0x4046c
3477 #define SRC_REG_KEYSEARCH_6 0x40470
3478 #define SRC_REG_KEYSEARCH_7 0x40474
3479 #define SRC_REG_KEYSEARCH_8 0x40478
3480 #define SRC_REG_KEYSEARCH_9 0x4047c
3481 #define SRC_REG_LASTFREE0 0x40530
3482 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
3483 /* [RW 1] Reset internal state machines. */
3484 #define SRC_REG_SOFT_RST 0x4049c
3485 /* [R 3] Interrupt register #0 read */
3486 #define SRC_REG_SRC_INT_STS 0x404ac
3487 /* [RW 3] Parity mask register #0 read/write */
3488 #define SRC_REG_SRC_PRTY_MASK 0x404c8
3489 /* [R 3] Parity register #0 read */
3490 #define SRC_REG_SRC_PRTY_STS 0x404bc
3491 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3492 #define TCM_REG_CAM_OCCUP 0x5017c
3493 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3494 disregarded; valid output is deasserted; all other signals are treated as
3495 usual; if 1 - normal activity. */
3496 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
3497 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3498 are disregarded; all other signals are treated as usual; if 1 - normal
3500 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
3501 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3502 disregarded; valid output is deasserted; all other signals are treated as
3503 usual; if 1 - normal activity. */
3504 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3505 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3506 input is disregarded; all other signals are treated as usual; if 1 -
3508 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
3509 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3510 the initial credit value; read returns the current value of the credit
3511 counter. Must be initialized to 1 at start-up. */
3512 #define TCM_REG_CFC_INIT_CRD 0x50204
3513 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3514 weight 8 (the most prioritised); 1 stands for weight 1(least
3515 prioritised); 2 stands for weight 2; tc. */
3516 #define TCM_REG_CP_WEIGHT 0x500c0
3517 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3518 disregarded; acknowledge output is deasserted; all other signals are
3519 treated as usual; if 1 - normal activity. */
3520 #define TCM_REG_CSEM_IFEN 0x5002c
3521 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
3523 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
3524 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3525 weight 8 (the most prioritised); 1 stands for weight 1(least
3526 prioritised); 2 stands for weight 2; tc. */
3527 #define TCM_REG_CSEM_WEIGHT 0x500bc
3528 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3529 #define TCM_REG_ERR_EVNT_ID 0x500a0
3530 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3531 #define TCM_REG_ERR_TCM_HDR 0x5009c
3532 /* [RW 8] The Event ID for Timers expiration. */
3533 #define TCM_REG_EXPR_EVNT_ID 0x500a4
3534 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3535 writes the initial credit value; read returns the current value of the
3536 credit counter. Must be initialized to 64 at start-up. */
3537 #define TCM_REG_FIC0_INIT_CRD 0x5020c
3538 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3539 writes the initial credit value; read returns the current value of the
3540 credit counter. Must be initialized to 64 at start-up. */
3541 #define TCM_REG_FIC1_INIT_CRD 0x50210
3542 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3543 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3544 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3545 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3546 #define TCM_REG_GR_ARB_TYPE 0x50114
3547 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3548 highest priority is 3. It is supposed that the Store channel is the
3549 compliment of the other 3 groups. */
3550 #define TCM_REG_GR_LD0_PR 0x5011c
3551 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3552 highest priority is 3. It is supposed that the Store channel is the
3553 compliment of the other 3 groups. */
3554 #define TCM_REG_GR_LD1_PR 0x50120
3555 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3556 sent to STORM; for a specific connection type. The double REG-pairs are
3557 used to align to STORM context row size of 128 bits. The offset of these
3558 data in the STORM context is always 0. Index _i stands for the connection
3559 type (one of 16). */
3560 #define TCM_REG_N_SM_CTX_LD_0 0x50050
3561 #define TCM_REG_N_SM_CTX_LD_1 0x50054
3562 #define TCM_REG_N_SM_CTX_LD_10 0x50078
3563 #define TCM_REG_N_SM_CTX_LD_11 0x5007c
3564 #define TCM_REG_N_SM_CTX_LD_12 0x50080
3565 #define TCM_REG_N_SM_CTX_LD_13 0x50084
3566 #define TCM_REG_N_SM_CTX_LD_14 0x50088
3567 #define TCM_REG_N_SM_CTX_LD_15 0x5008c
3568 #define TCM_REG_N_SM_CTX_LD_2 0x50058
3569 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
3570 #define TCM_REG_N_SM_CTX_LD_4 0x50060
3571 #define TCM_REG_N_SM_CTX_LD_5 0x50064
3572 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3573 acknowledge output is deasserted; all other signals are treated as usual;
3574 if 1 - normal activity. */
3575 #define TCM_REG_PBF_IFEN 0x50024
3576 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
3578 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
3579 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3580 weight 8 (the most prioritised); 1 stands for weight 1(least
3581 prioritised); 2 stands for weight 2; tc. */
3582 #define TCM_REG_PBF_WEIGHT 0x500b4
3583 #define TCM_REG_PHYS_QNUM0_0 0x500e0
3584 #define TCM_REG_PHYS_QNUM0_1 0x500e4
3585 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3586 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3587 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3588 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3589 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3590 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3591 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3592 acknowledge output is deasserted; all other signals are treated as usual;
3593 if 1 - normal activity. */
3594 #define TCM_REG_PRS_IFEN 0x50020
3595 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3597 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3598 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3599 weight 8 (the most prioritised); 1 stands for weight 1(least
3600 prioritised); 2 stands for weight 2; tc. */
3601 #define TCM_REG_PRS_WEIGHT 0x500b0
3602 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3603 #define TCM_REG_STOP_EVNT_ID 0x500a8
3604 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3606 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3607 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3608 disregarded; acknowledge output is deasserted; all other signals are
3609 treated as usual; if 1 - normal activity. */
3610 #define TCM_REG_STORM_TCM_IFEN 0x50010
3611 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3612 weight 8 (the most prioritised); 1 stands for weight 1(least
3613 prioritised); 2 stands for weight 2; tc. */
3614 #define TCM_REG_STORM_WEIGHT 0x500ac
3615 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3616 acknowledge output is deasserted; all other signals are treated as usual;
3617 if 1 - normal activity. */
3618 #define TCM_REG_TCM_CFC_IFEN 0x50040
3619 /* [RW 11] Interrupt mask register #0 read/write */
3620 #define TCM_REG_TCM_INT_MASK 0x501dc
3621 /* [R 11] Interrupt register #0 read */
3622 #define TCM_REG_TCM_INT_STS 0x501d0
3623 /* [R 27] Parity register #0 read */
3624 #define TCM_REG_TCM_PRTY_STS 0x501e0
3625 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3626 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3627 Is used to determine the number of the AG context REG-pairs written back;
3628 when the input message Reg1WbFlg isn't set. */
3629 #define TCM_REG_TCM_REG0_SZ 0x500d8
3630 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3631 disregarded; valid is deasserted; all other signals are treated as usual;
3632 if 1 - normal activity. */
3633 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3634 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3635 disregarded; valid is deasserted; all other signals are treated as usual;
3636 if 1 - normal activity. */
3637 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3638 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3639 disregarded; valid is deasserted; all other signals are treated as usual;
3640 if 1 - normal activity. */
3641 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3642 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3643 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3644 /* [RW 28] The CM header for Timers expiration command. */
3645 #define TCM_REG_TM_TCM_HDR 0x50098
3646 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3647 disregarded; acknowledge output is deasserted; all other signals are
3648 treated as usual; if 1 - normal activity. */
3649 #define TCM_REG_TM_TCM_IFEN 0x5001c
3650 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3651 weight 8 (the most prioritised); 1 stands for weight 1(least
3652 prioritised); 2 stands for weight 2; tc. */
3653 #define TCM_REG_TM_WEIGHT 0x500d0
3654 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3655 the initial credit value; read returns the current value of the credit
3656 counter. Must be initialized to 32 at start-up. */
3657 #define TCM_REG_TQM_INIT_CRD 0x5021c
3658 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3659 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3660 prioritised); 2 stands for weight 2; tc. */
3661 #define TCM_REG_TQM_P_WEIGHT 0x500c8
3662 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3663 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3664 prioritised); 2 stands for weight 2; tc. */
3665 #define TCM_REG_TQM_S_WEIGHT 0x500cc
3666 /* [RW 28] The CM header value for QM request (primary). */
3667 #define TCM_REG_TQM_TCM_HDR_P 0x50090
3668 /* [RW 28] The CM header value for QM request (secondary). */
3669 #define TCM_REG_TQM_TCM_HDR_S 0x50094
3670 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3671 acknowledge output is deasserted; all other signals are treated as usual;
3672 if 1 - normal activity. */
3673 #define TCM_REG_TQM_TCM_IFEN 0x50014
3674 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3675 acknowledge output is deasserted; all other signals are treated as usual;
3676 if 1 - normal activity. */
3677 #define TCM_REG_TSDM_IFEN 0x50018
3678 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
3680 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
3681 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3682 weight 8 (the most prioritised); 1 stands for weight 1(least
3683 prioritised); 2 stands for weight 2; tc. */
3684 #define TCM_REG_TSDM_WEIGHT 0x500c4
3685 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3686 disregarded; acknowledge output is deasserted; all other signals are
3687 treated as usual; if 1 - normal activity. */
3688 #define TCM_REG_USEM_IFEN 0x50028
3689 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
3691 #define TCM_REG_USEM_LENGTH_MIS 0x50170
3692 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3693 weight 8 (the most prioritised); 1 stands for weight 1(least
3694 prioritised); 2 stands for weight 2; tc. */
3695 #define TCM_REG_USEM_WEIGHT 0x500b8
3696 /* [RW 21] Indirect access to the descriptor table of the XX protection
3697 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3698 pointer; 20:16] - next pointer. */
3699 #define TCM_REG_XX_DESCR_TABLE 0x50280
3700 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
3701 /* [R 6] Use to read the value of XX protection Free counter. */
3702 #define TCM_REG_XX_FREE 0x50178
3703 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3704 of the Input Stage XX protection buffer by the XX protection pending
3705 messages. Max credit available - 127.Write writes the initial credit
3706 value; read returns the current value of the credit counter. Must be
3707 initialized to 19 at start-up. */
3708 #define TCM_REG_XX_INIT_CRD 0x50220
3709 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
3711 #define TCM_REG_XX_MAX_LL_SZ 0x50044
3712 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3713 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3714 #define TCM_REG_XX_MSG_NUM 0x50224
3715 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3716 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3717 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3718 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3720 #define TCM_REG_XX_TABLE 0x50240
3721 /* [RW 4] Load value for for cfc ac credit cnt. */
3722 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3723 /* [RW 4] Load value for cfc cld credit cnt. */
3724 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3725 /* [RW 8] Client0 context region. */
3726 #define TM_REG_CL0_CONT_REGION 0x164030
3727 /* [RW 8] Client1 context region. */
3728 #define TM_REG_CL1_CONT_REGION 0x164034
3729 /* [RW 8] Client2 context region. */
3730 #define TM_REG_CL2_CONT_REGION 0x164038
3731 /* [RW 2] Client in High priority client number. */
3732 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3733 /* [RW 4] Load value for clout0 cred cnt. */
3734 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3735 /* [RW 4] Load value for clout1 cred cnt. */
3736 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3737 /* [RW 4] Load value for clout2 cred cnt. */
3738 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3739 /* [RW 1] Enable client0 input. */
3740 #define TM_REG_EN_CL0_INPUT 0x164008
3741 /* [RW 1] Enable client1 input. */
3742 #define TM_REG_EN_CL1_INPUT 0x16400c
3743 /* [RW 1] Enable client2 input. */
3744 #define TM_REG_EN_CL2_INPUT 0x164010
3745 #define TM_REG_EN_LINEAR0_TIMER 0x164014
3746 /* [RW 1] Enable real time counter. */
3747 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3748 /* [RW 1] Enable for Timers state machines. */
3749 #define TM_REG_EN_TIMERS 0x164000
3750 /* [RW 4] Load value for expiration credit cnt. CFC max number of
3751 outstanding load requests for timers (expiration) context loading. */
3752 #define TM_REG_EXP_CRDCNT_VAL 0x164238
3753 /* [RW 32] Linear0 logic address. */
3754 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
3755 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3756 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3757 /* [WB 64] Linear0 phy address. */
3758 #define TM_REG_LIN0_PHY_ADDR 0x164270
3759 /* [RW 1] Linear0 physical address valid. */
3760 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
3761 /* [RW 24] Linear0 array scan timeout. */
3762 #define TM_REG_LIN0_SCAN_TIME 0x16403c
3763 /* [RW 32] Linear1 logic address. */
3764 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
3765 /* [WB 64] Linear1 phy address. */
3766 #define TM_REG_LIN1_PHY_ADDR 0x164280
3767 /* [RW 1] Linear1 physical address valid. */
3768 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
3769 /* [RW 6] Linear timer set_clear fifo threshold. */
3770 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3771 /* [RW 2] Load value for pci arbiter credit cnt. */
3772 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3773 /* [RW 1] Timer software reset - active high. */
3774 #define TM_REG_TIMER_SOFT_RST 0x164004
3775 /* [RW 20] The amount of hardware cycles for each timer tick. */
3776 #define TM_REG_TIMER_TICK_SIZE 0x16401c
3777 /* [RW 8] Timers Context region. */
3778 #define TM_REG_TM_CONTEXT_REGION 0x164044
3779 /* [RW 1] Interrupt mask register #0 read/write */
3780 #define TM_REG_TM_INT_MASK 0x1640fc
3781 /* [R 1] Interrupt register #0 read */
3782 #define TM_REG_TM_INT_STS 0x1640f0
3783 /* [RW 8] The event id for aggregated interrupt 0 */
3784 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
3785 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3786 #define TSDM_REG_AGG_INT_EVENT_10 0x42060
3787 #define TSDM_REG_AGG_INT_EVENT_11 0x42064
3788 #define TSDM_REG_AGG_INT_EVENT_12 0x42068
3789 #define TSDM_REG_AGG_INT_EVENT_13 0x4206c
3790 #define TSDM_REG_AGG_INT_EVENT_14 0x42070
3791 #define TSDM_REG_AGG_INT_EVENT_15 0x42074
3792 #define TSDM_REG_AGG_INT_EVENT_16 0x42078
3793 #define TSDM_REG_AGG_INT_EVENT_17 0x4207c
3794 #define TSDM_REG_AGG_INT_EVENT_18 0x42080
3795 #define TSDM_REG_AGG_INT_EVENT_19 0x42084
3796 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
3797 #define TSDM_REG_AGG_INT_EVENT_20 0x42088
3798 #define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3799 #define TSDM_REG_AGG_INT_EVENT_22 0x42090
3800 #define TSDM_REG_AGG_INT_EVENT_23 0x42094
3801 #define TSDM_REG_AGG_INT_EVENT_24 0x42098
3802 #define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3803 #define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3804 #define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3805 #define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3806 #define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3807 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
3808 #define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3809 #define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3810 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
3811 /* [RW 1] The T bit for aggregated interrupt 0 */
3812 #define TSDM_REG_AGG_INT_T_0 0x420b8
3813 #define TSDM_REG_AGG_INT_T_1 0x420bc
3814 #define TSDM_REG_AGG_INT_T_10 0x420e0
3815 #define TSDM_REG_AGG_INT_T_11 0x420e4
3816 #define TSDM_REG_AGG_INT_T_12 0x420e8
3817 #define TSDM_REG_AGG_INT_T_13 0x420ec
3818 #define TSDM_REG_AGG_INT_T_14 0x420f0
3819 #define TSDM_REG_AGG_INT_T_15 0x420f4
3820 #define TSDM_REG_AGG_INT_T_16 0x420f8
3821 #define TSDM_REG_AGG_INT_T_17 0x420fc
3822 #define TSDM_REG_AGG_INT_T_18 0x42100
3823 #define TSDM_REG_AGG_INT_T_19 0x42104
3824 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3825 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3826 /* [RW 16] The maximum value of the competion counter #0 */
3827 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3828 /* [RW 16] The maximum value of the competion counter #1 */
3829 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3830 /* [RW 16] The maximum value of the competion counter #2 */
3831 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3832 /* [RW 16] The maximum value of the competion counter #3 */
3833 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3834 /* [RW 13] The start address in the internal RAM for the completion
3836 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3837 #define TSDM_REG_ENABLE_IN1 0x42238
3838 #define TSDM_REG_ENABLE_IN2 0x4223c
3839 #define TSDM_REG_ENABLE_OUT1 0x42240
3840 #define TSDM_REG_ENABLE_OUT2 0x42244
3841 /* [RW 4] The initial number of messages that can be sent to the pxp control
3842 interface without receiving any ACK. */
3843 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3844 /* [ST 32] The number of ACK after placement messages received */
3845 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3846 /* [ST 32] The number of packet end messages received from the parser */
3847 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3848 /* [ST 32] The number of requests received from the pxp async if */
3849 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3850 /* [ST 32] The number of commands received in queue 0 */
3851 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3852 /* [ST 32] The number of commands received in queue 10 */
3853 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3854 /* [ST 32] The number of commands received in queue 11 */
3855 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3856 /* [ST 32] The number of commands received in queue 1 */
3857 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3858 /* [ST 32] The number of commands received in queue 3 */
3859 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3860 /* [ST 32] The number of commands received in queue 4 */
3861 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3862 /* [ST 32] The number of commands received in queue 5 */
3863 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3864 /* [ST 32] The number of commands received in queue 6 */
3865 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3866 /* [ST 32] The number of commands received in queue 7 */
3867 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3868 /* [ST 32] The number of commands received in queue 8 */
3869 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3870 /* [ST 32] The number of commands received in queue 9 */
3871 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3872 /* [RW 13] The start address in the internal RAM for the packet end message */
3873 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3874 /* [RW 13] The start address in the internal RAM for queue counters */
3875 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3876 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3877 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3878 /* [R 1] parser fifo empty in sdm_sync block */
3879 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3880 /* [R 1] parser serial fifo empty in sdm_sync block */
3881 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3882 /* [RW 32] Tick for timer counter. Applicable only when
3883 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3884 #define TSDM_REG_TIMER_TICK 0x42000
3885 /* [RW 32] Interrupt mask register #0 read/write */
3886 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3887 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3888 /* [R 32] Interrupt register #0 read */
3889 #define TSDM_REG_TSDM_INT_STS_0 0x42290
3890 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
3891 /* [RW 11] Parity mask register #0 read/write */
3892 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
3893 /* [R 11] Parity register #0 read */
3894 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
3895 /* [RW 5] The number of time_slots in the arbitration cycle */
3896 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3897 /* [RW 3] The source that is associated with arbitration element 0. Source
3898 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3899 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3900 #define TSEM_REG_ARB_ELEMENT0 0x180020
3901 /* [RW 3] The source that is associated with arbitration element 1. Source
3902 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3903 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3904 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3905 #define TSEM_REG_ARB_ELEMENT1 0x180024
3906 /* [RW 3] The source that is associated with arbitration element 2. Source
3907 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3908 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3909 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3910 and ~tsem_registers_arb_element1.arb_element1 */
3911 #define TSEM_REG_ARB_ELEMENT2 0x180028
3912 /* [RW 3] The source that is associated with arbitration element 3. Source
3913 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3914 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3915 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
3916 ~tsem_registers_arb_element1.arb_element1 and
3917 ~tsem_registers_arb_element2.arb_element2 */
3918 #define TSEM_REG_ARB_ELEMENT3 0x18002c
3919 /* [RW 3] The source that is associated with arbitration element 4. Source
3920 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3921 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3922 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3923 and ~tsem_registers_arb_element1.arb_element1 and
3924 ~tsem_registers_arb_element2.arb_element2 and
3925 ~tsem_registers_arb_element3.arb_element3 */
3926 #define TSEM_REG_ARB_ELEMENT4 0x180030
3927 #define TSEM_REG_ENABLE_IN 0x1800a4
3928 #define TSEM_REG_ENABLE_OUT 0x1800a8
3929 /* [RW 32] This address space contains all registers and memories that are
3930 placed in SEM_FAST block. The SEM_FAST registers are described in
3931 appendix B. In order to access the sem_fast registers the base address
3932 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3933 #define TSEM_REG_FAST_MEMORY 0x1a0000
3934 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3936 #define TSEM_REG_FIC0_DISABLE 0x180224
3937 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3939 #define TSEM_REG_FIC1_DISABLE 0x180234
3940 /* [RW 15] Interrupt table Read and write access to it is not possible in
3941 the middle of the work */
3942 #define TSEM_REG_INT_TABLE 0x180400
3943 /* [ST 24] Statistics register. The number of messages that entered through
3945 #define TSEM_REG_MSG_NUM_FIC0 0x180000
3946 /* [ST 24] Statistics register. The number of messages that entered through
3948 #define TSEM_REG_MSG_NUM_FIC1 0x180004
3949 /* [ST 24] Statistics register. The number of messages that were sent to
3951 #define TSEM_REG_MSG_NUM_FOC0 0x180008
3952 /* [ST 24] Statistics register. The number of messages that were sent to
3954 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
3955 /* [ST 24] Statistics register. The number of messages that were sent to
3957 #define TSEM_REG_MSG_NUM_FOC2 0x180010
3958 /* [ST 24] Statistics register. The number of messages that were sent to
3960 #define TSEM_REG_MSG_NUM_FOC3 0x180014
3961 /* [RW 1] Disables input messages from the passive buffer May be updated
3962 during run_time by the microcode */
3963 #define TSEM_REG_PAS_DISABLE 0x18024c
3964 /* [WB 128] Debug only. Passive buffer memory */
3965 #define TSEM_REG_PASSIVE_BUFFER 0x181000
3966 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3967 #define TSEM_REG_PRAM 0x1c0000
3968 /* [R 8] Valid sleeping threads indication have bit per thread */
3969 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
3970 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3971 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
3972 /* [RW 8] List of free threads . There is a bit per thread. */
3973 #define TSEM_REG_THREADS_LIST 0x1802e4
3974 /* [RW 3] The arbitration scheme of time_slot 0 */
3975 #define TSEM_REG_TS_0_AS 0x180038
3976 /* [RW 3] The arbitration scheme of time_slot 10 */
3977 #define TSEM_REG_TS_10_AS 0x180060
3978 /* [RW 3] The arbitration scheme of time_slot 11 */
3979 #define TSEM_REG_TS_11_AS 0x180064
3980 /* [RW 3] The arbitration scheme of time_slot 12 */
3981 #define TSEM_REG_TS_12_AS 0x180068
3982 /* [RW 3] The arbitration scheme of time_slot 13 */
3983 #define TSEM_REG_TS_13_AS 0x18006c
3984 /* [RW 3] The arbitration scheme of time_slot 14 */
3985 #define TSEM_REG_TS_14_AS 0x180070
3986 /* [RW 3] The arbitration scheme of time_slot 15 */
3987 #define TSEM_REG_TS_15_AS 0x180074
3988 /* [RW 3] The arbitration scheme of time_slot 16 */
3989 #define TSEM_REG_TS_16_AS 0x180078
3990 /* [RW 3] The arbitration scheme of time_slot 17 */
3991 #define TSEM_REG_TS_17_AS 0x18007c
3992 /* [RW 3] The arbitration scheme of time_slot 18 */
3993 #define TSEM_REG_TS_18_AS 0x180080
3994 /* [RW 3] The arbitration scheme of time_slot 1 */
3995 #define TSEM_REG_TS_1_AS 0x18003c
3996 /* [RW 3] The arbitration scheme of time_slot 2 */
3997 #define TSEM_REG_TS_2_AS 0x180040
3998 /* [RW 3] The arbitration scheme of time_slot 3 */
3999 #define TSEM_REG_TS_3_AS 0x180044
4000 /* [RW 3] The arbitration scheme of time_slot 4 */
4001 #define TSEM_REG_TS_4_AS 0x180048
4002 /* [RW 3] The arbitration scheme of time_slot 5 */
4003 #define TSEM_REG_TS_5_AS 0x18004c
4004 /* [RW 3] The arbitration scheme of time_slot 6 */
4005 #define TSEM_REG_TS_6_AS 0x180050
4006 /* [RW 3] The arbitration scheme of time_slot 7 */
4007 #define TSEM_REG_TS_7_AS 0x180054
4008 /* [RW 3] The arbitration scheme of time_slot 8 */
4009 #define TSEM_REG_TS_8_AS 0x180058
4010 /* [RW 3] The arbitration scheme of time_slot 9 */
4011 #define TSEM_REG_TS_9_AS 0x18005c
4012 /* [RW 32] Interrupt mask register #0 read/write */
4013 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4014 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4015 /* [R 32] Interrupt register #0 read */
4016 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4017 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4018 /* [RW 32] Parity mask register #0 read/write */
4019 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4020 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4021 /* [R 32] Parity register #0 read */
4022 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4023 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4024 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4025 #define UCM_REG_CAM_OCCUP 0xe0170
4026 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4027 disregarded; valid output is deasserted; all other signals are treated as
4028 usual; if 1 - normal activity. */
4029 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4030 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4031 are disregarded; all other signals are treated as usual; if 1 - normal
4033 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4034 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4035 disregarded; valid output is deasserted; all other signals are treated as
4036 usual; if 1 - normal activity. */
4037 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4038 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4039 input is disregarded; all other signals are treated as usual; if 1 -
4041 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4042 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4043 the initial credit value; read returns the current value of the credit
4044 counter. Must be initialized to 1 at start-up. */
4045 #define UCM_REG_CFC_INIT_CRD 0xe0204
4046 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4047 weight 8 (the most prioritised); 1 stands for weight 1(least
4048 prioritised); 2 stands for weight 2; tc. */
4049 #define UCM_REG_CP_WEIGHT 0xe00c4
4050 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4051 disregarded; acknowledge output is deasserted; all other signals are
4052 treated as usual; if 1 - normal activity. */
4053 #define UCM_REG_CSEM_IFEN 0xe0028
4054 /* [RC 1] Set when the message length mismatch (relative to last indication)
4055 at the csem interface is detected. */
4056 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4057 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4058 weight 8 (the most prioritised); 1 stands for weight 1(least
4059 prioritised); 2 stands for weight 2; tc. */
4060 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4061 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4062 disregarded; acknowledge output is deasserted; all other signals are
4063 treated as usual; if 1 - normal activity. */
4064 #define UCM_REG_DORQ_IFEN 0xe0030
4065 /* [RC 1] Set when the message length mismatch (relative to last indication)
4066 at the dorq interface is detected. */
4067 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4068 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4069 weight 8 (the most prioritised); 1 stands for weight 1(least
4070 prioritised); 2 stands for weight 2; tc. */
4071 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4072 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4073 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4074 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4075 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4076 /* [RW 8] The Event ID for Timers expiration. */
4077 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4078 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4079 writes the initial credit value; read returns the current value of the
4080 credit counter. Must be initialized to 64 at start-up. */
4081 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4082 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4083 writes the initial credit value; read returns the current value of the
4084 credit counter. Must be initialized to 64 at start-up. */
4085 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4086 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4087 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4088 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4089 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4090 #define UCM_REG_GR_ARB_TYPE 0xe0144
4091 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4092 highest priority is 3. It is supposed that the Store channel group is
4093 compliment to the others. */
4094 #define UCM_REG_GR_LD0_PR 0xe014c
4095 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4096 highest priority is 3. It is supposed that the Store channel group is
4097 compliment to the others. */
4098 #define UCM_REG_GR_LD1_PR 0xe0150
4099 /* [RW 2] The queue index for invalidate counter flag decision. */
4100 #define UCM_REG_INV_CFLG_Q 0xe00e4
4101 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4102 sent to STORM; for a specific connection type. the double REG-pairs are
4103 used in order to align to STORM context row size of 128 bits. The offset
4104 of these data in the STORM context is always 0. Index _i stands for the
4105 connection type (one of 16). */
4106 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4107 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4108 #define UCM_REG_N_SM_CTX_LD_10 0xe007c
4109 #define UCM_REG_N_SM_CTX_LD_11 0xe0080
4110 #define UCM_REG_N_SM_CTX_LD_12 0xe0084
4111 #define UCM_REG_N_SM_CTX_LD_13 0xe0088
4112 #define UCM_REG_N_SM_CTX_LD_14 0xe008c
4113 #define UCM_REG_N_SM_CTX_LD_15 0xe0090
4114 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4115 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4116 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4117 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4118 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4119 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4120 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4121 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4122 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4123 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4124 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4125 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4126 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4127 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4128 /* [RC 1] Set when the message length mismatch (relative to last indication)
4129 at the STORM interface is detected. */
4130 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4131 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4132 disregarded; acknowledge output is deasserted; all other signals are
4133 treated as usual; if 1 - normal activity. */
4134 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4135 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4136 weight 8 (the most prioritised); 1 stands for weight 1(least
4137 prioritised); 2 stands for weight 2; tc. */
4138 #define UCM_REG_STORM_WEIGHT 0xe00b0
4139 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4140 writes the initial credit value; read returns the current value of the
4141 credit counter. Must be initialized to 4 at start-up. */
4142 #define UCM_REG_TM_INIT_CRD 0xe021c
4143 /* [RW 28] The CM header for Timers expiration command. */
4144 #define UCM_REG_TM_UCM_HDR 0xe009c
4145 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4146 disregarded; acknowledge output is deasserted; all other signals are
4147 treated as usual; if 1 - normal activity. */
4148 #define UCM_REG_TM_UCM_IFEN 0xe001c
4149 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4150 weight 8 (the most prioritised); 1 stands for weight 1(least
4151 prioritised); 2 stands for weight 2; tc. */
4152 #define UCM_REG_TM_WEIGHT 0xe00d4
4153 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4154 disregarded; acknowledge output is deasserted; all other signals are
4155 treated as usual; if 1 - normal activity. */
4156 #define UCM_REG_TSEM_IFEN 0xe0024
4157 /* [RC 1] Set when the message length mismatch (relative to last indication)
4158 at the tsem interface is detected. */
4159 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4160 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4161 weight 8 (the most prioritised); 1 stands for weight 1(least
4162 prioritised); 2 stands for weight 2; tc. */
4163 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4164 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4165 acknowledge output is deasserted; all other signals are treated as usual;
4166 if 1 - normal activity. */
4167 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4168 /* [RW 11] Interrupt mask register #0 read/write */
4169 #define UCM_REG_UCM_INT_MASK 0xe01d4
4170 /* [R 11] Interrupt register #0 read */
4171 #define UCM_REG_UCM_INT_STS 0xe01c8
4172 /* [R 27] Parity register #0 read */
4173 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4174 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4175 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4176 Is used to determine the number of the AG context REG-pairs written back;
4177 when the Reg1WbFlg isn't set. */
4178 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4179 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4180 disregarded; valid is deasserted; all other signals are treated as usual;
4181 if 1 - normal activity. */
4182 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4183 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4184 disregarded; valid is deasserted; all other signals are treated as usual;
4185 if 1 - normal activity. */
4186 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4187 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4188 disregarded; acknowledge output is deasserted; all other signals are
4189 treated as usual; if 1 - normal activity. */
4190 #define UCM_REG_UCM_TM_IFEN 0xe0020
4191 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4192 disregarded; valid is deasserted; all other signals are treated as usual;
4193 if 1 - normal activity. */
4194 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4195 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4196 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4197 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4198 the initial credit value; read returns the current value of the credit
4199 counter. Must be initialized to 32 at start-up. */
4200 #define UCM_REG_UQM_INIT_CRD 0xe0220
4201 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4202 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4203 prioritised); 2 stands for weight 2; tc. */
4204 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4205 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4206 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4207 prioritised); 2 stands for weight 2; tc. */
4208 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4209 /* [RW 28] The CM header value for QM request (primary). */
4210 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4211 /* [RW 28] The CM header value for QM request (secondary). */
4212 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4213 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4214 acknowledge output is deasserted; all other signals are treated as usual;
4215 if 1 - normal activity. */
4216 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4217 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4218 acknowledge output is deasserted; all other signals are treated as usual;
4219 if 1 - normal activity. */
4220 #define UCM_REG_USDM_IFEN 0xe0018
4221 /* [RC 1] Set when the message length mismatch (relative to last indication)
4222 at the SDM interface is detected. */
4223 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4224 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4225 weight 8 (the most prioritised); 1 stands for weight 1(least
4226 prioritised); 2 stands for weight 2; tc. */
4227 #define UCM_REG_USDM_WEIGHT 0xe00c8
4228 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4229 disregarded; acknowledge output is deasserted; all other signals are
4230 treated as usual; if 1 - normal activity. */
4231 #define UCM_REG_XSEM_IFEN 0xe002c
4232 /* [RC 1] Set when the message length mismatch (relative to last indication)
4233 at the xsem interface isdetected. */
4234 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4235 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4236 weight 8 (the most prioritised); 1 stands for weight 1(least
4237 prioritised); 2 stands for weight 2; tc. */
4238 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4239 /* [RW 20] Indirect access to the descriptor table of the XX protection
4240 mechanism. The fields are:[5:0] - message length; 14:6] - message
4241 pointer; 19:15] - next pointer. */
4242 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4243 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
4244 /* [R 6] Use to read the XX protection Free counter. */
4245 #define UCM_REG_XX_FREE 0xe016c
4246 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4247 of the Input Stage XX protection buffer by the XX protection pending
4248 messages. Write writes the initial credit value; read returns the current
4249 value of the credit counter. Must be initialized to 12 at start-up. */
4250 #define UCM_REG_XX_INIT_CRD 0xe0224
4251 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4252 protection. ~ucm_registers_xx_free.xx_free read on read. */
4253 #define UCM_REG_XX_MSG_NUM 0xe0228
4254 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4255 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4256 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4257 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4259 #define UCM_REG_XX_TABLE 0xe0300
4260 /* [RW 8] The event id for aggregated interrupt 0 */
4261 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
4262 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
4263 #define USDM_REG_AGG_INT_EVENT_10 0xc4060
4264 #define USDM_REG_AGG_INT_EVENT_11 0xc4064
4265 #define USDM_REG_AGG_INT_EVENT_12 0xc4068
4266 #define USDM_REG_AGG_INT_EVENT_13 0xc406c
4267 #define USDM_REG_AGG_INT_EVENT_14 0xc4070
4268 #define USDM_REG_AGG_INT_EVENT_15 0xc4074
4269 #define USDM_REG_AGG_INT_EVENT_16 0xc4078
4270 #define USDM_REG_AGG_INT_EVENT_17 0xc407c
4271 #define USDM_REG_AGG_INT_EVENT_18 0xc4080
4272 #define USDM_REG_AGG_INT_EVENT_19 0xc4084
4273 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
4274 #define USDM_REG_AGG_INT_EVENT_20 0xc4088
4275 #define USDM_REG_AGG_INT_EVENT_21 0xc408c
4276 #define USDM_REG_AGG_INT_EVENT_22 0xc4090
4277 #define USDM_REG_AGG_INT_EVENT_23 0xc4094
4278 #define USDM_REG_AGG_INT_EVENT_24 0xc4098
4279 #define USDM_REG_AGG_INT_EVENT_25 0xc409c
4280 #define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4281 #define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4282 #define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4283 #define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4284 #define USDM_REG_AGG_INT_EVENT_3 0xc4044
4285 #define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4286 #define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4287 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
4288 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
4289 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4290 or auto-mask-mode (1) */
4291 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
4292 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
4293 #define USDM_REG_AGG_INT_MODE_10 0xc41e0
4294 #define USDM_REG_AGG_INT_MODE_11 0xc41e4
4295 #define USDM_REG_AGG_INT_MODE_12 0xc41e8
4296 #define USDM_REG_AGG_INT_MODE_13 0xc41ec
4297 #define USDM_REG_AGG_INT_MODE_14 0xc41f0
4298 #define USDM_REG_AGG_INT_MODE_15 0xc41f4
4299 #define USDM_REG_AGG_INT_MODE_16 0xc41f8
4300 #define USDM_REG_AGG_INT_MODE_17 0xc41fc
4301 #define USDM_REG_AGG_INT_MODE_18 0xc4200
4302 #define USDM_REG_AGG_INT_MODE_19 0xc4204
4303 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
4304 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
4305 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4306 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4307 /* [RW 16] The maximum value of the competion counter #0 */
4308 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4309 /* [RW 16] The maximum value of the competion counter #1 */
4310 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4311 /* [RW 16] The maximum value of the competion counter #2 */
4312 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4313 /* [RW 16] The maximum value of the competion counter #3 */
4314 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4315 /* [RW 13] The start address in the internal RAM for the completion
4317 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4318 #define USDM_REG_ENABLE_IN1 0xc4238
4319 #define USDM_REG_ENABLE_IN2 0xc423c
4320 #define USDM_REG_ENABLE_OUT1 0xc4240
4321 #define USDM_REG_ENABLE_OUT2 0xc4244
4322 /* [RW 4] The initial number of messages that can be sent to the pxp control
4323 interface without receiving any ACK. */
4324 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4325 /* [ST 32] The number of ACK after placement messages received */
4326 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4327 /* [ST 32] The number of packet end messages received from the parser */
4328 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4329 /* [ST 32] The number of requests received from the pxp async if */
4330 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4331 /* [ST 32] The number of commands received in queue 0 */
4332 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4333 /* [ST 32] The number of commands received in queue 10 */
4334 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4335 /* [ST 32] The number of commands received in queue 11 */
4336 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4337 /* [ST 32] The number of commands received in queue 1 */
4338 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4339 /* [ST 32] The number of commands received in queue 2 */
4340 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4341 /* [ST 32] The number of commands received in queue 3 */
4342 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4343 /* [ST 32] The number of commands received in queue 4 */
4344 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4345 /* [ST 32] The number of commands received in queue 5 */
4346 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4347 /* [ST 32] The number of commands received in queue 6 */
4348 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4349 /* [ST 32] The number of commands received in queue 7 */
4350 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4351 /* [ST 32] The number of commands received in queue 8 */
4352 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4353 /* [ST 32] The number of commands received in queue 9 */
4354 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4355 /* [RW 13] The start address in the internal RAM for the packet end message */
4356 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4357 /* [RW 13] The start address in the internal RAM for queue counters */
4358 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4359 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4360 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4361 /* [R 1] parser fifo empty in sdm_sync block */
4362 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4363 /* [R 1] parser serial fifo empty in sdm_sync block */
4364 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4365 /* [RW 32] Tick for timer counter. Applicable only when
4366 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4367 #define USDM_REG_TIMER_TICK 0xc4000
4368 /* [RW 32] Interrupt mask register #0 read/write */
4369 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
4370 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
4371 /* [R 32] Interrupt register #0 read */
4372 #define USDM_REG_USDM_INT_STS_0 0xc4294
4373 #define USDM_REG_USDM_INT_STS_1 0xc42a4
4374 /* [RW 11] Parity mask register #0 read/write */
4375 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
4376 /* [R 11] Parity register #0 read */
4377 #define USDM_REG_USDM_PRTY_STS 0xc42b4
4378 /* [RW 5] The number of time_slots in the arbitration cycle */
4379 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
4380 /* [RW 3] The source that is associated with arbitration element 0. Source
4381 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4382 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4383 #define USEM_REG_ARB_ELEMENT0 0x300020
4384 /* [RW 3] The source that is associated with arbitration element 1. Source
4385 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4386 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4387 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4388 #define USEM_REG_ARB_ELEMENT1 0x300024
4389 /* [RW 3] The source that is associated with arbitration element 2. Source
4390 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4391 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4392 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4393 and ~usem_registers_arb_element1.arb_element1 */
4394 #define USEM_REG_ARB_ELEMENT2 0x300028
4395 /* [RW 3] The source that is associated with arbitration element 3. Source
4396 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4397 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4398 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4399 ~usem_registers_arb_element1.arb_element1 and
4400 ~usem_registers_arb_element2.arb_element2 */
4401 #define USEM_REG_ARB_ELEMENT3 0x30002c
4402 /* [RW 3] The source that is associated with arbitration element 4. Source
4403 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4404 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4405 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4406 and ~usem_registers_arb_element1.arb_element1 and
4407 ~usem_registers_arb_element2.arb_element2 and
4408 ~usem_registers_arb_element3.arb_element3 */
4409 #define USEM_REG_ARB_ELEMENT4 0x300030
4410 #define USEM_REG_ENABLE_IN 0x3000a4
4411 #define USEM_REG_ENABLE_OUT 0x3000a8
4412 /* [RW 32] This address space contains all registers and memories that are
4413 placed in SEM_FAST block. The SEM_FAST registers are described in
4414 appendix B. In order to access the sem_fast registers the base address
4415 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4416 #define USEM_REG_FAST_MEMORY 0x320000
4417 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4419 #define USEM_REG_FIC0_DISABLE 0x300224
4420 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4422 #define USEM_REG_FIC1_DISABLE 0x300234
4423 /* [RW 15] Interrupt table Read and write access to it is not possible in
4424 the middle of the work */
4425 #define USEM_REG_INT_TABLE 0x300400
4426 /* [ST 24] Statistics register. The number of messages that entered through
4428 #define USEM_REG_MSG_NUM_FIC0 0x300000
4429 /* [ST 24] Statistics register. The number of messages that entered through
4431 #define USEM_REG_MSG_NUM_FIC1 0x300004
4432 /* [ST 24] Statistics register. The number of messages that were sent to
4434 #define USEM_REG_MSG_NUM_FOC0 0x300008
4435 /* [ST 24] Statistics register. The number of messages that were sent to
4437 #define USEM_REG_MSG_NUM_FOC1 0x30000c
4438 /* [ST 24] Statistics register. The number of messages that were sent to
4440 #define USEM_REG_MSG_NUM_FOC2 0x300010
4441 /* [ST 24] Statistics register. The number of messages that were sent to
4443 #define USEM_REG_MSG_NUM_FOC3 0x300014
4444 /* [RW 1] Disables input messages from the passive buffer May be updated
4445 during run_time by the microcode */
4446 #define USEM_REG_PAS_DISABLE 0x30024c
4447 /* [WB 128] Debug only. Passive buffer memory */
4448 #define USEM_REG_PASSIVE_BUFFER 0x302000
4449 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4450 #define USEM_REG_PRAM 0x340000
4451 /* [R 16] Valid sleeping threads indication have bit per thread */
4452 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4453 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4454 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4455 /* [RW 16] List of free threads . There is a bit per thread. */
4456 #define USEM_REG_THREADS_LIST 0x3002e4
4457 /* [RW 3] The arbitration scheme of time_slot 0 */
4458 #define USEM_REG_TS_0_AS 0x300038
4459 /* [RW 3] The arbitration scheme of time_slot 10 */
4460 #define USEM_REG_TS_10_AS 0x300060
4461 /* [RW 3] The arbitration scheme of time_slot 11 */
4462 #define USEM_REG_TS_11_AS 0x300064
4463 /* [RW 3] The arbitration scheme of time_slot 12 */
4464 #define USEM_REG_TS_12_AS 0x300068
4465 /* [RW 3] The arbitration scheme of time_slot 13 */
4466 #define USEM_REG_TS_13_AS 0x30006c
4467 /* [RW 3] The arbitration scheme of time_slot 14 */
4468 #define USEM_REG_TS_14_AS 0x300070
4469 /* [RW 3] The arbitration scheme of time_slot 15 */
4470 #define USEM_REG_TS_15_AS 0x300074
4471 /* [RW 3] The arbitration scheme of time_slot 16 */
4472 #define USEM_REG_TS_16_AS 0x300078
4473 /* [RW 3] The arbitration scheme of time_slot 17 */
4474 #define USEM_REG_TS_17_AS 0x30007c
4475 /* [RW 3] The arbitration scheme of time_slot 18 */
4476 #define USEM_REG_TS_18_AS 0x300080
4477 /* [RW 3] The arbitration scheme of time_slot 1 */
4478 #define USEM_REG_TS_1_AS 0x30003c
4479 /* [RW 3] The arbitration scheme of time_slot 2 */
4480 #define USEM_REG_TS_2_AS 0x300040
4481 /* [RW 3] The arbitration scheme of time_slot 3 */
4482 #define USEM_REG_TS_3_AS 0x300044
4483 /* [RW 3] The arbitration scheme of time_slot 4 */
4484 #define USEM_REG_TS_4_AS 0x300048
4485 /* [RW 3] The arbitration scheme of time_slot 5 */
4486 #define USEM_REG_TS_5_AS 0x30004c
4487 /* [RW 3] The arbitration scheme of time_slot 6 */
4488 #define USEM_REG_TS_6_AS 0x300050
4489 /* [RW 3] The arbitration scheme of time_slot 7 */
4490 #define USEM_REG_TS_7_AS 0x300054
4491 /* [RW 3] The arbitration scheme of time_slot 8 */
4492 #define USEM_REG_TS_8_AS 0x300058
4493 /* [RW 3] The arbitration scheme of time_slot 9 */
4494 #define USEM_REG_TS_9_AS 0x30005c
4495 /* [RW 32] Interrupt mask register #0 read/write */
4496 #define USEM_REG_USEM_INT_MASK_0 0x300110
4497 #define USEM_REG_USEM_INT_MASK_1 0x300120
4498 /* [R 32] Interrupt register #0 read */
4499 #define USEM_REG_USEM_INT_STS_0 0x300104
4500 #define USEM_REG_USEM_INT_STS_1 0x300114
4501 /* [RW 32] Parity mask register #0 read/write */
4502 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
4503 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
4504 /* [R 32] Parity register #0 read */
4505 #define USEM_REG_USEM_PRTY_STS_0 0x300124
4506 #define USEM_REG_USEM_PRTY_STS_1 0x300134
4507 /* [RW 2] The queue index for registration on Aux1 counter flag. */
4508 #define XCM_REG_AUX1_Q 0x20134
4509 /* [RW 2] Per each decision rule the queue index to register to. */
4510 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4511 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4512 #define XCM_REG_CAM_OCCUP 0x20244
4513 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4514 disregarded; valid output is deasserted; all other signals are treated as
4515 usual; if 1 - normal activity. */
4516 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
4517 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4518 are disregarded; all other signals are treated as usual; if 1 - normal
4520 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
4521 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4522 disregarded; valid output is deasserted; all other signals are treated as
4523 usual; if 1 - normal activity. */
4524 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4525 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4526 input is disregarded; all other signals are treated as usual; if 1 -
4528 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
4529 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4530 the initial credit value; read returns the current value of the credit
4531 counter. Must be initialized to 1 at start-up. */
4532 #define XCM_REG_CFC_INIT_CRD 0x20404
4533 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4534 weight 8 (the most prioritised); 1 stands for weight 1(least
4535 prioritised); 2 stands for weight 2; tc. */
4536 #define XCM_REG_CP_WEIGHT 0x200dc
4537 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4538 disregarded; acknowledge output is deasserted; all other signals are
4539 treated as usual; if 1 - normal activity. */
4540 #define XCM_REG_CSEM_IFEN 0x20028
4541 /* [RC 1] Set at message length mismatch (relative to last indication) at
4542 the csem interface. */
4543 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
4544 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4545 weight 8 (the most prioritised); 1 stands for weight 1(least
4546 prioritised); 2 stands for weight 2; tc. */
4547 #define XCM_REG_CSEM_WEIGHT 0x200c4
4548 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4549 disregarded; acknowledge output is deasserted; all other signals are
4550 treated as usual; if 1 - normal activity. */
4551 #define XCM_REG_DORQ_IFEN 0x20030
4552 /* [RC 1] Set at message length mismatch (relative to last indication) at
4553 the dorq interface. */
4554 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
4555 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4556 weight 8 (the most prioritised); 1 stands for weight 1(least
4557 prioritised); 2 stands for weight 2; tc. */
4558 #define XCM_REG_DORQ_WEIGHT 0x200cc
4559 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4560 #define XCM_REG_ERR_EVNT_ID 0x200b0
4561 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4562 #define XCM_REG_ERR_XCM_HDR 0x200ac
4563 /* [RW 8] The Event ID for Timers expiration. */
4564 #define XCM_REG_EXPR_EVNT_ID 0x200b4
4565 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4566 writes the initial credit value; read returns the current value of the
4567 credit counter. Must be initialized to 64 at start-up. */
4568 #define XCM_REG_FIC0_INIT_CRD 0x2040c
4569 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4570 writes the initial credit value; read returns the current value of the
4571 credit counter. Must be initialized to 64 at start-up. */
4572 #define XCM_REG_FIC1_INIT_CRD 0x20410
4573 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4574 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
4575 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4576 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4577 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4578 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4579 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4580 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4581 #define XCM_REG_GR_ARB_TYPE 0x2020c
4582 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4583 highest priority is 3. It is supposed that the Channel group is the
4584 compliment of the other 3 groups. */
4585 #define XCM_REG_GR_LD0_PR 0x20214
4586 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4587 highest priority is 3. It is supposed that the Channel group is the
4588 compliment of the other 3 groups. */
4589 #define XCM_REG_GR_LD1_PR 0x20218
4590 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4591 disregarded; acknowledge output is deasserted; all other signals are
4592 treated as usual; if 1 - normal activity. */
4593 #define XCM_REG_NIG0_IFEN 0x20038
4594 /* [RC 1] Set at message length mismatch (relative to last indication) at
4595 the nig0 interface. */
4596 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
4597 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4598 weight 8 (the most prioritised); 1 stands for weight 1(least
4599 prioritised); 2 stands for weight 2; tc. */
4600 #define XCM_REG_NIG0_WEIGHT 0x200d4
4601 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4602 disregarded; acknowledge output is deasserted; all other signals are
4603 treated as usual; if 1 - normal activity. */
4604 #define XCM_REG_NIG1_IFEN 0x2003c
4605 /* [RC 1] Set at message length mismatch (relative to last indication) at
4606 the nig1 interface. */
4607 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4608 /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
4609 weight 8 (the most prioritised); 1 stands for weight 1(least
4610 prioritised); 2 stands for weight 2; tc. */
4611 #define XCM_REG_NIG1_WEIGHT 0x200d8
4612 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4613 sent to STORM; for a specific connection type. The double REG-pairs are
4614 used in order to align to STORM context row size of 128 bits. The offset
4615 of these data in the STORM context is always 0. Index _i stands for the
4616 connection type (one of 16). */
4617 #define XCM_REG_N_SM_CTX_LD_0 0x20060
4618 #define XCM_REG_N_SM_CTX_LD_1 0x20064
4619 #define XCM_REG_N_SM_CTX_LD_10 0x20088
4620 #define XCM_REG_N_SM_CTX_LD_11 0x2008c
4621 #define XCM_REG_N_SM_CTX_LD_12 0x20090
4622 #define XCM_REG_N_SM_CTX_LD_13 0x20094
4623 #define XCM_REG_N_SM_CTX_LD_14 0x20098
4624 #define XCM_REG_N_SM_CTX_LD_15 0x2009c
4625 #define XCM_REG_N_SM_CTX_LD_2 0x20068
4626 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
4627 #define XCM_REG_N_SM_CTX_LD_4 0x20070
4628 #define XCM_REG_N_SM_CTX_LD_5 0x20074
4629 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4630 acknowledge output is deasserted; all other signals are treated as usual;
4631 if 1 - normal activity. */
4632 #define XCM_REG_PBF_IFEN 0x20034
4633 /* [RC 1] Set at message length mismatch (relative to last indication) at
4634 the pbf interface. */
4635 #define XCM_REG_PBF_LENGTH_MIS 0x20234
4636 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4637 weight 8 (the most prioritised); 1 stands for weight 1(least
4638 prioritised); 2 stands for weight 2; tc. */
4639 #define XCM_REG_PBF_WEIGHT 0x200d0
4640 #define XCM_REG_PHYS_QNUM3_0 0x20100
4641 #define XCM_REG_PHYS_QNUM3_1 0x20104
4642 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4643 #define XCM_REG_STOP_EVNT_ID 0x200b8
4644 /* [RC 1] Set at message length mismatch (relative to last indication) at
4645 the STORM interface. */
4646 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
4647 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4648 weight 8 (the most prioritised); 1 stands for weight 1(least
4649 prioritised); 2 stands for weight 2; tc. */
4650 #define XCM_REG_STORM_WEIGHT 0x200bc
4651 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4652 disregarded; acknowledge output is deasserted; all other signals are
4653 treated as usual; if 1 - normal activity. */
4654 #define XCM_REG_STORM_XCM_IFEN 0x20010
4655 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4656 writes the initial credit value; read returns the current value of the
4657 credit counter. Must be initialized to 4 at start-up. */
4658 #define XCM_REG_TM_INIT_CRD 0x2041c
4659 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4660 weight 8 (the most prioritised); 1 stands for weight 1(least
4661 prioritised); 2 stands for weight 2; tc. */
4662 #define XCM_REG_TM_WEIGHT 0x200ec
4663 /* [RW 28] The CM header for Timers expiration command. */
4664 #define XCM_REG_TM_XCM_HDR 0x200a8
4665 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4666 disregarded; acknowledge output is deasserted; all other signals are
4667 treated as usual; if 1 - normal activity. */
4668 #define XCM_REG_TM_XCM_IFEN 0x2001c
4669 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4670 disregarded; acknowledge output is deasserted; all other signals are
4671 treated as usual; if 1 - normal activity. */
4672 #define XCM_REG_TSEM_IFEN 0x20024
4673 /* [RC 1] Set at message length mismatch (relative to last indication) at
4674 the tsem interface. */
4675 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4676 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4677 weight 8 (the most prioritised); 1 stands for weight 1(least
4678 prioritised); 2 stands for weight 2; tc. */
4679 #define XCM_REG_TSEM_WEIGHT 0x200c0
4680 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4681 #define XCM_REG_UNA_GT_NXT_Q 0x20120
4682 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4683 disregarded; acknowledge output is deasserted; all other signals are
4684 treated as usual; if 1 - normal activity. */
4685 #define XCM_REG_USEM_IFEN 0x2002c
4686 /* [RC 1] Message length mismatch (relative to last indication) at the usem
4688 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
4689 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4690 weight 8 (the most prioritised); 1 stands for weight 1(least
4691 prioritised); 2 stands for weight 2; tc. */
4692 #define XCM_REG_USEM_WEIGHT 0x200c8
4693 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
4694 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
4695 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
4696 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
4697 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
4698 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
4699 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
4700 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
4701 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
4702 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
4703 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
4704 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4705 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4706 acknowledge output is deasserted; all other signals are treated as usual;
4707 if 1 - normal activity. */
4708 #define XCM_REG_XCM_CFC_IFEN 0x20050
4709 /* [RW 14] Interrupt mask register #0 read/write */
4710 #define XCM_REG_XCM_INT_MASK 0x202b4
4711 /* [R 14] Interrupt register #0 read */
4712 #define XCM_REG_XCM_INT_STS 0x202a8
4713 /* [R 30] Parity register #0 read */
4714 #define XCM_REG_XCM_PRTY_STS 0x202b8
4715 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4716 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4717 Is used to determine the number of the AG context REG-pairs written back;
4718 when the Reg1WbFlg isn't set. */
4719 #define XCM_REG_XCM_REG0_SZ 0x200f4
4720 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4721 disregarded; valid is deasserted; all other signals are treated as usual;
4722 if 1 - normal activity. */
4723 #define XCM_REG_XCM_STORM0_IFEN 0x20004
4724 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4725 disregarded; valid is deasserted; all other signals are treated as usual;
4726 if 1 - normal activity. */
4727 #define XCM_REG_XCM_STORM1_IFEN 0x20008
4728 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4729 disregarded; acknowledge output is deasserted; all other signals are
4730 treated as usual; if 1 - normal activity. */
4731 #define XCM_REG_XCM_TM_IFEN 0x20020
4732 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4733 disregarded; valid is deasserted; all other signals are treated as usual;
4734 if 1 - normal activity. */
4735 #define XCM_REG_XCM_XQM_IFEN 0x2000c
4736 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4737 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
4738 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4739 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4740 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4741 the initial credit value; read returns the current value of the credit
4742 counter. Must be initialized to 32 at start-up. */
4743 #define XCM_REG_XQM_INIT_CRD 0x20420
4744 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4745 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4746 prioritised); 2 stands for weight 2; tc. */
4747 #define XCM_REG_XQM_P_WEIGHT 0x200e4
4748 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4749 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4750 prioritised); 2 stands for weight 2; tc. */
4751 #define XCM_REG_XQM_S_WEIGHT 0x200e8
4752 /* [RW 28] The CM header value for QM request (primary). */
4753 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
4754 /* [RW 28] The CM header value for QM request (secondary). */
4755 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
4756 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4757 acknowledge output is deasserted; all other signals are treated as usual;
4758 if 1 - normal activity. */
4759 #define XCM_REG_XQM_XCM_IFEN 0x20014
4760 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4761 acknowledge output is deasserted; all other signals are treated as usual;
4762 if 1 - normal activity. */
4763 #define XCM_REG_XSDM_IFEN 0x20018
4764 /* [RC 1] Set at message length mismatch (relative to last indication) at
4765 the SDM interface. */
4766 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
4767 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4768 weight 8 (the most prioritised); 1 stands for weight 1(least
4769 prioritised); 2 stands for weight 2; tc. */
4770 #define XCM_REG_XSDM_WEIGHT 0x200e0
4771 /* [RW 17] Indirect access to the descriptor table of the XX protection
4772 mechanism. The fields are: [5:0] - message length; 11:6] - message
4773 pointer; 16:12] - next pointer. */
4774 #define XCM_REG_XX_DESCR_TABLE 0x20480
4775 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
4776 /* [R 6] Used to read the XX protection Free counter. */
4777 #define XCM_REG_XX_FREE 0x20240
4778 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4779 of the Input Stage XX protection buffer by the XX protection pending
4780 messages. Max credit available - 3.Write writes the initial credit value;
4781 read returns the current value of the credit counter. Must be initialized
4782 to 2 at start-up. */
4783 #define XCM_REG_XX_INIT_CRD 0x20424
4784 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4785 protection. ~xcm_registers_xx_free.xx_free read on read. */
4786 #define XCM_REG_XX_MSG_NUM 0x20428
4787 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4788 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
4789 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4790 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4792 #define XCM_REG_XX_TABLE 0x20500
4793 /* [RW 8] The event id for aggregated interrupt 0 */
4794 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
4795 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4796 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4797 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4798 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4799 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4800 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4801 #define XSDM_REG_AGG_INT_EVENT_15 0x166074
4802 #define XSDM_REG_AGG_INT_EVENT_16 0x166078
4803 #define XSDM_REG_AGG_INT_EVENT_17 0x16607c
4804 #define XSDM_REG_AGG_INT_EVENT_18 0x166080
4805 #define XSDM_REG_AGG_INT_EVENT_19 0x166084
4806 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4807 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4808 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4809 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4810 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4811 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
4812 #define XSDM_REG_AGG_INT_EVENT_20 0x166088
4813 #define XSDM_REG_AGG_INT_EVENT_21 0x16608c
4814 #define XSDM_REG_AGG_INT_EVENT_22 0x166090
4815 #define XSDM_REG_AGG_INT_EVENT_23 0x166094
4816 #define XSDM_REG_AGG_INT_EVENT_24 0x166098
4817 #define XSDM_REG_AGG_INT_EVENT_25 0x16609c
4818 #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
4819 #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
4820 #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
4821 #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
4822 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
4823 #define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4824 #define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4825 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
4826 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4827 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
4828 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
4829 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
4830 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
4831 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4832 or auto-mask-mode (1) */
4833 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4834 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4835 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0
4836 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4
4837 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8
4838 #define XSDM_REG_AGG_INT_MODE_13 0x1661ec
4839 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0
4840 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4
4841 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8
4842 #define XSDM_REG_AGG_INT_MODE_17 0x1661fc
4843 #define XSDM_REG_AGG_INT_MODE_18 0x166200
4844 #define XSDM_REG_AGG_INT_MODE_19 0x166204
4845 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4846 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4847 /* [RW 16] The maximum value of the competion counter #0 */
4848 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4849 /* [RW 16] The maximum value of the competion counter #1 */
4850 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4851 /* [RW 16] The maximum value of the competion counter #2 */
4852 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4853 /* [RW 16] The maximum value of the competion counter #3 */
4854 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4855 /* [RW 13] The start address in the internal RAM for the completion
4857 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4858 #define XSDM_REG_ENABLE_IN1 0x166238
4859 #define XSDM_REG_ENABLE_IN2 0x16623c
4860 #define XSDM_REG_ENABLE_OUT1 0x166240
4861 #define XSDM_REG_ENABLE_OUT2 0x166244
4862 /* [RW 4] The initial number of messages that can be sent to the pxp control
4863 interface without receiving any ACK. */
4864 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4865 /* [ST 32] The number of ACK after placement messages received */
4866 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4867 /* [ST 32] The number of packet end messages received from the parser */
4868 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4869 /* [ST 32] The number of requests received from the pxp async if */
4870 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4871 /* [ST 32] The number of commands received in queue 0 */
4872 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4873 /* [ST 32] The number of commands received in queue 10 */
4874 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4875 /* [ST 32] The number of commands received in queue 11 */
4876 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4877 /* [ST 32] The number of commands received in queue 1 */
4878 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4879 /* [ST 32] The number of commands received in queue 3 */
4880 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4881 /* [ST 32] The number of commands received in queue 4 */
4882 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4883 /* [ST 32] The number of commands received in queue 5 */
4884 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4885 /* [ST 32] The number of commands received in queue 6 */
4886 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4887 /* [ST 32] The number of commands received in queue 7 */
4888 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4889 /* [ST 32] The number of commands received in queue 8 */
4890 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4891 /* [ST 32] The number of commands received in queue 9 */
4892 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4893 /* [RW 13] The start address in the internal RAM for queue counters */
4894 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4895 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4896 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4897 /* [R 1] parser fifo empty in sdm_sync block */
4898 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4899 /* [R 1] parser serial fifo empty in sdm_sync block */
4900 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4901 /* [RW 32] Tick for timer counter. Applicable only when
4902 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4903 #define XSDM_REG_TIMER_TICK 0x166000
4904 /* [RW 32] Interrupt mask register #0 read/write */
4905 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
4906 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
4907 /* [R 32] Interrupt register #0 read */
4908 #define XSDM_REG_XSDM_INT_STS_0 0x166290
4909 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
4910 /* [RW 11] Parity mask register #0 read/write */
4911 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
4912 /* [R 11] Parity register #0 read */
4913 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
4914 /* [RW 5] The number of time_slots in the arbitration cycle */
4915 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
4916 /* [RW 3] The source that is associated with arbitration element 0. Source
4917 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4918 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4919 #define XSEM_REG_ARB_ELEMENT0 0x280020
4920 /* [RW 3] The source that is associated with arbitration element 1. Source
4921 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4922 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4923 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
4924 #define XSEM_REG_ARB_ELEMENT1 0x280024
4925 /* [RW 3] The source that is associated with arbitration element 2. Source
4926 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4927 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4928 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4929 and ~xsem_registers_arb_element1.arb_element1 */
4930 #define XSEM_REG_ARB_ELEMENT2 0x280028
4931 /* [RW 3] The source that is associated with arbitration element 3. Source
4932 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4933 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4934 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
4935 ~xsem_registers_arb_element1.arb_element1 and
4936 ~xsem_registers_arb_element2.arb_element2 */
4937 #define XSEM_REG_ARB_ELEMENT3 0x28002c
4938 /* [RW 3] The source that is associated with arbitration element 4. Source
4939 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4940 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4941 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4942 and ~xsem_registers_arb_element1.arb_element1 and
4943 ~xsem_registers_arb_element2.arb_element2 and
4944 ~xsem_registers_arb_element3.arb_element3 */
4945 #define XSEM_REG_ARB_ELEMENT4 0x280030
4946 #define XSEM_REG_ENABLE_IN 0x2800a4
4947 #define XSEM_REG_ENABLE_OUT 0x2800a8
4948 /* [RW 32] This address space contains all registers and memories that are
4949 placed in SEM_FAST block. The SEM_FAST registers are described in
4950 appendix B. In order to access the sem_fast registers the base address
4951 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4952 #define XSEM_REG_FAST_MEMORY 0x2a0000
4953 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4955 #define XSEM_REG_FIC0_DISABLE 0x280224
4956 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4958 #define XSEM_REG_FIC1_DISABLE 0x280234
4959 /* [RW 15] Interrupt table Read and write access to it is not possible in
4960 the middle of the work */
4961 #define XSEM_REG_INT_TABLE 0x280400
4962 /* [ST 24] Statistics register. The number of messages that entered through
4964 #define XSEM_REG_MSG_NUM_FIC0 0x280000
4965 /* [ST 24] Statistics register. The number of messages that entered through
4967 #define XSEM_REG_MSG_NUM_FIC1 0x280004
4968 /* [ST 24] Statistics register. The number of messages that were sent to
4970 #define XSEM_REG_MSG_NUM_FOC0 0x280008
4971 /* [ST 24] Statistics register. The number of messages that were sent to
4973 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
4974 /* [ST 24] Statistics register. The number of messages that were sent to
4976 #define XSEM_REG_MSG_NUM_FOC2 0x280010
4977 /* [ST 24] Statistics register. The number of messages that were sent to
4979 #define XSEM_REG_MSG_NUM_FOC3 0x280014
4980 /* [RW 1] Disables input messages from the passive buffer May be updated
4981 during run_time by the microcode */
4982 #define XSEM_REG_PAS_DISABLE 0x28024c
4983 /* [WB 128] Debug only. Passive buffer memory */
4984 #define XSEM_REG_PASSIVE_BUFFER 0x282000
4985 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4986 #define XSEM_REG_PRAM 0x2c0000
4987 /* [R 16] Valid sleeping threads indication have bit per thread */
4988 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
4989 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4990 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
4991 /* [RW 16] List of free threads . There is a bit per thread. */
4992 #define XSEM_REG_THREADS_LIST 0x2802e4
4993 /* [RW 3] The arbitration scheme of time_slot 0 */
4994 #define XSEM_REG_TS_0_AS 0x280038
4995 /* [RW 3] The arbitration scheme of time_slot 10 */
4996 #define XSEM_REG_TS_10_AS 0x280060
4997 /* [RW 3] The arbitration scheme of time_slot 11 */
4998 #define XSEM_REG_TS_11_AS 0x280064
4999 /* [RW 3] The arbitration scheme of time_slot 12 */
5000 #define XSEM_REG_TS_12_AS 0x280068
5001 /* [RW 3] The arbitration scheme of time_slot 13 */
5002 #define XSEM_REG_TS_13_AS 0x28006c
5003 /* [RW 3] The arbitration scheme of time_slot 14 */
5004 #define XSEM_REG_TS_14_AS 0x280070
5005 /* [RW 3] The arbitration scheme of time_slot 15 */
5006 #define XSEM_REG_TS_15_AS 0x280074
5007 /* [RW 3] The arbitration scheme of time_slot 16 */
5008 #define XSEM_REG_TS_16_AS 0x280078
5009 /* [RW 3] The arbitration scheme of time_slot 17 */
5010 #define XSEM_REG_TS_17_AS 0x28007c
5011 /* [RW 3] The arbitration scheme of time_slot 18 */
5012 #define XSEM_REG_TS_18_AS 0x280080
5013 /* [RW 3] The arbitration scheme of time_slot 1 */
5014 #define XSEM_REG_TS_1_AS 0x28003c
5015 /* [RW 3] The arbitration scheme of time_slot 2 */
5016 #define XSEM_REG_TS_2_AS 0x280040
5017 /* [RW 3] The arbitration scheme of time_slot 3 */
5018 #define XSEM_REG_TS_3_AS 0x280044
5019 /* [RW 3] The arbitration scheme of time_slot 4 */
5020 #define XSEM_REG_TS_4_AS 0x280048
5021 /* [RW 3] The arbitration scheme of time_slot 5 */
5022 #define XSEM_REG_TS_5_AS 0x28004c
5023 /* [RW 3] The arbitration scheme of time_slot 6 */
5024 #define XSEM_REG_TS_6_AS 0x280050
5025 /* [RW 3] The arbitration scheme of time_slot 7 */
5026 #define XSEM_REG_TS_7_AS 0x280054
5027 /* [RW 3] The arbitration scheme of time_slot 8 */
5028 #define XSEM_REG_TS_8_AS 0x280058
5029 /* [RW 3] The arbitration scheme of time_slot 9 */
5030 #define XSEM_REG_TS_9_AS 0x28005c
5031 /* [RW 32] Interrupt mask register #0 read/write */
5032 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5033 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5034 /* [R 32] Interrupt register #0 read */
5035 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5036 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5037 /* [RW 32] Parity mask register #0 read/write */
5038 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5039 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5040 /* [R 32] Parity register #0 read */
5041 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5042 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5043 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5044 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5045 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5046 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5047 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
5048 #define MCPR_NVM_COMMAND_DONE (1L<<3)
5049 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
5050 #define MCPR_NVM_COMMAND_LAST (1L<<8)
5051 #define MCPR_NVM_COMMAND_WR (1L<<5)
5052 #define MCPR_NVM_COMMAND_WREN (1L<<16)
5053 #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
5054 #define MCPR_NVM_COMMAND_WRDI (1L<<17)
5055 #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
5056 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5057 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5058 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5059 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5060 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5061 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5062 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5063 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5064 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5065 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5066 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5067 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5068 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5069 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5070 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5071 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5072 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5073 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5074 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
5075 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
5076 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5077 #define EMAC_LED_OVERRIDE (1L<<0)
5078 #define EMAC_LED_TRAFFIC (1L<<6)
5079 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5080 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5081 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5082 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5083 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5084 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5085 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5086 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5087 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5088 #define EMAC_MODE_25G_MODE (1L<<5)
5089 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
5090 #define EMAC_MODE_PORT_GMII (2L<<2)
5091 #define EMAC_MODE_PORT_MII (1L<<2)
5092 #define EMAC_MODE_PORT_MII_10M (3L<<2)
5093 #define EMAC_MODE_RESET (1L<<0)
5094 #define EMAC_REG_EMAC_LED 0xc
5095 #define EMAC_REG_EMAC_MAC_MATCH 0x10
5096 #define EMAC_REG_EMAC_MDIO_COMM 0xac
5097 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5098 #define EMAC_REG_EMAC_MODE 0x0
5099 #define EMAC_REG_EMAC_RX_MODE 0xc8
5100 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5101 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5102 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5103 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5104 #define EMAC_REG_EMAC_TX_MODE 0xbc
5105 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5106 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5107 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5108 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5109 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5110 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5111 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5112 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5113 #define MISC_REGISTERS_GPIO_0 0
5114 #define MISC_REGISTERS_GPIO_1 1
5115 #define MISC_REGISTERS_GPIO_2 2
5116 #define MISC_REGISTERS_GPIO_3 3
5117 #define MISC_REGISTERS_GPIO_CLR_POS 16
5118 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5119 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5120 #define MISC_REGISTERS_GPIO_HIGH 1
5121 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5122 #define MISC_REGISTERS_GPIO_LOW 0
5123 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5124 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5125 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5126 #define MISC_REGISTERS_GPIO_SET_POS 8
5127 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5128 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5129 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5130 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5131 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5132 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5133 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5134 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5135 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5136 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5137 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5138 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5139 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5140 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5141 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5142 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5143 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5144 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5145 #define MISC_REGISTERS_SPIO_4 4
5146 #define MISC_REGISTERS_SPIO_5 5
5147 #define MISC_REGISTERS_SPIO_7 7
5148 #define MISC_REGISTERS_SPIO_CLR_POS 16
5149 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5150 #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
5151 #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
5152 #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
5153 #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
5154 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5155 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5156 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5157 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5158 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5159 #define MISC_REGISTERS_SPIO_SET_POS 8
5160 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5161 #define HW_LOCK_RESOURCE_8072_MDIO 0
5162 #define HW_LOCK_RESOURCE_GPIO 1
5163 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5164 #define HW_LOCK_RESOURCE_SPIO 2
5165 #define HW_LOCK_RESOURCE_UNDI 5
5166 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5167 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5168 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5169 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5170 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5171 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5172 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5173 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5174 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5175 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5176 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5177 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5178 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5179 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5180 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5181 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5182 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5183 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5184 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5185 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5186 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5187 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5188 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5189 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5190 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5191 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5192 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
5193 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
5194 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5195 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5196 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5197 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5198 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5199 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5200 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5201 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5202 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5203 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5204 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5205 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5206 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5207 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5208 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5209 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5210 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5211 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5212 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5213 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
5215 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
5216 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5218 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
5219 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
5220 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
5221 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
5222 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
5223 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
5224 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
5225 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
5226 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
5227 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
5228 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
5229 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
5230 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
5231 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
5232 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
5233 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
5235 /* storm asserts attention bits */
5236 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5237 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5238 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5239 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5241 /* mcp error attention bit */
5242 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5244 /*E1H NIG status sync attention mapped to group 4-7*/
5245 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5246 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5247 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5248 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5249 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5250 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5251 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5252 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5255 #define LATCHED_ATTN_RBCR 23
5256 #define LATCHED_ATTN_RBCT 24
5257 #define LATCHED_ATTN_RBCN 25
5258 #define LATCHED_ATTN_RBCU 26
5259 #define LATCHED_ATTN_RBCP 27
5260 #define LATCHED_ATTN_TIMEOUT_GRC 28
5261 #define LATCHED_ATTN_RSVD_GRC 29
5262 #define LATCHED_ATTN_ROM_PARITY_MCP 30
5263 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5264 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5265 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5267 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5268 #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
5270 * This file defines GRC base address for every block.
5271 * This file is included by chipsim, asm microcode and cpp microcode.
5272 * These values are used in Design.xml on regBase attribute
5273 * Use the base with the generated offsets of specific registers.
5276 #define GRCBASE_PXPCS 0x000000
5277 #define GRCBASE_PCICONFIG 0x002000
5278 #define GRCBASE_PCIREG 0x002400
5279 #define GRCBASE_EMAC0 0x008000
5280 #define GRCBASE_EMAC1 0x008400
5281 #define GRCBASE_DBU 0x008800
5282 #define GRCBASE_MISC 0x00A000
5283 #define GRCBASE_DBG 0x00C000
5284 #define GRCBASE_NIG 0x010000
5285 #define GRCBASE_XCM 0x020000
5286 #define GRCBASE_PRS 0x040000
5287 #define GRCBASE_SRCH 0x040400
5288 #define GRCBASE_TSDM 0x042000
5289 #define GRCBASE_TCM 0x050000
5290 #define GRCBASE_BRB1 0x060000
5291 #define GRCBASE_MCP 0x080000
5292 #define GRCBASE_UPB 0x0C1000
5293 #define GRCBASE_CSDM 0x0C2000
5294 #define GRCBASE_USDM 0x0C4000
5295 #define GRCBASE_CCM 0x0D0000
5296 #define GRCBASE_UCM 0x0E0000
5297 #define GRCBASE_CDU 0x101000
5298 #define GRCBASE_DMAE 0x102000
5299 #define GRCBASE_PXP 0x103000
5300 #define GRCBASE_CFC 0x104000
5301 #define GRCBASE_HC 0x108000
5302 #define GRCBASE_PXP2 0x120000
5303 #define GRCBASE_PBF 0x140000
5304 #define GRCBASE_XPB 0x161000
5305 #define GRCBASE_TIMERS 0x164000
5306 #define GRCBASE_XSDM 0x166000
5307 #define GRCBASE_QM 0x168000
5308 #define GRCBASE_DQ 0x170000
5309 #define GRCBASE_TSEM 0x180000
5310 #define GRCBASE_CSEM 0x200000
5311 #define GRCBASE_XSEM 0x280000
5312 #define GRCBASE_USEM 0x300000
5313 #define GRCBASE_MISC_AEU GRCBASE_MISC
5316 /* offset of configuration space in the pci core register */
5317 #define PCICFG_OFFSET 0x2000
5318 #define PCICFG_VENDOR_ID_OFFSET 0x00
5319 #define PCICFG_DEVICE_ID_OFFSET 0x02
5320 #define PCICFG_COMMAND_OFFSET 0x04
5321 #define PCICFG_COMMAND_IO_SPACE (1<<0)
5322 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
5323 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
5324 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5325 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5326 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5327 #define PCICFG_COMMAND_PERR_ENA (1<<6)
5328 #define PCICFG_COMMAND_STEPPING (1<<7)
5329 #define PCICFG_COMMAND_SERR_ENA (1<<8)
5330 #define PCICFG_COMMAND_FAST_B2B (1<<9)
5331 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
5332 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
5333 #define PCICFG_STATUS_OFFSET 0x06
5334 #define PCICFG_REVESION_ID 0x08
5335 #define PCICFG_CACHE_LINE_SIZE 0x0c
5336 #define PCICFG_LATENCY_TIMER 0x0d
5337 #define PCICFG_BAR_1_LOW 0x10
5338 #define PCICFG_BAR_1_HIGH 0x14
5339 #define PCICFG_BAR_2_LOW 0x18
5340 #define PCICFG_BAR_2_HIGH 0x1c
5341 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5342 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5343 #define PCICFG_INT_LINE 0x3c
5344 #define PCICFG_INT_PIN 0x3d
5345 #define PCICFG_PM_CAPABILITY 0x48
5346 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5347 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5348 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5349 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
5350 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5351 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5352 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5353 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5354 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5355 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5356 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5357 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5358 #define PCICFG_PM_CSR_OFFSET 0x4c
5359 #define PCICFG_PM_CSR_STATE (0x3<<0)
5360 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5361 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
5362 #define PCICFG_GRC_ADDRESS 0x78
5363 #define PCICFG_GRC_DATA 0x80
5364 #define PCICFG_DEVICE_CONTROL 0xb4
5365 #define PCICFG_LINK_CONTROL 0xbc
5368 #define BAR_USTRORM_INTMEM 0x400000
5369 #define BAR_CSTRORM_INTMEM 0x410000
5370 #define BAR_XSTRORM_INTMEM 0x420000
5371 #define BAR_TSTRORM_INTMEM 0x430000
5373 /* for accessing the IGU in case of status block ACK */
5374 #define BAR_IGU_INTMEM 0x440000
5376 #define BAR_DOORBELL_OFFSET 0x800000
5378 #define BAR_ME_REGISTER 0x450000
5380 /* config_2 offset */
5381 #define GRC_CONFIG_2_SIZE_REG 0x408
5382 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5383 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5384 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5385 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5386 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5387 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5388 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5389 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5390 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5391 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5392 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5393 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5394 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5395 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5396 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5397 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5398 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5399 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5400 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5401 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5402 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5403 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5404 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5405 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5406 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5407 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5408 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5409 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5410 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5411 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5412 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5413 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5414 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5415 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5416 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5417 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5418 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5419 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5420 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5421 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5423 /* config_3 offset */
5424 #define GRC_CONFIG_3_SIZE_REG 0x40c
5425 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5426 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
5427 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
5428 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5429 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5430 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5431 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
5433 #define GRC_BAR2_CONFIG 0x4e0
5434 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5435 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5436 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5437 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5438 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5439 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5440 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5441 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5442 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5443 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5444 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5445 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5446 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5447 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5448 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5449 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5450 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5451 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5453 #define PCI_PM_DATA_A 0x410
5454 #define PCI_PM_DATA_B 0x414
5455 #define PCI_ID_VAL1 0x434
5456 #define PCI_ID_VAL2 0x438
5459 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
5460 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5461 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5462 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5463 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5465 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
5466 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
5467 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5468 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5469 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5470 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5472 #define MDIO_REG_BANK_RX0 0x80b0
5473 #define MDIO_RX0_RX_EQ_BOOST 0x1c
5474 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5475 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5477 #define MDIO_REG_BANK_RX1 0x80c0
5478 #define MDIO_RX1_RX_EQ_BOOST 0x1c
5479 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5480 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5482 #define MDIO_REG_BANK_RX2 0x80d0
5483 #define MDIO_RX2_RX_EQ_BOOST 0x1c
5484 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5485 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5487 #define MDIO_REG_BANK_RX3 0x80e0
5488 #define MDIO_RX3_RX_EQ_BOOST 0x1c
5489 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5490 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5492 #define MDIO_REG_BANK_RX_ALL 0x80f0
5493 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5494 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5495 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
5497 #define MDIO_REG_BANK_TX0 0x8060
5498 #define MDIO_TX0_TX_DRIVER 0x17
5499 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5500 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5501 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5502 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5503 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5504 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5505 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5506 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5507 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5509 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5510 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
5512 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5513 #define MDIO_BLOCK1_LANE_CTRL0 0x15
5514 #define MDIO_BLOCK1_LANE_CTRL1 0x16
5515 #define MDIO_BLOCK1_LANE_CTRL2 0x17
5516 #define MDIO_BLOCK1_LANE_PRBS 0x19
5518 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
5519 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
5520 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
5521 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
5522 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
5523 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
5524 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
5525 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
5526 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
5527 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
5529 #define MDIO_REG_BANK_GP_STATUS 0x8120
5530 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
5531 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
5532 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
5533 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
5534 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
5535 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
5536 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
5537 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
5538 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
5539 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
5540 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
5541 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
5542 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
5543 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
5544 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
5545 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
5546 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
5547 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
5548 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
5549 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
5550 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
5551 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
5552 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5553 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5554 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
5557 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
5558 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
5559 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
5560 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
5561 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
5563 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
5564 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
5565 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
5566 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
5567 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
5568 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
5569 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
5570 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
5571 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
5572 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
5573 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
5574 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
5575 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
5576 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
5577 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
5578 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
5579 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
5580 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
5581 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
5582 #define MDIO_SERDES_DIGITAL_MISC1 0x18
5583 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
5584 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
5585 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
5586 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
5587 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
5588 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
5589 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
5590 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
5591 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
5592 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
5593 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
5594 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
5595 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
5596 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
5597 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
5598 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
5599 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
5600 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
5602 #define MDIO_REG_BANK_OVER_1G 0x8320
5603 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
5604 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
5605 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5606 #define MDIO_OVER_1G_UP1 0x19
5607 #define MDIO_OVER_1G_UP1_2_5G 0x0001
5608 #define MDIO_OVER_1G_UP1_5G 0x0002
5609 #define MDIO_OVER_1G_UP1_6G 0x0004
5610 #define MDIO_OVER_1G_UP1_10G 0x0010
5611 #define MDIO_OVER_1G_UP1_10GH 0x0008
5612 #define MDIO_OVER_1G_UP1_12G 0x0020
5613 #define MDIO_OVER_1G_UP1_12_5G 0x0040
5614 #define MDIO_OVER_1G_UP1_13G 0x0080
5615 #define MDIO_OVER_1G_UP1_15G 0x0100
5616 #define MDIO_OVER_1G_UP1_16G 0x0200
5617 #define MDIO_OVER_1G_UP2 0x1A
5618 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5619 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5620 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5621 #define MDIO_OVER_1G_UP3 0x1B
5622 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5623 #define MDIO_OVER_1G_LP_UP1 0x1C
5624 #define MDIO_OVER_1G_LP_UP2 0x1D
5625 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5626 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5627 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5628 #define MDIO_OVER_1G_LP_UP3 0x1E
5630 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
5631 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5632 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5633 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5635 #define MDIO_REG_BANK_CL73_USERB0 0x8370
5636 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5637 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5638 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5639 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5640 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5641 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5643 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5644 #define MDIO_AER_BLOCK_AER_REG 0x1E
5646 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5647 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5648 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5649 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5650 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5651 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5652 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5653 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5654 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5655 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5656 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5657 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5658 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5659 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5660 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5661 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5662 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5663 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5664 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5665 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5666 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5667 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5668 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5669 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5670 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5671 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5672 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5673 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5674 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5675 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5676 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5677 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5678 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5679 Theotherbitsarereservedandshouldbezero*/
5680 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5683 #define MDIO_PMA_DEVAD 0x1
5685 #define MDIO_PMA_REG_CTRL 0x0
5686 #define MDIO_PMA_REG_STATUS 0x1
5687 #define MDIO_PMA_REG_10G_CTRL2 0x7
5688 #define MDIO_PMA_REG_RX_SD 0xa
5690 #define MDIO_PMA_REG_BCM_CTRL 0x0096
5691 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
5692 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5693 #define MDIO_PMA_REG_LASI_CTRL 0x9002
5694 #define MDIO_PMA_REG_RX_ALARM 0x9003
5695 #define MDIO_PMA_REG_TX_ALARM 0x9004
5696 #define MDIO_PMA_REG_LASI_STATUS 0x9005
5697 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5698 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5699 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5700 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5701 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5702 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
5703 #define MDIO_PMA_REG_GEN_CTRL 0xca10
5704 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5705 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5706 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5707 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
5708 #define MDIO_PMA_REG_ROM_VER1 0xca19
5709 #define MDIO_PMA_REG_ROM_VER2 0xca1a
5710 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5711 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5712 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5713 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
5715 #define MDIO_PMA_REG_7101_RESET 0xc000
5716 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5717 #define MDIO_PMA_REG_7101_VER1 0xc026
5718 #define MDIO_PMA_REG_7101_VER2 0xc027
5721 #define MDIO_WIS_DEVAD 0x2
5723 #define MDIO_WIS_REG_LASI_CNTL 0x9002
5724 #define MDIO_WIS_REG_LASI_STATUS 0x9005
5726 #define MDIO_PCS_DEVAD 0x3
5727 #define MDIO_PCS_REG_STATUS 0x0020
5728 #define MDIO_PCS_REG_LASI_STATUS 0x9005
5729 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5730 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5731 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5732 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5733 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5734 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5735 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5736 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5737 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5740 #define MDIO_XS_DEVAD 0x4
5741 #define MDIO_XS_PLL_SEQUENCER 0x8000
5742 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
5744 #define MDIO_AN_DEVAD 0x7
5746 #define MDIO_AN_REG_CTRL 0x0000
5747 #define MDIO_AN_REG_STATUS 0x0001
5748 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5749 #define MDIO_AN_REG_ADV_PAUSE 0x0010
5750 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5751 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5752 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5753 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5754 #define MDIO_AN_REG_ADV 0x0011
5755 #define MDIO_AN_REG_ADV2 0x0012
5756 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5757 #define MDIO_AN_REG_MASTER_STATUS 0x0021
5759 #define MDIO_AN_REG_LINK_STATUS 0x8304
5760 #define MDIO_AN_REG_CL37_CL73 0x8370
5761 #define MDIO_AN_REG_CL37_AN 0xffe0
5762 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
5763 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
5766 #define IGU_FUNC_BASE 0x0400
5768 #define IGU_ADDR_MSIX 0x0000
5769 #define IGU_ADDR_INT_ACK 0x0200
5770 #define IGU_ADDR_PROD_UPD 0x0201
5771 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
5772 #define IGU_ADDR_ATTN_BITS_SET 0x0203
5773 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
5774 #define IGU_ADDR_COALESCE_NOW 0x0205
5775 #define IGU_ADDR_SIMD_MASK 0x0206
5776 #define IGU_ADDR_SIMD_NOMASK 0x0207
5777 #define IGU_ADDR_MSI_CTL 0x0210
5778 #define IGU_ADDR_MSI_ADDR_LO 0x0211
5779 #define IGU_ADDR_MSI_ADDR_HI 0x0212
5780 #define IGU_ADDR_MSI_DATA 0x0213
5782 #define IGU_INT_ENABLE 0
5783 #define IGU_INT_DISABLE 1
5784 #define IGU_INT_NOP 2
5785 #define IGU_INT_NOP2 3
5787 #define COMMAND_REG_INT_ACK 0x0
5788 #define COMMAND_REG_PROD_UPD 0x4
5789 #define COMMAND_REG_ATTN_BITS_UPD 0x8
5790 #define COMMAND_REG_ATTN_BITS_SET 0xc
5791 #define COMMAND_REG_ATTN_BITS_CLR 0x10
5792 #define COMMAND_REG_COALESCE_NOW 0x14
5793 #define COMMAND_REG_SIMD_MASK 0x18
5794 #define COMMAND_REG_SIMD_NOMASK 0x1c
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