2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/can.h>
40 #include <linux/can/dev.h>
41 #include <linux/can/error.h>
42 #include <linux/can/led.h>
46 /* Number of interface registers */
47 #define IF_ENUM_REG_LEN 11
48 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
50 /* control extension register D_CAN specific */
51 #define CONTROL_EX_PDR BIT(8)
53 /* control register */
54 #define CONTROL_TEST BIT(7)
55 #define CONTROL_CCE BIT(6)
56 #define CONTROL_DISABLE_AR BIT(5)
57 #define CONTROL_ENABLE_AR (0 << 5)
58 #define CONTROL_EIE BIT(3)
59 #define CONTROL_SIE BIT(2)
60 #define CONTROL_IE BIT(1)
61 #define CONTROL_INIT BIT(0)
63 #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
66 #define TEST_RX BIT(7)
67 #define TEST_TX1 BIT(6)
68 #define TEST_TX2 BIT(5)
69 #define TEST_LBACK BIT(4)
70 #define TEST_SILENT BIT(3)
71 #define TEST_BASIC BIT(2)
74 #define STATUS_PDA BIT(10)
75 #define STATUS_BOFF BIT(7)
76 #define STATUS_EWARN BIT(6)
77 #define STATUS_EPASS BIT(5)
78 #define STATUS_RXOK BIT(4)
79 #define STATUS_TXOK BIT(3)
81 /* error counter register */
82 #define ERR_CNT_TEC_MASK 0xff
83 #define ERR_CNT_TEC_SHIFT 0
84 #define ERR_CNT_REC_SHIFT 8
85 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
86 #define ERR_CNT_RP_SHIFT 15
87 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
89 /* bit-timing register */
90 #define BTR_BRP_MASK 0x3f
91 #define BTR_BRP_SHIFT 0
92 #define BTR_SJW_SHIFT 6
93 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
94 #define BTR_TSEG1_SHIFT 8
95 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
96 #define BTR_TSEG2_SHIFT 12
97 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
99 /* brp extension register */
100 #define BRP_EXT_BRPE_MASK 0x0f
101 #define BRP_EXT_BRPE_SHIFT 0
103 /* IFx command request */
104 #define IF_COMR_BUSY BIT(15)
106 /* IFx command mask */
107 #define IF_COMM_WR BIT(7)
108 #define IF_COMM_MASK BIT(6)
109 #define IF_COMM_ARB BIT(5)
110 #define IF_COMM_CONTROL BIT(4)
111 #define IF_COMM_CLR_INT_PND BIT(3)
112 #define IF_COMM_TXRQST BIT(2)
113 #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
114 #define IF_COMM_DATAA BIT(1)
115 #define IF_COMM_DATAB BIT(0)
117 /* TX buffer setup */
118 #define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \
120 IF_COMM_DATAA | IF_COMM_DATAB)
122 /* For the low buffers we clear the interrupt bit, but keep newdat */
123 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
124 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
125 IF_COMM_DATAA | IF_COMM_DATAB)
127 /* For the high buffers we clear the interrupt bit and newdat */
128 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
131 /* Receive setup of message objects */
132 #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
134 /* Invalidation of message objects */
135 #define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL)
137 /* IFx arbitration */
138 #define IF_ARB_MSGVAL BIT(31)
139 #define IF_ARB_MSGXTD BIT(30)
140 #define IF_ARB_TRANSMIT BIT(29)
142 /* IFx message control */
143 #define IF_MCONT_NEWDAT BIT(15)
144 #define IF_MCONT_MSGLST BIT(14)
145 #define IF_MCONT_INTPND BIT(13)
146 #define IF_MCONT_UMASK BIT(12)
147 #define IF_MCONT_TXIE BIT(11)
148 #define IF_MCONT_RXIE BIT(10)
149 #define IF_MCONT_RMTEN BIT(9)
150 #define IF_MCONT_TXRQST BIT(8)
151 #define IF_MCONT_EOB BIT(7)
152 #define IF_MCONT_DLC_MASK 0xf
154 #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
155 #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
157 #define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB)
160 * Use IF1 for RX and IF2 for TX
165 /* minimum timeout for checking BUSY status */
166 #define MIN_TIMEOUT_VALUE 6
168 /* Wait for ~1 sec for INIT bit */
169 #define INIT_WAIT_MS 1000
172 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
174 /* c_can lec values */
175 enum c_can_lec_type {
184 LEC_MASK = LEC_UNUSED,
189 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
191 enum c_can_bus_error_types {
198 static const struct can_bittiming_const c_can_bittiming_const = {
199 .name = KBUILD_MODNAME,
200 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
202 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
206 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
210 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
213 pm_runtime_enable(priv->device);
216 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
219 pm_runtime_disable(priv->device);
222 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
225 pm_runtime_get_sync(priv->device);
228 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
231 pm_runtime_put_sync(priv->device);
234 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
237 priv->raminit(priv, enable);
240 static void c_can_irq_control(struct c_can_priv *priv, bool enable)
242 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
245 ctrl |= CONTROL_IRQMSK;
247 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
250 static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
252 struct c_can_priv *priv = netdev_priv(dev);
253 int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
255 priv->write_reg32(priv, reg, (cmd << 16) | obj);
257 for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
258 if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
262 netdev_err(dev, "Updating object timed out\n");
266 static inline void c_can_object_get(struct net_device *dev, int iface,
269 c_can_obj_update(dev, iface, cmd, obj);
272 static inline void c_can_object_put(struct net_device *dev, int iface,
275 c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
279 * Note: According to documentation clearing TXIE while MSGVAL is set
280 * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
281 * load significantly.
283 static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
285 struct c_can_priv *priv = netdev_priv(dev);
287 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
288 c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
291 static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
293 struct c_can_priv *priv = netdev_priv(dev);
295 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
296 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
297 c_can_inval_tx_object(dev, iface, obj);
300 static void c_can_setup_tx_object(struct net_device *dev, int iface,
301 struct can_frame *frame, int idx)
303 struct c_can_priv *priv = netdev_priv(dev);
304 u16 ctrl = IF_MCONT_TX | frame->can_dlc;
305 bool rtr = frame->can_id & CAN_RTR_FLAG;
306 u32 arb = IF_ARB_MSGVAL;
309 if (frame->can_id & CAN_EFF_FLAG) {
310 arb |= frame->can_id & CAN_EFF_MASK;
311 arb |= IF_ARB_MSGXTD;
313 arb |= (frame->can_id & CAN_SFF_MASK) << 18;
317 arb |= IF_ARB_TRANSMIT;
320 * If we change the DIR bit, we need to invalidate the buffer
321 * first, i.e. clear the MSGVAL flag in the arbiter.
323 if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
324 u32 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
326 c_can_inval_msg_object(dev, iface, obj);
327 change_bit(idx, &priv->tx_dir);
330 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
332 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
334 for (i = 0; i < frame->can_dlc; i += 2) {
335 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
336 frame->data[i] | (frame->data[i + 1] << 8));
340 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
345 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++)
346 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT);
349 static int c_can_handle_lost_msg_obj(struct net_device *dev,
350 int iface, int objno, u32 ctrl)
352 struct net_device_stats *stats = &dev->stats;
353 struct c_can_priv *priv = netdev_priv(dev);
354 struct can_frame *frame;
357 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
358 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
359 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
362 stats->rx_over_errors++;
364 /* create an error msg */
365 skb = alloc_can_err_skb(dev, &frame);
369 frame->can_id |= CAN_ERR_CRTL;
370 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
372 netif_receive_skb(skb);
376 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
378 struct net_device_stats *stats = &dev->stats;
379 struct c_can_priv *priv = netdev_priv(dev);
380 struct can_frame *frame;
384 skb = alloc_can_skb(dev, &frame);
390 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
392 arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
394 if (arb & IF_ARB_MSGXTD)
395 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
397 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
399 if (arb & IF_ARB_TRANSMIT) {
400 frame->can_id |= CAN_RTR_FLAG;
402 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
404 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) {
405 data = priv->read_reg(priv, dreg);
406 frame->data[i] = data;
407 frame->data[i + 1] = data >> 8;
412 stats->rx_bytes += frame->can_dlc;
414 netif_receive_skb(skb);
418 static void c_can_setup_receive_object(struct net_device *dev, int iface,
419 u32 obj, u32 mask, u32 id, u32 mcont)
421 struct c_can_priv *priv = netdev_priv(dev);
424 priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
427 priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
429 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
430 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
433 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
434 struct net_device *dev)
436 struct can_frame *frame = (struct can_frame *)skb->data;
437 struct c_can_priv *priv = netdev_priv(dev);
440 if (can_dropped_invalid_skb(dev, skb))
443 * This is not a FIFO. C/D_CAN sends out the buffers
444 * prioritized. The lowest buffer number wins.
446 idx = fls(atomic_read(&priv->tx_active));
447 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
449 /* If this is the last buffer, stop the xmit queue */
450 if (idx == C_CAN_MSG_OBJ_TX_NUM - 1)
451 netif_stop_queue(dev);
453 * Store the message in the interface so we can call
454 * can_put_echo_skb(). We must do this before we enable
455 * transmit as we might race against do_tx().
457 c_can_setup_tx_object(dev, IF_TX, frame, idx);
458 priv->dlc[idx] = frame->can_dlc;
459 can_put_echo_skb(skb, dev, idx);
461 /* Update the active bits */
462 atomic_add((1 << idx), &priv->tx_active);
463 /* Start transmission */
464 c_can_object_put(dev, IF_TX, obj, IF_COMM_TX);
469 static int c_can_wait_for_ctrl_init(struct net_device *dev,
470 struct c_can_priv *priv, u32 init)
474 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
476 if (retry++ > 1000) {
477 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
484 static int c_can_set_bittiming(struct net_device *dev)
486 unsigned int reg_btr, reg_brpe, ctrl_save;
487 u8 brp, brpe, sjw, tseg1, tseg2;
489 struct c_can_priv *priv = netdev_priv(dev);
490 const struct can_bittiming *bt = &priv->can.bittiming;
493 /* c_can provides a 6-bit brp and 4-bit brpe fields */
494 ten_bit_brp = bt->brp - 1;
495 brp = ten_bit_brp & BTR_BRP_MASK;
496 brpe = ten_bit_brp >> 6;
499 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
500 tseg2 = bt->phase_seg2 - 1;
501 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
502 (tseg2 << BTR_TSEG2_SHIFT);
503 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
506 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
508 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
509 ctrl_save &= ~CONTROL_INIT;
510 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
511 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
515 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
516 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
517 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
519 return c_can_wait_for_ctrl_init(dev, priv, 0);
523 * Configure C_CAN message objects for Tx and Rx purposes:
524 * C_CAN provides a total of 32 message objects that can be configured
525 * either for Tx or Rx purposes. Here the first 16 message objects are used as
526 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
527 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
528 * See user guide document for further details on configuring message
531 static void c_can_configure_msg_objects(struct net_device *dev)
535 /* first invalidate all message objects */
536 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
537 c_can_inval_msg_object(dev, IF_RX, i);
539 /* setup receive message objects */
540 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
541 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV);
543 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
548 * Configure C_CAN chip:
549 * - enable/disable auto-retransmission
550 * - set operating mode
551 * - configure message objects
553 static int c_can_chip_config(struct net_device *dev)
555 struct c_can_priv *priv = netdev_priv(dev);
557 /* enable automatic retransmission */
558 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
560 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
561 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
562 /* loopback + silent mode : useful for hot self-test */
563 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
564 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
565 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
566 /* loopback mode : useful for self-test function */
567 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
568 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
569 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
570 /* silent mode : bus-monitoring mode */
571 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
572 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
575 /* configure message objects */
576 c_can_configure_msg_objects(dev);
578 /* set a `lec` value so that we can check for updates later */
579 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
581 /* Clear all internal status */
582 atomic_set(&priv->tx_active, 0);
586 /* set bittiming params */
587 return c_can_set_bittiming(dev);
590 static int c_can_start(struct net_device *dev)
592 struct c_can_priv *priv = netdev_priv(dev);
595 /* basic c_can configuration */
596 err = c_can_chip_config(dev);
600 /* Setup the command for new messages */
601 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
602 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
604 priv->can.state = CAN_STATE_ERROR_ACTIVE;
609 static void c_can_stop(struct net_device *dev)
611 struct c_can_priv *priv = netdev_priv(dev);
613 c_can_irq_control(priv, false);
614 priv->can.state = CAN_STATE_STOPPED;
617 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
619 struct c_can_priv *priv = netdev_priv(dev);
624 err = c_can_start(dev);
627 netif_wake_queue(dev);
628 c_can_irq_control(priv, true);
637 static int __c_can_get_berr_counter(const struct net_device *dev,
638 struct can_berr_counter *bec)
640 unsigned int reg_err_counter;
641 struct c_can_priv *priv = netdev_priv(dev);
643 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
644 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
646 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
651 static int c_can_get_berr_counter(const struct net_device *dev,
652 struct can_berr_counter *bec)
654 struct c_can_priv *priv = netdev_priv(dev);
657 c_can_pm_runtime_get_sync(priv);
658 err = __c_can_get_berr_counter(dev, bec);
659 c_can_pm_runtime_put_sync(priv);
664 static void c_can_do_tx(struct net_device *dev)
666 struct c_can_priv *priv = netdev_priv(dev);
667 struct net_device_stats *stats = &dev->stats;
668 u32 idx, obj, pkts = 0, bytes = 0, pend, clr;
670 clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
672 while ((idx = ffs(pend))) {
675 obj = idx + C_CAN_MSG_OBJ_TX_FIRST;
676 c_can_inval_tx_object(dev, IF_RX, obj);
677 can_get_echo_skb(dev, idx);
678 bytes += priv->dlc[idx];
682 /* Clear the bits in the tx_active mask */
683 atomic_sub(clr, &priv->tx_active);
685 if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1)))
686 netif_wake_queue(dev);
689 stats->tx_bytes += bytes;
690 stats->tx_packets += pkts;
691 can_led_event(dev, CAN_LED_EVENT_TX);
696 * If we have a gap in the pending bits, that means we either
697 * raced with the hardware or failed to readout all upper
698 * objects in the last run due to quota limit.
700 static u32 c_can_adjust_pending(u32 pend)
704 if (pend == RECEIVE_OBJECT_BITS)
708 * If the last set bit is larger than the number of pending
709 * bits we have a gap.
711 weight = hweight32(pend);
714 /* If the bits are linear, nothing to do */
719 * Find the first set bit after the gap. We walk backwards
720 * from the last set bit.
722 for (lasts--; pend & (1 << (lasts - 1)); lasts--);
724 return pend & ~((1 << lasts) - 1);
727 static inline void c_can_rx_object_get(struct net_device *dev,
728 struct c_can_priv *priv, u32 obj)
730 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high);
733 static inline void c_can_rx_finalize(struct net_device *dev,
734 struct c_can_priv *priv, u32 obj)
736 if (priv->type != BOSCH_D_CAN)
737 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT);
740 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
743 u32 pkts = 0, ctrl, obj;
745 while ((obj = ffs(pend)) && quota > 0) {
746 pend &= ~BIT(obj - 1);
748 c_can_rx_object_get(dev, priv, obj);
749 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
751 if (ctrl & IF_MCONT_MSGLST) {
752 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
760 * This really should not happen, but this covers some
761 * odd HW behaviour. Do not remove that unless you
762 * want to brick your machine.
764 if (!(ctrl & IF_MCONT_NEWDAT))
767 /* read the data from the message object */
768 c_can_read_msg_object(dev, IF_RX, ctrl);
770 c_can_rx_finalize(dev, priv, obj);
779 static inline u32 c_can_get_pending(struct c_can_priv *priv)
781 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
787 * theory of operation:
789 * c_can core saves a received CAN message into the first free message
790 * object it finds free (starting with the lowest). Bits NEWDAT and
791 * INTPND are set for this message object indicating that a new message
792 * has arrived. To work-around this issue, we keep two groups of message
793 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
795 * We clear the newdat bit right away.
797 * This can result in packet reordering when the readout is slow.
799 static int c_can_do_rx_poll(struct net_device *dev, int quota)
801 struct c_can_priv *priv = netdev_priv(dev);
802 u32 pkts = 0, pend = 0, toread, n;
805 * It is faster to read only one 16bit register. This is only possible
806 * for a maximum number of 16 objects.
808 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
809 "Implementation does not support more message objects than 16");
813 pend = c_can_get_pending(priv);
817 * If the pending field has a gap, handle the
818 * bits above the gap first.
820 toread = c_can_adjust_pending(pend);
824 /* Remove the bits from pend */
826 /* Read the objects */
827 n = c_can_read_objects(dev, priv, toread, quota);
833 can_led_event(dev, CAN_LED_EVENT_RX);
838 static int c_can_handle_state_change(struct net_device *dev,
839 enum c_can_bus_error_types error_type)
841 unsigned int reg_err_counter;
842 unsigned int rx_err_passive;
843 struct c_can_priv *priv = netdev_priv(dev);
844 struct net_device_stats *stats = &dev->stats;
845 struct can_frame *cf;
847 struct can_berr_counter bec;
849 switch (error_type) {
850 case C_CAN_ERROR_WARNING:
851 /* error warning state */
852 priv->can.can_stats.error_warning++;
853 priv->can.state = CAN_STATE_ERROR_WARNING;
855 case C_CAN_ERROR_PASSIVE:
856 /* error passive state */
857 priv->can.can_stats.error_passive++;
858 priv->can.state = CAN_STATE_ERROR_PASSIVE;
862 priv->can.state = CAN_STATE_BUS_OFF;
869 /* propagate the error condition to the CAN stack */
870 skb = alloc_can_err_skb(dev, &cf);
874 __c_can_get_berr_counter(dev, &bec);
875 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
876 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
879 switch (error_type) {
880 case C_CAN_ERROR_WARNING:
881 /* error warning state */
882 cf->can_id |= CAN_ERR_CRTL;
883 cf->data[1] = (bec.txerr > bec.rxerr) ?
884 CAN_ERR_CRTL_TX_WARNING :
885 CAN_ERR_CRTL_RX_WARNING;
886 cf->data[6] = bec.txerr;
887 cf->data[7] = bec.rxerr;
890 case C_CAN_ERROR_PASSIVE:
891 /* error passive state */
892 cf->can_id |= CAN_ERR_CRTL;
894 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
896 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
898 cf->data[6] = bec.txerr;
899 cf->data[7] = bec.rxerr;
903 cf->can_id |= CAN_ERR_BUSOFF;
911 stats->rx_bytes += cf->can_dlc;
912 netif_receive_skb(skb);
917 static int c_can_handle_bus_err(struct net_device *dev,
918 enum c_can_lec_type lec_type)
920 struct c_can_priv *priv = netdev_priv(dev);
921 struct net_device_stats *stats = &dev->stats;
922 struct can_frame *cf;
926 * early exit if no lec update or no error.
927 * no lec update means that no CAN bus event has been detected
928 * since CPU wrote 0x7 value to status reg.
930 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
933 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
936 /* common for all type of bus errors */
937 priv->can.can_stats.bus_error++;
940 /* propagate the error condition to the CAN stack */
941 skb = alloc_can_err_skb(dev, &cf);
946 * check for 'last error code' which tells us the
947 * type of the last error to occur on the CAN bus
949 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
950 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
953 case LEC_STUFF_ERROR:
954 netdev_dbg(dev, "stuff error\n");
955 cf->data[2] |= CAN_ERR_PROT_STUFF;
958 netdev_dbg(dev, "form error\n");
959 cf->data[2] |= CAN_ERR_PROT_FORM;
962 netdev_dbg(dev, "ack error\n");
963 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
964 CAN_ERR_PROT_LOC_ACK_DEL);
967 netdev_dbg(dev, "bit1 error\n");
968 cf->data[2] |= CAN_ERR_PROT_BIT1;
971 netdev_dbg(dev, "bit0 error\n");
972 cf->data[2] |= CAN_ERR_PROT_BIT0;
975 netdev_dbg(dev, "CRC error\n");
976 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
977 CAN_ERR_PROT_LOC_CRC_DEL);
984 stats->rx_bytes += cf->can_dlc;
985 netif_receive_skb(skb);
989 static int c_can_poll(struct napi_struct *napi, int quota)
991 struct net_device *dev = napi->dev;
992 struct c_can_priv *priv = netdev_priv(dev);
993 u16 curr, last = priv->last_status;
996 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG);
997 /* Ack status on C_CAN. D_CAN is self clearing */
998 if (priv->type != BOSCH_D_CAN)
999 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1001 /* handle state changes */
1002 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1003 netdev_dbg(dev, "entered error warning state\n");
1004 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1007 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1008 netdev_dbg(dev, "entered error passive state\n");
1009 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1012 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1013 netdev_dbg(dev, "entered bus off state\n");
1014 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1018 /* handle bus recovery events */
1019 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1020 netdev_dbg(dev, "left bus off state\n");
1021 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1023 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1024 netdev_dbg(dev, "left error passive state\n");
1025 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1028 /* handle lec errors on the bus */
1029 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1031 /* Handle Tx/Rx events. We do this unconditionally */
1032 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1036 if (work_done < quota) {
1037 napi_complete(napi);
1038 /* enable all IRQs if we are not in bus off state */
1039 if (priv->can.state != CAN_STATE_BUS_OFF)
1040 c_can_irq_control(priv, true);
1046 static irqreturn_t c_can_isr(int irq, void *dev_id)
1048 struct net_device *dev = (struct net_device *)dev_id;
1049 struct c_can_priv *priv = netdev_priv(dev);
1051 if (!priv->read_reg(priv, C_CAN_INT_REG))
1054 /* disable all interrupts and schedule the NAPI */
1055 c_can_irq_control(priv, false);
1056 napi_schedule(&priv->napi);
1061 static int c_can_open(struct net_device *dev)
1064 struct c_can_priv *priv = netdev_priv(dev);
1066 c_can_pm_runtime_get_sync(priv);
1067 c_can_reset_ram(priv, true);
1069 /* open the can device */
1070 err = open_candev(dev);
1072 netdev_err(dev, "failed to open can device\n");
1073 goto exit_open_fail;
1076 /* register interrupt handler */
1077 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1080 netdev_err(dev, "failed to request interrupt\n");
1084 /* start the c_can controller */
1085 err = c_can_start(dev);
1087 goto exit_start_fail;
1089 can_led_event(dev, CAN_LED_EVENT_OPEN);
1091 napi_enable(&priv->napi);
1092 /* enable status change, error and module interrupts */
1093 c_can_irq_control(priv, true);
1094 netif_start_queue(dev);
1099 free_irq(dev->irq, dev);
1103 c_can_reset_ram(priv, false);
1104 c_can_pm_runtime_put_sync(priv);
1108 static int c_can_close(struct net_device *dev)
1110 struct c_can_priv *priv = netdev_priv(dev);
1112 netif_stop_queue(dev);
1113 napi_disable(&priv->napi);
1115 free_irq(dev->irq, dev);
1118 c_can_reset_ram(priv, false);
1119 c_can_pm_runtime_put_sync(priv);
1121 can_led_event(dev, CAN_LED_EVENT_STOP);
1126 struct net_device *alloc_c_can_dev(void)
1128 struct net_device *dev;
1129 struct c_can_priv *priv;
1131 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1135 priv = netdev_priv(dev);
1136 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1139 priv->can.bittiming_const = &c_can_bittiming_const;
1140 priv->can.do_set_mode = c_can_set_mode;
1141 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1142 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1143 CAN_CTRLMODE_LISTENONLY |
1144 CAN_CTRLMODE_BERR_REPORTING;
1148 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1151 int c_can_power_down(struct net_device *dev)
1154 unsigned long time_out;
1155 struct c_can_priv *priv = netdev_priv(dev);
1157 if (!(dev->flags & IFF_UP))
1160 WARN_ON(priv->type != BOSCH_D_CAN);
1162 /* set PDR value so the device goes to power down mode */
1163 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1164 val |= CONTROL_EX_PDR;
1165 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1167 /* Wait for the PDA bit to get set */
1168 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1169 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1170 time_after(time_out, jiffies))
1173 if (time_after(jiffies, time_out))
1178 c_can_reset_ram(priv, false);
1179 c_can_pm_runtime_put_sync(priv);
1183 EXPORT_SYMBOL_GPL(c_can_power_down);
1185 int c_can_power_up(struct net_device *dev)
1188 unsigned long time_out;
1189 struct c_can_priv *priv = netdev_priv(dev);
1192 if (!(dev->flags & IFF_UP))
1195 WARN_ON(priv->type != BOSCH_D_CAN);
1197 c_can_pm_runtime_get_sync(priv);
1198 c_can_reset_ram(priv, true);
1200 /* Clear PDR and INIT bits */
1201 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1202 val &= ~CONTROL_EX_PDR;
1203 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1204 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1205 val &= ~CONTROL_INIT;
1206 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1208 /* Wait for the PDA bit to get clear */
1209 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1210 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1211 time_after(time_out, jiffies))
1214 if (time_after(jiffies, time_out))
1217 ret = c_can_start(dev);
1219 c_can_irq_control(priv, true);
1223 EXPORT_SYMBOL_GPL(c_can_power_up);
1226 void free_c_can_dev(struct net_device *dev)
1228 struct c_can_priv *priv = netdev_priv(dev);
1230 netif_napi_del(&priv->napi);
1233 EXPORT_SYMBOL_GPL(free_c_can_dev);
1235 static const struct net_device_ops c_can_netdev_ops = {
1236 .ndo_open = c_can_open,
1237 .ndo_stop = c_can_close,
1238 .ndo_start_xmit = c_can_start_xmit,
1239 .ndo_change_mtu = can_change_mtu,
1242 int register_c_can_dev(struct net_device *dev)
1244 struct c_can_priv *priv = netdev_priv(dev);
1247 c_can_pm_runtime_enable(priv);
1249 dev->flags |= IFF_ECHO; /* we support local echo */
1250 dev->netdev_ops = &c_can_netdev_ops;
1252 err = register_candev(dev);
1254 c_can_pm_runtime_disable(priv);
1256 devm_can_led_init(dev);
1260 EXPORT_SYMBOL_GPL(register_c_can_dev);
1262 void unregister_c_can_dev(struct net_device *dev)
1264 struct c_can_priv *priv = netdev_priv(dev);
1266 unregister_candev(dev);
1268 c_can_pm_runtime_disable(priv);
1270 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1272 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1273 MODULE_LICENSE("GPL v2");
1274 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");