2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/can.h>
40 #include <linux/can/dev.h>
41 #include <linux/can/error.h>
42 #include <linux/can/led.h>
46 /* Number of interface registers */
47 #define IF_ENUM_REG_LEN 11
48 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
50 /* control extension register D_CAN specific */
51 #define CONTROL_EX_PDR BIT(8)
53 /* control register */
54 #define CONTROL_TEST BIT(7)
55 #define CONTROL_CCE BIT(6)
56 #define CONTROL_DISABLE_AR BIT(5)
57 #define CONTROL_ENABLE_AR (0 << 5)
58 #define CONTROL_EIE BIT(3)
59 #define CONTROL_SIE BIT(2)
60 #define CONTROL_IE BIT(1)
61 #define CONTROL_INIT BIT(0)
64 #define TEST_RX BIT(7)
65 #define TEST_TX1 BIT(6)
66 #define TEST_TX2 BIT(5)
67 #define TEST_LBACK BIT(4)
68 #define TEST_SILENT BIT(3)
69 #define TEST_BASIC BIT(2)
72 #define STATUS_PDA BIT(10)
73 #define STATUS_BOFF BIT(7)
74 #define STATUS_EWARN BIT(6)
75 #define STATUS_EPASS BIT(5)
76 #define STATUS_RXOK BIT(4)
77 #define STATUS_TXOK BIT(3)
79 /* error counter register */
80 #define ERR_CNT_TEC_MASK 0xff
81 #define ERR_CNT_TEC_SHIFT 0
82 #define ERR_CNT_REC_SHIFT 8
83 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
84 #define ERR_CNT_RP_SHIFT 15
85 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
87 /* bit-timing register */
88 #define BTR_BRP_MASK 0x3f
89 #define BTR_BRP_SHIFT 0
90 #define BTR_SJW_SHIFT 6
91 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
92 #define BTR_TSEG1_SHIFT 8
93 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
94 #define BTR_TSEG2_SHIFT 12
95 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
97 /* brp extension register */
98 #define BRP_EXT_BRPE_MASK 0x0f
99 #define BRP_EXT_BRPE_SHIFT 0
101 /* IFx command request */
102 #define IF_COMR_BUSY BIT(15)
104 /* IFx command mask */
105 #define IF_COMM_WR BIT(7)
106 #define IF_COMM_MASK BIT(6)
107 #define IF_COMM_ARB BIT(5)
108 #define IF_COMM_CONTROL BIT(4)
109 #define IF_COMM_CLR_INT_PND BIT(3)
110 #define IF_COMM_TXRQST BIT(2)
111 #define IF_COMM_DATAA BIT(1)
112 #define IF_COMM_DATAB BIT(0)
113 #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
114 IF_COMM_CONTROL | IF_COMM_TXRQST | \
115 IF_COMM_DATAA | IF_COMM_DATAB)
117 /* IFx arbitration */
118 #define IF_ARB_MSGVAL BIT(15)
119 #define IF_ARB_MSGXTD BIT(14)
120 #define IF_ARB_TRANSMIT BIT(13)
122 /* IFx message control */
123 #define IF_MCONT_NEWDAT BIT(15)
124 #define IF_MCONT_MSGLST BIT(14)
125 #define IF_MCONT_INTPND BIT(13)
126 #define IF_MCONT_UMASK BIT(12)
127 #define IF_MCONT_TXIE BIT(11)
128 #define IF_MCONT_RXIE BIT(10)
129 #define IF_MCONT_RMTEN BIT(9)
130 #define IF_MCONT_TXRQST BIT(8)
131 #define IF_MCONT_EOB BIT(7)
132 #define IF_MCONT_DLC_MASK 0xf
135 * Use IF1 for RX and IF2 for TX
141 * IFx register masks:
142 * allow easy operation on 16-bit registers when the
143 * argument is 32-bit instead
145 #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
146 #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
148 /* message object split */
149 #define C_CAN_NO_OF_OBJECTS 32
150 #define C_CAN_MSG_OBJ_RX_NUM 16
151 #define C_CAN_MSG_OBJ_TX_NUM 16
153 #define C_CAN_MSG_OBJ_RX_FIRST 1
154 #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
155 C_CAN_MSG_OBJ_RX_NUM - 1)
157 #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
158 #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
159 C_CAN_MSG_OBJ_TX_NUM - 1)
161 #define C_CAN_MSG_OBJ_RX_SPLIT 9
162 #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
164 #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
165 #define RECEIVE_OBJECT_BITS 0x0000ffff
167 /* status interrupt */
168 #define STATUS_INTERRUPT 0x8000
170 /* global interrupt masks */
171 #define ENABLE_ALL_INTERRUPTS 1
172 #define DISABLE_ALL_INTERRUPTS 0
174 /* minimum timeout for checking BUSY status */
175 #define MIN_TIMEOUT_VALUE 6
177 /* Wait for ~1 sec for INIT bit */
178 #define INIT_WAIT_MS 1000
181 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
183 /* c_can lec values */
184 enum c_can_lec_type {
197 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
199 enum c_can_bus_error_types {
206 static const struct can_bittiming_const c_can_bittiming_const = {
207 .name = KBUILD_MODNAME,
208 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
210 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
214 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
218 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
221 pm_runtime_enable(priv->device);
224 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
227 pm_runtime_disable(priv->device);
230 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
233 pm_runtime_get_sync(priv->device);
236 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
239 pm_runtime_put_sync(priv->device);
242 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
245 priv->raminit(priv, enable);
248 static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
250 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
251 C_CAN_MSG_OBJ_TX_FIRST;
254 static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
256 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
257 C_CAN_MSG_OBJ_TX_FIRST;
260 static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
262 u32 val = priv->read_reg(priv, index);
263 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
267 static void c_can_enable_all_interrupts(struct c_can_priv *priv,
270 unsigned int cntrl_save = priv->read_reg(priv,
274 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
276 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
278 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save);
281 static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
283 int count = MIN_TIMEOUT_VALUE;
285 while (count && priv->read_reg(priv,
286 C_CAN_IFACE(COMREQ_REG, iface)) &
298 static inline void c_can_object_get(struct net_device *dev,
299 int iface, int objno, int mask)
301 struct c_can_priv *priv = netdev_priv(dev);
304 * As per specs, after writting the message object number in the
305 * IF command request register the transfer b/w interface
306 * register and message RAM must be complete in 6 CAN-CLK
309 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
310 IFX_WRITE_LOW_16BIT(mask));
311 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
312 IFX_WRITE_LOW_16BIT(objno));
314 if (c_can_msg_obj_is_busy(priv, iface))
315 netdev_err(dev, "timed out in object get\n");
318 static inline void c_can_object_put(struct net_device *dev,
319 int iface, int objno, int mask)
321 struct c_can_priv *priv = netdev_priv(dev);
324 * As per specs, after writting the message object number in the
325 * IF command request register the transfer b/w interface
326 * register and message RAM must be complete in 6 CAN-CLK
329 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
330 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
331 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
332 IFX_WRITE_LOW_16BIT(objno));
334 if (c_can_msg_obj_is_busy(priv, iface))
335 netdev_err(dev, "timed out in object put\n");
338 static void c_can_write_msg_object(struct net_device *dev,
339 int iface, struct can_frame *frame, int objno)
344 struct c_can_priv *priv = netdev_priv(dev);
346 if (!(frame->can_id & CAN_RTR_FLAG))
347 flags |= IF_ARB_TRANSMIT;
349 if (frame->can_id & CAN_EFF_FLAG) {
350 id = frame->can_id & CAN_EFF_MASK;
351 flags |= IF_ARB_MSGXTD;
353 id = ((frame->can_id & CAN_SFF_MASK) << 18);
355 flags |= IF_ARB_MSGVAL;
357 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
358 IFX_WRITE_LOW_16BIT(id));
359 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
360 IFX_WRITE_HIGH_16BIT(id));
362 for (i = 0; i < frame->can_dlc; i += 2) {
363 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
364 frame->data[i] | (frame->data[i + 1] << 8));
367 /* enable interrupt for this message object */
368 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
369 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
371 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
374 static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
375 int iface, int ctrl_mask,
378 struct c_can_priv *priv = netdev_priv(dev);
380 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
381 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
382 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
386 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
391 struct c_can_priv *priv = netdev_priv(dev);
393 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
394 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
395 ctrl_mask & ~(IF_MCONT_MSGLST |
396 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
397 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
401 static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
402 int iface, int ctrl_mask,
405 struct c_can_priv *priv = netdev_priv(dev);
407 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
408 ctrl_mask & ~(IF_MCONT_MSGLST |
409 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
410 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
413 static int c_can_handle_lost_msg_obj(struct net_device *dev,
414 int iface, int objno, u32 ctrl)
416 struct net_device_stats *stats = &dev->stats;
417 struct c_can_priv *priv = netdev_priv(dev);
418 struct can_frame *frame;
421 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
422 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
423 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
425 /* create an error msg */
426 skb = alloc_can_err_skb(dev, &frame);
430 frame->can_id |= CAN_ERR_CRTL;
431 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
433 stats->rx_over_errors++;
435 netif_receive_skb(skb);
439 static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
444 struct c_can_priv *priv = netdev_priv(dev);
445 struct net_device_stats *stats = &dev->stats;
447 struct can_frame *frame;
449 skb = alloc_can_skb(dev, &frame);
455 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
457 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface));
458 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) |
461 if (flags & IF_ARB_MSGXTD)
462 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
464 frame->can_id = (val >> 18) & CAN_SFF_MASK;
466 if (flags & IF_ARB_TRANSMIT)
467 frame->can_id |= CAN_RTR_FLAG;
469 for (i = 0; i < frame->can_dlc; i += 2) {
470 data = priv->read_reg(priv,
471 C_CAN_IFACE(DATA1_REG, iface) + i / 2);
472 frame->data[i] = data;
473 frame->data[i + 1] = data >> 8;
477 netif_receive_skb(skb);
480 stats->rx_bytes += frame->can_dlc;
482 can_led_event(dev, CAN_LED_EVENT_RX);
487 static void c_can_setup_receive_object(struct net_device *dev, int iface,
488 int objno, unsigned int mask,
489 unsigned int id, unsigned int mcont)
491 struct c_can_priv *priv = netdev_priv(dev);
493 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface),
494 IFX_WRITE_LOW_16BIT(mask));
496 /* According to C_CAN documentation, the reserved bit
497 * in IFx_MASK2 register is fixed 1
499 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
500 IFX_WRITE_HIGH_16BIT(mask) | BIT(13));
502 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
503 IFX_WRITE_LOW_16BIT(id));
504 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface),
505 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
507 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
508 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
510 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
511 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
514 static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
516 struct c_can_priv *priv = netdev_priv(dev);
518 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
519 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
520 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
522 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
524 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
525 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
528 static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
530 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
533 * as transmission request register's bit n-1 corresponds to
534 * message object n, we need to handle the same properly.
536 if (val & (1 << (objno - 1)))
542 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
543 struct net_device *dev)
546 struct c_can_priv *priv = netdev_priv(dev);
547 struct can_frame *frame = (struct can_frame *)skb->data;
549 if (can_dropped_invalid_skb(dev, skb))
552 spin_lock_bh(&priv->xmit_lock);
553 msg_obj_no = get_tx_next_msg_obj(priv);
555 /* prepare message object for transmission */
556 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no);
557 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
560 * we have to stop the queue in case of a wrap around or
561 * if the next TX message object is still in use
564 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
565 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
566 netif_stop_queue(dev);
567 spin_unlock_bh(&priv->xmit_lock);
572 static int c_can_wait_for_ctrl_init(struct net_device *dev,
573 struct c_can_priv *priv, u32 init)
577 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
579 if (retry++ > 1000) {
580 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
587 static int c_can_set_bittiming(struct net_device *dev)
589 unsigned int reg_btr, reg_brpe, ctrl_save;
590 u8 brp, brpe, sjw, tseg1, tseg2;
592 struct c_can_priv *priv = netdev_priv(dev);
593 const struct can_bittiming *bt = &priv->can.bittiming;
596 /* c_can provides a 6-bit brp and 4-bit brpe fields */
597 ten_bit_brp = bt->brp - 1;
598 brp = ten_bit_brp & BTR_BRP_MASK;
599 brpe = ten_bit_brp >> 6;
602 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
603 tseg2 = bt->phase_seg2 - 1;
604 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
605 (tseg2 << BTR_TSEG2_SHIFT);
606 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
609 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
611 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
612 ctrl_save &= ~CONTROL_INIT;
613 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
614 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
618 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
619 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
620 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
622 return c_can_wait_for_ctrl_init(dev, priv, 0);
626 * Configure C_CAN message objects for Tx and Rx purposes:
627 * C_CAN provides a total of 32 message objects that can be configured
628 * either for Tx or Rx purposes. Here the first 16 message objects are used as
629 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
630 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
631 * See user guide document for further details on configuring message
634 static void c_can_configure_msg_objects(struct net_device *dev)
638 /* first invalidate all message objects */
639 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
640 c_can_inval_msg_object(dev, IF_RX, i);
642 /* setup receive message objects */
643 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
644 c_can_setup_receive_object(dev, IF_RX, i, 0, 0,
645 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
647 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
648 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
652 * Configure C_CAN chip:
653 * - enable/disable auto-retransmission
654 * - set operating mode
655 * - configure message objects
657 static int c_can_chip_config(struct net_device *dev)
659 struct c_can_priv *priv = netdev_priv(dev);
661 /* enable automatic retransmission */
662 priv->write_reg(priv, C_CAN_CTRL_REG,
665 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
666 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
667 /* loopback + silent mode : useful for hot self-test */
668 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
669 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
670 priv->write_reg(priv, C_CAN_TEST_REG,
671 TEST_LBACK | TEST_SILENT);
672 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
673 /* loopback mode : useful for self-test function */
674 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
675 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
676 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
677 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
678 /* silent mode : bus-monitoring mode */
679 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
680 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
681 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
684 priv->write_reg(priv, C_CAN_CTRL_REG,
685 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
687 /* configure message objects */
688 c_can_configure_msg_objects(dev);
690 /* set a `lec` value so that we can check for updates later */
691 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
693 /* set bittiming params */
694 return c_can_set_bittiming(dev);
697 static int c_can_start(struct net_device *dev)
699 struct c_can_priv *priv = netdev_priv(dev);
702 /* basic c_can configuration */
703 err = c_can_chip_config(dev);
707 priv->can.state = CAN_STATE_ERROR_ACTIVE;
709 /* reset tx helper pointers */
710 priv->tx_next = priv->tx_echo = 0;
712 /* enable status change, error and module interrupts */
713 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
718 static void c_can_stop(struct net_device *dev)
720 struct c_can_priv *priv = netdev_priv(dev);
722 /* disable all interrupts */
723 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
725 /* set the state as STOPPED */
726 priv->can.state = CAN_STATE_STOPPED;
729 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
735 err = c_can_start(dev);
738 netif_wake_queue(dev);
747 static int __c_can_get_berr_counter(const struct net_device *dev,
748 struct can_berr_counter *bec)
750 unsigned int reg_err_counter;
751 struct c_can_priv *priv = netdev_priv(dev);
753 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
754 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
756 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
761 static int c_can_get_berr_counter(const struct net_device *dev,
762 struct can_berr_counter *bec)
764 struct c_can_priv *priv = netdev_priv(dev);
767 c_can_pm_runtime_get_sync(priv);
768 err = __c_can_get_berr_counter(dev, bec);
769 c_can_pm_runtime_put_sync(priv);
775 * theory of operation:
777 * priv->tx_echo holds the number of the oldest can_frame put for
778 * transmission into the hardware, but not yet ACKed by the CAN tx
781 * We iterate from priv->tx_echo to priv->tx_next and check if the
782 * packet has been transmitted, echo it back to the CAN framework.
783 * If we discover a not yet transmitted packet, stop looking for more.
785 static void c_can_do_tx(struct net_device *dev)
789 struct c_can_priv *priv = netdev_priv(dev);
790 struct net_device_stats *stats = &dev->stats;
792 spin_lock_bh(&priv->xmit_lock);
794 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
795 msg_obj_no = get_tx_echo_msg_obj(priv);
796 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
797 if (!(val & (1 << (msg_obj_no - 1)))) {
798 can_get_echo_skb(dev,
799 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
800 c_can_object_get(dev, IF_TX, msg_obj_no, IF_COMM_ALL);
801 stats->tx_bytes += priv->read_reg(priv,
802 C_CAN_IFACE(MSGCTRL_REG, IF_TX))
805 can_led_event(dev, CAN_LED_EVENT_TX);
806 c_can_inval_msg_object(dev, IF_TX, msg_obj_no);
812 /* restart queue if wrap-up or if queue stalled on last pkt */
813 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
814 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
815 netif_wake_queue(dev);
817 spin_unlock_bh(&priv->xmit_lock);
821 * If we have a gap in the pending bits, that means we either
822 * raced with the hardware or failed to readout all upper
823 * objects in the last run due to quota limit.
825 static u32 c_can_adjust_pending(u32 pend)
829 if (pend == RECEIVE_OBJECT_BITS)
833 * If the last set bit is larger than the number of pending
834 * bits we have a gap.
836 weight = hweight32(pend);
839 /* If the bits are linear, nothing to do */
844 * Find the first set bit after the gap. We walk backwards
845 * from the last set bit.
847 for (lasts--; pend & (1 << (lasts - 1)); lasts--);
849 return pend & ~((1 << lasts) - 1);
852 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
855 u32 pkts = 0, ctrl, obj;
857 while ((obj = ffs(pend)) && quota > 0) {
858 pend &= ~BIT(obj - 1);
860 c_can_object_get(dev, IF_RX, obj, IF_COMM_ALL & ~IF_COMM_TXRQST);
861 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
863 if (ctrl & IF_MCONT_MSGLST) {
864 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
872 * This really should not happen, but this covers some
873 * odd HW behaviour. Do not remove that unless you
874 * want to brick your machine.
876 if (!(ctrl & IF_MCONT_NEWDAT))
879 /* read the data from the message object */
880 c_can_read_msg_object(dev, IF_RX, ctrl);
882 if (obj < C_CAN_MSG_RX_LOW_LAST)
883 c_can_mark_rx_msg_obj(dev, IF_RX, ctrl, obj);
884 else if (obj > C_CAN_MSG_RX_LOW_LAST)
885 /* activate this msg obj */
886 c_can_activate_rx_msg_obj(dev, IF_RX, ctrl, obj);
887 else if (obj == C_CAN_MSG_RX_LOW_LAST)
888 /* activate all lower message objects */
889 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl);
899 * theory of operation:
901 * c_can core saves a received CAN message into the first free message
902 * object it finds free (starting with the lowest). Bits NEWDAT and
903 * INTPND are set for this message object indicating that a new message
904 * has arrived. To work-around this issue, we keep two groups of message
905 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
907 * To ensure in-order frame reception we use the following
908 * approach while re-activating a message object to receive further
910 * - if the current message object number is lower than
911 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
913 * - if the current message object number is equal to
914 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
915 * receive message objects.
916 * - if the current message object number is greater than
917 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
918 * only this message object.
920 static int c_can_do_rx_poll(struct net_device *dev, int quota)
922 struct c_can_priv *priv = netdev_priv(dev);
923 u32 pkts = 0, pend = 0, toread, n;
926 * It is faster to read only one 16bit register. This is only possible
927 * for a maximum number of 16 objects.
929 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
930 "Implementation does not support more message objects than 16");
934 pend = priv->read_reg(priv, C_CAN_INTPND1_REG);
938 * If the pending field has a gap, handle the
939 * bits above the gap first.
941 toread = c_can_adjust_pending(pend);
945 /* Remove the bits from pend */
947 /* Read the objects */
948 n = c_can_read_objects(dev, priv, toread, quota);
955 static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
957 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
958 (priv->current_status & LEC_UNUSED);
961 static int c_can_handle_state_change(struct net_device *dev,
962 enum c_can_bus_error_types error_type)
964 unsigned int reg_err_counter;
965 unsigned int rx_err_passive;
966 struct c_can_priv *priv = netdev_priv(dev);
967 struct net_device_stats *stats = &dev->stats;
968 struct can_frame *cf;
970 struct can_berr_counter bec;
972 /* propagate the error condition to the CAN stack */
973 skb = alloc_can_err_skb(dev, &cf);
977 __c_can_get_berr_counter(dev, &bec);
978 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
979 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
982 switch (error_type) {
983 case C_CAN_ERROR_WARNING:
984 /* error warning state */
985 priv->can.can_stats.error_warning++;
986 priv->can.state = CAN_STATE_ERROR_WARNING;
987 cf->can_id |= CAN_ERR_CRTL;
988 cf->data[1] = (bec.txerr > bec.rxerr) ?
989 CAN_ERR_CRTL_TX_WARNING :
990 CAN_ERR_CRTL_RX_WARNING;
991 cf->data[6] = bec.txerr;
992 cf->data[7] = bec.rxerr;
995 case C_CAN_ERROR_PASSIVE:
996 /* error passive state */
997 priv->can.can_stats.error_passive++;
998 priv->can.state = CAN_STATE_ERROR_PASSIVE;
999 cf->can_id |= CAN_ERR_CRTL;
1001 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
1002 if (bec.txerr > 127)
1003 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
1005 cf->data[6] = bec.txerr;
1006 cf->data[7] = bec.rxerr;
1010 priv->can.state = CAN_STATE_BUS_OFF;
1011 cf->can_id |= CAN_ERR_BUSOFF;
1013 * disable all interrupts in bus-off mode to ensure that
1014 * the CPU is not hogged down
1016 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1023 netif_receive_skb(skb);
1024 stats->rx_packets++;
1025 stats->rx_bytes += cf->can_dlc;
1030 static int c_can_handle_bus_err(struct net_device *dev,
1031 enum c_can_lec_type lec_type)
1033 struct c_can_priv *priv = netdev_priv(dev);
1034 struct net_device_stats *stats = &dev->stats;
1035 struct can_frame *cf;
1036 struct sk_buff *skb;
1039 * early exit if no lec update or no error.
1040 * no lec update means that no CAN bus event has been detected
1041 * since CPU wrote 0x7 value to status reg.
1043 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
1046 /* propagate the error condition to the CAN stack */
1047 skb = alloc_can_err_skb(dev, &cf);
1052 * check for 'last error code' which tells us the
1053 * type of the last error to occur on the CAN bus
1056 /* common for all type of bus errors */
1057 priv->can.can_stats.bus_error++;
1059 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1060 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
1063 case LEC_STUFF_ERROR:
1064 netdev_dbg(dev, "stuff error\n");
1065 cf->data[2] |= CAN_ERR_PROT_STUFF;
1067 case LEC_FORM_ERROR:
1068 netdev_dbg(dev, "form error\n");
1069 cf->data[2] |= CAN_ERR_PROT_FORM;
1072 netdev_dbg(dev, "ack error\n");
1073 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
1074 CAN_ERR_PROT_LOC_ACK_DEL);
1076 case LEC_BIT1_ERROR:
1077 netdev_dbg(dev, "bit1 error\n");
1078 cf->data[2] |= CAN_ERR_PROT_BIT1;
1080 case LEC_BIT0_ERROR:
1081 netdev_dbg(dev, "bit0 error\n");
1082 cf->data[2] |= CAN_ERR_PROT_BIT0;
1085 netdev_dbg(dev, "CRC error\n");
1086 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
1087 CAN_ERR_PROT_LOC_CRC_DEL);
1093 /* set a `lec` value so that we can check for updates later */
1094 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1096 netif_receive_skb(skb);
1097 stats->rx_packets++;
1098 stats->rx_bytes += cf->can_dlc;
1103 static int c_can_poll(struct napi_struct *napi, int quota)
1108 struct net_device *dev = napi->dev;
1109 struct c_can_priv *priv = netdev_priv(dev);
1111 irqstatus = priv->irqstatus;
1115 /* status events have the highest priority */
1116 if (irqstatus == STATUS_INTERRUPT) {
1117 priv->current_status = priv->read_reg(priv,
1120 /* handle Tx/Rx events */
1121 if (priv->current_status & STATUS_TXOK)
1122 priv->write_reg(priv, C_CAN_STS_REG,
1123 priv->current_status & ~STATUS_TXOK);
1125 if (priv->current_status & STATUS_RXOK)
1126 priv->write_reg(priv, C_CAN_STS_REG,
1127 priv->current_status & ~STATUS_RXOK);
1129 /* handle state changes */
1130 if ((priv->current_status & STATUS_EWARN) &&
1131 (!(priv->last_status & STATUS_EWARN))) {
1132 netdev_dbg(dev, "entered error warning state\n");
1133 work_done += c_can_handle_state_change(dev,
1134 C_CAN_ERROR_WARNING);
1136 if ((priv->current_status & STATUS_EPASS) &&
1137 (!(priv->last_status & STATUS_EPASS))) {
1138 netdev_dbg(dev, "entered error passive state\n");
1139 work_done += c_can_handle_state_change(dev,
1140 C_CAN_ERROR_PASSIVE);
1142 if ((priv->current_status & STATUS_BOFF) &&
1143 (!(priv->last_status & STATUS_BOFF))) {
1144 netdev_dbg(dev, "entered bus off state\n");
1145 work_done += c_can_handle_state_change(dev,
1149 /* handle bus recovery events */
1150 if ((!(priv->current_status & STATUS_BOFF)) &&
1151 (priv->last_status & STATUS_BOFF)) {
1152 netdev_dbg(dev, "left bus off state\n");
1153 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1155 if ((!(priv->current_status & STATUS_EPASS)) &&
1156 (priv->last_status & STATUS_EPASS)) {
1157 netdev_dbg(dev, "left error passive state\n");
1158 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1161 priv->last_status = priv->current_status;
1163 /* handle lec errors on the bus */
1164 lec_type = c_can_has_and_handle_berr(priv);
1166 work_done += c_can_handle_bus_err(dev, lec_type);
1167 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1168 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1169 /* handle events corresponding to receive message objects */
1170 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1171 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1172 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1173 /* handle events corresponding to transmit message objects */
1178 if (work_done < quota) {
1179 napi_complete(napi);
1180 /* enable all IRQs */
1181 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
1187 static irqreturn_t c_can_isr(int irq, void *dev_id)
1189 struct net_device *dev = (struct net_device *)dev_id;
1190 struct c_can_priv *priv = netdev_priv(dev);
1192 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG);
1193 if (!priv->irqstatus)
1196 /* disable all interrupts and schedule the NAPI */
1197 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1198 napi_schedule(&priv->napi);
1203 static int c_can_open(struct net_device *dev)
1206 struct c_can_priv *priv = netdev_priv(dev);
1208 c_can_pm_runtime_get_sync(priv);
1209 c_can_reset_ram(priv, true);
1211 /* open the can device */
1212 err = open_candev(dev);
1214 netdev_err(dev, "failed to open can device\n");
1215 goto exit_open_fail;
1218 /* register interrupt handler */
1219 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1222 netdev_err(dev, "failed to request interrupt\n");
1226 /* start the c_can controller */
1227 err = c_can_start(dev);
1229 goto exit_start_fail;
1231 can_led_event(dev, CAN_LED_EVENT_OPEN);
1233 napi_enable(&priv->napi);
1234 netif_start_queue(dev);
1239 free_irq(dev->irq, dev);
1243 c_can_reset_ram(priv, false);
1244 c_can_pm_runtime_put_sync(priv);
1248 static int c_can_close(struct net_device *dev)
1250 struct c_can_priv *priv = netdev_priv(dev);
1252 netif_stop_queue(dev);
1253 napi_disable(&priv->napi);
1255 free_irq(dev->irq, dev);
1258 c_can_reset_ram(priv, false);
1259 c_can_pm_runtime_put_sync(priv);
1261 can_led_event(dev, CAN_LED_EVENT_STOP);
1266 struct net_device *alloc_c_can_dev(void)
1268 struct net_device *dev;
1269 struct c_can_priv *priv;
1271 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1275 priv = netdev_priv(dev);
1276 spin_lock_init(&priv->xmit_lock);
1277 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1280 priv->can.bittiming_const = &c_can_bittiming_const;
1281 priv->can.do_set_mode = c_can_set_mode;
1282 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1283 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1284 CAN_CTRLMODE_LISTENONLY |
1285 CAN_CTRLMODE_BERR_REPORTING;
1289 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1292 int c_can_power_down(struct net_device *dev)
1295 unsigned long time_out;
1296 struct c_can_priv *priv = netdev_priv(dev);
1298 if (!(dev->flags & IFF_UP))
1301 WARN_ON(priv->type != BOSCH_D_CAN);
1303 /* set PDR value so the device goes to power down mode */
1304 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1305 val |= CONTROL_EX_PDR;
1306 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1308 /* Wait for the PDA bit to get set */
1309 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1310 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1311 time_after(time_out, jiffies))
1314 if (time_after(jiffies, time_out))
1319 c_can_reset_ram(priv, false);
1320 c_can_pm_runtime_put_sync(priv);
1324 EXPORT_SYMBOL_GPL(c_can_power_down);
1326 int c_can_power_up(struct net_device *dev)
1329 unsigned long time_out;
1330 struct c_can_priv *priv = netdev_priv(dev);
1332 if (!(dev->flags & IFF_UP))
1335 WARN_ON(priv->type != BOSCH_D_CAN);
1337 c_can_pm_runtime_get_sync(priv);
1338 c_can_reset_ram(priv, true);
1340 /* Clear PDR and INIT bits */
1341 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1342 val &= ~CONTROL_EX_PDR;
1343 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1344 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1345 val &= ~CONTROL_INIT;
1346 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1348 /* Wait for the PDA bit to get clear */
1349 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1350 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1351 time_after(time_out, jiffies))
1354 if (time_after(jiffies, time_out))
1357 return c_can_start(dev);
1359 EXPORT_SYMBOL_GPL(c_can_power_up);
1362 void free_c_can_dev(struct net_device *dev)
1364 struct c_can_priv *priv = netdev_priv(dev);
1366 netif_napi_del(&priv->napi);
1369 EXPORT_SYMBOL_GPL(free_c_can_dev);
1371 static const struct net_device_ops c_can_netdev_ops = {
1372 .ndo_open = c_can_open,
1373 .ndo_stop = c_can_close,
1374 .ndo_start_xmit = c_can_start_xmit,
1377 int register_c_can_dev(struct net_device *dev)
1379 struct c_can_priv *priv = netdev_priv(dev);
1382 c_can_pm_runtime_enable(priv);
1384 dev->flags |= IFF_ECHO; /* we support local echo */
1385 dev->netdev_ops = &c_can_netdev_ops;
1387 err = register_candev(dev);
1389 c_can_pm_runtime_disable(priv);
1391 devm_can_led_init(dev);
1395 EXPORT_SYMBOL_GPL(register_c_can_dev);
1397 void unregister_c_can_dev(struct net_device *dev)
1399 struct c_can_priv *priv = netdev_priv(dev);
1401 unregister_candev(dev);
1403 c_can_pm_runtime_disable(priv);
1405 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1407 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1408 MODULE_LICENSE("GPL v2");
1409 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");