2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/can.h>
40 #include <linux/can/dev.h>
41 #include <linux/can/error.h>
42 #include <linux/can/led.h>
46 /* Number of interface registers */
47 #define IF_ENUM_REG_LEN 11
48 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
50 /* control extension register D_CAN specific */
51 #define CONTROL_EX_PDR BIT(8)
53 /* control register */
54 #define CONTROL_TEST BIT(7)
55 #define CONTROL_CCE BIT(6)
56 #define CONTROL_DISABLE_AR BIT(5)
57 #define CONTROL_ENABLE_AR (0 << 5)
58 #define CONTROL_EIE BIT(3)
59 #define CONTROL_SIE BIT(2)
60 #define CONTROL_IE BIT(1)
61 #define CONTROL_INIT BIT(0)
64 #define TEST_RX BIT(7)
65 #define TEST_TX1 BIT(6)
66 #define TEST_TX2 BIT(5)
67 #define TEST_LBACK BIT(4)
68 #define TEST_SILENT BIT(3)
69 #define TEST_BASIC BIT(2)
72 #define STATUS_PDA BIT(10)
73 #define STATUS_BOFF BIT(7)
74 #define STATUS_EWARN BIT(6)
75 #define STATUS_EPASS BIT(5)
76 #define STATUS_RXOK BIT(4)
77 #define STATUS_TXOK BIT(3)
79 /* error counter register */
80 #define ERR_CNT_TEC_MASK 0xff
81 #define ERR_CNT_TEC_SHIFT 0
82 #define ERR_CNT_REC_SHIFT 8
83 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
84 #define ERR_CNT_RP_SHIFT 15
85 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
87 /* bit-timing register */
88 #define BTR_BRP_MASK 0x3f
89 #define BTR_BRP_SHIFT 0
90 #define BTR_SJW_SHIFT 6
91 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
92 #define BTR_TSEG1_SHIFT 8
93 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
94 #define BTR_TSEG2_SHIFT 12
95 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
97 /* brp extension register */
98 #define BRP_EXT_BRPE_MASK 0x0f
99 #define BRP_EXT_BRPE_SHIFT 0
101 /* IFx command request */
102 #define IF_COMR_BUSY BIT(15)
104 /* IFx command mask */
105 #define IF_COMM_WR BIT(7)
106 #define IF_COMM_MASK BIT(6)
107 #define IF_COMM_ARB BIT(5)
108 #define IF_COMM_CONTROL BIT(4)
109 #define IF_COMM_CLR_INT_PND BIT(3)
110 #define IF_COMM_TXRQST BIT(2)
111 #define IF_COMM_DATAA BIT(1)
112 #define IF_COMM_DATAB BIT(0)
113 #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
114 IF_COMM_CONTROL | IF_COMM_TXRQST | \
115 IF_COMM_DATAA | IF_COMM_DATAB)
117 /* For the low buffers we clear the interrupt bit, but keep newdat */
118 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
119 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
120 IF_COMM_DATAA | IF_COMM_DATAB)
122 /* For the high buffers we clear the interrupt bit and newdat */
123 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST)
125 /* IFx arbitration */
126 #define IF_ARB_MSGVAL BIT(15)
127 #define IF_ARB_MSGXTD BIT(14)
128 #define IF_ARB_TRANSMIT BIT(13)
130 /* IFx message control */
131 #define IF_MCONT_NEWDAT BIT(15)
132 #define IF_MCONT_MSGLST BIT(14)
133 #define IF_MCONT_INTPND BIT(13)
134 #define IF_MCONT_UMASK BIT(12)
135 #define IF_MCONT_TXIE BIT(11)
136 #define IF_MCONT_RXIE BIT(10)
137 #define IF_MCONT_RMTEN BIT(9)
138 #define IF_MCONT_TXRQST BIT(8)
139 #define IF_MCONT_EOB BIT(7)
140 #define IF_MCONT_DLC_MASK 0xf
143 * Use IF1 for RX and IF2 for TX
148 /* status interrupt */
149 #define STATUS_INTERRUPT 0x8000
151 /* global interrupt masks */
152 #define ENABLE_ALL_INTERRUPTS 1
153 #define DISABLE_ALL_INTERRUPTS 0
155 /* minimum timeout for checking BUSY status */
156 #define MIN_TIMEOUT_VALUE 6
158 /* Wait for ~1 sec for INIT bit */
159 #define INIT_WAIT_MS 1000
162 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
164 /* c_can lec values */
165 enum c_can_lec_type {
178 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
180 enum c_can_bus_error_types {
187 static const struct can_bittiming_const c_can_bittiming_const = {
188 .name = KBUILD_MODNAME,
189 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
191 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
195 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
199 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
202 pm_runtime_enable(priv->device);
205 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
208 pm_runtime_disable(priv->device);
211 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
214 pm_runtime_get_sync(priv->device);
217 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
220 pm_runtime_put_sync(priv->device);
223 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
226 priv->raminit(priv, enable);
229 static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
231 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
232 C_CAN_MSG_OBJ_TX_FIRST;
235 static inline int get_tx_echo_msg_obj(int txecho)
237 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST;
240 static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
242 u32 val = priv->read_reg(priv, index);
243 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
247 static void c_can_enable_all_interrupts(struct c_can_priv *priv,
250 unsigned int cntrl_save = priv->read_reg(priv,
254 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
256 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
258 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save);
261 static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
263 int count = MIN_TIMEOUT_VALUE;
265 while (count && priv->read_reg(priv,
266 C_CAN_IFACE(COMREQ_REG, iface)) &
278 static inline void c_can_object_get(struct net_device *dev,
279 int iface, int objno, int mask)
281 struct c_can_priv *priv = netdev_priv(dev);
284 * As per specs, after writting the message object number in the
285 * IF command request register the transfer b/w interface
286 * register and message RAM must be complete in 6 CAN-CLK
289 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
290 IFX_WRITE_LOW_16BIT(mask));
291 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
292 IFX_WRITE_LOW_16BIT(objno));
294 if (c_can_msg_obj_is_busy(priv, iface))
295 netdev_err(dev, "timed out in object get\n");
298 static inline void c_can_object_put(struct net_device *dev,
299 int iface, int objno, int mask)
301 struct c_can_priv *priv = netdev_priv(dev);
304 * As per specs, after writting the message object number in the
305 * IF command request register the transfer b/w interface
306 * register and message RAM must be complete in 6 CAN-CLK
309 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
310 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
311 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
312 IFX_WRITE_LOW_16BIT(objno));
314 if (c_can_msg_obj_is_busy(priv, iface))
315 netdev_err(dev, "timed out in object put\n");
318 static void c_can_write_msg_object(struct net_device *dev,
319 int iface, struct can_frame *frame, int objno)
324 struct c_can_priv *priv = netdev_priv(dev);
326 if (!(frame->can_id & CAN_RTR_FLAG))
327 flags |= IF_ARB_TRANSMIT;
329 if (frame->can_id & CAN_EFF_FLAG) {
330 id = frame->can_id & CAN_EFF_MASK;
331 flags |= IF_ARB_MSGXTD;
333 id = ((frame->can_id & CAN_SFF_MASK) << 18);
335 flags |= IF_ARB_MSGVAL;
337 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
338 IFX_WRITE_LOW_16BIT(id));
339 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
340 IFX_WRITE_HIGH_16BIT(id));
342 for (i = 0; i < frame->can_dlc; i += 2) {
343 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
344 frame->data[i] | (frame->data[i + 1] << 8));
347 /* enable interrupt for this message object */
348 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
349 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
351 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
354 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
359 struct c_can_priv *priv = netdev_priv(dev);
361 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
362 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
363 ctrl_mask & ~IF_MCONT_NEWDAT);
364 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
368 static int c_can_handle_lost_msg_obj(struct net_device *dev,
369 int iface, int objno, u32 ctrl)
371 struct net_device_stats *stats = &dev->stats;
372 struct c_can_priv *priv = netdev_priv(dev);
373 struct can_frame *frame;
376 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
377 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
378 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
380 /* create an error msg */
381 skb = alloc_can_err_skb(dev, &frame);
385 frame->can_id |= CAN_ERR_CRTL;
386 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
388 stats->rx_over_errors++;
390 netif_receive_skb(skb);
394 static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
399 struct c_can_priv *priv = netdev_priv(dev);
400 struct net_device_stats *stats = &dev->stats;
402 struct can_frame *frame;
404 skb = alloc_can_skb(dev, &frame);
410 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
412 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface));
413 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) |
416 if (flags & IF_ARB_MSGXTD)
417 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
419 frame->can_id = (val >> 18) & CAN_SFF_MASK;
421 if (flags & IF_ARB_TRANSMIT)
422 frame->can_id |= CAN_RTR_FLAG;
424 for (i = 0; i < frame->can_dlc; i += 2) {
425 data = priv->read_reg(priv,
426 C_CAN_IFACE(DATA1_REG, iface) + i / 2);
427 frame->data[i] = data;
428 frame->data[i + 1] = data >> 8;
432 netif_receive_skb(skb);
435 stats->rx_bytes += frame->can_dlc;
439 static void c_can_setup_receive_object(struct net_device *dev, int iface,
440 int objno, unsigned int mask,
441 unsigned int id, unsigned int mcont)
443 struct c_can_priv *priv = netdev_priv(dev);
445 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface),
446 IFX_WRITE_LOW_16BIT(mask));
448 /* According to C_CAN documentation, the reserved bit
449 * in IFx_MASK2 register is fixed 1
451 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
452 IFX_WRITE_HIGH_16BIT(mask) | BIT(13));
454 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
455 IFX_WRITE_LOW_16BIT(id));
456 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface),
457 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
459 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
460 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
462 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
463 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
466 static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
468 struct c_can_priv *priv = netdev_priv(dev);
470 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
471 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
472 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
474 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
476 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
477 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
480 static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
482 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
485 * as transmission request register's bit n-1 corresponds to
486 * message object n, we need to handle the same properly.
488 if (val & (1 << (objno - 1)))
494 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
495 struct net_device *dev)
498 struct c_can_priv *priv = netdev_priv(dev);
499 struct can_frame *frame = (struct can_frame *)skb->data;
501 if (can_dropped_invalid_skb(dev, skb))
504 spin_lock_bh(&priv->xmit_lock);
505 msg_obj_no = get_tx_next_msg_obj(priv);
507 /* prepare message object for transmission */
508 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no);
509 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc;
510 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
513 * we have to stop the queue in case of a wrap around or
514 * if the next TX message object is still in use
517 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
518 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
519 netif_stop_queue(dev);
520 spin_unlock_bh(&priv->xmit_lock);
525 static int c_can_wait_for_ctrl_init(struct net_device *dev,
526 struct c_can_priv *priv, u32 init)
530 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
532 if (retry++ > 1000) {
533 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
540 static int c_can_set_bittiming(struct net_device *dev)
542 unsigned int reg_btr, reg_brpe, ctrl_save;
543 u8 brp, brpe, sjw, tseg1, tseg2;
545 struct c_can_priv *priv = netdev_priv(dev);
546 const struct can_bittiming *bt = &priv->can.bittiming;
549 /* c_can provides a 6-bit brp and 4-bit brpe fields */
550 ten_bit_brp = bt->brp - 1;
551 brp = ten_bit_brp & BTR_BRP_MASK;
552 brpe = ten_bit_brp >> 6;
555 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
556 tseg2 = bt->phase_seg2 - 1;
557 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
558 (tseg2 << BTR_TSEG2_SHIFT);
559 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
562 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
564 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
565 ctrl_save &= ~CONTROL_INIT;
566 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
567 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
571 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
572 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
573 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
575 return c_can_wait_for_ctrl_init(dev, priv, 0);
579 * Configure C_CAN message objects for Tx and Rx purposes:
580 * C_CAN provides a total of 32 message objects that can be configured
581 * either for Tx or Rx purposes. Here the first 16 message objects are used as
582 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
583 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
584 * See user guide document for further details on configuring message
587 static void c_can_configure_msg_objects(struct net_device *dev)
591 /* first invalidate all message objects */
592 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
593 c_can_inval_msg_object(dev, IF_RX, i);
595 /* setup receive message objects */
596 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
597 c_can_setup_receive_object(dev, IF_RX, i, 0, 0,
598 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
600 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
601 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
605 * Configure C_CAN chip:
606 * - enable/disable auto-retransmission
607 * - set operating mode
608 * - configure message objects
610 static int c_can_chip_config(struct net_device *dev)
612 struct c_can_priv *priv = netdev_priv(dev);
614 /* enable automatic retransmission */
615 priv->write_reg(priv, C_CAN_CTRL_REG,
618 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
619 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
620 /* loopback + silent mode : useful for hot self-test */
621 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
622 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
623 priv->write_reg(priv, C_CAN_TEST_REG,
624 TEST_LBACK | TEST_SILENT);
625 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
626 /* loopback mode : useful for self-test function */
627 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
628 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
629 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
630 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
631 /* silent mode : bus-monitoring mode */
632 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
633 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
634 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
637 priv->write_reg(priv, C_CAN_CTRL_REG,
638 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
640 /* configure message objects */
641 c_can_configure_msg_objects(dev);
643 /* set a `lec` value so that we can check for updates later */
644 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
646 /* set bittiming params */
647 return c_can_set_bittiming(dev);
650 static int c_can_start(struct net_device *dev)
652 struct c_can_priv *priv = netdev_priv(dev);
655 /* basic c_can configuration */
656 err = c_can_chip_config(dev);
660 priv->can.state = CAN_STATE_ERROR_ACTIVE;
662 /* reset tx helper pointers */
663 priv->tx_next = priv->tx_echo = 0;
665 /* enable status change, error and module interrupts */
666 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
671 static void c_can_stop(struct net_device *dev)
673 struct c_can_priv *priv = netdev_priv(dev);
675 /* disable all interrupts */
676 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
678 /* set the state as STOPPED */
679 priv->can.state = CAN_STATE_STOPPED;
682 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
688 err = c_can_start(dev);
691 netif_wake_queue(dev);
700 static int __c_can_get_berr_counter(const struct net_device *dev,
701 struct can_berr_counter *bec)
703 unsigned int reg_err_counter;
704 struct c_can_priv *priv = netdev_priv(dev);
706 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
707 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
709 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
714 static int c_can_get_berr_counter(const struct net_device *dev,
715 struct can_berr_counter *bec)
717 struct c_can_priv *priv = netdev_priv(dev);
720 c_can_pm_runtime_get_sync(priv);
721 err = __c_can_get_berr_counter(dev, bec);
722 c_can_pm_runtime_put_sync(priv);
728 * priv->tx_echo holds the number of the oldest can_frame put for
729 * transmission into the hardware, but not yet ACKed by the CAN tx
732 * We iterate from priv->tx_echo to priv->tx_next and check if the
733 * packet has been transmitted, echo it back to the CAN framework.
734 * If we discover a not yet transmitted packet, stop looking for more.
736 static void c_can_do_tx(struct net_device *dev)
738 struct c_can_priv *priv = netdev_priv(dev);
739 struct net_device_stats *stats = &dev->stats;
740 u32 val, obj, pkts = 0, bytes = 0;
742 spin_lock_bh(&priv->xmit_lock);
744 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
745 obj = get_tx_echo_msg_obj(priv->tx_echo);
746 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
748 if (val & (1 << (obj - 1)))
751 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST);
752 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST];
754 c_can_inval_msg_object(dev, IF_TX, obj);
757 /* restart queue if wrap-up or if queue stalled on last pkt */
758 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
759 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
760 netif_wake_queue(dev);
762 spin_unlock_bh(&priv->xmit_lock);
765 stats->tx_bytes += bytes;
766 stats->tx_packets += pkts;
767 can_led_event(dev, CAN_LED_EVENT_TX);
772 * If we have a gap in the pending bits, that means we either
773 * raced with the hardware or failed to readout all upper
774 * objects in the last run due to quota limit.
776 static u32 c_can_adjust_pending(u32 pend)
780 if (pend == RECEIVE_OBJECT_BITS)
784 * If the last set bit is larger than the number of pending
785 * bits we have a gap.
787 weight = hweight32(pend);
790 /* If the bits are linear, nothing to do */
795 * Find the first set bit after the gap. We walk backwards
796 * from the last set bit.
798 for (lasts--; pend & (1 << (lasts - 1)); lasts--);
800 return pend & ~((1 << lasts) - 1);
803 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
806 u32 pkts = 0, ctrl, obj, mcmd;
808 while ((obj = ffs(pend)) && quota > 0) {
809 pend &= ~BIT(obj - 1);
811 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ?
812 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
814 c_can_object_get(dev, IF_RX, obj, mcmd);
815 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
817 if (ctrl & IF_MCONT_MSGLST) {
818 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
826 * This really should not happen, but this covers some
827 * odd HW behaviour. Do not remove that unless you
828 * want to brick your machine.
830 if (!(ctrl & IF_MCONT_NEWDAT))
833 /* read the data from the message object */
834 c_can_read_msg_object(dev, IF_RX, ctrl);
836 if (obj == C_CAN_MSG_RX_LOW_LAST)
837 /* activate all lower message objects */
838 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl);
848 * theory of operation:
850 * c_can core saves a received CAN message into the first free message
851 * object it finds free (starting with the lowest). Bits NEWDAT and
852 * INTPND are set for this message object indicating that a new message
853 * has arrived. To work-around this issue, we keep two groups of message
854 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
856 * To ensure in-order frame reception we use the following
857 * approach while re-activating a message object to receive further
859 * - if the current message object number is lower than
860 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
862 * - if the current message object number is equal to
863 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
864 * receive message objects.
865 * - if the current message object number is greater than
866 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
867 * only this message object.
869 static int c_can_do_rx_poll(struct net_device *dev, int quota)
871 struct c_can_priv *priv = netdev_priv(dev);
872 u32 pkts = 0, pend = 0, toread, n;
875 * It is faster to read only one 16bit register. This is only possible
876 * for a maximum number of 16 objects.
878 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
879 "Implementation does not support more message objects than 16");
883 pend = priv->read_reg(priv, C_CAN_INTPND1_REG);
887 * If the pending field has a gap, handle the
888 * bits above the gap first.
890 toread = c_can_adjust_pending(pend);
894 /* Remove the bits from pend */
896 /* Read the objects */
897 n = c_can_read_objects(dev, priv, toread, quota);
903 can_led_event(dev, CAN_LED_EVENT_RX);
908 static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
910 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
911 (priv->current_status & LEC_UNUSED);
914 static int c_can_handle_state_change(struct net_device *dev,
915 enum c_can_bus_error_types error_type)
917 unsigned int reg_err_counter;
918 unsigned int rx_err_passive;
919 struct c_can_priv *priv = netdev_priv(dev);
920 struct net_device_stats *stats = &dev->stats;
921 struct can_frame *cf;
923 struct can_berr_counter bec;
925 /* propagate the error condition to the CAN stack */
926 skb = alloc_can_err_skb(dev, &cf);
930 __c_can_get_berr_counter(dev, &bec);
931 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
932 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
935 switch (error_type) {
936 case C_CAN_ERROR_WARNING:
937 /* error warning state */
938 priv->can.can_stats.error_warning++;
939 priv->can.state = CAN_STATE_ERROR_WARNING;
940 cf->can_id |= CAN_ERR_CRTL;
941 cf->data[1] = (bec.txerr > bec.rxerr) ?
942 CAN_ERR_CRTL_TX_WARNING :
943 CAN_ERR_CRTL_RX_WARNING;
944 cf->data[6] = bec.txerr;
945 cf->data[7] = bec.rxerr;
948 case C_CAN_ERROR_PASSIVE:
949 /* error passive state */
950 priv->can.can_stats.error_passive++;
951 priv->can.state = CAN_STATE_ERROR_PASSIVE;
952 cf->can_id |= CAN_ERR_CRTL;
954 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
956 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
958 cf->data[6] = bec.txerr;
959 cf->data[7] = bec.rxerr;
963 priv->can.state = CAN_STATE_BUS_OFF;
964 cf->can_id |= CAN_ERR_BUSOFF;
966 * disable all interrupts in bus-off mode to ensure that
967 * the CPU is not hogged down
969 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
976 netif_receive_skb(skb);
978 stats->rx_bytes += cf->can_dlc;
983 static int c_can_handle_bus_err(struct net_device *dev,
984 enum c_can_lec_type lec_type)
986 struct c_can_priv *priv = netdev_priv(dev);
987 struct net_device_stats *stats = &dev->stats;
988 struct can_frame *cf;
992 * early exit if no lec update or no error.
993 * no lec update means that no CAN bus event has been detected
994 * since CPU wrote 0x7 value to status reg.
996 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
999 /* propagate the error condition to the CAN stack */
1000 skb = alloc_can_err_skb(dev, &cf);
1005 * check for 'last error code' which tells us the
1006 * type of the last error to occur on the CAN bus
1009 /* common for all type of bus errors */
1010 priv->can.can_stats.bus_error++;
1012 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1013 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
1016 case LEC_STUFF_ERROR:
1017 netdev_dbg(dev, "stuff error\n");
1018 cf->data[2] |= CAN_ERR_PROT_STUFF;
1020 case LEC_FORM_ERROR:
1021 netdev_dbg(dev, "form error\n");
1022 cf->data[2] |= CAN_ERR_PROT_FORM;
1025 netdev_dbg(dev, "ack error\n");
1026 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
1027 CAN_ERR_PROT_LOC_ACK_DEL);
1029 case LEC_BIT1_ERROR:
1030 netdev_dbg(dev, "bit1 error\n");
1031 cf->data[2] |= CAN_ERR_PROT_BIT1;
1033 case LEC_BIT0_ERROR:
1034 netdev_dbg(dev, "bit0 error\n");
1035 cf->data[2] |= CAN_ERR_PROT_BIT0;
1038 netdev_dbg(dev, "CRC error\n");
1039 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
1040 CAN_ERR_PROT_LOC_CRC_DEL);
1046 /* set a `lec` value so that we can check for updates later */
1047 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1049 netif_receive_skb(skb);
1050 stats->rx_packets++;
1051 stats->rx_bytes += cf->can_dlc;
1056 static int c_can_poll(struct napi_struct *napi, int quota)
1061 struct net_device *dev = napi->dev;
1062 struct c_can_priv *priv = netdev_priv(dev);
1064 irqstatus = priv->irqstatus;
1068 /* status events have the highest priority */
1069 if (irqstatus == STATUS_INTERRUPT) {
1070 priv->current_status = priv->read_reg(priv,
1073 /* handle Tx/Rx events */
1074 if (priv->current_status & STATUS_TXOK)
1075 priv->write_reg(priv, C_CAN_STS_REG,
1076 priv->current_status & ~STATUS_TXOK);
1078 if (priv->current_status & STATUS_RXOK)
1079 priv->write_reg(priv, C_CAN_STS_REG,
1080 priv->current_status & ~STATUS_RXOK);
1082 /* handle state changes */
1083 if ((priv->current_status & STATUS_EWARN) &&
1084 (!(priv->last_status & STATUS_EWARN))) {
1085 netdev_dbg(dev, "entered error warning state\n");
1086 work_done += c_can_handle_state_change(dev,
1087 C_CAN_ERROR_WARNING);
1089 if ((priv->current_status & STATUS_EPASS) &&
1090 (!(priv->last_status & STATUS_EPASS))) {
1091 netdev_dbg(dev, "entered error passive state\n");
1092 work_done += c_can_handle_state_change(dev,
1093 C_CAN_ERROR_PASSIVE);
1095 if ((priv->current_status & STATUS_BOFF) &&
1096 (!(priv->last_status & STATUS_BOFF))) {
1097 netdev_dbg(dev, "entered bus off state\n");
1098 work_done += c_can_handle_state_change(dev,
1102 /* handle bus recovery events */
1103 if ((!(priv->current_status & STATUS_BOFF)) &&
1104 (priv->last_status & STATUS_BOFF)) {
1105 netdev_dbg(dev, "left bus off state\n");
1106 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1108 if ((!(priv->current_status & STATUS_EPASS)) &&
1109 (priv->last_status & STATUS_EPASS)) {
1110 netdev_dbg(dev, "left error passive state\n");
1111 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1114 priv->last_status = priv->current_status;
1116 /* handle lec errors on the bus */
1117 lec_type = c_can_has_and_handle_berr(priv);
1119 work_done += c_can_handle_bus_err(dev, lec_type);
1120 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1121 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1122 /* handle events corresponding to receive message objects */
1123 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1124 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1125 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1126 /* handle events corresponding to transmit message objects */
1131 if (work_done < quota) {
1132 napi_complete(napi);
1133 /* enable all IRQs */
1134 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
1140 static irqreturn_t c_can_isr(int irq, void *dev_id)
1142 struct net_device *dev = (struct net_device *)dev_id;
1143 struct c_can_priv *priv = netdev_priv(dev);
1145 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG);
1146 if (!priv->irqstatus)
1149 /* disable all interrupts and schedule the NAPI */
1150 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1151 napi_schedule(&priv->napi);
1156 static int c_can_open(struct net_device *dev)
1159 struct c_can_priv *priv = netdev_priv(dev);
1161 c_can_pm_runtime_get_sync(priv);
1162 c_can_reset_ram(priv, true);
1164 /* open the can device */
1165 err = open_candev(dev);
1167 netdev_err(dev, "failed to open can device\n");
1168 goto exit_open_fail;
1171 /* register interrupt handler */
1172 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1175 netdev_err(dev, "failed to request interrupt\n");
1179 /* start the c_can controller */
1180 err = c_can_start(dev);
1182 goto exit_start_fail;
1184 can_led_event(dev, CAN_LED_EVENT_OPEN);
1186 napi_enable(&priv->napi);
1187 netif_start_queue(dev);
1192 free_irq(dev->irq, dev);
1196 c_can_reset_ram(priv, false);
1197 c_can_pm_runtime_put_sync(priv);
1201 static int c_can_close(struct net_device *dev)
1203 struct c_can_priv *priv = netdev_priv(dev);
1205 netif_stop_queue(dev);
1206 napi_disable(&priv->napi);
1208 free_irq(dev->irq, dev);
1211 c_can_reset_ram(priv, false);
1212 c_can_pm_runtime_put_sync(priv);
1214 can_led_event(dev, CAN_LED_EVENT_STOP);
1219 struct net_device *alloc_c_can_dev(void)
1221 struct net_device *dev;
1222 struct c_can_priv *priv;
1224 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1228 priv = netdev_priv(dev);
1229 spin_lock_init(&priv->xmit_lock);
1230 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1233 priv->can.bittiming_const = &c_can_bittiming_const;
1234 priv->can.do_set_mode = c_can_set_mode;
1235 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1236 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1237 CAN_CTRLMODE_LISTENONLY |
1238 CAN_CTRLMODE_BERR_REPORTING;
1242 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1245 int c_can_power_down(struct net_device *dev)
1248 unsigned long time_out;
1249 struct c_can_priv *priv = netdev_priv(dev);
1251 if (!(dev->flags & IFF_UP))
1254 WARN_ON(priv->type != BOSCH_D_CAN);
1256 /* set PDR value so the device goes to power down mode */
1257 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1258 val |= CONTROL_EX_PDR;
1259 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1261 /* Wait for the PDA bit to get set */
1262 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1263 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1264 time_after(time_out, jiffies))
1267 if (time_after(jiffies, time_out))
1272 c_can_reset_ram(priv, false);
1273 c_can_pm_runtime_put_sync(priv);
1277 EXPORT_SYMBOL_GPL(c_can_power_down);
1279 int c_can_power_up(struct net_device *dev)
1282 unsigned long time_out;
1283 struct c_can_priv *priv = netdev_priv(dev);
1285 if (!(dev->flags & IFF_UP))
1288 WARN_ON(priv->type != BOSCH_D_CAN);
1290 c_can_pm_runtime_get_sync(priv);
1291 c_can_reset_ram(priv, true);
1293 /* Clear PDR and INIT bits */
1294 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1295 val &= ~CONTROL_EX_PDR;
1296 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1297 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1298 val &= ~CONTROL_INIT;
1299 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1301 /* Wait for the PDA bit to get clear */
1302 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1303 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1304 time_after(time_out, jiffies))
1307 if (time_after(jiffies, time_out))
1310 return c_can_start(dev);
1312 EXPORT_SYMBOL_GPL(c_can_power_up);
1315 void free_c_can_dev(struct net_device *dev)
1317 struct c_can_priv *priv = netdev_priv(dev);
1319 netif_napi_del(&priv->napi);
1322 EXPORT_SYMBOL_GPL(free_c_can_dev);
1324 static const struct net_device_ops c_can_netdev_ops = {
1325 .ndo_open = c_can_open,
1326 .ndo_stop = c_can_close,
1327 .ndo_start_xmit = c_can_start_xmit,
1328 .ndo_change_mtu = can_change_mtu,
1331 int register_c_can_dev(struct net_device *dev)
1333 struct c_can_priv *priv = netdev_priv(dev);
1336 c_can_pm_runtime_enable(priv);
1338 dev->flags |= IFF_ECHO; /* we support local echo */
1339 dev->netdev_ops = &c_can_netdev_ops;
1341 err = register_candev(dev);
1343 c_can_pm_runtime_disable(priv);
1345 devm_can_led_init(dev);
1349 EXPORT_SYMBOL_GPL(register_c_can_dev);
1351 void unregister_c_can_dev(struct net_device *dev)
1353 struct c_can_priv *priv = netdev_priv(dev);
1355 unregister_candev(dev);
1357 c_can_pm_runtime_disable(priv);
1359 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1361 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1362 MODULE_LICENSE("GPL v2");
1363 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");