2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/can.h>
40 #include <linux/can/dev.h>
41 #include <linux/can/error.h>
42 #include <linux/can/led.h>
46 /* Number of interface registers */
47 #define IF_ENUM_REG_LEN 11
48 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
50 /* control extension register D_CAN specific */
51 #define CONTROL_EX_PDR BIT(8)
53 /* control register */
54 #define CONTROL_TEST BIT(7)
55 #define CONTROL_CCE BIT(6)
56 #define CONTROL_DISABLE_AR BIT(5)
57 #define CONTROL_ENABLE_AR (0 << 5)
58 #define CONTROL_EIE BIT(3)
59 #define CONTROL_SIE BIT(2)
60 #define CONTROL_IE BIT(1)
61 #define CONTROL_INIT BIT(0)
63 #define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
66 #define TEST_RX BIT(7)
67 #define TEST_TX1 BIT(6)
68 #define TEST_TX2 BIT(5)
69 #define TEST_LBACK BIT(4)
70 #define TEST_SILENT BIT(3)
71 #define TEST_BASIC BIT(2)
74 #define STATUS_PDA BIT(10)
75 #define STATUS_BOFF BIT(7)
76 #define STATUS_EWARN BIT(6)
77 #define STATUS_EPASS BIT(5)
78 #define STATUS_RXOK BIT(4)
79 #define STATUS_TXOK BIT(3)
81 /* error counter register */
82 #define ERR_CNT_TEC_MASK 0xff
83 #define ERR_CNT_TEC_SHIFT 0
84 #define ERR_CNT_REC_SHIFT 8
85 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
86 #define ERR_CNT_RP_SHIFT 15
87 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
89 /* bit-timing register */
90 #define BTR_BRP_MASK 0x3f
91 #define BTR_BRP_SHIFT 0
92 #define BTR_SJW_SHIFT 6
93 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
94 #define BTR_TSEG1_SHIFT 8
95 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
96 #define BTR_TSEG2_SHIFT 12
97 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
99 /* brp extension register */
100 #define BRP_EXT_BRPE_MASK 0x0f
101 #define BRP_EXT_BRPE_SHIFT 0
103 /* IFx command request */
104 #define IF_COMR_BUSY BIT(15)
106 /* IFx command mask */
107 #define IF_COMM_WR BIT(7)
108 #define IF_COMM_MASK BIT(6)
109 #define IF_COMM_ARB BIT(5)
110 #define IF_COMM_CONTROL BIT(4)
111 #define IF_COMM_CLR_INT_PND BIT(3)
112 #define IF_COMM_TXRQST BIT(2)
113 #define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST
114 #define IF_COMM_DATAA BIT(1)
115 #define IF_COMM_DATAB BIT(0)
116 #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
117 IF_COMM_CONTROL | IF_COMM_TXRQST | \
118 IF_COMM_DATAA | IF_COMM_DATAB)
120 /* For the low buffers we clear the interrupt bit, but keep newdat */
121 #define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \
122 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
123 IF_COMM_DATAA | IF_COMM_DATAB)
125 /* For the high buffers we clear the interrupt bit and newdat */
126 #define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
129 /* Receive setup of message objects */
130 #define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
132 /* IFx arbitration */
133 #define IF_ARB_MSGVAL BIT(15)
134 #define IF_ARB_MSGXTD BIT(14)
135 #define IF_ARB_TRANSMIT BIT(13)
137 /* IFx message control */
138 #define IF_MCONT_NEWDAT BIT(15)
139 #define IF_MCONT_MSGLST BIT(14)
140 #define IF_MCONT_INTPND BIT(13)
141 #define IF_MCONT_UMASK BIT(12)
142 #define IF_MCONT_TXIE BIT(11)
143 #define IF_MCONT_RXIE BIT(10)
144 #define IF_MCONT_RMTEN BIT(9)
145 #define IF_MCONT_TXRQST BIT(8)
146 #define IF_MCONT_EOB BIT(7)
147 #define IF_MCONT_DLC_MASK 0xf
149 #define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK)
150 #define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB)
153 * Use IF1 for RX and IF2 for TX
158 /* minimum timeout for checking BUSY status */
159 #define MIN_TIMEOUT_VALUE 6
161 /* Wait for ~1 sec for INIT bit */
162 #define INIT_WAIT_MS 1000
165 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
167 /* c_can lec values */
168 enum c_can_lec_type {
177 LEC_MASK = LEC_UNUSED,
182 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
184 enum c_can_bus_error_types {
191 static const struct can_bittiming_const c_can_bittiming_const = {
192 .name = KBUILD_MODNAME,
193 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
195 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
199 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
203 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
206 pm_runtime_enable(priv->device);
209 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
212 pm_runtime_disable(priv->device);
215 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
218 pm_runtime_get_sync(priv->device);
221 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
224 pm_runtime_put_sync(priv->device);
227 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
230 priv->raminit(priv, enable);
233 static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
235 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
236 C_CAN_MSG_OBJ_TX_FIRST;
239 static inline int get_tx_echo_msg_obj(int txecho)
241 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST;
244 static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
246 u32 val = priv->read_reg(priv, index);
247 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
251 static void c_can_irq_control(struct c_can_priv *priv, bool enable)
253 u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
256 ctrl |= CONTROL_IRQMSK;
258 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
261 static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
263 int count = MIN_TIMEOUT_VALUE;
265 while (count && priv->read_reg(priv,
266 C_CAN_IFACE(COMREQ_REG, iface)) &
278 static inline void c_can_object_get(struct net_device *dev,
279 int iface, int objno, int mask)
281 struct c_can_priv *priv = netdev_priv(dev);
284 * As per specs, after writting the message object number in the
285 * IF command request register the transfer b/w interface
286 * register and message RAM must be complete in 6 CAN-CLK
289 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
290 IFX_WRITE_LOW_16BIT(mask));
291 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
292 IFX_WRITE_LOW_16BIT(objno));
294 if (c_can_msg_obj_is_busy(priv, iface))
295 netdev_err(dev, "timed out in object get\n");
298 static inline void c_can_object_put(struct net_device *dev,
299 int iface, int objno, int mask)
301 struct c_can_priv *priv = netdev_priv(dev);
304 * As per specs, after writting the message object number in the
305 * IF command request register the transfer b/w interface
306 * register and message RAM must be complete in 6 CAN-CLK
309 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
310 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
311 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
312 IFX_WRITE_LOW_16BIT(objno));
314 if (c_can_msg_obj_is_busy(priv, iface))
315 netdev_err(dev, "timed out in object put\n");
318 static void c_can_write_msg_object(struct net_device *dev,
319 int iface, struct can_frame *frame, int objno)
324 struct c_can_priv *priv = netdev_priv(dev);
326 if (!(frame->can_id & CAN_RTR_FLAG))
327 flags |= IF_ARB_TRANSMIT;
329 if (frame->can_id & CAN_EFF_FLAG) {
330 id = frame->can_id & CAN_EFF_MASK;
331 flags |= IF_ARB_MSGXTD;
333 id = ((frame->can_id & CAN_SFF_MASK) << 18);
335 flags |= IF_ARB_MSGVAL;
337 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
338 IFX_WRITE_LOW_16BIT(id));
339 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
340 IFX_WRITE_HIGH_16BIT(id));
342 for (i = 0; i < frame->can_dlc; i += 2) {
343 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
344 frame->data[i] | (frame->data[i + 1] << 8));
347 /* enable interrupt for this message object */
348 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
349 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
351 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
354 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
359 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++)
360 c_can_object_get(dev, iface, i, IF_COMM_CLR_NEWDAT);
363 static int c_can_handle_lost_msg_obj(struct net_device *dev,
364 int iface, int objno, u32 ctrl)
366 struct net_device_stats *stats = &dev->stats;
367 struct c_can_priv *priv = netdev_priv(dev);
368 struct can_frame *frame;
371 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
372 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
373 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
376 stats->rx_over_errors++;
378 /* create an error msg */
379 skb = alloc_can_err_skb(dev, &frame);
383 frame->can_id |= CAN_ERR_CRTL;
384 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
386 netif_receive_skb(skb);
390 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
392 struct net_device_stats *stats = &dev->stats;
393 struct c_can_priv *priv = netdev_priv(dev);
394 struct can_frame *frame;
398 skb = alloc_can_skb(dev, &frame);
404 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
406 arb = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface));
407 arb |= priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)) << 16;
409 if (arb & (IF_ARB_MSGXTD << 16))
410 frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
412 frame->can_id = (arb >> 18) & CAN_SFF_MASK;
414 if (arb & (IF_ARB_TRANSMIT << 16)) {
415 frame->can_id |= CAN_RTR_FLAG;
417 int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
419 for (i = 0; i < frame->can_dlc; i += 2, dreg ++) {
420 data = priv->read_reg(priv, dreg);
421 frame->data[i] = data;
422 frame->data[i + 1] = data >> 8;
427 stats->rx_bytes += frame->can_dlc;
429 netif_receive_skb(skb);
433 static void c_can_setup_receive_object(struct net_device *dev, int iface,
434 u32 obj, u32 mask, u32 id, u32 mcont)
436 struct c_can_priv *priv = netdev_priv(dev);
439 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
440 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), mask >> 16);
442 id |= IF_ARB_MSGVAL << 16;
443 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), id);
444 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), id >> 16);
446 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
447 c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
450 static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
452 struct c_can_priv *priv = netdev_priv(dev);
454 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
455 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
456 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
458 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
460 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
461 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
464 static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
466 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
469 * as transmission request register's bit n-1 corresponds to
470 * message object n, we need to handle the same properly.
472 if (val & (1 << (objno - 1)))
478 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
479 struct net_device *dev)
482 struct c_can_priv *priv = netdev_priv(dev);
483 struct can_frame *frame = (struct can_frame *)skb->data;
485 if (can_dropped_invalid_skb(dev, skb))
488 spin_lock_bh(&priv->xmit_lock);
489 msg_obj_no = get_tx_next_msg_obj(priv);
491 /* prepare message object for transmission */
492 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no);
493 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc;
494 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
497 * we have to stop the queue in case of a wrap around or
498 * if the next TX message object is still in use
501 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
502 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
503 netif_stop_queue(dev);
504 spin_unlock_bh(&priv->xmit_lock);
509 static int c_can_wait_for_ctrl_init(struct net_device *dev,
510 struct c_can_priv *priv, u32 init)
514 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
516 if (retry++ > 1000) {
517 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
524 static int c_can_set_bittiming(struct net_device *dev)
526 unsigned int reg_btr, reg_brpe, ctrl_save;
527 u8 brp, brpe, sjw, tseg1, tseg2;
529 struct c_can_priv *priv = netdev_priv(dev);
530 const struct can_bittiming *bt = &priv->can.bittiming;
533 /* c_can provides a 6-bit brp and 4-bit brpe fields */
534 ten_bit_brp = bt->brp - 1;
535 brp = ten_bit_brp & BTR_BRP_MASK;
536 brpe = ten_bit_brp >> 6;
539 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
540 tseg2 = bt->phase_seg2 - 1;
541 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
542 (tseg2 << BTR_TSEG2_SHIFT);
543 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
546 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
548 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
549 ctrl_save &= ~CONTROL_INIT;
550 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
551 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
555 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
556 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
557 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
559 return c_can_wait_for_ctrl_init(dev, priv, 0);
563 * Configure C_CAN message objects for Tx and Rx purposes:
564 * C_CAN provides a total of 32 message objects that can be configured
565 * either for Tx or Rx purposes. Here the first 16 message objects are used as
566 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
567 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
568 * See user guide document for further details on configuring message
571 static void c_can_configure_msg_objects(struct net_device *dev)
575 /* first invalidate all message objects */
576 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
577 c_can_inval_msg_object(dev, IF_RX, i);
579 /* setup receive message objects */
580 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
581 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV);
583 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
588 * Configure C_CAN chip:
589 * - enable/disable auto-retransmission
590 * - set operating mode
591 * - configure message objects
593 static int c_can_chip_config(struct net_device *dev)
595 struct c_can_priv *priv = netdev_priv(dev);
597 /* enable automatic retransmission */
598 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
600 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
601 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
602 /* loopback + silent mode : useful for hot self-test */
603 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
604 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
605 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
606 /* loopback mode : useful for self-test function */
607 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
608 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
609 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
610 /* silent mode : bus-monitoring mode */
611 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
612 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
615 /* configure message objects */
616 c_can_configure_msg_objects(dev);
618 /* set a `lec` value so that we can check for updates later */
619 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
621 /* set bittiming params */
622 return c_can_set_bittiming(dev);
625 static int c_can_start(struct net_device *dev)
627 struct c_can_priv *priv = netdev_priv(dev);
630 /* basic c_can configuration */
631 err = c_can_chip_config(dev);
635 /* Setup the command for new messages */
636 priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
637 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
639 priv->can.state = CAN_STATE_ERROR_ACTIVE;
641 /* reset tx helper pointers and the rx mask */
642 priv->tx_next = priv->tx_echo = 0;
648 static void c_can_stop(struct net_device *dev)
650 struct c_can_priv *priv = netdev_priv(dev);
652 c_can_irq_control(priv, false);
653 priv->can.state = CAN_STATE_STOPPED;
656 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
658 struct c_can_priv *priv = netdev_priv(dev);
663 err = c_can_start(dev);
666 netif_wake_queue(dev);
667 c_can_irq_control(priv, true);
676 static int __c_can_get_berr_counter(const struct net_device *dev,
677 struct can_berr_counter *bec)
679 unsigned int reg_err_counter;
680 struct c_can_priv *priv = netdev_priv(dev);
682 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
683 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
685 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
690 static int c_can_get_berr_counter(const struct net_device *dev,
691 struct can_berr_counter *bec)
693 struct c_can_priv *priv = netdev_priv(dev);
696 c_can_pm_runtime_get_sync(priv);
697 err = __c_can_get_berr_counter(dev, bec);
698 c_can_pm_runtime_put_sync(priv);
704 * priv->tx_echo holds the number of the oldest can_frame put for
705 * transmission into the hardware, but not yet ACKed by the CAN tx
708 * We iterate from priv->tx_echo to priv->tx_next and check if the
709 * packet has been transmitted, echo it back to the CAN framework.
710 * If we discover a not yet transmitted packet, stop looking for more.
712 static void c_can_do_tx(struct net_device *dev)
714 struct c_can_priv *priv = netdev_priv(dev);
715 struct net_device_stats *stats = &dev->stats;
716 u32 val, obj, pkts = 0, bytes = 0;
718 spin_lock_bh(&priv->xmit_lock);
720 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
721 obj = get_tx_echo_msg_obj(priv->tx_echo);
722 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
724 if (val & (1 << (obj - 1)))
727 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST);
728 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST];
730 c_can_inval_msg_object(dev, IF_TX, obj);
733 /* restart queue if wrap-up or if queue stalled on last pkt */
734 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
735 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
736 netif_wake_queue(dev);
738 spin_unlock_bh(&priv->xmit_lock);
741 stats->tx_bytes += bytes;
742 stats->tx_packets += pkts;
743 can_led_event(dev, CAN_LED_EVENT_TX);
748 * If we have a gap in the pending bits, that means we either
749 * raced with the hardware or failed to readout all upper
750 * objects in the last run due to quota limit.
752 static u32 c_can_adjust_pending(u32 pend)
756 if (pend == RECEIVE_OBJECT_BITS)
760 * If the last set bit is larger than the number of pending
761 * bits we have a gap.
763 weight = hweight32(pend);
766 /* If the bits are linear, nothing to do */
771 * Find the first set bit after the gap. We walk backwards
772 * from the last set bit.
774 for (lasts--; pend & (1 << (lasts - 1)); lasts--);
776 return pend & ~((1 << lasts) - 1);
779 static inline void c_can_rx_object_get(struct net_device *dev,
780 struct c_can_priv *priv, u32 obj)
782 #ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING
783 if (obj < C_CAN_MSG_RX_LOW_LAST)
784 c_can_object_get(dev, IF_RX, obj, IF_COMM_RCV_LOW);
787 c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high);
790 static inline void c_can_rx_finalize(struct net_device *dev,
791 struct c_can_priv *priv, u32 obj)
793 #ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING
794 if (obj < C_CAN_MSG_RX_LOW_LAST)
795 priv->rxmasked |= BIT(obj - 1);
796 else if (obj == C_CAN_MSG_RX_LOW_LAST) {
798 /* activate all lower message objects */
799 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX);
802 if (priv->type != BOSCH_D_CAN)
803 c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT);
806 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
809 u32 pkts = 0, ctrl, obj;
811 while ((obj = ffs(pend)) && quota > 0) {
812 pend &= ~BIT(obj - 1);
814 c_can_rx_object_get(dev, priv, obj);
815 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX));
817 if (ctrl & IF_MCONT_MSGLST) {
818 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl);
826 * This really should not happen, but this covers some
827 * odd HW behaviour. Do not remove that unless you
828 * want to brick your machine.
830 if (!(ctrl & IF_MCONT_NEWDAT))
833 /* read the data from the message object */
834 c_can_read_msg_object(dev, IF_RX, ctrl);
836 c_can_rx_finalize(dev, priv, obj);
845 static inline u32 c_can_get_pending(struct c_can_priv *priv)
847 u32 pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
849 #ifdef CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING
850 pend &= ~priv->rxmasked;
856 * theory of operation:
858 * c_can core saves a received CAN message into the first free message
859 * object it finds free (starting with the lowest). Bits NEWDAT and
860 * INTPND are set for this message object indicating that a new message
861 * has arrived. To work-around this issue, we keep two groups of message
862 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
864 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = y
866 * To ensure in-order frame reception we use the following
867 * approach while re-activating a message object to receive further
869 * - if the current message object number is lower than
870 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
872 * - if the current message object number is equal to
873 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
874 * receive message objects.
875 * - if the current message object number is greater than
876 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
877 * only this message object.
879 * This can cause packet loss!
881 * If CONFIG_CAN_C_CAN_STRICT_FRAME_ORDERING = n
883 * We clear the newdat bit right away.
885 * This can result in packet reordering when the readout is slow.
887 static int c_can_do_rx_poll(struct net_device *dev, int quota)
889 struct c_can_priv *priv = netdev_priv(dev);
890 u32 pkts = 0, pend = 0, toread, n;
893 * It is faster to read only one 16bit register. This is only possible
894 * for a maximum number of 16 objects.
896 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16,
897 "Implementation does not support more message objects than 16");
901 pend = c_can_get_pending(priv);
905 * If the pending field has a gap, handle the
906 * bits above the gap first.
908 toread = c_can_adjust_pending(pend);
912 /* Remove the bits from pend */
914 /* Read the objects */
915 n = c_can_read_objects(dev, priv, toread, quota);
921 can_led_event(dev, CAN_LED_EVENT_RX);
926 static int c_can_handle_state_change(struct net_device *dev,
927 enum c_can_bus_error_types error_type)
929 unsigned int reg_err_counter;
930 unsigned int rx_err_passive;
931 struct c_can_priv *priv = netdev_priv(dev);
932 struct net_device_stats *stats = &dev->stats;
933 struct can_frame *cf;
935 struct can_berr_counter bec;
937 switch (error_type) {
938 case C_CAN_ERROR_WARNING:
939 /* error warning state */
940 priv->can.can_stats.error_warning++;
941 priv->can.state = CAN_STATE_ERROR_WARNING;
943 case C_CAN_ERROR_PASSIVE:
944 /* error passive state */
945 priv->can.can_stats.error_passive++;
946 priv->can.state = CAN_STATE_ERROR_PASSIVE;
950 priv->can.state = CAN_STATE_BUS_OFF;
957 /* propagate the error condition to the CAN stack */
958 skb = alloc_can_err_skb(dev, &cf);
962 __c_can_get_berr_counter(dev, &bec);
963 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
964 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
967 switch (error_type) {
968 case C_CAN_ERROR_WARNING:
969 /* error warning state */
970 cf->can_id |= CAN_ERR_CRTL;
971 cf->data[1] = (bec.txerr > bec.rxerr) ?
972 CAN_ERR_CRTL_TX_WARNING :
973 CAN_ERR_CRTL_RX_WARNING;
974 cf->data[6] = bec.txerr;
975 cf->data[7] = bec.rxerr;
978 case C_CAN_ERROR_PASSIVE:
979 /* error passive state */
980 cf->can_id |= CAN_ERR_CRTL;
982 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
984 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
986 cf->data[6] = bec.txerr;
987 cf->data[7] = bec.rxerr;
991 cf->can_id |= CAN_ERR_BUSOFF;
999 stats->rx_bytes += cf->can_dlc;
1000 netif_receive_skb(skb);
1005 static int c_can_handle_bus_err(struct net_device *dev,
1006 enum c_can_lec_type lec_type)
1008 struct c_can_priv *priv = netdev_priv(dev);
1009 struct net_device_stats *stats = &dev->stats;
1010 struct can_frame *cf;
1011 struct sk_buff *skb;
1014 * early exit if no lec update or no error.
1015 * no lec update means that no CAN bus event has been detected
1016 * since CPU wrote 0x7 value to status reg.
1018 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
1021 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1024 /* common for all type of bus errors */
1025 priv->can.can_stats.bus_error++;
1028 /* propagate the error condition to the CAN stack */
1029 skb = alloc_can_err_skb(dev, &cf);
1034 * check for 'last error code' which tells us the
1035 * type of the last error to occur on the CAN bus
1037 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1038 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
1041 case LEC_STUFF_ERROR:
1042 netdev_dbg(dev, "stuff error\n");
1043 cf->data[2] |= CAN_ERR_PROT_STUFF;
1045 case LEC_FORM_ERROR:
1046 netdev_dbg(dev, "form error\n");
1047 cf->data[2] |= CAN_ERR_PROT_FORM;
1050 netdev_dbg(dev, "ack error\n");
1051 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
1052 CAN_ERR_PROT_LOC_ACK_DEL);
1054 case LEC_BIT1_ERROR:
1055 netdev_dbg(dev, "bit1 error\n");
1056 cf->data[2] |= CAN_ERR_PROT_BIT1;
1058 case LEC_BIT0_ERROR:
1059 netdev_dbg(dev, "bit0 error\n");
1060 cf->data[2] |= CAN_ERR_PROT_BIT0;
1063 netdev_dbg(dev, "CRC error\n");
1064 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
1065 CAN_ERR_PROT_LOC_CRC_DEL);
1071 stats->rx_packets++;
1072 stats->rx_bytes += cf->can_dlc;
1073 netif_receive_skb(skb);
1077 static int c_can_poll(struct napi_struct *napi, int quota)
1079 struct net_device *dev = napi->dev;
1080 struct c_can_priv *priv = netdev_priv(dev);
1081 u16 curr, last = priv->last_status;
1084 priv->last_status = curr = priv->read_reg(priv, C_CAN_STS_REG);
1085 /* Ack status on C_CAN. D_CAN is self clearing */
1086 if (priv->type != BOSCH_D_CAN)
1087 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1089 /* handle state changes */
1090 if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1091 netdev_dbg(dev, "entered error warning state\n");
1092 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1095 if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1096 netdev_dbg(dev, "entered error passive state\n");
1097 work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1100 if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1101 netdev_dbg(dev, "entered bus off state\n");
1102 work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1106 /* handle bus recovery events */
1107 if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1108 netdev_dbg(dev, "left bus off state\n");
1109 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1111 if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1112 netdev_dbg(dev, "left error passive state\n");
1113 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1116 /* handle lec errors on the bus */
1117 work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1119 /* Handle Tx/Rx events. We do this unconditionally */
1120 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1124 if (work_done < quota) {
1125 napi_complete(napi);
1126 /* enable all IRQs if we are not in bus off state */
1127 if (priv->can.state != CAN_STATE_BUS_OFF)
1128 c_can_irq_control(priv, true);
1134 static irqreturn_t c_can_isr(int irq, void *dev_id)
1136 struct net_device *dev = (struct net_device *)dev_id;
1137 struct c_can_priv *priv = netdev_priv(dev);
1139 if (!priv->read_reg(priv, C_CAN_INT_REG))
1142 /* disable all interrupts and schedule the NAPI */
1143 c_can_irq_control(priv, false);
1144 napi_schedule(&priv->napi);
1149 static int c_can_open(struct net_device *dev)
1152 struct c_can_priv *priv = netdev_priv(dev);
1154 c_can_pm_runtime_get_sync(priv);
1155 c_can_reset_ram(priv, true);
1157 /* open the can device */
1158 err = open_candev(dev);
1160 netdev_err(dev, "failed to open can device\n");
1161 goto exit_open_fail;
1164 /* register interrupt handler */
1165 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1168 netdev_err(dev, "failed to request interrupt\n");
1172 /* start the c_can controller */
1173 err = c_can_start(dev);
1175 goto exit_start_fail;
1177 can_led_event(dev, CAN_LED_EVENT_OPEN);
1179 napi_enable(&priv->napi);
1180 /* enable status change, error and module interrupts */
1181 c_can_irq_control(priv, true);
1182 netif_start_queue(dev);
1187 free_irq(dev->irq, dev);
1191 c_can_reset_ram(priv, false);
1192 c_can_pm_runtime_put_sync(priv);
1196 static int c_can_close(struct net_device *dev)
1198 struct c_can_priv *priv = netdev_priv(dev);
1200 netif_stop_queue(dev);
1201 napi_disable(&priv->napi);
1203 free_irq(dev->irq, dev);
1206 c_can_reset_ram(priv, false);
1207 c_can_pm_runtime_put_sync(priv);
1209 can_led_event(dev, CAN_LED_EVENT_STOP);
1214 struct net_device *alloc_c_can_dev(void)
1216 struct net_device *dev;
1217 struct c_can_priv *priv;
1219 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1223 priv = netdev_priv(dev);
1224 spin_lock_init(&priv->xmit_lock);
1225 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1228 priv->can.bittiming_const = &c_can_bittiming_const;
1229 priv->can.do_set_mode = c_can_set_mode;
1230 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1231 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1232 CAN_CTRLMODE_LISTENONLY |
1233 CAN_CTRLMODE_BERR_REPORTING;
1237 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1240 int c_can_power_down(struct net_device *dev)
1243 unsigned long time_out;
1244 struct c_can_priv *priv = netdev_priv(dev);
1246 if (!(dev->flags & IFF_UP))
1249 WARN_ON(priv->type != BOSCH_D_CAN);
1251 /* set PDR value so the device goes to power down mode */
1252 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1253 val |= CONTROL_EX_PDR;
1254 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1256 /* Wait for the PDA bit to get set */
1257 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1258 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1259 time_after(time_out, jiffies))
1262 if (time_after(jiffies, time_out))
1267 c_can_reset_ram(priv, false);
1268 c_can_pm_runtime_put_sync(priv);
1272 EXPORT_SYMBOL_GPL(c_can_power_down);
1274 int c_can_power_up(struct net_device *dev)
1277 unsigned long time_out;
1278 struct c_can_priv *priv = netdev_priv(dev);
1281 if (!(dev->flags & IFF_UP))
1284 WARN_ON(priv->type != BOSCH_D_CAN);
1286 c_can_pm_runtime_get_sync(priv);
1287 c_can_reset_ram(priv, true);
1289 /* Clear PDR and INIT bits */
1290 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1291 val &= ~CONTROL_EX_PDR;
1292 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1293 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1294 val &= ~CONTROL_INIT;
1295 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1297 /* Wait for the PDA bit to get clear */
1298 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1299 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1300 time_after(time_out, jiffies))
1303 if (time_after(jiffies, time_out))
1306 ret = c_can_start(dev);
1308 c_can_irq_control(priv, true);
1312 EXPORT_SYMBOL_GPL(c_can_power_up);
1315 void free_c_can_dev(struct net_device *dev)
1317 struct c_can_priv *priv = netdev_priv(dev);
1319 netif_napi_del(&priv->napi);
1322 EXPORT_SYMBOL_GPL(free_c_can_dev);
1324 static const struct net_device_ops c_can_netdev_ops = {
1325 .ndo_open = c_can_open,
1326 .ndo_stop = c_can_close,
1327 .ndo_start_xmit = c_can_start_xmit,
1328 .ndo_change_mtu = can_change_mtu,
1331 int register_c_can_dev(struct net_device *dev)
1333 struct c_can_priv *priv = netdev_priv(dev);
1336 c_can_pm_runtime_enable(priv);
1338 dev->flags |= IFF_ECHO; /* we support local echo */
1339 dev->netdev_ops = &c_can_netdev_ops;
1341 err = register_candev(dev);
1343 c_can_pm_runtime_disable(priv);
1345 devm_can_led_init(dev);
1349 EXPORT_SYMBOL_GPL(register_c_can_dev);
1351 void unregister_c_can_dev(struct net_device *dev)
1353 struct c_can_priv *priv = netdev_priv(dev);
1355 unregister_candev(dev);
1357 c_can_pm_runtime_disable(priv);
1359 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1361 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1362 MODULE_LICENSE("GPL v2");
1363 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");