2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/platform/flexcan.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/platform_device.h>
39 #define DRV_NAME "flexcan"
41 /* 8 for RX fifo and 2 error handling */
42 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
44 /* FLEXCAN module configuration register (CANMCR) bits */
45 #define FLEXCAN_MCR_MDIS BIT(31)
46 #define FLEXCAN_MCR_FRZ BIT(30)
47 #define FLEXCAN_MCR_FEN BIT(29)
48 #define FLEXCAN_MCR_HALT BIT(28)
49 #define FLEXCAN_MCR_NOT_RDY BIT(27)
50 #define FLEXCAN_MCR_WAK_MSK BIT(26)
51 #define FLEXCAN_MCR_SOFTRST BIT(25)
52 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
53 #define FLEXCAN_MCR_SUPV BIT(23)
54 #define FLEXCAN_MCR_SLF_WAK BIT(22)
55 #define FLEXCAN_MCR_WRN_EN BIT(21)
56 #define FLEXCAN_MCR_LPM_ACK BIT(20)
57 #define FLEXCAN_MCR_WAK_SRC BIT(19)
58 #define FLEXCAN_MCR_DOZE BIT(18)
59 #define FLEXCAN_MCR_SRX_DIS BIT(17)
60 #define FLEXCAN_MCR_BCC BIT(16)
61 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
62 #define FLEXCAN_MCR_AEN BIT(12)
63 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
64 #define FLEXCAN_MCR_IDAM_A (0 << 8)
65 #define FLEXCAN_MCR_IDAM_B (1 << 8)
66 #define FLEXCAN_MCR_IDAM_C (2 << 8)
67 #define FLEXCAN_MCR_IDAM_D (3 << 8)
69 /* FLEXCAN control register (CANCTRL) bits */
70 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
71 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
72 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
73 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
74 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
75 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
76 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
77 #define FLEXCAN_CTRL_LPB BIT(12)
78 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
79 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
80 #define FLEXCAN_CTRL_SMP BIT(7)
81 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
82 #define FLEXCAN_CTRL_TSYN BIT(5)
83 #define FLEXCAN_CTRL_LBUF BIT(4)
84 #define FLEXCAN_CTRL_LOM BIT(3)
85 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
86 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
87 #define FLEXCAN_CTRL_ERR_STATE \
88 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
89 FLEXCAN_CTRL_BOFF_MSK)
90 #define FLEXCAN_CTRL_ERR_ALL \
91 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
93 /* FLEXCAN error and status register (ESR) bits */
94 #define FLEXCAN_ESR_TWRN_INT BIT(17)
95 #define FLEXCAN_ESR_RWRN_INT BIT(16)
96 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
97 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
98 #define FLEXCAN_ESR_ACK_ERR BIT(13)
99 #define FLEXCAN_ESR_CRC_ERR BIT(12)
100 #define FLEXCAN_ESR_FRM_ERR BIT(11)
101 #define FLEXCAN_ESR_STF_ERR BIT(10)
102 #define FLEXCAN_ESR_TX_WRN BIT(9)
103 #define FLEXCAN_ESR_RX_WRN BIT(8)
104 #define FLEXCAN_ESR_IDLE BIT(7)
105 #define FLEXCAN_ESR_TXRX BIT(6)
106 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
107 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
108 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
109 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
110 #define FLEXCAN_ESR_BOFF_INT BIT(2)
111 #define FLEXCAN_ESR_ERR_INT BIT(1)
112 #define FLEXCAN_ESR_WAK_INT BIT(0)
113 #define FLEXCAN_ESR_ERR_BUS \
114 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
115 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
116 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
117 #define FLEXCAN_ESR_ERR_STATE \
118 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
119 #define FLEXCAN_ESR_ERR_ALL \
120 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
122 /* FLEXCAN interrupt flag register (IFLAG) bits */
123 #define FLEXCAN_TX_BUF_ID 8
124 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
125 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
126 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
127 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
128 #define FLEXCAN_IFLAG_DEFAULT \
129 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
130 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
132 /* FLEXCAN message buffers */
133 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
134 #define FLEXCAN_MB_CNT_SRR BIT(22)
135 #define FLEXCAN_MB_CNT_IDE BIT(21)
136 #define FLEXCAN_MB_CNT_RTR BIT(20)
137 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
138 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
140 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
142 /* Structure of the message buffer */
149 /* Structure of the hardware registers */
150 struct flexcan_regs {
153 u32 timer; /* 0x08 */
154 u32 _reserved1; /* 0x0c */
155 u32 rxgmask; /* 0x10 */
156 u32 rx14mask; /* 0x14 */
157 u32 rx15mask; /* 0x18 */
160 u32 imask2; /* 0x24 */
161 u32 imask1; /* 0x28 */
162 u32 iflag2; /* 0x2c */
163 u32 iflag1; /* 0x30 */
165 struct flexcan_mb cantxfg[64];
168 struct flexcan_priv {
170 struct net_device *dev;
171 struct napi_struct napi;
175 u32 reg_ctrl_default;
178 struct flexcan_platform_data *pdata;
181 static struct can_bittiming_const flexcan_bittiming_const = {
194 * Abstract off the read/write for arm versus ppc.
196 #if defined(__BIG_ENDIAN)
197 static inline u32 flexcan_read(void __iomem *addr)
199 return in_be32(addr);
202 static inline void flexcan_write(u32 val, void __iomem *addr)
207 static inline u32 flexcan_read(void __iomem *addr)
212 static inline void flexcan_write(u32 val, void __iomem *addr)
219 * Swtich transceiver on or off
221 static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
223 if (priv->pdata && priv->pdata->transceiver_switch)
224 priv->pdata->transceiver_switch(on);
227 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
230 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
231 (reg_esr & FLEXCAN_ESR_ERR_BUS);
234 static inline void flexcan_chip_enable(struct flexcan_priv *priv)
236 struct flexcan_regs __iomem *regs = priv->base;
239 reg = flexcan_read(®s->mcr);
240 reg &= ~FLEXCAN_MCR_MDIS;
241 flexcan_write(reg, ®s->mcr);
246 static inline void flexcan_chip_disable(struct flexcan_priv *priv)
248 struct flexcan_regs __iomem *regs = priv->base;
251 reg = flexcan_read(®s->mcr);
252 reg |= FLEXCAN_MCR_MDIS;
253 flexcan_write(reg, ®s->mcr);
256 static int flexcan_get_berr_counter(const struct net_device *dev,
257 struct can_berr_counter *bec)
259 const struct flexcan_priv *priv = netdev_priv(dev);
260 struct flexcan_regs __iomem *regs = priv->base;
261 u32 reg = flexcan_read(®s->ecr);
263 bec->txerr = (reg >> 0) & 0xff;
264 bec->rxerr = (reg >> 8) & 0xff;
269 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
271 const struct flexcan_priv *priv = netdev_priv(dev);
272 struct net_device_stats *stats = &dev->stats;
273 struct flexcan_regs __iomem *regs = priv->base;
274 struct can_frame *cf = (struct can_frame *)skb->data;
276 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
278 if (can_dropped_invalid_skb(dev, skb))
281 netif_stop_queue(dev);
283 if (cf->can_id & CAN_EFF_FLAG) {
284 can_id = cf->can_id & CAN_EFF_MASK;
285 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
287 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
290 if (cf->can_id & CAN_RTR_FLAG)
291 ctrl |= FLEXCAN_MB_CNT_RTR;
293 if (cf->can_dlc > 0) {
294 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
295 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
297 if (cf->can_dlc > 3) {
298 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
299 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
302 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
303 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
307 /* tx_packets is incremented in flexcan_irq */
308 stats->tx_bytes += cf->can_dlc;
313 static void do_bus_err(struct net_device *dev,
314 struct can_frame *cf, u32 reg_esr)
316 struct flexcan_priv *priv = netdev_priv(dev);
317 int rx_errors = 0, tx_errors = 0;
319 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
321 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
322 dev_dbg(dev->dev.parent, "BIT1_ERR irq\n");
323 cf->data[2] |= CAN_ERR_PROT_BIT1;
326 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
327 dev_dbg(dev->dev.parent, "BIT0_ERR irq\n");
328 cf->data[2] |= CAN_ERR_PROT_BIT0;
331 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
332 dev_dbg(dev->dev.parent, "ACK_ERR irq\n");
333 cf->can_id |= CAN_ERR_ACK;
334 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
337 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
338 dev_dbg(dev->dev.parent, "CRC_ERR irq\n");
339 cf->data[2] |= CAN_ERR_PROT_BIT;
340 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
343 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
344 dev_dbg(dev->dev.parent, "FRM_ERR irq\n");
345 cf->data[2] |= CAN_ERR_PROT_FORM;
348 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
349 dev_dbg(dev->dev.parent, "STF_ERR irq\n");
350 cf->data[2] |= CAN_ERR_PROT_STUFF;
354 priv->can.can_stats.bus_error++;
356 dev->stats.rx_errors++;
358 dev->stats.tx_errors++;
361 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
364 struct can_frame *cf;
366 skb = alloc_can_err_skb(dev, &cf);
370 do_bus_err(dev, cf, reg_esr);
371 netif_receive_skb(skb);
373 dev->stats.rx_packets++;
374 dev->stats.rx_bytes += cf->can_dlc;
379 static void do_state(struct net_device *dev,
380 struct can_frame *cf, enum can_state new_state)
382 struct flexcan_priv *priv = netdev_priv(dev);
383 struct can_berr_counter bec;
385 flexcan_get_berr_counter(dev, &bec);
387 switch (priv->can.state) {
388 case CAN_STATE_ERROR_ACTIVE:
391 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
392 * => : there was a warning int
394 if (new_state >= CAN_STATE_ERROR_WARNING &&
395 new_state <= CAN_STATE_BUS_OFF) {
396 dev_dbg(dev->dev.parent, "Error Warning IRQ\n");
397 priv->can.can_stats.error_warning++;
399 cf->can_id |= CAN_ERR_CRTL;
400 cf->data[1] = (bec.txerr > bec.rxerr) ?
401 CAN_ERR_CRTL_TX_WARNING :
402 CAN_ERR_CRTL_RX_WARNING;
404 case CAN_STATE_ERROR_WARNING: /* fallthrough */
406 * from: ERROR_ACTIVE, ERROR_WARNING
407 * to : ERROR_PASSIVE, BUS_OFF
408 * => : error passive int
410 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
411 new_state <= CAN_STATE_BUS_OFF) {
412 dev_dbg(dev->dev.parent, "Error Passive IRQ\n");
413 priv->can.can_stats.error_passive++;
415 cf->can_id |= CAN_ERR_CRTL;
416 cf->data[1] = (bec.txerr > bec.rxerr) ?
417 CAN_ERR_CRTL_TX_PASSIVE :
418 CAN_ERR_CRTL_RX_PASSIVE;
421 case CAN_STATE_BUS_OFF:
422 dev_err(dev->dev.parent,
423 "BUG! hardware recovered automatically from BUS_OFF\n");
429 /* process state changes depending on the new state */
431 case CAN_STATE_ERROR_ACTIVE:
432 dev_dbg(dev->dev.parent, "Error Active\n");
433 cf->can_id |= CAN_ERR_PROT;
434 cf->data[2] = CAN_ERR_PROT_ACTIVE;
436 case CAN_STATE_BUS_OFF:
437 cf->can_id |= CAN_ERR_BUSOFF;
445 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
447 struct flexcan_priv *priv = netdev_priv(dev);
449 struct can_frame *cf;
450 enum can_state new_state;
453 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
454 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
455 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
456 FLEXCAN_ESR_RX_WRN))))
457 new_state = CAN_STATE_ERROR_ACTIVE;
459 new_state = CAN_STATE_ERROR_WARNING;
460 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
461 new_state = CAN_STATE_ERROR_PASSIVE;
463 new_state = CAN_STATE_BUS_OFF;
465 /* state hasn't changed */
466 if (likely(new_state == priv->can.state))
469 skb = alloc_can_err_skb(dev, &cf);
473 do_state(dev, cf, new_state);
474 priv->can.state = new_state;
475 netif_receive_skb(skb);
477 dev->stats.rx_packets++;
478 dev->stats.rx_bytes += cf->can_dlc;
483 static void flexcan_read_fifo(const struct net_device *dev,
484 struct can_frame *cf)
486 const struct flexcan_priv *priv = netdev_priv(dev);
487 struct flexcan_regs __iomem *regs = priv->base;
488 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
489 u32 reg_ctrl, reg_id;
491 reg_ctrl = flexcan_read(&mb->can_ctrl);
492 reg_id = flexcan_read(&mb->can_id);
493 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
494 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
496 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
498 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
499 cf->can_id |= CAN_RTR_FLAG;
500 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
502 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
503 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
506 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
507 flexcan_read(®s->timer);
510 static int flexcan_read_frame(struct net_device *dev)
512 struct net_device_stats *stats = &dev->stats;
513 struct can_frame *cf;
516 skb = alloc_can_skb(dev, &cf);
517 if (unlikely(!skb)) {
522 flexcan_read_fifo(dev, cf);
523 netif_receive_skb(skb);
526 stats->rx_bytes += cf->can_dlc;
531 static int flexcan_poll(struct napi_struct *napi, int quota)
533 struct net_device *dev = napi->dev;
534 const struct flexcan_priv *priv = netdev_priv(dev);
535 struct flexcan_regs __iomem *regs = priv->base;
536 u32 reg_iflag1, reg_esr;
540 * The error bits are cleared on read,
541 * use saved value from irq handler.
543 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
545 /* handle state changes */
546 work_done += flexcan_poll_state(dev, reg_esr);
549 reg_iflag1 = flexcan_read(®s->iflag1);
550 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
552 work_done += flexcan_read_frame(dev);
553 reg_iflag1 = flexcan_read(®s->iflag1);
556 /* report bus errors */
557 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
558 work_done += flexcan_poll_bus_err(dev, reg_esr);
560 if (work_done < quota) {
563 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
564 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
570 static irqreturn_t flexcan_irq(int irq, void *dev_id)
572 struct net_device *dev = dev_id;
573 struct net_device_stats *stats = &dev->stats;
574 struct flexcan_priv *priv = netdev_priv(dev);
575 struct flexcan_regs __iomem *regs = priv->base;
576 u32 reg_iflag1, reg_esr;
578 reg_iflag1 = flexcan_read(®s->iflag1);
579 reg_esr = flexcan_read(®s->esr);
580 flexcan_write(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */
583 * schedule NAPI in case of:
586 * - bus error IRQ and bus error reporting is activated
588 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
589 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
590 flexcan_has_and_handle_berr(priv, reg_esr)) {
592 * The error bits are cleared on read,
593 * save them for later use.
595 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
596 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
597 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
598 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
600 napi_schedule(&priv->napi);
604 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
605 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
606 dev->stats.rx_over_errors++;
607 dev->stats.rx_errors++;
610 /* transmission complete interrupt */
611 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
612 /* tx_bytes is incremented in flexcan_start_xmit */
614 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
615 netif_wake_queue(dev);
621 static void flexcan_set_bittiming(struct net_device *dev)
623 const struct flexcan_priv *priv = netdev_priv(dev);
624 const struct can_bittiming *bt = &priv->can.bittiming;
625 struct flexcan_regs __iomem *regs = priv->base;
628 reg = flexcan_read(®s->ctrl);
629 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
630 FLEXCAN_CTRL_RJW(0x3) |
631 FLEXCAN_CTRL_PSEG1(0x7) |
632 FLEXCAN_CTRL_PSEG2(0x7) |
633 FLEXCAN_CTRL_PROPSEG(0x7) |
638 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
639 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
640 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
641 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
642 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
644 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
645 reg |= FLEXCAN_CTRL_LPB;
646 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
647 reg |= FLEXCAN_CTRL_LOM;
648 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
649 reg |= FLEXCAN_CTRL_SMP;
651 dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg);
652 flexcan_write(reg, ®s->ctrl);
654 /* print chip status */
655 dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
656 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
662 * this functions is entered with clocks enabled
665 static int flexcan_chip_start(struct net_device *dev)
667 struct flexcan_priv *priv = netdev_priv(dev);
668 struct flexcan_regs __iomem *regs = priv->base;
671 u32 reg_mcr, reg_ctrl;
674 flexcan_chip_enable(priv);
677 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
680 reg_mcr = flexcan_read(®s->mcr);
681 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
682 dev_err(dev->dev.parent,
683 "Failed to softreset can module (mcr=0x%08x)\n",
689 flexcan_set_bittiming(dev);
697 * only supervisor access
702 reg_mcr = flexcan_read(®s->mcr);
703 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
704 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
706 dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr);
707 flexcan_write(reg_mcr, ®s->mcr);
712 * disable timer sync feature
714 * disable auto busoff recovery
715 * transmit lowest buffer first
717 * enable tx and rx warning interrupt
718 * enable bus off interrupt
719 * (== FLEXCAN_CTRL_ERR_STATE)
721 * _note_: we enable the "error interrupt"
722 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
723 * warning or bus passive interrupts.
725 reg_ctrl = flexcan_read(®s->ctrl);
726 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
727 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
728 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK;
730 /* save for later use */
731 priv->reg_ctrl_default = reg_ctrl;
732 dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
733 flexcan_write(reg_ctrl, ®s->ctrl);
735 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
736 flexcan_write(0, ®s->cantxfg[i].can_ctrl);
737 flexcan_write(0, ®s->cantxfg[i].can_id);
738 flexcan_write(0, ®s->cantxfg[i].data[0]);
739 flexcan_write(0, ®s->cantxfg[i].data[1]);
741 /* put MB into rx queue */
742 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
743 ®s->cantxfg[i].can_ctrl);
746 /* acceptance mask/acceptance code (accept everything) */
747 flexcan_write(0x0, ®s->rxgmask);
748 flexcan_write(0x0, ®s->rx14mask);
749 flexcan_write(0x0, ®s->rx15mask);
751 flexcan_transceiver_switch(priv, 1);
753 /* synchronize with the can bus */
754 reg_mcr = flexcan_read(®s->mcr);
755 reg_mcr &= ~FLEXCAN_MCR_HALT;
756 flexcan_write(reg_mcr, ®s->mcr);
758 priv->can.state = CAN_STATE_ERROR_ACTIVE;
760 /* enable FIFO interrupts */
761 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
763 /* print chip status */
764 dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n",
765 __func__, flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
770 flexcan_chip_disable(priv);
777 * this functions is entered with clocks enabled
780 static void flexcan_chip_stop(struct net_device *dev)
782 struct flexcan_priv *priv = netdev_priv(dev);
783 struct flexcan_regs __iomem *regs = priv->base;
786 /* Disable all interrupts */
787 flexcan_write(0, ®s->imask1);
789 /* Disable + halt module */
790 reg = flexcan_read(®s->mcr);
791 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
792 flexcan_write(reg, ®s->mcr);
794 flexcan_transceiver_switch(priv, 0);
795 priv->can.state = CAN_STATE_STOPPED;
800 static int flexcan_open(struct net_device *dev)
802 struct flexcan_priv *priv = netdev_priv(dev);
805 clk_enable(priv->clk);
807 err = open_candev(dev);
811 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
815 /* start chip and queuing */
816 err = flexcan_chip_start(dev);
819 napi_enable(&priv->napi);
820 netif_start_queue(dev);
827 clk_disable(priv->clk);
832 static int flexcan_close(struct net_device *dev)
834 struct flexcan_priv *priv = netdev_priv(dev);
836 netif_stop_queue(dev);
837 napi_disable(&priv->napi);
838 flexcan_chip_stop(dev);
840 free_irq(dev->irq, dev);
841 clk_disable(priv->clk);
848 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
854 err = flexcan_chip_start(dev);
858 netif_wake_queue(dev);
868 static const struct net_device_ops flexcan_netdev_ops = {
869 .ndo_open = flexcan_open,
870 .ndo_stop = flexcan_close,
871 .ndo_start_xmit = flexcan_start_xmit,
874 static int __devinit register_flexcandev(struct net_device *dev)
876 struct flexcan_priv *priv = netdev_priv(dev);
877 struct flexcan_regs __iomem *regs = priv->base;
880 clk_enable(priv->clk);
882 /* select "bus clock", chip must be disabled */
883 flexcan_chip_disable(priv);
884 reg = flexcan_read(®s->ctrl);
885 reg |= FLEXCAN_CTRL_CLK_SRC;
886 flexcan_write(reg, ®s->ctrl);
888 flexcan_chip_enable(priv);
890 /* set freeze, halt and activate FIFO, restrict register access */
891 reg = flexcan_read(®s->mcr);
892 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
893 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
894 flexcan_write(reg, ®s->mcr);
897 * Currently we only support newer versions of this core
898 * featuring a RX FIFO. Older cores found on some Coldfire
899 * derivates are not yet supported.
901 reg = flexcan_read(®s->mcr);
902 if (!(reg & FLEXCAN_MCR_FEN)) {
903 dev_err(dev->dev.parent,
904 "Could not enable RX FIFO, unsupported core\n");
909 err = register_candev(dev);
912 /* disable core and turn off clocks */
913 flexcan_chip_disable(priv);
914 clk_disable(priv->clk);
919 static void __devexit unregister_flexcandev(struct net_device *dev)
921 unregister_candev(dev);
924 static int __devinit flexcan_probe(struct platform_device *pdev)
926 struct net_device *dev;
927 struct flexcan_priv *priv;
928 struct resource *mem;
929 struct clk *clk = NULL;
931 resource_size_t mem_size;
935 if (pdev->dev.of_node) {
936 const u32 *clock_freq_p;
938 clock_freq_p = of_get_property(pdev->dev.of_node,
939 "clock-frequency", NULL);
941 clock_freq = *clock_freq_p;
945 clk = clk_get(&pdev->dev, NULL);
947 dev_err(&pdev->dev, "no clock defined\n");
951 clock_freq = clk_get_rate(clk);
954 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
955 irq = platform_get_irq(pdev, 0);
956 if (!mem || irq <= 0) {
961 mem_size = resource_size(mem);
962 if (!request_mem_region(mem->start, mem_size, pdev->name)) {
967 base = ioremap(mem->start, mem_size);
973 dev = alloc_candev(sizeof(struct flexcan_priv), 0);
979 dev->netdev_ops = &flexcan_netdev_ops;
981 dev->flags |= IFF_ECHO; /* we support local echo in hardware */
983 priv = netdev_priv(dev);
984 priv->can.clock.freq = clock_freq;
985 priv->can.bittiming_const = &flexcan_bittiming_const;
986 priv->can.do_set_mode = flexcan_set_mode;
987 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
988 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
989 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
990 CAN_CTRLMODE_BERR_REPORTING;
994 priv->pdata = pdev->dev.platform_data;
996 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
998 dev_set_drvdata(&pdev->dev, dev);
999 SET_NETDEV_DEV(dev, &pdev->dev);
1001 err = register_flexcandev(dev);
1003 dev_err(&pdev->dev, "registering netdev failed\n");
1004 goto failed_register;
1007 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1008 priv->base, dev->irq);
1017 release_mem_region(mem->start, mem_size);
1025 static int __devexit flexcan_remove(struct platform_device *pdev)
1027 struct net_device *dev = platform_get_drvdata(pdev);
1028 struct flexcan_priv *priv = netdev_priv(dev);
1029 struct resource *mem;
1031 unregister_flexcandev(dev);
1032 platform_set_drvdata(pdev, NULL);
1033 iounmap(priv->base);
1035 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1036 release_mem_region(mem->start, resource_size(mem));
1046 static struct of_device_id flexcan_of_match[] = {
1048 .compatible = "fsl,p1010-flexcan",
1053 static struct platform_driver flexcan_driver = {
1056 .owner = THIS_MODULE,
1057 .of_match_table = flexcan_of_match,
1059 .probe = flexcan_probe,
1060 .remove = __devexit_p(flexcan_remove),
1063 static int __init flexcan_init(void)
1065 pr_info("%s netdevice driver\n", DRV_NAME);
1066 return platform_driver_register(&flexcan_driver);
1069 static void __exit flexcan_exit(void)
1071 platform_driver_unregister(&flexcan_driver);
1072 pr_info("%s: driver removed\n", DRV_NAME);
1075 module_init(flexcan_init);
1076 module_exit(flexcan_exit);
1078 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1079 "Marc Kleine-Budde <kernel@pengutronix.de>");
1080 MODULE_LICENSE("GPL v2");
1081 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");