2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
41 #define DRV_NAME "flexcan"
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95 /* FLEXCAN control register 2 (CTRL2) bits */
96 #define FLEXCAN_CRL2_ECRWRE BIT(29)
97 #define FLEXCAN_CRL2_WRMFRZ BIT(28)
98 #define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24)
99 #define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19)
100 #define FLEXCAN_CRL2_MRP BIT(18)
101 #define FLEXCAN_CRL2_RRS BIT(17)
102 #define FLEXCAN_CRL2_EACEN BIT(16)
104 /* FLEXCAN memory error control register (MECR) bits */
105 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
106 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
107 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
108 #define FLEXCAN_MECR_CEI_MSK BIT(16)
109 #define FLEXCAN_MECR_HAERRIE BIT(15)
110 #define FLEXCAN_MECR_FAERRIE BIT(14)
111 #define FLEXCAN_MECR_EXTERRIE BIT(13)
112 #define FLEXCAN_MECR_RERRDIS BIT(9)
113 #define FLEXCAN_MECR_ECCDIS BIT(8)
114 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
116 /* FLEXCAN error and status register (ESR) bits */
117 #define FLEXCAN_ESR_TWRN_INT BIT(17)
118 #define FLEXCAN_ESR_RWRN_INT BIT(16)
119 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
120 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
121 #define FLEXCAN_ESR_ACK_ERR BIT(13)
122 #define FLEXCAN_ESR_CRC_ERR BIT(12)
123 #define FLEXCAN_ESR_FRM_ERR BIT(11)
124 #define FLEXCAN_ESR_STF_ERR BIT(10)
125 #define FLEXCAN_ESR_TX_WRN BIT(9)
126 #define FLEXCAN_ESR_RX_WRN BIT(8)
127 #define FLEXCAN_ESR_IDLE BIT(7)
128 #define FLEXCAN_ESR_TXRX BIT(6)
129 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
130 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
133 #define FLEXCAN_ESR_BOFF_INT BIT(2)
134 #define FLEXCAN_ESR_ERR_INT BIT(1)
135 #define FLEXCAN_ESR_WAK_INT BIT(0)
136 #define FLEXCAN_ESR_ERR_BUS \
137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
140 #define FLEXCAN_ESR_ERR_STATE \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
142 #define FLEXCAN_ESR_ERR_ALL \
143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
144 #define FLEXCAN_ESR_ALL_INT \
145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
148 /* FLEXCAN interrupt flag register (IFLAG) bits */
149 /* Errata ERR005829 step7: Reserve first valid MB */
150 #define FLEXCAN_TX_BUF_RESERVED 8
151 #define FLEXCAN_TX_BUF_ID 9
152 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
153 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
154 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
155 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
156 #define FLEXCAN_IFLAG_DEFAULT \
157 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
158 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
162 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
163 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
164 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
165 #define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24)
166 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
168 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
169 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
170 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
171 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
173 #define FLEXCAN_MB_CNT_SRR BIT(22)
174 #define FLEXCAN_MB_CNT_IDE BIT(21)
175 #define FLEXCAN_MB_CNT_RTR BIT(20)
176 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
177 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
179 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
181 #define FLEXCAN_TIMEOUT_US (50)
184 * FLEXCAN hardware feature flags
186 * Below is some version info we got:
187 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err
188 * Filter? connected? detection
189 * MX25 FlexCAN2 03.00.00.00 no no no
190 * MX28 FlexCAN2 03.00.04.00 yes yes no
191 * MX35 FlexCAN2 03.00.00.00 no no no
192 * MX53 FlexCAN2 03.00.00.00 yes no no
193 * MX6s FlexCAN3 10.00.12.00 yes yes no
194 * VF610 FlexCAN3 ? no yes yes
196 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
198 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
199 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
200 #define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
202 /* Structure of the message buffer */
209 /* Structure of the hardware registers */
210 struct flexcan_regs {
213 u32 timer; /* 0x08 */
214 u32 _reserved1; /* 0x0c */
215 u32 rxgmask; /* 0x10 */
216 u32 rx14mask; /* 0x14 */
217 u32 rx15mask; /* 0x18 */
220 u32 imask2; /* 0x24 */
221 u32 imask1; /* 0x28 */
222 u32 iflag2; /* 0x2c */
223 u32 iflag1; /* 0x30 */
226 u32 imeur; /* 0x3c */
229 u32 rxfgmask; /* 0x48 */
230 u32 rxfir; /* 0x4c */
231 u32 _reserved3[12]; /* 0x50 */
232 struct flexcan_mb cantxfg[64]; /* 0x80 */
234 u32 mecr; /* 0xae0 */
235 u32 erriar; /* 0xae4 */
236 u32 erridpr; /* 0xae8 */
237 u32 errippr; /* 0xaec */
238 u32 rerrar; /* 0xaf0 */
239 u32 rerrdr; /* 0xaf4 */
240 u32 rerrsynr; /* 0xaf8 */
241 u32 errsr; /* 0xafc */
244 struct flexcan_devtype_data {
245 u32 features; /* hardware controller features */
248 struct flexcan_priv {
250 struct napi_struct napi;
254 u32 reg_ctrl_default;
258 struct flexcan_platform_data *pdata;
259 const struct flexcan_devtype_data *devtype_data;
260 struct regulator *reg_xceiver;
263 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
264 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
266 static struct flexcan_devtype_data fsl_imx28_devtype_data;
267 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
268 .features = FLEXCAN_HAS_V10_FEATURES,
270 static struct flexcan_devtype_data fsl_vf610_devtype_data = {
271 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
274 static const struct can_bittiming_const flexcan_bittiming_const = {
287 * Abstract off the read/write for arm versus ppc. This
288 * assumes that PPC uses big-endian registers and everything
289 * else uses little-endian registers, independent of CPU
292 #if defined(CONFIG_PPC)
293 static inline u32 flexcan_read(void __iomem *addr)
295 return in_be32(addr);
298 static inline void flexcan_write(u32 val, void __iomem *addr)
303 static inline u32 flexcan_read(void __iomem *addr)
308 static inline void flexcan_write(u32 val, void __iomem *addr)
314 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
316 if (!priv->reg_xceiver)
319 return regulator_enable(priv->reg_xceiver);
322 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
324 if (!priv->reg_xceiver)
327 return regulator_disable(priv->reg_xceiver);
330 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
333 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
334 (reg_esr & FLEXCAN_ESR_ERR_BUS);
337 static int flexcan_chip_enable(struct flexcan_priv *priv)
339 struct flexcan_regs __iomem *regs = priv->base;
340 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
343 reg = flexcan_read(®s->mcr);
344 reg &= ~FLEXCAN_MCR_MDIS;
345 flexcan_write(reg, ®s->mcr);
347 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
350 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
356 static int flexcan_chip_disable(struct flexcan_priv *priv)
358 struct flexcan_regs __iomem *regs = priv->base;
359 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
362 reg = flexcan_read(®s->mcr);
363 reg |= FLEXCAN_MCR_MDIS;
364 flexcan_write(reg, ®s->mcr);
366 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
369 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
375 static int flexcan_chip_freeze(struct flexcan_priv *priv)
377 struct flexcan_regs __iomem *regs = priv->base;
378 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
381 reg = flexcan_read(®s->mcr);
382 reg |= FLEXCAN_MCR_HALT;
383 flexcan_write(reg, ®s->mcr);
385 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
388 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
394 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
396 struct flexcan_regs __iomem *regs = priv->base;
397 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
400 reg = flexcan_read(®s->mcr);
401 reg &= ~FLEXCAN_MCR_HALT;
402 flexcan_write(reg, ®s->mcr);
404 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
407 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
413 static int flexcan_chip_softreset(struct flexcan_priv *priv)
415 struct flexcan_regs __iomem *regs = priv->base;
416 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
418 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
419 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
422 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
429 static int __flexcan_get_berr_counter(const struct net_device *dev,
430 struct can_berr_counter *bec)
432 const struct flexcan_priv *priv = netdev_priv(dev);
433 struct flexcan_regs __iomem *regs = priv->base;
434 u32 reg = flexcan_read(®s->ecr);
436 bec->txerr = (reg >> 0) & 0xff;
437 bec->rxerr = (reg >> 8) & 0xff;
442 static int flexcan_get_berr_counter(const struct net_device *dev,
443 struct can_berr_counter *bec)
445 const struct flexcan_priv *priv = netdev_priv(dev);
448 err = clk_prepare_enable(priv->clk_ipg);
452 err = clk_prepare_enable(priv->clk_per);
454 goto out_disable_ipg;
456 err = __flexcan_get_berr_counter(dev, bec);
458 clk_disable_unprepare(priv->clk_per);
460 clk_disable_unprepare(priv->clk_ipg);
465 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
467 const struct flexcan_priv *priv = netdev_priv(dev);
468 struct flexcan_regs __iomem *regs = priv->base;
469 struct can_frame *cf = (struct can_frame *)skb->data;
471 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
473 if (can_dropped_invalid_skb(dev, skb))
476 netif_stop_queue(dev);
478 if (cf->can_id & CAN_EFF_FLAG) {
479 can_id = cf->can_id & CAN_EFF_MASK;
480 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
482 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
485 if (cf->can_id & CAN_RTR_FLAG)
486 ctrl |= FLEXCAN_MB_CNT_RTR;
488 if (cf->can_dlc > 0) {
489 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
490 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
492 if (cf->can_dlc > 3) {
493 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
494 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
497 can_put_echo_skb(skb, dev, 0);
499 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
500 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
502 /* Errata ERR005829 step8:
503 * Write twice INACTIVE(0x8) code to first MB.
505 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
506 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
507 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
508 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
513 static void do_bus_err(struct net_device *dev,
514 struct can_frame *cf, u32 reg_esr)
516 struct flexcan_priv *priv = netdev_priv(dev);
517 int rx_errors = 0, tx_errors = 0;
519 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
521 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
522 netdev_dbg(dev, "BIT1_ERR irq\n");
523 cf->data[2] |= CAN_ERR_PROT_BIT1;
526 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
527 netdev_dbg(dev, "BIT0_ERR irq\n");
528 cf->data[2] |= CAN_ERR_PROT_BIT0;
531 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
532 netdev_dbg(dev, "ACK_ERR irq\n");
533 cf->can_id |= CAN_ERR_ACK;
534 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
537 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
538 netdev_dbg(dev, "CRC_ERR irq\n");
539 cf->data[2] |= CAN_ERR_PROT_BIT;
540 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
543 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
544 netdev_dbg(dev, "FRM_ERR irq\n");
545 cf->data[2] |= CAN_ERR_PROT_FORM;
548 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
549 netdev_dbg(dev, "STF_ERR irq\n");
550 cf->data[2] |= CAN_ERR_PROT_STUFF;
554 priv->can.can_stats.bus_error++;
556 dev->stats.rx_errors++;
558 dev->stats.tx_errors++;
561 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
564 struct can_frame *cf;
566 skb = alloc_can_err_skb(dev, &cf);
570 do_bus_err(dev, cf, reg_esr);
571 netif_receive_skb(skb);
573 dev->stats.rx_packets++;
574 dev->stats.rx_bytes += cf->can_dlc;
579 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
581 struct flexcan_priv *priv = netdev_priv(dev);
583 struct can_frame *cf;
584 enum can_state new_state = 0, rx_state = 0, tx_state = 0;
586 struct can_berr_counter bec;
588 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
589 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
590 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
591 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
592 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
593 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
594 new_state = max(tx_state, rx_state);
596 __flexcan_get_berr_counter(dev, &bec);
597 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
598 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
599 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
600 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
603 /* state hasn't changed */
604 if (likely(new_state == priv->can.state))
607 skb = alloc_can_err_skb(dev, &cf);
611 can_change_state(dev, cf, tx_state, rx_state);
613 if (unlikely(new_state == CAN_STATE_BUS_OFF))
616 netif_receive_skb(skb);
618 dev->stats.rx_packets++;
619 dev->stats.rx_bytes += cf->can_dlc;
624 static void flexcan_read_fifo(const struct net_device *dev,
625 struct can_frame *cf)
627 const struct flexcan_priv *priv = netdev_priv(dev);
628 struct flexcan_regs __iomem *regs = priv->base;
629 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
630 u32 reg_ctrl, reg_id;
632 reg_ctrl = flexcan_read(&mb->can_ctrl);
633 reg_id = flexcan_read(&mb->can_id);
634 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
635 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
637 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
639 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
640 cf->can_id |= CAN_RTR_FLAG;
641 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
643 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
644 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
647 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
648 flexcan_read(®s->timer);
651 static int flexcan_read_frame(struct net_device *dev)
653 struct net_device_stats *stats = &dev->stats;
654 struct can_frame *cf;
657 skb = alloc_can_skb(dev, &cf);
658 if (unlikely(!skb)) {
663 flexcan_read_fifo(dev, cf);
664 netif_receive_skb(skb);
667 stats->rx_bytes += cf->can_dlc;
669 can_led_event(dev, CAN_LED_EVENT_RX);
674 static int flexcan_poll(struct napi_struct *napi, int quota)
676 struct net_device *dev = napi->dev;
677 const struct flexcan_priv *priv = netdev_priv(dev);
678 struct flexcan_regs __iomem *regs = priv->base;
679 u32 reg_iflag1, reg_esr;
683 * The error bits are cleared on read,
684 * use saved value from irq handler.
686 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
688 /* handle state changes */
689 work_done += flexcan_poll_state(dev, reg_esr);
692 reg_iflag1 = flexcan_read(®s->iflag1);
693 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
695 work_done += flexcan_read_frame(dev);
696 reg_iflag1 = flexcan_read(®s->iflag1);
699 /* report bus errors */
700 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
701 work_done += flexcan_poll_bus_err(dev, reg_esr);
703 if (work_done < quota) {
706 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
707 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
713 static irqreturn_t flexcan_irq(int irq, void *dev_id)
715 struct net_device *dev = dev_id;
716 struct net_device_stats *stats = &dev->stats;
717 struct flexcan_priv *priv = netdev_priv(dev);
718 struct flexcan_regs __iomem *regs = priv->base;
719 u32 reg_iflag1, reg_esr;
721 reg_iflag1 = flexcan_read(®s->iflag1);
722 reg_esr = flexcan_read(®s->esr);
723 /* ACK all bus error and state change IRQ sources */
724 if (reg_esr & FLEXCAN_ESR_ALL_INT)
725 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
728 * schedule NAPI in case of:
731 * - bus error IRQ and bus error reporting is activated
733 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
734 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
735 flexcan_has_and_handle_berr(priv, reg_esr)) {
737 * The error bits are cleared on read,
738 * save them for later use.
740 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
741 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
742 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
743 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
745 napi_schedule(&priv->napi);
749 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
750 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
751 dev->stats.rx_over_errors++;
752 dev->stats.rx_errors++;
755 /* transmission complete interrupt */
756 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
757 stats->tx_bytes += can_get_echo_skb(dev, 0);
759 can_led_event(dev, CAN_LED_EVENT_TX);
760 /* after sending a RTR frame mailbox is in RX mode */
761 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
762 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
763 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
764 netif_wake_queue(dev);
770 static void flexcan_set_bittiming(struct net_device *dev)
772 const struct flexcan_priv *priv = netdev_priv(dev);
773 const struct can_bittiming *bt = &priv->can.bittiming;
774 struct flexcan_regs __iomem *regs = priv->base;
777 reg = flexcan_read(®s->ctrl);
778 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
779 FLEXCAN_CTRL_RJW(0x3) |
780 FLEXCAN_CTRL_PSEG1(0x7) |
781 FLEXCAN_CTRL_PSEG2(0x7) |
782 FLEXCAN_CTRL_PROPSEG(0x7) |
787 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
788 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
789 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
790 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
791 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
793 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
794 reg |= FLEXCAN_CTRL_LPB;
795 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
796 reg |= FLEXCAN_CTRL_LOM;
797 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
798 reg |= FLEXCAN_CTRL_SMP;
800 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
801 flexcan_write(reg, ®s->ctrl);
803 /* print chip status */
804 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
805 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
811 * this functions is entered with clocks enabled
814 static int flexcan_chip_start(struct net_device *dev)
816 struct flexcan_priv *priv = netdev_priv(dev);
817 struct flexcan_regs __iomem *regs = priv->base;
818 u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr;
822 err = flexcan_chip_enable(priv);
827 err = flexcan_chip_softreset(priv);
829 goto out_chip_disable;
831 flexcan_set_bittiming(dev);
839 * only supervisor access
845 reg_mcr = flexcan_read(®s->mcr);
846 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
847 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
848 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
849 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
850 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
851 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
852 flexcan_write(reg_mcr, ®s->mcr);
857 * disable timer sync feature
859 * disable auto busoff recovery
860 * transmit lowest buffer first
862 * enable tx and rx warning interrupt
863 * enable bus off interrupt
864 * (== FLEXCAN_CTRL_ERR_STATE)
866 reg_ctrl = flexcan_read(®s->ctrl);
867 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
868 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
869 FLEXCAN_CTRL_ERR_STATE;
871 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
872 * on most Flexcan cores, too. Otherwise we don't get
873 * any error warning or passive interrupts.
875 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
876 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
877 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
879 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
881 /* save for later use */
882 priv->reg_ctrl_default = reg_ctrl;
883 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
884 flexcan_write(reg_ctrl, ®s->ctrl);
886 /* clear and invalidate all mailboxes first */
887 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
888 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
889 ®s->cantxfg[i].can_ctrl);
892 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
893 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
894 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
896 /* mark TX mailbox as INACTIVE */
897 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
898 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
900 /* acceptance mask/acceptance code (accept everything) */
901 flexcan_write(0x0, ®s->rxgmask);
902 flexcan_write(0x0, ®s->rx14mask);
903 flexcan_write(0x0, ®s->rx15mask);
905 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
906 flexcan_write(0x0, ®s->rxfgmask);
909 * On Vybrid, disable memory error detection interrupts
911 * This also works around errata e5295 which generates
912 * false positive memory errors and put the device in
915 if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) {
917 * Follow the protocol as described in "Detection
918 * and Correction of Memory Errors" to write to
921 reg_crl2 = flexcan_read(®s->crl2);
922 reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
923 flexcan_write(reg_crl2, ®s->crl2);
925 reg_mecr = flexcan_read(®s->mecr);
926 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
927 flexcan_write(reg_mecr, ®s->mecr);
928 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
929 FLEXCAN_MECR_FANCEI_MSK);
930 flexcan_write(reg_mecr, ®s->mecr);
933 err = flexcan_transceiver_enable(priv);
935 goto out_chip_disable;
937 /* synchronize with the can bus */
938 err = flexcan_chip_unfreeze(priv);
940 goto out_transceiver_disable;
942 priv->can.state = CAN_STATE_ERROR_ACTIVE;
944 /* enable FIFO interrupts */
945 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
947 /* print chip status */
948 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
949 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
953 out_transceiver_disable:
954 flexcan_transceiver_disable(priv);
956 flexcan_chip_disable(priv);
963 * this functions is entered with clocks enabled
966 static void flexcan_chip_stop(struct net_device *dev)
968 struct flexcan_priv *priv = netdev_priv(dev);
969 struct flexcan_regs __iomem *regs = priv->base;
971 /* freeze + disable module */
972 flexcan_chip_freeze(priv);
973 flexcan_chip_disable(priv);
975 /* Disable all interrupts */
976 flexcan_write(0, ®s->imask1);
977 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
980 flexcan_transceiver_disable(priv);
981 priv->can.state = CAN_STATE_STOPPED;
986 static int flexcan_open(struct net_device *dev)
988 struct flexcan_priv *priv = netdev_priv(dev);
991 err = clk_prepare_enable(priv->clk_ipg);
995 err = clk_prepare_enable(priv->clk_per);
997 goto out_disable_ipg;
999 err = open_candev(dev);
1001 goto out_disable_per;
1003 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1007 /* start chip and queuing */
1008 err = flexcan_chip_start(dev);
1012 can_led_event(dev, CAN_LED_EVENT_OPEN);
1014 napi_enable(&priv->napi);
1015 netif_start_queue(dev);
1020 free_irq(dev->irq, dev);
1024 clk_disable_unprepare(priv->clk_per);
1026 clk_disable_unprepare(priv->clk_ipg);
1031 static int flexcan_close(struct net_device *dev)
1033 struct flexcan_priv *priv = netdev_priv(dev);
1035 netif_stop_queue(dev);
1036 napi_disable(&priv->napi);
1037 flexcan_chip_stop(dev);
1039 free_irq(dev->irq, dev);
1040 clk_disable_unprepare(priv->clk_per);
1041 clk_disable_unprepare(priv->clk_ipg);
1045 can_led_event(dev, CAN_LED_EVENT_STOP);
1050 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1055 case CAN_MODE_START:
1056 err = flexcan_chip_start(dev);
1060 netif_wake_queue(dev);
1070 static const struct net_device_ops flexcan_netdev_ops = {
1071 .ndo_open = flexcan_open,
1072 .ndo_stop = flexcan_close,
1073 .ndo_start_xmit = flexcan_start_xmit,
1074 .ndo_change_mtu = can_change_mtu,
1077 static int register_flexcandev(struct net_device *dev)
1079 struct flexcan_priv *priv = netdev_priv(dev);
1080 struct flexcan_regs __iomem *regs = priv->base;
1083 err = clk_prepare_enable(priv->clk_ipg);
1087 err = clk_prepare_enable(priv->clk_per);
1089 goto out_disable_ipg;
1091 /* select "bus clock", chip must be disabled */
1092 err = flexcan_chip_disable(priv);
1094 goto out_disable_per;
1095 reg = flexcan_read(®s->ctrl);
1096 reg |= FLEXCAN_CTRL_CLK_SRC;
1097 flexcan_write(reg, ®s->ctrl);
1099 err = flexcan_chip_enable(priv);
1101 goto out_chip_disable;
1103 /* set freeze, halt and activate FIFO, restrict register access */
1104 reg = flexcan_read(®s->mcr);
1105 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1106 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1107 flexcan_write(reg, ®s->mcr);
1110 * Currently we only support newer versions of this core
1111 * featuring a RX FIFO. Older cores found on some Coldfire
1112 * derivates are not yet supported.
1114 reg = flexcan_read(®s->mcr);
1115 if (!(reg & FLEXCAN_MCR_FEN)) {
1116 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1118 goto out_chip_disable;
1121 err = register_candev(dev);
1123 /* disable core and turn off clocks */
1125 flexcan_chip_disable(priv);
1127 clk_disable_unprepare(priv->clk_per);
1129 clk_disable_unprepare(priv->clk_ipg);
1134 static void unregister_flexcandev(struct net_device *dev)
1136 unregister_candev(dev);
1139 static const struct of_device_id flexcan_of_match[] = {
1140 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1141 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1142 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1143 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1146 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1148 static const struct platform_device_id flexcan_id_table[] = {
1149 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1152 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1154 static int flexcan_probe(struct platform_device *pdev)
1156 const struct of_device_id *of_id;
1157 const struct flexcan_devtype_data *devtype_data;
1158 struct net_device *dev;
1159 struct flexcan_priv *priv;
1160 struct resource *mem;
1161 struct clk *clk_ipg = NULL, *clk_per = NULL;
1166 if (pdev->dev.of_node)
1167 of_property_read_u32(pdev->dev.of_node,
1168 "clock-frequency", &clock_freq);
1171 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1172 if (IS_ERR(clk_ipg)) {
1173 dev_err(&pdev->dev, "no ipg clock defined\n");
1174 return PTR_ERR(clk_ipg);
1177 clk_per = devm_clk_get(&pdev->dev, "per");
1178 if (IS_ERR(clk_per)) {
1179 dev_err(&pdev->dev, "no per clock defined\n");
1180 return PTR_ERR(clk_per);
1182 clock_freq = clk_get_rate(clk_per);
1185 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186 irq = platform_get_irq(pdev, 0);
1190 base = devm_ioremap_resource(&pdev->dev, mem);
1192 return PTR_ERR(base);
1194 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1196 devtype_data = of_id->data;
1197 } else if (platform_get_device_id(pdev)->driver_data) {
1198 devtype_data = (struct flexcan_devtype_data *)
1199 platform_get_device_id(pdev)->driver_data;
1204 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1208 dev->netdev_ops = &flexcan_netdev_ops;
1210 dev->flags |= IFF_ECHO;
1212 priv = netdev_priv(dev);
1213 priv->can.clock.freq = clock_freq;
1214 priv->can.bittiming_const = &flexcan_bittiming_const;
1215 priv->can.do_set_mode = flexcan_set_mode;
1216 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1217 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1218 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1219 CAN_CTRLMODE_BERR_REPORTING;
1221 priv->clk_ipg = clk_ipg;
1222 priv->clk_per = clk_per;
1223 priv->pdata = dev_get_platdata(&pdev->dev);
1224 priv->devtype_data = devtype_data;
1226 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1227 if (IS_ERR(priv->reg_xceiver))
1228 priv->reg_xceiver = NULL;
1230 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1232 platform_set_drvdata(pdev, dev);
1233 SET_NETDEV_DEV(dev, &pdev->dev);
1235 err = register_flexcandev(dev);
1237 dev_err(&pdev->dev, "registering netdev failed\n");
1238 goto failed_register;
1241 devm_can_led_init(dev);
1243 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1244 priv->base, dev->irq);
1253 static int flexcan_remove(struct platform_device *pdev)
1255 struct net_device *dev = platform_get_drvdata(pdev);
1256 struct flexcan_priv *priv = netdev_priv(dev);
1258 unregister_flexcandev(dev);
1259 netif_napi_del(&priv->napi);
1265 static int __maybe_unused flexcan_suspend(struct device *device)
1267 struct net_device *dev = dev_get_drvdata(device);
1268 struct flexcan_priv *priv = netdev_priv(dev);
1271 err = flexcan_chip_disable(priv);
1275 if (netif_running(dev)) {
1276 netif_stop_queue(dev);
1277 netif_device_detach(dev);
1279 priv->can.state = CAN_STATE_SLEEPING;
1284 static int __maybe_unused flexcan_resume(struct device *device)
1286 struct net_device *dev = dev_get_drvdata(device);
1287 struct flexcan_priv *priv = netdev_priv(dev);
1289 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1290 if (netif_running(dev)) {
1291 netif_device_attach(dev);
1292 netif_start_queue(dev);
1294 return flexcan_chip_enable(priv);
1297 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1299 static struct platform_driver flexcan_driver = {
1302 .pm = &flexcan_pm_ops,
1303 .of_match_table = flexcan_of_match,
1305 .probe = flexcan_probe,
1306 .remove = flexcan_remove,
1307 .id_table = flexcan_id_table,
1310 module_platform_driver(flexcan_driver);
1312 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1313 "Marc Kleine-Budde <kernel@pengutronix.de>");
1314 MODULE_LICENSE("GPL v2");
1315 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");