2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
41 #define DRV_NAME "flexcan"
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95 /* FLEXCAN control register 2 (CTRL2) bits */
96 #define FLEXCAN_CRL2_ECRWRE BIT(29)
97 #define FLEXCAN_CRL2_WRMFRZ BIT(28)
98 #define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24)
99 #define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19)
100 #define FLEXCAN_CRL2_MRP BIT(18)
101 #define FLEXCAN_CRL2_RRS BIT(17)
102 #define FLEXCAN_CRL2_EACEN BIT(16)
104 /* FLEXCAN memory error control register (MECR) bits */
105 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
106 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
107 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
108 #define FLEXCAN_MECR_CEI_MSK BIT(16)
109 #define FLEXCAN_MECR_HAERRIE BIT(15)
110 #define FLEXCAN_MECR_FAERRIE BIT(14)
111 #define FLEXCAN_MECR_EXTERRIE BIT(13)
112 #define FLEXCAN_MECR_RERRDIS BIT(9)
113 #define FLEXCAN_MECR_ECCDIS BIT(8)
114 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
116 /* FLEXCAN error and status register (ESR) bits */
117 #define FLEXCAN_ESR_TWRN_INT BIT(17)
118 #define FLEXCAN_ESR_RWRN_INT BIT(16)
119 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
120 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
121 #define FLEXCAN_ESR_ACK_ERR BIT(13)
122 #define FLEXCAN_ESR_CRC_ERR BIT(12)
123 #define FLEXCAN_ESR_FRM_ERR BIT(11)
124 #define FLEXCAN_ESR_STF_ERR BIT(10)
125 #define FLEXCAN_ESR_TX_WRN BIT(9)
126 #define FLEXCAN_ESR_RX_WRN BIT(8)
127 #define FLEXCAN_ESR_IDLE BIT(7)
128 #define FLEXCAN_ESR_TXRX BIT(6)
129 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
130 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
133 #define FLEXCAN_ESR_BOFF_INT BIT(2)
134 #define FLEXCAN_ESR_ERR_INT BIT(1)
135 #define FLEXCAN_ESR_WAK_INT BIT(0)
136 #define FLEXCAN_ESR_ERR_BUS \
137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
140 #define FLEXCAN_ESR_ERR_STATE \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
142 #define FLEXCAN_ESR_ERR_ALL \
143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
144 #define FLEXCAN_ESR_ALL_INT \
145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
148 /* FLEXCAN interrupt flag register (IFLAG) bits */
149 /* Errata ERR005829 step7: Reserve first valid MB */
150 #define FLEXCAN_TX_BUF_RESERVED 8
151 #define FLEXCAN_TX_BUF_ID 9
152 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
153 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
154 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
155 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
156 #define FLEXCAN_IFLAG_DEFAULT \
157 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
158 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
162 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
163 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
164 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
165 #define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24)
166 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
168 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
169 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
170 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
171 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
173 #define FLEXCAN_MB_CNT_SRR BIT(22)
174 #define FLEXCAN_MB_CNT_IDE BIT(21)
175 #define FLEXCAN_MB_CNT_RTR BIT(20)
176 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
177 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
179 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
181 #define FLEXCAN_TIMEOUT_US (50)
184 * FLEXCAN hardware feature flags
186 * Below is some version info we got:
187 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err
188 * Filter? connected? detection
189 * MX25 FlexCAN2 03.00.00.00 no no no
190 * MX28 FlexCAN2 03.00.04.00 yes yes no
191 * MX35 FlexCAN2 03.00.00.00 no no no
192 * MX53 FlexCAN2 03.00.00.00 yes no no
193 * MX6s FlexCAN3 10.00.12.00 yes yes no
194 * VF610 FlexCAN3 ? no yes yes
196 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
198 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
199 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
200 #define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
202 /* Structure of the message buffer */
209 /* Structure of the hardware registers */
210 struct flexcan_regs {
213 u32 timer; /* 0x08 */
214 u32 _reserved1; /* 0x0c */
215 u32 rxgmask; /* 0x10 */
216 u32 rx14mask; /* 0x14 */
217 u32 rx15mask; /* 0x18 */
220 u32 imask2; /* 0x24 */
221 u32 imask1; /* 0x28 */
222 u32 iflag2; /* 0x2c */
223 u32 iflag1; /* 0x30 */
226 u32 imeur; /* 0x3c */
229 u32 rxfgmask; /* 0x48 */
230 u32 rxfir; /* 0x4c */
231 u32 _reserved3[12]; /* 0x50 */
232 struct flexcan_mb cantxfg[64]; /* 0x80 */
234 u32 mecr; /* 0xae0 */
235 u32 erriar; /* 0xae4 */
236 u32 erridpr; /* 0xae8 */
237 u32 errippr; /* 0xaec */
238 u32 rerrar; /* 0xaf0 */
239 u32 rerrdr; /* 0xaf4 */
240 u32 rerrsynr; /* 0xaf8 */
241 u32 errsr; /* 0xafc */
244 struct flexcan_devtype_data {
245 u32 features; /* hardware controller features */
248 struct flexcan_priv {
250 struct net_device *dev;
251 struct napi_struct napi;
255 u32 reg_ctrl_default;
259 struct flexcan_platform_data *pdata;
260 const struct flexcan_devtype_data *devtype_data;
261 struct regulator *reg_xceiver;
264 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
265 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
267 static struct flexcan_devtype_data fsl_imx28_devtype_data;
268 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
269 .features = FLEXCAN_HAS_V10_FEATURES,
271 static struct flexcan_devtype_data fsl_vf610_devtype_data = {
272 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
275 static const struct can_bittiming_const flexcan_bittiming_const = {
288 * Abstract off the read/write for arm versus ppc. This
289 * assumes that PPC uses big-endian registers and everything
290 * else uses little-endian registers, independent of CPU
293 #if defined(CONFIG_PPC)
294 static inline u32 flexcan_read(void __iomem *addr)
296 return in_be32(addr);
299 static inline void flexcan_write(u32 val, void __iomem *addr)
304 static inline u32 flexcan_read(void __iomem *addr)
309 static inline void flexcan_write(u32 val, void __iomem *addr)
315 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
317 if (!priv->reg_xceiver)
320 return regulator_enable(priv->reg_xceiver);
323 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
325 if (!priv->reg_xceiver)
328 return regulator_disable(priv->reg_xceiver);
331 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
334 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
335 (reg_esr & FLEXCAN_ESR_ERR_BUS);
338 static int flexcan_chip_enable(struct flexcan_priv *priv)
340 struct flexcan_regs __iomem *regs = priv->base;
341 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
344 reg = flexcan_read(®s->mcr);
345 reg &= ~FLEXCAN_MCR_MDIS;
346 flexcan_write(reg, ®s->mcr);
348 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
351 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
357 static int flexcan_chip_disable(struct flexcan_priv *priv)
359 struct flexcan_regs __iomem *regs = priv->base;
360 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
363 reg = flexcan_read(®s->mcr);
364 reg |= FLEXCAN_MCR_MDIS;
365 flexcan_write(reg, ®s->mcr);
367 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
370 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
376 static int flexcan_chip_freeze(struct flexcan_priv *priv)
378 struct flexcan_regs __iomem *regs = priv->base;
379 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
382 reg = flexcan_read(®s->mcr);
383 reg |= FLEXCAN_MCR_HALT;
384 flexcan_write(reg, ®s->mcr);
386 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
389 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
395 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
397 struct flexcan_regs __iomem *regs = priv->base;
398 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
401 reg = flexcan_read(®s->mcr);
402 reg &= ~FLEXCAN_MCR_HALT;
403 flexcan_write(reg, ®s->mcr);
405 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
408 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
414 static int flexcan_chip_softreset(struct flexcan_priv *priv)
416 struct flexcan_regs __iomem *regs = priv->base;
417 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
419 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
420 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
423 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
430 static int __flexcan_get_berr_counter(const struct net_device *dev,
431 struct can_berr_counter *bec)
433 const struct flexcan_priv *priv = netdev_priv(dev);
434 struct flexcan_regs __iomem *regs = priv->base;
435 u32 reg = flexcan_read(®s->ecr);
437 bec->txerr = (reg >> 0) & 0xff;
438 bec->rxerr = (reg >> 8) & 0xff;
443 static int flexcan_get_berr_counter(const struct net_device *dev,
444 struct can_berr_counter *bec)
446 const struct flexcan_priv *priv = netdev_priv(dev);
449 err = clk_prepare_enable(priv->clk_ipg);
453 err = clk_prepare_enable(priv->clk_per);
455 goto out_disable_ipg;
457 err = __flexcan_get_berr_counter(dev, bec);
459 clk_disable_unprepare(priv->clk_per);
461 clk_disable_unprepare(priv->clk_ipg);
466 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
468 const struct flexcan_priv *priv = netdev_priv(dev);
469 struct flexcan_regs __iomem *regs = priv->base;
470 struct can_frame *cf = (struct can_frame *)skb->data;
472 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
474 if (can_dropped_invalid_skb(dev, skb))
477 netif_stop_queue(dev);
479 if (cf->can_id & CAN_EFF_FLAG) {
480 can_id = cf->can_id & CAN_EFF_MASK;
481 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
483 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
486 if (cf->can_id & CAN_RTR_FLAG)
487 ctrl |= FLEXCAN_MB_CNT_RTR;
489 if (cf->can_dlc > 0) {
490 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
491 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
493 if (cf->can_dlc > 3) {
494 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
495 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
498 can_put_echo_skb(skb, dev, 0);
500 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
501 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
503 /* Errata ERR005829 step8:
504 * Write twice INACTIVE(0x8) code to first MB.
506 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
507 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
508 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
509 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
514 static void do_bus_err(struct net_device *dev,
515 struct can_frame *cf, u32 reg_esr)
517 struct flexcan_priv *priv = netdev_priv(dev);
518 int rx_errors = 0, tx_errors = 0;
520 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
522 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
523 netdev_dbg(dev, "BIT1_ERR irq\n");
524 cf->data[2] |= CAN_ERR_PROT_BIT1;
527 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
528 netdev_dbg(dev, "BIT0_ERR irq\n");
529 cf->data[2] |= CAN_ERR_PROT_BIT0;
532 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
533 netdev_dbg(dev, "ACK_ERR irq\n");
534 cf->can_id |= CAN_ERR_ACK;
535 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
538 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
539 netdev_dbg(dev, "CRC_ERR irq\n");
540 cf->data[2] |= CAN_ERR_PROT_BIT;
541 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
544 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
545 netdev_dbg(dev, "FRM_ERR irq\n");
546 cf->data[2] |= CAN_ERR_PROT_FORM;
549 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
550 netdev_dbg(dev, "STF_ERR irq\n");
551 cf->data[2] |= CAN_ERR_PROT_STUFF;
555 priv->can.can_stats.bus_error++;
557 dev->stats.rx_errors++;
559 dev->stats.tx_errors++;
562 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
565 struct can_frame *cf;
567 skb = alloc_can_err_skb(dev, &cf);
571 do_bus_err(dev, cf, reg_esr);
572 netif_receive_skb(skb);
574 dev->stats.rx_packets++;
575 dev->stats.rx_bytes += cf->can_dlc;
580 static void do_state(struct net_device *dev,
581 struct can_frame *cf, enum can_state new_state)
583 struct flexcan_priv *priv = netdev_priv(dev);
584 struct can_berr_counter bec;
586 __flexcan_get_berr_counter(dev, &bec);
588 switch (priv->can.state) {
589 case CAN_STATE_ERROR_ACTIVE:
592 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
593 * => : there was a warning int
595 if (new_state >= CAN_STATE_ERROR_WARNING &&
596 new_state <= CAN_STATE_BUS_OFF) {
597 netdev_dbg(dev, "Error Warning IRQ\n");
598 priv->can.can_stats.error_warning++;
600 cf->can_id |= CAN_ERR_CRTL;
601 cf->data[1] = (bec.txerr > bec.rxerr) ?
602 CAN_ERR_CRTL_TX_WARNING :
603 CAN_ERR_CRTL_RX_WARNING;
605 case CAN_STATE_ERROR_WARNING: /* fallthrough */
607 * from: ERROR_ACTIVE, ERROR_WARNING
608 * to : ERROR_PASSIVE, BUS_OFF
609 * => : error passive int
611 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
612 new_state <= CAN_STATE_BUS_OFF) {
613 netdev_dbg(dev, "Error Passive IRQ\n");
614 priv->can.can_stats.error_passive++;
616 cf->can_id |= CAN_ERR_CRTL;
617 cf->data[1] = (bec.txerr > bec.rxerr) ?
618 CAN_ERR_CRTL_TX_PASSIVE :
619 CAN_ERR_CRTL_RX_PASSIVE;
622 case CAN_STATE_BUS_OFF:
623 netdev_err(dev, "BUG! "
624 "hardware recovered automatically from BUS_OFF\n");
630 /* process state changes depending on the new state */
632 case CAN_STATE_ERROR_WARNING:
633 netdev_dbg(dev, "Error Warning\n");
634 cf->can_id |= CAN_ERR_CRTL;
635 cf->data[1] = (bec.txerr > bec.rxerr) ?
636 CAN_ERR_CRTL_TX_WARNING :
637 CAN_ERR_CRTL_RX_WARNING;
639 case CAN_STATE_ERROR_ACTIVE:
640 netdev_dbg(dev, "Error Active\n");
641 cf->can_id |= CAN_ERR_PROT;
642 cf->data[2] = CAN_ERR_PROT_ACTIVE;
644 case CAN_STATE_BUS_OFF:
645 cf->can_id |= CAN_ERR_BUSOFF;
653 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
655 struct flexcan_priv *priv = netdev_priv(dev);
657 struct can_frame *cf;
658 enum can_state new_state;
661 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
662 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
663 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
664 FLEXCAN_ESR_RX_WRN))))
665 new_state = CAN_STATE_ERROR_ACTIVE;
667 new_state = CAN_STATE_ERROR_WARNING;
668 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
669 new_state = CAN_STATE_ERROR_PASSIVE;
671 new_state = CAN_STATE_BUS_OFF;
673 /* state hasn't changed */
674 if (likely(new_state == priv->can.state))
677 skb = alloc_can_err_skb(dev, &cf);
681 do_state(dev, cf, new_state);
682 priv->can.state = new_state;
683 netif_receive_skb(skb);
685 dev->stats.rx_packets++;
686 dev->stats.rx_bytes += cf->can_dlc;
691 static void flexcan_read_fifo(const struct net_device *dev,
692 struct can_frame *cf)
694 const struct flexcan_priv *priv = netdev_priv(dev);
695 struct flexcan_regs __iomem *regs = priv->base;
696 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
697 u32 reg_ctrl, reg_id;
699 reg_ctrl = flexcan_read(&mb->can_ctrl);
700 reg_id = flexcan_read(&mb->can_id);
701 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
702 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
704 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
706 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
707 cf->can_id |= CAN_RTR_FLAG;
708 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
710 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
711 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
714 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
715 flexcan_read(®s->timer);
718 static int flexcan_read_frame(struct net_device *dev)
720 struct net_device_stats *stats = &dev->stats;
721 struct can_frame *cf;
724 skb = alloc_can_skb(dev, &cf);
725 if (unlikely(!skb)) {
730 flexcan_read_fifo(dev, cf);
731 netif_receive_skb(skb);
734 stats->rx_bytes += cf->can_dlc;
736 can_led_event(dev, CAN_LED_EVENT_RX);
741 static int flexcan_poll(struct napi_struct *napi, int quota)
743 struct net_device *dev = napi->dev;
744 const struct flexcan_priv *priv = netdev_priv(dev);
745 struct flexcan_regs __iomem *regs = priv->base;
746 u32 reg_iflag1, reg_esr;
750 * The error bits are cleared on read,
751 * use saved value from irq handler.
753 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
755 /* handle state changes */
756 work_done += flexcan_poll_state(dev, reg_esr);
759 reg_iflag1 = flexcan_read(®s->iflag1);
760 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
762 work_done += flexcan_read_frame(dev);
763 reg_iflag1 = flexcan_read(®s->iflag1);
766 /* report bus errors */
767 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
768 work_done += flexcan_poll_bus_err(dev, reg_esr);
770 if (work_done < quota) {
773 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
774 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
780 static irqreturn_t flexcan_irq(int irq, void *dev_id)
782 struct net_device *dev = dev_id;
783 struct net_device_stats *stats = &dev->stats;
784 struct flexcan_priv *priv = netdev_priv(dev);
785 struct flexcan_regs __iomem *regs = priv->base;
786 u32 reg_iflag1, reg_esr;
788 reg_iflag1 = flexcan_read(®s->iflag1);
789 reg_esr = flexcan_read(®s->esr);
790 /* ACK all bus error and state change IRQ sources */
791 if (reg_esr & FLEXCAN_ESR_ALL_INT)
792 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
795 * schedule NAPI in case of:
798 * - bus error IRQ and bus error reporting is activated
800 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
801 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
802 flexcan_has_and_handle_berr(priv, reg_esr)) {
804 * The error bits are cleared on read,
805 * save them for later use.
807 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
808 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
809 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
810 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
812 napi_schedule(&priv->napi);
816 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
817 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
818 dev->stats.rx_over_errors++;
819 dev->stats.rx_errors++;
822 /* transmission complete interrupt */
823 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
824 stats->tx_bytes += can_get_echo_skb(dev, 0);
826 can_led_event(dev, CAN_LED_EVENT_TX);
827 /* after sending a RTR frame mailbox is in RX mode */
828 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
829 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
830 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
831 netif_wake_queue(dev);
837 static void flexcan_set_bittiming(struct net_device *dev)
839 const struct flexcan_priv *priv = netdev_priv(dev);
840 const struct can_bittiming *bt = &priv->can.bittiming;
841 struct flexcan_regs __iomem *regs = priv->base;
844 reg = flexcan_read(®s->ctrl);
845 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
846 FLEXCAN_CTRL_RJW(0x3) |
847 FLEXCAN_CTRL_PSEG1(0x7) |
848 FLEXCAN_CTRL_PSEG2(0x7) |
849 FLEXCAN_CTRL_PROPSEG(0x7) |
854 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
855 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
856 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
857 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
858 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
860 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
861 reg |= FLEXCAN_CTRL_LPB;
862 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
863 reg |= FLEXCAN_CTRL_LOM;
864 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
865 reg |= FLEXCAN_CTRL_SMP;
867 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
868 flexcan_write(reg, ®s->ctrl);
870 /* print chip status */
871 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
872 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
878 * this functions is entered with clocks enabled
881 static int flexcan_chip_start(struct net_device *dev)
883 struct flexcan_priv *priv = netdev_priv(dev);
884 struct flexcan_regs __iomem *regs = priv->base;
885 u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr;
889 err = flexcan_chip_enable(priv);
894 err = flexcan_chip_softreset(priv);
896 goto out_chip_disable;
898 flexcan_set_bittiming(dev);
906 * only supervisor access
912 reg_mcr = flexcan_read(®s->mcr);
913 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
914 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
915 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
916 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
917 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
918 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
919 flexcan_write(reg_mcr, ®s->mcr);
924 * disable timer sync feature
926 * disable auto busoff recovery
927 * transmit lowest buffer first
929 * enable tx and rx warning interrupt
930 * enable bus off interrupt
931 * (== FLEXCAN_CTRL_ERR_STATE)
933 reg_ctrl = flexcan_read(®s->ctrl);
934 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
935 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
936 FLEXCAN_CTRL_ERR_STATE;
938 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
939 * on most Flexcan cores, too. Otherwise we don't get
940 * any error warning or passive interrupts.
942 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
943 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
944 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
946 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
948 /* save for later use */
949 priv->reg_ctrl_default = reg_ctrl;
950 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
951 flexcan_write(reg_ctrl, ®s->ctrl);
953 /* clear and invalidate all mailboxes first */
954 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
955 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
956 ®s->cantxfg[i].can_ctrl);
959 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
960 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
961 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
963 /* mark TX mailbox as INACTIVE */
964 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
965 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
967 /* acceptance mask/acceptance code (accept everything) */
968 flexcan_write(0x0, ®s->rxgmask);
969 flexcan_write(0x0, ®s->rx14mask);
970 flexcan_write(0x0, ®s->rx15mask);
972 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
973 flexcan_write(0x0, ®s->rxfgmask);
976 * On Vybrid, disable memory error detection interrupts
978 * This also works around errata e5295 which generates
979 * false positive memory errors and put the device in
982 if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) {
984 * Follow the protocol as described in "Detection
985 * and Correction of Memory Errors" to write to
988 reg_crl2 = flexcan_read(®s->crl2);
989 reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
990 flexcan_write(reg_crl2, ®s->crl2);
992 reg_mecr = flexcan_read(®s->mecr);
993 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
994 flexcan_write(reg_mecr, ®s->mecr);
995 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
996 FLEXCAN_MECR_FANCEI_MSK);
997 flexcan_write(reg_mecr, ®s->mecr);
1000 err = flexcan_transceiver_enable(priv);
1002 goto out_chip_disable;
1004 /* synchronize with the can bus */
1005 err = flexcan_chip_unfreeze(priv);
1007 goto out_transceiver_disable;
1009 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1011 /* enable FIFO interrupts */
1012 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
1014 /* print chip status */
1015 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1016 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
1020 out_transceiver_disable:
1021 flexcan_transceiver_disable(priv);
1023 flexcan_chip_disable(priv);
1030 * this functions is entered with clocks enabled
1033 static void flexcan_chip_stop(struct net_device *dev)
1035 struct flexcan_priv *priv = netdev_priv(dev);
1036 struct flexcan_regs __iomem *regs = priv->base;
1038 /* freeze + disable module */
1039 flexcan_chip_freeze(priv);
1040 flexcan_chip_disable(priv);
1042 /* Disable all interrupts */
1043 flexcan_write(0, ®s->imask1);
1044 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1047 flexcan_transceiver_disable(priv);
1048 priv->can.state = CAN_STATE_STOPPED;
1053 static int flexcan_open(struct net_device *dev)
1055 struct flexcan_priv *priv = netdev_priv(dev);
1058 err = clk_prepare_enable(priv->clk_ipg);
1062 err = clk_prepare_enable(priv->clk_per);
1064 goto out_disable_ipg;
1066 err = open_candev(dev);
1068 goto out_disable_per;
1070 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1074 /* start chip and queuing */
1075 err = flexcan_chip_start(dev);
1079 can_led_event(dev, CAN_LED_EVENT_OPEN);
1081 napi_enable(&priv->napi);
1082 netif_start_queue(dev);
1087 free_irq(dev->irq, dev);
1091 clk_disable_unprepare(priv->clk_per);
1093 clk_disable_unprepare(priv->clk_ipg);
1098 static int flexcan_close(struct net_device *dev)
1100 struct flexcan_priv *priv = netdev_priv(dev);
1102 netif_stop_queue(dev);
1103 napi_disable(&priv->napi);
1104 flexcan_chip_stop(dev);
1106 free_irq(dev->irq, dev);
1107 clk_disable_unprepare(priv->clk_per);
1108 clk_disable_unprepare(priv->clk_ipg);
1112 can_led_event(dev, CAN_LED_EVENT_STOP);
1117 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1122 case CAN_MODE_START:
1123 err = flexcan_chip_start(dev);
1127 netif_wake_queue(dev);
1137 static const struct net_device_ops flexcan_netdev_ops = {
1138 .ndo_open = flexcan_open,
1139 .ndo_stop = flexcan_close,
1140 .ndo_start_xmit = flexcan_start_xmit,
1141 .ndo_change_mtu = can_change_mtu,
1144 static int register_flexcandev(struct net_device *dev)
1146 struct flexcan_priv *priv = netdev_priv(dev);
1147 struct flexcan_regs __iomem *regs = priv->base;
1150 err = clk_prepare_enable(priv->clk_ipg);
1154 err = clk_prepare_enable(priv->clk_per);
1156 goto out_disable_ipg;
1158 /* select "bus clock", chip must be disabled */
1159 err = flexcan_chip_disable(priv);
1161 goto out_disable_per;
1162 reg = flexcan_read(®s->ctrl);
1163 reg |= FLEXCAN_CTRL_CLK_SRC;
1164 flexcan_write(reg, ®s->ctrl);
1166 err = flexcan_chip_enable(priv);
1168 goto out_chip_disable;
1170 /* set freeze, halt and activate FIFO, restrict register access */
1171 reg = flexcan_read(®s->mcr);
1172 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1173 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1174 flexcan_write(reg, ®s->mcr);
1177 * Currently we only support newer versions of this core
1178 * featuring a RX FIFO. Older cores found on some Coldfire
1179 * derivates are not yet supported.
1181 reg = flexcan_read(®s->mcr);
1182 if (!(reg & FLEXCAN_MCR_FEN)) {
1183 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1185 goto out_chip_disable;
1188 err = register_candev(dev);
1190 /* disable core and turn off clocks */
1192 flexcan_chip_disable(priv);
1194 clk_disable_unprepare(priv->clk_per);
1196 clk_disable_unprepare(priv->clk_ipg);
1201 static void unregister_flexcandev(struct net_device *dev)
1203 unregister_candev(dev);
1206 static const struct of_device_id flexcan_of_match[] = {
1207 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1208 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1209 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1210 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1213 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1215 static const struct platform_device_id flexcan_id_table[] = {
1216 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1219 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1221 static int flexcan_probe(struct platform_device *pdev)
1223 const struct of_device_id *of_id;
1224 const struct flexcan_devtype_data *devtype_data;
1225 struct net_device *dev;
1226 struct flexcan_priv *priv;
1227 struct resource *mem;
1228 struct clk *clk_ipg = NULL, *clk_per = NULL;
1233 if (pdev->dev.of_node)
1234 of_property_read_u32(pdev->dev.of_node,
1235 "clock-frequency", &clock_freq);
1238 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1239 if (IS_ERR(clk_ipg)) {
1240 dev_err(&pdev->dev, "no ipg clock defined\n");
1241 return PTR_ERR(clk_ipg);
1244 clk_per = devm_clk_get(&pdev->dev, "per");
1245 if (IS_ERR(clk_per)) {
1246 dev_err(&pdev->dev, "no per clock defined\n");
1247 return PTR_ERR(clk_per);
1249 clock_freq = clk_get_rate(clk_per);
1252 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1253 irq = platform_get_irq(pdev, 0);
1257 base = devm_ioremap_resource(&pdev->dev, mem);
1259 return PTR_ERR(base);
1261 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1263 devtype_data = of_id->data;
1264 } else if (platform_get_device_id(pdev)->driver_data) {
1265 devtype_data = (struct flexcan_devtype_data *)
1266 platform_get_device_id(pdev)->driver_data;
1271 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1275 dev->netdev_ops = &flexcan_netdev_ops;
1277 dev->flags |= IFF_ECHO;
1279 priv = netdev_priv(dev);
1280 priv->can.clock.freq = clock_freq;
1281 priv->can.bittiming_const = &flexcan_bittiming_const;
1282 priv->can.do_set_mode = flexcan_set_mode;
1283 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1284 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1285 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1286 CAN_CTRLMODE_BERR_REPORTING;
1289 priv->clk_ipg = clk_ipg;
1290 priv->clk_per = clk_per;
1291 priv->pdata = dev_get_platdata(&pdev->dev);
1292 priv->devtype_data = devtype_data;
1294 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1295 if (IS_ERR(priv->reg_xceiver))
1296 priv->reg_xceiver = NULL;
1298 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1300 platform_set_drvdata(pdev, dev);
1301 SET_NETDEV_DEV(dev, &pdev->dev);
1303 err = register_flexcandev(dev);
1305 dev_err(&pdev->dev, "registering netdev failed\n");
1306 goto failed_register;
1309 devm_can_led_init(dev);
1311 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1312 priv->base, dev->irq);
1321 static int flexcan_remove(struct platform_device *pdev)
1323 struct net_device *dev = platform_get_drvdata(pdev);
1324 struct flexcan_priv *priv = netdev_priv(dev);
1326 unregister_flexcandev(dev);
1327 netif_napi_del(&priv->napi);
1333 static int __maybe_unused flexcan_suspend(struct device *device)
1335 struct net_device *dev = dev_get_drvdata(device);
1336 struct flexcan_priv *priv = netdev_priv(dev);
1339 err = flexcan_chip_disable(priv);
1343 if (netif_running(dev)) {
1344 netif_stop_queue(dev);
1345 netif_device_detach(dev);
1347 priv->can.state = CAN_STATE_SLEEPING;
1352 static int __maybe_unused flexcan_resume(struct device *device)
1354 struct net_device *dev = dev_get_drvdata(device);
1355 struct flexcan_priv *priv = netdev_priv(dev);
1357 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1358 if (netif_running(dev)) {
1359 netif_device_attach(dev);
1360 netif_start_queue(dev);
1362 return flexcan_chip_enable(priv);
1365 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1367 static struct platform_driver flexcan_driver = {
1370 .owner = THIS_MODULE,
1371 .pm = &flexcan_pm_ops,
1372 .of_match_table = flexcan_of_match,
1374 .probe = flexcan_probe,
1375 .remove = flexcan_remove,
1376 .id_table = flexcan_id_table,
1379 module_platform_driver(flexcan_driver);
1381 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1382 "Marc Kleine-Budde <kernel@pengutronix.de>");
1383 MODULE_LICENSE("GPL v2");
1384 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");